ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

update Cube driver to v1.4.0

pull/1909/head
ohagendorf 2016-06-02 00:06:57 +02:00 committed by Olaf Hagendorf
parent 4261a225f4
commit db7ca8086d
137 changed files with 32102 additions and 14041 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

204
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/Release_Notes_stm32f7xx_hal.html
View File

File diff suppressed because one or more lines are too long

295
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32_hal_legacy.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -103,6 +103,7 @@
#define ADC_EXTERNALTRIG_EDGE_RISING ADC_EXTERNALTRIGCONVEDGE_RISING
#define ADC_EXTERNALTRIG_EDGE_FALLING ADC_EXTERNALTRIGCONVEDGE_FALLING
#define ADC_EXTERNALTRIG_EDGE_RISINGFALLING ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING
#define ADC_SAMPLETIME_2CYCLE_5 ADC_SAMPLETIME_2CYCLES_5
#define HAL_ADC_STATE_BUSY_REG HAL_ADC_STATE_REG_BUSY
#define HAL_ADC_STATE_BUSY_INJ HAL_ADC_STATE_INJ_BUSY
@ -128,7 +129,6 @@
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
#define COMP_WINDOWMODE_DISABLED COMP_WINDOWMODE_DISABLE
#define COMP_WINDOWMODE_ENABLED COMP_WINDOWMODE_ENABLE
#define COMP_EXTI_LINE_COMP1_EVENT COMP_EXTI_LINE_COMP1
@ -143,6 +143,62 @@
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
#define COMP_OUTPUT_TIM3OCREFCLR COMP_OUTPUT_COMP1_TIM3OCREFCLR
#endif /* STM32F373xC || STM32F378xx */
#if defined(STM32L0) || defined(STM32L4)
#define COMP_WINDOWMODE_ENABLE COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON
#define COMP_NONINVERTINGINPUT_IO1 COMP_INPUT_PLUS_IO1
#define COMP_NONINVERTINGINPUT_IO2 COMP_INPUT_PLUS_IO2
#define COMP_NONINVERTINGINPUT_IO3 COMP_INPUT_PLUS_IO3
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
#define COMP_INVERTINGINPUT_VREFINT COMP_INPUT_MINUS_VREFINT
#define COMP_INVERTINGINPUT_DAC1_CH1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC1_CH2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_DAC1 COMP_INPUT_MINUS_DAC1_CH1
#define COMP_INVERTINGINPUT_DAC2 COMP_INPUT_MINUS_DAC1_CH2
#define COMP_INVERTINGINPUT_IO1 COMP_INPUT_MINUS_IO1
#define COMP_INVERTINGINPUT_IO2 COMP_INPUT_MINUS_IO2
#define COMP_INVERTINGINPUT_IO3 COMP_INPUT_MINUS_IO3
#define COMP_INVERTINGINPUT_IO4 COMP_INPUT_MINUS_IO4
#define COMP_INVERTINGINPUT_IO5 COMP_INPUT_MINUS_IO5
#define COMP_OUTPUTLEVEL_LOW COMP_OUTPUT_LEVEL_LOW
#define COMP_OUTPUTLEVEL_HIGH COMP_OUTPUT_LEVEL_HIGH
/* Note: Literal "COMP_FLAG_LOCK" kept for legacy purpose. */
/* To check COMP lock state, use macro "__HAL_COMP_IS_LOCKED()". */
#if defined(COMP_CSR_LOCK)
#define COMP_FLAG_LOCK COMP_CSR_LOCK
#elif defined(COMP_CSR_COMP1LOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMP1LOCK
#elif defined(COMP_CSR_COMPxLOCK)
#define COMP_FLAG_LOCK COMP_CSR_COMPxLOCK
#endif
#if defined(STM32L4)
#define COMP_BLANKINGSRCE_TIM1OC5 COMP_BLANKINGSRC_TIM1_OC5_COMP1
#define COMP_BLANKINGSRCE_TIM2OC3 COMP_BLANKINGSRC_TIM2_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC3 COMP_BLANKINGSRC_TIM3_OC3_COMP1
#define COMP_BLANKINGSRCE_TIM3OC4 COMP_BLANKINGSRC_TIM3_OC4_COMP2
#define COMP_BLANKINGSRCE_TIM8OC5 COMP_BLANKINGSRC_TIM8_OC5_COMP2
#define COMP_BLANKINGSRCE_TIM15OC1 COMP_BLANKINGSRC_TIM15_OC1_COMP2
#define COMP_BLANKINGSRCE_NONE COMP_BLANKINGSRC_NONE
#endif
#if defined(STM32L0)
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWSPEED COMP_POWERMODE_ULTRALOWPOWER
#else
#define COMP_MODE_HIGHSPEED COMP_POWERMODE_HIGHSPEED
#define COMP_MODE_MEDIUMSPEED COMP_POWERMODE_MEDIUMSPEED
#define COMP_MODE_LOWPOWER COMP_POWERMODE_LOWPOWER
#define COMP_MODE_ULTRALOWPOWER COMP_POWERMODE_ULTRALOWPOWER
#endif
#endif
/**
* @}
*/
@ -173,7 +229,7 @@
#define DAC1_CHANNEL_1 DAC_CHANNEL_1
#define DAC1_CHANNEL_2 DAC_CHANNEL_2
#define DAC2_CHANNEL_1 DAC_CHANNEL_1
#define DAC_WAVE_NONE ((uint32_t)0x00000000)
#define DAC_WAVE_NONE ((uint32_t)0x00000000U)
#define DAC_WAVE_NOISE ((uint32_t)DAC_CR_WAVE1_0)
#define DAC_WAVE_TRIANGLE ((uint32_t)DAC_CR_WAVE1_1)
#define DAC_WAVEGENERATION_NONE DAC_WAVE_NONE
@ -377,12 +433,13 @@
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F3) || defined(STM32F1)
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_HIGH
#endif /* STM32F3 */
#endif /* STM32F0 || STM32F3 || STM32F1 */
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
/**
* @}
*/
@ -423,6 +480,14 @@
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_MASTER_BUSY_RX HAL_I2C_STATE_BUSY_RX
#define HAL_I2C_STATE_SLAVE_BUSY_TX HAL_I2C_STATE_BUSY_TX
#define HAL_I2C_STATE_SLAVE_BUSY_RX HAL_I2C_STATE_BUSY_RX
#endif
/**
* @}
*/
@ -479,6 +544,11 @@
/** @defgroup HAL_NAND_Aliased_Defines HAL NAND Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_NAND_Read_Page HAL_NAND_Read_Page_8b
#define HAL_NAND_Write_Page HAL_NAND_Write_Page_8b
#define HAL_NAND_Read_SpareArea HAL_NAND_Read_SpareArea_8b
#define HAL_NAND_Write_SpareArea HAL_NAND_Write_SpareArea_8b
#define NAND_AddressTypedef NAND_AddressTypeDef
#define __ARRAY_ADDRESS ARRAY_ADDRESS
@ -542,6 +612,9 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
* @}
*/
@ -637,7 +710,7 @@
*/
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
#define SMBUS_DUALADDRESS_DISABLED SMBUS_DUALADDRESS_DISABLE
@ -655,7 +728,7 @@
* @}
*/
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
#define SPI_TIMODE_DISABLED SPI_TIMODE_DISABLE
@ -808,9 +881,9 @@
#define CAN_IT_RQCP2 CAN_IT_TME
#define INAK_TIMEOUT CAN_TIMEOUT_VALUE
#define SLAK_TIMEOUT CAN_TIMEOUT_VALUE
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00)
#define CAN_TXSTATUS_OK ((uint8_t)0x01)
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02)
#define CAN_TXSTATUS_FAILED ((uint8_t)0x00U)
#define CAN_TXSTATUS_OK ((uint8_t)0x01U)
#define CAN_TXSTATUS_PENDING ((uint8_t)0x02U)
/**
* @}
@ -829,21 +902,95 @@
#define MACFCR_CLEAR_MASK ETH_MACFCR_CLEAR_MASK
#define DMAOMR_CLEAR_MASK ETH_DMAOMR_CLEAR_MASK
#define ETH_MMCCR ((uint32_t)0x00000100)
#define ETH_MMCRIR ((uint32_t)0x00000104)
#define ETH_MMCTIR ((uint32_t)0x00000108)
#define ETH_MMCRIMR ((uint32_t)0x0000010C)
#define ETH_MMCTIMR ((uint32_t)0x00000110)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150)
#define ETH_MMCTGFCR ((uint32_t)0x00000168)
#define ETH_MMCRFCECR ((uint32_t)0x00000194)
#define ETH_MMCRFAECR ((uint32_t)0x00000198)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4)
#define ETH_MMCCR ((uint32_t)0x00000100U)
#define ETH_MMCRIR ((uint32_t)0x00000104U)
#define ETH_MMCTIR ((uint32_t)0x00000108U)
#define ETH_MMCRIMR ((uint32_t)0x0000010CU)
#define ETH_MMCTIMR ((uint32_t)0x00000110U)
#define ETH_MMCTGFSCCR ((uint32_t)0x0000014CU)
#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150U)
#define ETH_MMCTGFCR ((uint32_t)0x00000168U)
#define ETH_MMCRFCECR ((uint32_t)0x00000194U)
#define ETH_MMCRFAECR ((uint32_t)0x00000198U)
#define ETH_MMCRGUFCR ((uint32_t)0x000001C4U)
#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
#if defined(STM32F1)
#else
#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
#endif
#define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
/**
* @}
*/
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
#define HAL_DCMI_ERROR_OVF HAL_DCMI_ERROR_OVR
#define DCMI_IT_OVF DCMI_IT_OVR
#define DCMI_FLAG_OVFRI DCMI_FLAG_OVRRI
#define DCMI_FLAG_OVFMI DCMI_FLAG_OVRMI
#define HAL_DCMI_ConfigCROP HAL_DCMI_ConfigCrop
#define HAL_DCMI_EnableCROP HAL_DCMI_EnableCrop
#define HAL_DCMI_DisableCROP HAL_DCMI_DisableCrop
/**
* @}
*/
#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
#define CM_RGB888 DMA2D_INPUT_RGB888
#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
#define CM_L8 DMA2D_INPUT_L8
#define CM_AL44 DMA2D_INPUT_AL44
#define CM_AL88 DMA2D_INPUT_AL88
#define CM_L4 DMA2D_INPUT_L4
#define CM_A8 DMA2D_INPUT_A8
#define CM_A4 DMA2D_INPUT_A4
/**
* @}
*/
#endif /* STM32L4xx || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
@ -901,7 +1048,10 @@
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
#if defined(STM32L0)
#else
#define HAL_VREFINT_Cmd(cmd) (((cmd)==ENABLE)? HAL_SYSCFG_EnableVREFINT() : HAL_SYSCFG_DisableVREFINT())
#endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
/**
@ -926,8 +1076,10 @@
/** @defgroup HAL_I2C_Aliased_Functions HAL I2C Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_I2CEx_AnalogFilter_Config HAL_I2CEx_ConfigAnalogFilter
#define HAL_I2CEx_DigitalFilter_Config HAL_I2CEx_ConfigDigitalFilter
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
/**
@ -1028,7 +1180,7 @@
*/
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
@ -1403,10 +1555,28 @@
#define __HAL_COMP_GET_EXTI_LINE COMP_GET_EXTI_LINE
#if defined(STM32L0) || defined(STM32L4)
/* Note: On these STM32 families, the only argument of this macro */
/* is COMP_FLAG_LOCK. */
/* This macro is replaced by __HAL_COMP_IS_LOCKED with only HAL handle */
/* argument. */
#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_COMP_IS_LOCKED(__HANDLE__))
#endif
/**
* @}
*/
#if defined(STM32L0) || defined(STM32L4)
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
/**
* @}
*/
#endif
/** @defgroup HAL_DAC_Aliased_Macros HAL DAC Aliased Macros maintained for legacy purpose
* @{
*/
@ -2450,7 +2620,7 @@
#endif
#if defined(STM32F7)
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_CLK48 RCC_SDMMC1CLKSOURCE_CLK48
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
@ -2564,6 +2734,34 @@
#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE __HAL_RCC_CRS_RELOADVALUE_CALCULATE
#define __HAL_RCC_GET_IT_SOURCE __HAL_RCC_GET_IT
#define RCC_CRS_SYNCWARM RCC_CRS_SYNCWARN
#define RCC_CRS_TRIMOV RCC_CRS_TRIMOVF
#define RCC_PERIPHCLK_CK48 RCC_PERIPHCLK_CLK48
#define RCC_CK48CLKSOURCE_PLLQ RCC_CLK48CLKSOURCE_PLLQ
#define RCC_CK48CLKSOURCE_PLLSAIP RCC_CLK48CLKSOURCE_PLLSAIP
#define RCC_CK48CLKSOURCE_PLLI2SQ RCC_CLK48CLKSOURCE_PLLI2SQ
#define IS_RCC_CK48CLKSOURCE IS_RCC_CLK48CLKSOURCE
#define RCC_SDIOCLKSOURCE_CK48 RCC_SDIOCLKSOURCE_CLK48
#define __HAL_RCC_DFSDM_CLK_ENABLE __HAL_RCC_DFSDM1_CLK_ENABLE
#define __HAL_RCC_DFSDM_CLK_DISABLE __HAL_RCC_DFSDM1_CLK_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_ENABLED __HAL_RCC_DFSDM1_IS_CLK_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_DISABLED __HAL_RCC_DFSDM1_IS_CLK_DISABLED
#define __HAL_RCC_DFSDM_FORCE_RESET __HAL_RCC_DFSDM1_FORCE_RESET
#define __HAL_RCC_DFSDM_RELEASE_RESET __HAL_RCC_DFSDM1_RELEASE_RESET
#define __HAL_RCC_DFSDM_CLK_SLEEP_ENABLE __HAL_RCC_DFSDM1_CLK_SLEEP_ENABLE
#define __HAL_RCC_DFSDM_CLK_SLEEP_DISABLE __HAL_RCC_DFSDM1_CLK_SLEEP_DISABLE
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_ENABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_DFSDM_IS_CLK_SLEEP_DISABLED __HAL_RCC_DFSDM1_IS_CLK_SLEEP_DISABLED
#define DfsdmClockSelection Dfsdm1ClockSelection
#define RCC_PERIPHCLK_DFSDM RCC_PERIPHCLK_DFSDM1
#define RCC_DFSDMCLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK
#define RCC_DFSDMCLKSOURCE_SYSCLK RCC_DFSDM1CLKSOURCE_SYSCLK
#define __HAL_RCC_DFSDM_CONFIG __HAL_RCC_DFSDM1_CONFIG
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
/**
* @}
*/
@ -2853,31 +3051,7 @@
#define __HAL_TIM_SetCompare __HAL_TIM_SET_COMPARE
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
#define TIM_TS_ITR0 ((uint32_t)0x0000)
#define TIM_TS_ITR1 ((uint32_t)0x0010)
#define TIM_TS_ITR2 ((uint32_t)0x0020)
#define TIM_TS_ITR3 ((uint32_t)0x0030)
#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
((SELECTION) == TIM_TS_ITR1) || \
((SELECTION) == TIM_TS_ITR2) || \
((SELECTION) == TIM_TS_ITR3))
#define TIM_CHANNEL_1 ((uint32_t)0x0000)
#define TIM_CHANNEL_2 ((uint32_t)0x0004)
#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
((CHANNEL) == TIM_CHANNEL_2))
#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
((STATE) == TIM_OUTPUTNSTATE_ENABLE))
#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
((STATE) == TIM_OUTPUTSTATE_ENABLE))
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
/**
* @}
*/
@ -2917,14 +3091,15 @@
#define SAI_MASTERDIVIDER_ENABLED SAI_MASTERDIVIDER_ENABLE
#define SAI_MASTERDIVIDER_DISABLED SAI_MASTERDIVIDER_DISABLE
#define SAI_STREOMODE SAI_STEREOMODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_FIFOStatus_Empty SAI_FIFOSTATUS_EMPTY
#define SAI_FIFOStatus_Less1QuarterFull SAI_FIFOSTATUS_LESS1QUARTERFULL
#define SAI_FIFOStatus_1QuarterFull SAI_FIFOSTATUS_1QUARTERFULL
#define SAI_FIFOStatus_HalfFull SAI_FIFOSTATUS_HALFFULL
#define SAI_FIFOStatus_3QuartersFull SAI_FIFOSTATUS_3QUARTERFULL
#define SAI_FIFOStatus_Full SAI_FIFOSTATUS_FULL
#define IS_SAI_BLOCK_MONO_STREO_MODE IS_SAI_BLOCK_MONO_STEREO_MODE
#define SAI_SYNCHRONOUS_EXT SAI_SYNCHRONOUS_EXT_SAI1
#define SAI_SYNCEXT_IN_ENABLE SAI_SYNCEXT_OUTBLOCKA_ENABLE
/**
* @}
*/

50
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -68,11 +68,11 @@
* @{
*/
/**
* @brief STM32F7xx HAL Driver version number V1.0.4
* @brief STM32F7xx HAL Driver version number V1.1.0
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F7xx_HAL_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@ -89,7 +89,7 @@
/** @addtogroup HAL_Private_Variables
* @{
*/
static __IO uint32_t uwTick;
__IO uint32_t uwTick;
/**
* @}
*/
@ -242,7 +242,7 @@ __weak void HAL_MspDeInit(void)
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
/*Configure the SysTick to have interrupt in 1ms time basis*/
HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
HAL_SYSTICK_Config(SystemCoreClock/1000);
/*Configure the SysTick IRQ priority */
HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
@ -370,7 +370,7 @@ uint32_t HAL_GetHalVersion(void)
*/
uint32_t HAL_GetREVID(void)
{
return((DBGMCU->IDCODE) >> 16);
return((DBGMCU->IDCODE) >> 16U);
}
/**
@ -485,6 +485,38 @@ void HAL_DisableFMCMemorySwapping(void)
SYSCFG->MEMRMP &= (uint32_t)~((uint32_t)SYSCFG_MEMRMP_SWP_FMC);
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/**
* @brief Enable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
*
* @note Flash Bank2 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
* and Flash Bank1 mapped at 0x08100000 (AXI) (aliased at 0x00300000 (TCM))
*
* @retval None
*/
void HAL_EnableMemorySwappingBank(void)
{
SET_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
}
/**
* @brief Disable the Internal FLASH Bank Swapping.
*
* @note This function can be used only for STM32F77xx/STM32F76xx devices.
*
* @note The default state : Flash Bank1 mapped at 0x08000000 (AXI) (aliased at 0x00200000 (TCM))
* and Flash Bank2 mapped at 0x08100000 (AXI)( aliased at 0x00300000 (TCM))
*
* @retval None
*/
void HAL_DisableMemorySwappingBank(void)
{
CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_SWP_FB);
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

50
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f7xx_hal.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -57,6 +57,23 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants
* @{
*/
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
#define SYSCFG_MEM_BOOT_ADD0 ((uint32_t)0x00000000U)
#define SYSCFG_MEM_BOOT_ADD1 SYSCFG_MEMRMP_MEM_BOOT
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
@ -125,6 +142,29 @@
#define __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_SWP_FMC);\
SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_SWP_FMC_0);\
}while(0);
/**
* @brief Return the memory boot mapping as configured by user.
* @retval The boot mode as configured by user. The returned value can be one
* of the following values:
* @arg @ref SYSCFG_MEM_BOOT_ADD0
* @arg @ref SYSCFG_MEM_BOOT_ADD1
*/
#define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_BOOT)
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @brief SYSCFG Break Cortex-M7 Lockup lock.
* Enable and lock the connection of Cortex-M7 LOCKUP (Hardfault) output to TIM1/8 Break input.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_CLL)
/** @brief SYSCFG Break PVD lock.
* Enable and lock the PVD connection to Timer1/8 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR1 register.
* @note The selected configuration is locked and can be unlocked only by system reset.
*/
#define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CBR, SYSCFG_CBR_PVDL)
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
@ -168,6 +208,10 @@ void HAL_EnableCompensationCell(void);
void HAL_DisableCompensationCell(void);
void HAL_EnableFMCMemorySwapping(void);
void HAL_DisableFMCMemorySwapping(void);
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
void HAL_EnableMemorySwappingBank(void);
void HAL_DisableMemorySwappingBank(void);
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

21
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the Analog to Digital Convertor (ADC) peripheral:
* + Initialization and de-initialization functions
@ -164,7 +164,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -498,7 +498,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Check if Multimode enabled */
if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI))
@ -789,7 +789,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable end of conversion interrupt for regular group */
__HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
@ -843,6 +843,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
/* Check if ADC is effectively disabled */
if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON))
{
/* Disable ADC end of conversion interrupt for regular group */
__HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
/* Set ADC state */
ADC_STATE_CLR_SET(hadc->State,
HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
@ -1084,7 +1087,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
/* Clear regular group conversion flag and overrun flag */
/* (To ensure of no unknown state from potential previous ADC operations) */
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
__HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC | ADC_FLAG_OVR);
/* Enable ADC overrun interrupt */
__HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
@ -1225,6 +1228,12 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
/**
* @brief Error ADC callback.
* @note In case of error due to overrun when using ADC with DMA transfer
* (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
* - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
* - If needed, restart a new ADC conversion using function
* "HAL_ADC_Start_DMA()"
* (this function is also clearing overrun flag)
* @param hadc: pointer to a ADC_HandleTypeDef structure that contains
* the configuration information for the specified ADC.
* @retval None

87
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of ADC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -81,13 +81,14 @@ typedef struct
This parameter can be a value of @ref ADC_Resolution */
uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
This parameter can be a value of @ref ADC_data_align */
This parameter can be a value of @ref ADC_Data_Align */
uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
Scan direction is upward: from rank1 to rank 'n'. */
Scan direction is upward: from rank1 to rank 'n'.
This parameter can be set to ENABLE or DISABLE */
uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
This parameter can be a value of @ref ADC_EOCSelection.
Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
@ -171,34 +172,34 @@ typedef struct
* @brief HAL ADC state machine: ADC states definition (bitfields)
*/
/* States of ADC global scope */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004) /*!< TimeOut occurrence */
#define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
#define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
#define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
#define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
/* States of ADC errors */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040) /*!< DMA error occurrence */
#define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
#define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
#define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
/* States of ADC group regular */
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
#define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400) /*!< Overrun occurrence */
#define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
#define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
/* States of ADC group injected */
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
#define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000) /*!< Conversion data available on group injected */
#define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
/* States of ADC analog watchdogs */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
#define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
#define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
#define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
/* States of ADC multi-mode */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000) /*!< Not available on STM32F4 device: ADC in multimode slave state, controlled by another ADC master ( */
#define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
/**
@ -232,11 +233,11 @@ typedef struct
/** @defgroup ADC_Error_Code ADC Error Code
* @{
*/
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01) /*!< ADC IP internal error: if problem of clocking,
#define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
#define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
enable/disable, erroneous state */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04) /*!< DMA transfer error */
#define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
#define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
/**
* @}
*/
@ -245,7 +246,7 @@ typedef struct
/** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
* @{
*/
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000)
#define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
#define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
#define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
#define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
@ -256,7 +257,7 @@ typedef struct
/** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
* @{
*/
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000)
#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
@ -279,7 +280,7 @@ typedef struct
/** @defgroup ADC_Resolution ADC Resolution
* @{
*/
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000)
#define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
#define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
#define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
#define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
@ -290,7 +291,7 @@ typedef struct
/** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
* @{
*/
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
#define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
@ -305,7 +306,7 @@ typedef struct
/* compatibility with other STM32 devices. */
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
#define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
#define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
@ -327,10 +328,10 @@ typedef struct
* @}
*/
/** @defgroup ADC_data_align ADC Data Align
/** @defgroup ADC_Data_Align ADC Data Align
* @{
*/
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000)
#define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
#define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
/**
* @}
@ -339,7 +340,7 @@ typedef struct
/** @defgroup ADC_channels ADC Common Channels
* @{
*/
#define ADC_CHANNEL_0 ((uint32_t)0x00000000)
#define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
#define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
#define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
#define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
@ -368,7 +369,7 @@ typedef struct
/** @defgroup ADC_sampling_times ADC Sampling Times
* @{
*/
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000)
#define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
#define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
#define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
#define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
@ -383,9 +384,9 @@ typedef struct
/** @defgroup ADC_EOCSelection ADC EOC Selection
* @{
*/
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000)
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002) /*!< reserved for future use */
#define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
#define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
#define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
/**
* @}
*/
@ -408,7 +409,7 @@ typedef struct
#define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
#define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
#define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000)
#define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -440,9 +441,9 @@ typedef struct
/** @defgroup ADC_channels_type ADC Channels Type
* @{
*/
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001)
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002) /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003) /*!< reserved for future use */
#define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
#define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
#define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
/**
* @}
*/
@ -600,11 +601,11 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/* Delay for ADC stabilization time. */
/* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
/* Unit: us */
#define ADC_STAB_DELAY_US ((uint32_t) 3)
#define ADC_STAB_DELAY_US ((uint32_t) 3U)
/* Delay for temperature sensor stabilization time. */
/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
/* Unit: us */
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10)
#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
/**
* @}
*/

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_adc_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief This file provides firmware functions to manage the following
* functionalities of the ADC extension peripheral:
* + Extended features functions
@ -86,7 +86,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

28
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_adc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_adc.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -77,7 +77,7 @@ typedef struct
This parameter can be a value of @ref ADC_channels
Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
uint32_t InjectedRank; /*!< Rank in the injected group sequencer
This parameter must be a value of @ref ADCEx_injected_channel_selection
This parameter must be a value of @ref ADCEx_injected_rank
Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
Unit: ADC clock cycles
@ -155,7 +155,7 @@ typedef struct
/** @defgroup ADCEx_Common_mode ADC Common Mode
* @{
*/
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
#define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000U)
#define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
#define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
#define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
@ -175,7 +175,7 @@ typedef struct
/** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode ADC Direct Memory Access Mode For Multi Mode
* @{
*/
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000U) /*!< DMA mode disabled */
#define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
#define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
#define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
@ -186,7 +186,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_edge_Injected ADC External Trigger Edge Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
#define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
#define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
@ -197,7 +197,7 @@ typedef struct
/** @defgroup ADCEx_External_trigger_Source_Injected ADC External Trigger Source Injected
* @{
*/
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000)
#define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)0x00000000U)
#define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)ADC_CR2_JEXTSEL_0)
#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)ADC_CR2_JEXTSEL_1)
#define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
@ -217,13 +217,13 @@ typedef struct
* @}
*/
/** @defgroup ADCEx_injected_channel_selection ADC Injected Channel Selection
/** @defgroup ADCEx_injected_rank ADC Injected Rank
* @{
*/
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
#define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001U)
#define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002U)
#define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003U)
#define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004U)
/**
* @}
*/
@ -231,7 +231,7 @@ typedef struct
/** @defgroup ADCEx_channels ADC Specific Channels
* @{
*/
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000)
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18 | 0x10000000U)
/**
* @}
*/

439
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief CAN HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
@ -18,7 +18,8 @@
==============================================================================
[..]
(#) Enable the CAN controller interface clock using
__HAL_RCC_CAN1_CLK_ENABLE() for CAN1 and __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
__HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
-@- In case you are using CAN2 only, you have to enable the CAN1 clock.
(#) CAN pins configuration
@ -30,9 +31,13 @@
(#) Initialize and configure the CAN using HAL_CAN_Init() function.
(#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
(#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
(#) Receive a CAN frame using HAL_CAN_Receive() function.
(#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
*** Polling mode IO operation ***
=================================
[..]
@ -73,7 +78,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -165,7 +170,7 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
*/
HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
{
uint32_t InitStatus = 3;
uint32_t InitStatus = CAN_INITSTATUS_FAILED;
uint32_t tickstart = 0;
/* Check CAN handle */
@ -222,11 +227,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
}
/* Check acknowledge */
if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_FAILED;
}
else
if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
/* Set the time triggered communication mode */
if (hcan->Init.TTCM == ENABLE)
@ -293,32 +294,28 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
((uint32_t)hcan->Init.SJW) | \
((uint32_t)hcan->Init.BS1) | \
((uint32_t)hcan->Init.BS2) | \
((uint32_t)hcan->Init.Prescaler - 1);
((uint32_t)hcan->Init.Prescaler - 1);
/* Request leave initialisation */
hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
/* Get tick */
tickstart = HAL_GetTick();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
/* Wait the acknowledge */
while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
{
hcan->State= HAL_CAN_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hcan);
return HAL_TIMEOUT;
}
}
/* Check acknowledged */
if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_FAILED;
}
else
if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
{
InitStatus = CAN_INITSTATUS_SUCCESS;
}
@ -357,6 +354,7 @@ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
{
uint32_t filternbrbitpos = 0;
CAN_TypeDef *can_ip;
/* Check the parameters */
assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
@ -367,84 +365,99 @@ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTy
assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
#if defined (CAN3)
/* Check the CAN instance */
if(hcan->Instance == CAN3)
{
can_ip = CAN3;
}
else
{
can_ip = CAN1;
}
#else
can_ip = CAN1;
#endif
/* Initialisation mode for the filter */
CAN1->FMR |= (uint32_t)CAN_FMR_FINIT;
can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
/* Select the start slave bank */
CAN1->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
CAN1->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
/* Filter Deactivation */
CAN1->FA1R &= ~(uint32_t)filternbrbitpos;
can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
/* Filter Scale */
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
{
/* 16-bit scale for the filter */
CAN1->FS1R &= ~(uint32_t)filternbrbitpos;
can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
/* First 16-bit identifier and First 16-bit mask */
/* Or First 16-bit identifier and Second 16-bit identifier */
CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
/* Second 16-bit identifier and Second 16-bit mask */
/* Or Third 16-bit identifier and Fourth 16-bit identifier */
CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
}
if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
{
/* 32-bit scale for the filter */
CAN1->FS1R |= filternbrbitpos;
can_ip->FS1R |= filternbrbitpos;
/* 32-bit identifier or First 32-bit identifier */
CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
/* 32-bit mask or Second 32-bit identifier */
CAN1->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
(0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
}
/* Filter Mode */
if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
{
/*Id/Mask mode for the filter*/
CAN1->FM1R &= ~(uint32_t)filternbrbitpos;
can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
}
else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
{
/*Identifier list mode for the filter*/
CAN1->FM1R |= (uint32_t)filternbrbitpos;
can_ip->FM1R |= (uint32_t)filternbrbitpos;
}
/* Filter FIFO assignment */
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
{
/* FIFO 0 assignation for the filter */
CAN1->FFA1R &= ~(uint32_t)filternbrbitpos;
can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
}
if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
{
/* FIFO 1 assignation for the filter */
CAN1->FFA1R |= (uint32_t)filternbrbitpos;
can_ip->FFA1R |= (uint32_t)filternbrbitpos;
}
/* Filter activation */
if (sFilterConfig->FilterActivation == ENABLE)
{
CAN1->FA1R |= filternbrbitpos;
can_ip->FA1R |= filternbrbitpos;
}
/* Leave the initialisation mode for the filter */
CAN1->FMR &= ~((uint32_t)CAN_FMR_FINIT);
can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
/* Return function status */
return HAL_OK;
}
@ -542,48 +555,46 @@ __weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
*/
HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
uint32_t transmitmailbox = 5;
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Select one empty transmit mailbox */
if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = 0;
}
else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = 1;
}
else if ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
{
transmitmailbox = 2;
}
else
{
transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
}
if (transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
{
if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process locked */
__HAL_LOCK(hcan);
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Select one empty transmit mailbox */
if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = CAN_TXMAILBOX_0;
}
else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
transmitmailbox = CAN_TXMAILBOX_2;
}
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if (hcan->pTxMsg->IDE == CAN_ID_STD)
@ -601,8 +612,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
@ -617,8 +628,8 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
/* Get tick */
tickstart = HAL_GetTick();
/* Get tick */
tickstart = HAL_GetTick();
/* Check End of transmission flag */
while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
@ -639,29 +650,23 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_RX;
/* Process unlocked */
__HAL_UNLOCK(hcan);
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcan);
}
/* Process unlocked */
__HAL_UNLOCK(hcan);
/* Return function status */
return HAL_OK;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
/* Process unlocked */
__HAL_UNLOCK(hcan);
hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
@ -676,16 +681,16 @@ HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
*/
HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
{
uint32_t transmitmailbox = 5;
uint32_t tmp = 0;
uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
/* Check the parameters */
assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
tmp = hcan->State;
if((tmp == HAL_CAN_STATE_READY) || (tmp == HAL_CAN_STATE_BUSY_RX))
if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
{
/* Process Locked */
__HAL_LOCK(hcan);
@ -693,96 +698,84 @@ HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
/* Select one empty transmit mailbox */
if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
{
transmitmailbox = 0;
transmitmailbox = CAN_TXMAILBOX_0;
}
else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
{
transmitmailbox = 1;
}
else if((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
{
transmitmailbox = 2;
transmitmailbox = CAN_TXMAILBOX_1;
}
else
{
transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
transmitmailbox = CAN_TXMAILBOX_2;
}
if(transmitmailbox != CAN_TXSTATUS_NOMAILBOX)
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
/* Set up the Id */
hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
if(hcan->pTxMsg->IDE == CAN_ID_STD)
{
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
hcan->pTxMsg->IDE | \
hcan->pTxMsg->RTR);
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
((uint32_t)hcan->pTxMsg->Data[2] << 16) |
((uint32_t)hcan->pTxMsg->Data[1] << 8) |
((uint32_t)hcan->pTxMsg->Data[0]));
hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
((uint32_t)hcan->pTxMsg->Data[6] << 16) |
((uint32_t)hcan->pTxMsg->Data[5] << 8) |
((uint32_t)hcan->pTxMsg->Data[4]));
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcan);
/* Enable Error warning Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
/* Enable Error passive Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
/* Enable Bus-off Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
/* Enable Last error code Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
/* Enable Error Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
/* Enable Transmit mailbox empty Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_TME);
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21) | \
hcan->pTxMsg->RTR);
}
else
{
assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3) | \
hcan->pTxMsg->IDE | \
hcan->pTxMsg->RTR);
}
/* Set up the DLC */
hcan->pTxMsg->DLC &= (uint8_t)0x0000000FU;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
/* Set up the data field */
hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3] << 24) |
((uint32_t)hcan->pTxMsg->Data[2] << 16) |
((uint32_t)hcan->pTxMsg->Data[1] << 8) |
((uint32_t)hcan->pTxMsg->Data[0]));
hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7] << 24) |
((uint32_t)hcan->pTxMsg->Data[6] << 16) |
((uint32_t)hcan->pTxMsg->Data[5] << 8) |
((uint32_t)hcan->pTxMsg->Data[4]));
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX_RX;
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
}
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Process Unlocked */
__HAL_UNLOCK(hcan);
/* Enable Error warning, Error passive, Bus-off,
Last error and Error Interrupts */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR |
CAN_IT_TME);
/* Request transmission */
hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
}
else
{
return HAL_BUSY;
/* Change CAN state */
hcan->State = HAL_CAN_STATE_ERROR;
/* Return function status */
return HAL_ERROR;
}
return HAL_OK;
@ -878,19 +871,16 @@ HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, u
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_BUSY_TX;
/* Process unlocked */
__HAL_UNLOCK(hcan);
}
else
{
/* Change CAN state */
hcan->State = HAL_CAN_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hcan);
}
/* Process unlocked */
__HAL_UNLOCK(hcan);
/* Return function status */
return HAL_OK;
}
@ -928,21 +918,14 @@ HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber
/* Set CAN error code to none */
hcan->ErrorCode = HAL_CAN_ERROR_NONE;
/* Enable Error warning Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG);
/* Enable Error passive Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EPV);
/* Enable Bus-off Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_BOF);
/* Enable Last error code Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_LEC);
/* Enable Error Interrupt */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_ERR);
/* Enable Error warning, Error passive, Bus-off,
Last error and Error Interrupts */
__HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR);
/* Process unlocked */
__HAL_UNLOCK(hcan);
@ -997,7 +980,7 @@ HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
return HAL_ERROR;
}
/* Get tick */
/* Get tick */
tickstart = HAL_GetTick();
/* Wait the acknowledge */
@ -1303,20 +1286,13 @@ static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
if(hcan->State == HAL_CAN_STATE_BUSY_TX)
{
/* Disable Error warning Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
/* Disable Error passive Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
/* Disable Bus-off Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
/* Disable Last error code Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
/* Disable Error Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
/* Disable Error warning, Error passive, Bus-off, Last error code
and Error Interrupts */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR );
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)
@ -1391,20 +1367,13 @@ static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONum
if(hcan->State == HAL_CAN_STATE_BUSY_RX)
{
/* Disable Error warning Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG);
/* Disable Error passive Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EPV);
/* Disable Bus-off Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_BOF);
/* Disable Last error code Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_LEC);
/* Disable Error Interrupt */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_ERR);
/* Disable Error warning, Error passive, Bus-off, Last error code
and Error Interrupts */
__HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
CAN_IT_EPV |
CAN_IT_BOF |
CAN_IT_LEC |
CAN_IT_ERR);
}
if(hcan->State == HAL_CAN_STATE_BUSY_TX_RX)

130
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_can.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_can.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,14 +64,14 @@
*/
typedef enum
{
HAL_CAN_STATE_RESET = 0x00, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_CAN_STATE_ERROR = 0x04 /*!< CAN error state */
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_RX = 0x22U, /*!< CAN process is ongoing */
HAL_CAN_STATE_BUSY_TX_RX = 0x32U, /*!< CAN process is ongoing */
HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
}HAL_CAN_StateTypeDef;
@ -248,16 +248,16 @@ typedef struct
/** @defgroup HAL_CAN_Error_Code HAL CAN Error Code
* @{
*/
#define HAL_CAN_ERROR_NONE 0x00 /*!< No error */
#define HAL_CAN_ERROR_EWG 0x01 /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02 /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04 /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08 /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x10 /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x20 /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x40 /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x80 /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x100 /*!< LEC transfer error */
#define HAL_CAN_ERROR_NONE 0x00U /*!< No error */
#define HAL_CAN_ERROR_EWG 0x01U /*!< EWG error */
#define HAL_CAN_ERROR_EPV 0x02U /*!< EPV error */
#define HAL_CAN_ERROR_BOF 0x04U /*!< BOF error */
#define HAL_CAN_ERROR_STF 0x08U /*!< Stuff error */
#define HAL_CAN_ERROR_FOR 0x10U /*!< Form error */
#define HAL_CAN_ERROR_ACK 0x20U /*!< Acknowledgment error */
#define HAL_CAN_ERROR_BR 0x40U /*!< Bit recessive */
#define HAL_CAN_ERROR_BD 0x80U /*!< LEC dominant */
#define HAL_CAN_ERROR_CRC 0x100U /*!< LEC transfer error */
/**
* @}
*/
@ -265,8 +265,8 @@ typedef struct
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
/**
* @}
*/
@ -274,7 +274,7 @@ typedef struct
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
#define CAN_MODE_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@ -285,7 +285,7 @@ typedef struct
/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
* @{
*/
#define CAN_SJW_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@ -296,7 +296,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
* @{
*/
#define CAN_BS1_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@ -319,7 +319,7 @@ typedef struct
/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
* @{
*/
#define CAN_BS2_1TQ ((uint32_t)0x00000000) /*!< 1 time quantum */
#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@ -334,8 +334,8 @@ typedef struct
/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
/**
* @}
*/
@ -343,8 +343,8 @@ typedef struct
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
/**
* @}
*/
@ -352,8 +352,8 @@ typedef struct
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
@ -361,8 +361,8 @@ typedef struct
/** @defgroup CAN_Identifier_Type CAN Identifier Type
* @{
*/
#define CAN_ID_STD ((uint32_t)0x00000000) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004) /*!< Extended Id */
#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
/**
* @}
*/
@ -370,8 +370,8 @@ typedef struct
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
#define CAN_RTR_DATA ((uint32_t)0x00000000) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002) /*!< Remote frame */
#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
/**
* @}
*/
@ -379,8 +379,8 @@ typedef struct
/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
* @{
*/
#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
/**
* @}
*/
@ -394,37 +394,37 @@ typedef struct
CAN_GetFlagStatus() function. */
/* Transmit Flags */
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)0x0000051A) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)0x0000051B) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)0x0000051C) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
/* Receive Flags */
#define CAN_FLAG_FF0 ((uint32_t)0x00000203) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)0x00000403) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404) /*!< FIFO 1 Overrun flag */
#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
/* Operating Mode Flags */
#define CAN_FLAG_INAK ((uint32_t)0x00000100) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI ((uint32_t)0x00000102) /*!< Error flag */
#define CAN_FLAG_WKU ((uint32_t)0x00000103) /*!< Wake up flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104) /*!< Sleep acknowledge flag */
#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
In this case the SLAK bit can be polled.*/
/* Error Flags */
#define CAN_FLAG_EWG ((uint32_t)0x00000300) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302) /*!< Bus-Off flag */
#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
@ -459,9 +459,9 @@ typedef struct
/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
* @{
*/
#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
/**
* @}
*/
@ -700,8 +700,8 @@ HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK ((uint32_t)0x000000FF)
#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
/**
* @}
*/

903
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.c
View File

File diff suppressed because it is too large Load Diff

212
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cec.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -107,8 +107,6 @@ typedef struct
uint32_t SignalFreeTimeOption; /*!< Set SFTOP bit @ref CEC_SFT_Option : specifies when SFT timer starts.
CEC_SFT_START_ON_TXSOM SFT: timer starts when TXSOM is set by software.
CEC_SFT_START_ON_TX_RX_END: SFT timer starts automatically at the end of message transmission/reception. */
uint32_t OwnAddress; /*!< Set OAR field, specifies CEC device address within a 15-bit long field */
uint32_t ListenMode; /*!< Set LSTN bit @ref CEC_Listening_Mode : specifies device listening mode. It can take two values:
@ -120,23 +118,68 @@ typedef struct
address (OAR) with positive acknowledge. Messages addressed to different destination
are received, but without interfering with the CEC bus: no acknowledge sent. */
uint8_t InitiatorAddress; /* Initiator address (source logical address, sent in each header) */
uint16_t OwnAddress; /*!< Own addresses configuration
This parameter can be a value of @ref CEC_OWN_ADDRESS */
uint8_t *RxBuffer; /*!< CEC Rx buffer pointeur */
}CEC_InitTypeDef;
/**
* @brief HAL CEC State structures definition
* @brief HAL CEC State structures definition
* @note HAL CEC State value is a combination of 2 different substates: gState and RxState.
* - gState contains CEC state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6 Error information
* 0 : No Error
* 1 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized. HAL CEC Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_CEC_STATE_RESET = 0x00, /*!< Peripheral Reset state */
HAL_CEC_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_CEC_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_CEC_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
HAL_CEC_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
HAL_CEC_STATE_STANDBY_RX = 0x05, /*!< IP ready to receive, doesn't prevent IP to transmit */
HAL_CEC_STATE_TIMEOUT = 0x06, /*!< Timeout state */
HAL_CEC_STATE_ERROR = 0x07 /*!< State Error */
HAL_CEC_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_CEC_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_CEC_STATE_BUSY = 0x24U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_CEC_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_BUSY_RX_TX = 0x23U, /*!< an internal process is ongoing
Value is allowed for gState only */
HAL_CEC_STATE_ERROR = 0x60U /*!< Error Value is allowed for gState only */
}HAL_CEC_StateTypeDef;
/**
@ -144,25 +187,27 @@ typedef enum
*/
typedef struct
{
CEC_TypeDef *Instance; /* CEC registers base address */
CEC_TypeDef *Instance; /*!< CEC registers base address */
CEC_InitTypeDef Init; /* CEC communication parameters */
CEC_InitTypeDef Init; /*!< CEC communication parameters */
uint8_t *pTxBuffPtr; /* Pointer to CEC Tx transfer Buffer */
uint8_t *pTxBuffPtr; /*!< Pointer to CEC Tx transfer Buffer */
uint16_t TxXferCount; /* CEC Tx Transfer Counter */
uint16_t TxXferCount; /*!< CEC Tx Transfer Counter */
uint8_t *pRxBuffPtr; /* Pointer to CEC Rx transfer Buffer */
uint16_t RxXferSize; /*!< CEC Rx Transfer size, 0: header received only */
uint16_t RxXferSize; /* CEC Rx Transfer size, 0: header received only */
HAL_LockTypeDef Lock; /*!< Locking object */
HAL_CEC_StateTypeDef gState; /*!< CEC state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
uint32_t ErrorCode; /* For errors handling purposes, copy of ISR register
in case error is reported */
HAL_CEC_StateTypeDef RxState; /*!< CEC state information related to Rx operations.
This parameter can be a value of @ref HAL_CEC_StateTypeDef */
HAL_LockTypeDef Lock; /* Locking object */
HAL_CEC_StateTypeDef State; /* CEC communication state */
uint32_t ErrorCode; /*!< For errors handling purposes, copy of ISR register
in case error is reported */
}CEC_HandleTypeDef;
/**
* @}
@ -176,7 +221,7 @@ typedef struct
/** @defgroup CEC_Error_Code CEC Error Code
* @{
*/
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0 /*!< no error */
#define HAL_CEC_ERROR_NONE (uint32_t) 0x0000U /*!< no error */
#define HAL_CEC_ERROR_RXOVR CEC_ISR_RXOVR /*!< CEC Rx-Overrun */
#define HAL_CEC_ERROR_BRE CEC_ISR_BRE /*!< CEC Rx Bit Rising Error */
#define HAL_CEC_ERROR_SBPE CEC_ISR_SBPE /*!< CEC Rx Short Bit period Error */
@ -193,14 +238,14 @@ typedef struct
/** @defgroup CEC_Signal_Free_Time CEC Signal Free Time setting parameter
* @{
*/
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000)
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001)
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002)
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003)
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004)
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007)
#define CEC_DEFAULT_SFT ((uint32_t)0x00000000U)
#define CEC_0_5_BITPERIOD_SFT ((uint32_t)0x00000001U)
#define CEC_1_5_BITPERIOD_SFT ((uint32_t)0x00000002U)
#define CEC_2_5_BITPERIOD_SFT ((uint32_t)0x00000003U)
#define CEC_3_5_BITPERIOD_SFT ((uint32_t)0x00000004U)
#define CEC_4_5_BITPERIOD_SFT ((uint32_t)0x00000005U)
#define CEC_5_5_BITPERIOD_SFT ((uint32_t)0x00000006U)
#define CEC_6_5_BITPERIOD_SFT ((uint32_t)0x00000007U)
/**
* @}
*/
@ -208,7 +253,7 @@ typedef struct
/** @defgroup CEC_Tolerance CEC Receiver Tolerance
* @{
*/
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000)
#define CEC_STANDARD_TOLERANCE ((uint32_t)0x00000000U)
#define CEC_EXTENDED_TOLERANCE ((uint32_t)CEC_CFGR_RXTOL)
/**
* @}
@ -217,7 +262,7 @@ typedef struct
/** @defgroup CEC_BRERxStop CEC Reception Stop on Error
* @{
*/
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000)
#define CEC_NO_RX_STOP_ON_BRE ((uint32_t)0x00000000U)
#define CEC_RX_STOP_ON_BRE ((uint32_t)CEC_CFGR_BRESTP)
/**
* @}
@ -226,7 +271,7 @@ typedef struct
/** @defgroup CEC_BREErrorBitGen CEC Error Bit Generation if Bit Rise Error reported
* @{
*/
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define CEC_BRE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_BRE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BREGEN)
/**
* @}
@ -235,7 +280,7 @@ typedef struct
/** @defgroup CEC_LBPEErrorBitGen CEC Error Bit Generation if Long Bit Period Error reported
* @{
*/
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000)
#define CEC_LBPE_ERRORBIT_NO_GENERATION ((uint32_t)0x00000000U)
#define CEC_LBPE_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_LBPEGEN)
/**
* @}
@ -244,7 +289,7 @@ typedef struct
/** @defgroup CEC_BroadCastMsgErrorBitGen CEC Error Bit Generation on Broadcast message
* @{
*/
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000)
#define CEC_BROADCASTERROR_ERRORBIT_GENERATION ((uint32_t)0x00000000U)
#define CEC_BROADCASTERROR_NO_ERRORBIT_GENERATION ((uint32_t)CEC_CFGR_BRDNOGEN)
/**
* @}
@ -253,7 +298,7 @@ typedef struct
/** @defgroup CEC_SFT_Option CEC Signal Free Time start option
* @{
*/
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000)
#define CEC_SFT_START_ON_TXSOM ((uint32_t)0x00000000U)
#define CEC_SFT_START_ON_TX_RX_END ((uint32_t)CEC_CFGR_SFTOPT)
/**
* @}
@ -262,7 +307,7 @@ typedef struct
/** @defgroup CEC_Listening_Mode CEC Listening mode option
* @{
*/
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000)
#define CEC_REDUCED_LISTENING_MODE ((uint32_t)0x00000000U)
#define CEC_FULL_LISTENING_MODE ((uint32_t)CEC_CFGR_LSTN)
/**
* @}
@ -271,7 +316,7 @@ typedef struct
/** @defgroup CEC_OAR_Position CEC Device Own Address position in CEC CFGR register
* @{
*/
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16)
#define CEC_CFGR_OAR_LSB_POS ((uint32_t) 16U)
/**
* @}
*/
@ -279,11 +324,34 @@ typedef struct
/** @defgroup CEC_Initiator_Position CEC Initiator logical address position in message header
* @{
*/
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4)
#define CEC_INITIATOR_LSB_POS ((uint32_t) 4U)
/**
* @}
*/
/** @defgroup CEC_OWN_ADDRESS CEC Own Address
* @{
*/
#define CEC_OWN_ADDRESS_NONE ((uint16_t) 0x0000U) /* Reset value */
#define CEC_OWN_ADDRESS_0 ((uint16_t) 0x0001U) /* Logical Address 0 */
#define CEC_OWN_ADDRESS_1 ((uint16_t) 0x0002U) /* Logical Address 1 */
#define CEC_OWN_ADDRESS_2 ((uint16_t) 0x0004U) /* Logical Address 2 */
#define CEC_OWN_ADDRESS_3 ((uint16_t) 0x0008U) /* Logical Address 3 */
#define CEC_OWN_ADDRESS_4 ((uint16_t) 0x0010U) /* Logical Address 4 */
#define CEC_OWN_ADDRESS_5 ((uint16_t) 0x0020U) /* Logical Address 5 */
#define CEC_OWN_ADDRESS_6 ((uint16_t) 0x0040U) /* Logical Address 6 */
#define CEC_OWN_ADDRESS_7 ((uint16_t) 0x0080U) /* Logical Address 7 */
#define CEC_OWN_ADDRESS_8 ((uint16_t) 0x0100U) /* Logical Address 9 */
#define CEC_OWN_ADDRESS_9 ((uint16_t) 0x0200U) /* Logical Address 10 */
#define CEC_OWN_ADDRESS_10 ((uint16_t) 0x0400U) /* Logical Address 11 */
#define CEC_OWN_ADDRESS_11 ((uint16_t) 0x0800U) /* Logical Address 12 */
#define CEC_OWN_ADDRESS_12 ((uint16_t) 0x1000U) /* Logical Address 13 */
#define CEC_OWN_ADDRESS_13 ((uint16_t) 0x2000U) /* Logical Address 14 */
#define CEC_OWN_ADDRESS_14 ((uint16_t) 0x4000U) /* Logical Address 15 */
/**
* @}
*/
/** @defgroup CEC_Interrupts_Definitions CEC Interrupts definition
* @{
*/
@ -358,11 +426,14 @@ typedef struct
* @{
*/
/** @brief Reset CEC handle state
/** @brief Reset CEC handle gstate & RxState
* @param __HANDLE__: CEC handle.
* @retval None
*/
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CEC_STATE_RESET)
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->gState = HAL_CEC_STATE_RESET; \
(__HANDLE__)->RxState = HAL_CEC_STATE_RESET; \
} while(0)
/** @brief Checks whether or not the specified CEC interrupt flag is set.
* @param __HANDLE__: specifies the CEC Handle.
@ -534,6 +605,7 @@ typedef struct
/* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress);
void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec);
void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
/**
@ -544,14 +616,12 @@ void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec);
* @{
*/
/* I/O operation functions ***************************************************/
HAL_StatusTypeDef HAL_CEC_Transmit(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_CEC_Receive(CEC_HandleTypeDef *hcec, uint8_t *pData, uint32_t Timeout);
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
HAL_StatusTypeDef HAL_CEC_Receive_IT(CEC_HandleTypeDef *hcec, uint8_t *pData);
uint32_t HAL_CEC_GetReceivedFrameSize(CEC_HandleTypeDef *hcec);
HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t InitiatorAddress,uint8_t DestinationAddress, uint8_t *pData, uint32_t Size);
uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec);
void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer);
void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec);
void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec);
void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize);
void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec);
/**
* @}
@ -625,20 +695,6 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
#define IS_CEC_LISTENING_MODE(__MODE__) (((__MODE__) == CEC_REDUCED_LISTENING_MODE) || \
((__MODE__) == CEC_FULL_LISTENING_MODE))
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__: CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OAR_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x07FFF)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__: CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
/** @brief Check CEC message size.
* The message size is the payload size: without counting the header,
@ -647,12 +703,24 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
* @param __SIZE__: CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0xF)
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
* @param __ADDRESS__: CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
* @param __ADDRESS__: CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
/**
* @}
*/
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup CEC_Private_Functions CEC Private Functions
* @{

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief CORTEX HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the CORTEX:
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

144
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cortex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_cortex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CORTEX HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -105,15 +105,15 @@ typedef struct
/** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group
* @{
*/
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
#define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007U) /*!< 0 bits for pre-emption priority
4 bits for subpriority */
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
#define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006U) /*!< 1 bits for pre-emption priority
3 bits for subpriority */
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
#define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005U) /*!< 2 bits for pre-emption priority
2 bits for subpriority */
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
#define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004U) /*!< 3 bits for pre-emption priority
1 bits for subpriority */
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
#define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003U) /*!< 4 bits for pre-emption priority
0 bits for subpriority */
/**
* @}
@ -122,8 +122,8 @@ typedef struct
/** @defgroup CORTEX_SysTick_clock_source CORTEX _SysTick clock source
* @{
*/
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004)
#define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000U)
#define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004U)
/**
* @}
@ -133,10 +133,10 @@ typedef struct
/** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control
* @{
*/
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006)
#define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000U)
#define MPU_HARDFAULT_NMI ((uint32_t)0x00000002U)
#define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004U)
#define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006U)
/**
* @}
*/
@ -144,8 +144,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable
* @{
*/
#define MPU_REGION_ENABLE ((uint8_t)0x01)
#define MPU_REGION_DISABLE ((uint8_t)0x00)
#define MPU_REGION_ENABLE ((uint8_t)0x01U)
#define MPU_REGION_DISABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -153,8 +153,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access
* @{
*/
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01)
#define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00U)
#define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01U)
/**
* @}
*/
@ -162,8 +162,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable
* @{
*/
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00)
#define MPU_ACCESS_SHAREABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -171,8 +171,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable
* @{
*/
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00)
#define MPU_ACCESS_CACHEABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -180,8 +180,8 @@ typedef struct
/** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable
* @{
*/
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00)
#define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01U)
#define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00U)
/**
* @}
*/
@ -189,9 +189,9 @@ typedef struct
/** @defgroup CORTEX_MPU_TEX_Levels MPU TEX Levels
* @{
*/
#define MPU_TEX_LEVEL0 ((uint8_t)0x00)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02)
#define MPU_TEX_LEVEL0 ((uint8_t)0x00U)
#define MPU_TEX_LEVEL1 ((uint8_t)0x01U)
#define MPU_TEX_LEVEL2 ((uint8_t)0x02U)
/**
* @}
*/
@ -199,34 +199,34 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size
* @{
*/
#define MPU_REGION_SIZE_32B ((uint8_t)0x04)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0A)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0B)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0C)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0D)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0E)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0F)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1A)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1B)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1C)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1D)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1E)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1F)
#define MPU_REGION_SIZE_32B ((uint8_t)0x04U)
#define MPU_REGION_SIZE_64B ((uint8_t)0x05U)
#define MPU_REGION_SIZE_128B ((uint8_t)0x06U)
#define MPU_REGION_SIZE_256B ((uint8_t)0x07U)
#define MPU_REGION_SIZE_512B ((uint8_t)0x08U)
#define MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
#define MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
#define MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
#define MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
#define MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
#define MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
#define MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
#define MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
#define MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
#define MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
#define MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
#define MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
#define MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
#define MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
#define MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
#define MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
#define MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
#define MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
#define MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
#define MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
#define MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
#define MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
#define MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
/**
* @}
*/
@ -234,12 +234,12 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes
* @{
*/
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06)
#define MPU_REGION_NO_ACCESS ((uint8_t)0x00U)
#define MPU_REGION_PRIV_RW ((uint8_t)0x01U)
#define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02U)
#define MPU_REGION_FULL_ACCESS ((uint8_t)0x03U)
#define MPU_REGION_PRIV_RO ((uint8_t)0x05U)
#define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06U)
/**
* @}
*/
@ -247,14 +247,14 @@ typedef struct
/** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number
* @{
*/
#define MPU_REGION_NUMBER0 ((uint8_t)0x00)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07)
#define MPU_REGION_NUMBER0 ((uint8_t)0x00U)
#define MPU_REGION_NUMBER1 ((uint8_t)0x01U)
#define MPU_REGION_NUMBER2 ((uint8_t)0x02U)
#define MPU_REGION_NUMBER3 ((uint8_t)0x03U)
#define MPU_REGION_NUMBER4 ((uint8_t)0x04U)
#define MPU_REGION_NUMBER5 ((uint8_t)0x05U)
#define MPU_REGION_NUMBER6 ((uint8_t)0x06U)
#define MPU_REGION_NUMBER7 ((uint8_t)0x07U)
/**
* @}
*/
@ -323,9 +323,9 @@ void HAL_SYSTICK_Callback(void);
((GROUP) == NVIC_PRIORITYGROUP_3) || \
((GROUP) == NVIC_PRIORITYGROUP_4))
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10U)
#define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00)
@ -397,7 +397,7 @@ void HAL_SYSTICK_Callback(void);
((SIZE) == MPU_REGION_SIZE_2GB) || \
((SIZE) == MPU_REGION_SIZE_4GB))
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF)
#define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU)
#endif /* __MPU_PRESENT */
/**

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief CRC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@ -37,7 +37,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -432,11 +432,11 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
}
if(BufferLength%4 == 2)
{
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
}
if(BufferLength%4 == 3)
{
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)(((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
*(__IO uint16_t*) (&hcrc->Instance->DR) = (uint16_t)((uint16_t)((uint16_t)(pBuffer[4*i])<<8) | (uint16_t)(pBuffer[4*i+1]));
*(__IO uint8_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
}
}

46
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_crc.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CRC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -65,11 +65,11 @@
*/
typedef enum
{
HAL_CRC_STATE_RESET = 0x00, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04 /*!< CRC error state */
HAL_CRC_STATE_RESET = 0x00U, /*!< CRC not yet initialized or disabled */
HAL_CRC_STATE_READY = 0x01U, /*!< CRC initialized and ready for use */
HAL_CRC_STATE_BUSY = 0x02U, /*!< CRC internal process is ongoing */
HAL_CRC_STATE_TIMEOUT = 0x03U, /*!< CRC timeout state */
HAL_CRC_STATE_ERROR = 0x04U /*!< CRC error state */
}HAL_CRC_StateTypeDef;
/**
* @}
@ -159,7 +159,7 @@ typedef struct
/** @defgroup CRC_Default_Polynomial_Value Default CRC generating polynomial
* @{
*/
#define DEFAULT_CRC32_POLY 0x04C11DB7
#define DEFAULT_CRC32_POLY 0x04C11DB7U
/**
* @}
@ -168,7 +168,7 @@ typedef struct
/** @defgroup CRC_Default_InitValue Default CRC computation initialization value
* @{
*/
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFF
#define DEFAULT_CRC_INITVALUE 0xFFFFFFFFU
/**
* @}
@ -177,8 +177,8 @@ typedef struct
/** @defgroup CRC_Default_Polynomial Indicates whether or not default polynomial is used
* @{
*/
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01)
#define DEFAULT_POLYNOMIAL_ENABLE ((uint8_t)0x00U)
#define DEFAULT_POLYNOMIAL_DISABLE ((uint8_t)0x01U)
/**
@ -188,8 +188,8 @@ typedef struct
/** @defgroup CRC_Default_InitValue_Use Indicates whether or not default init value is used
* @{
*/
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00)
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01)
#define DEFAULT_INIT_VALUE_ENABLE ((uint8_t)0x00U)
#define DEFAULT_INIT_VALUE_DISABLE ((uint8_t)0x01U)
/**
* @}
@ -198,7 +198,7 @@ typedef struct
/** @defgroup CRC_Polynomial_Sizes Polynomial sizes to configure the IP
* @{
*/
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000)
#define CRC_POLYLENGTH_32B ((uint32_t)0x00000000U)
#define CRC_POLYLENGTH_16B ((uint32_t)CRC_CR_POLYSIZE_0)
#define CRC_POLYLENGTH_8B ((uint32_t)CRC_CR_POLYSIZE_1)
#define CRC_POLYLENGTH_7B ((uint32_t)CRC_CR_POLYSIZE)
@ -209,10 +209,10 @@ typedef struct
/** @defgroup CRC_Polynomial_Size_Definitions CRC polynomial possible sizes actual definitions
* @{
*/
#define HAL_CRC_LENGTH_32B 32
#define HAL_CRC_LENGTH_16B 16
#define HAL_CRC_LENGTH_8B 8
#define HAL_CRC_LENGTH_7B 7
#define HAL_CRC_LENGTH_32B 32U
#define HAL_CRC_LENGTH_16B 16U
#define HAL_CRC_LENGTH_8B 8U
#define HAL_CRC_LENGTH_7B 7U
/**
* @}
@ -225,10 +225,10 @@ typedef struct
* an error is triggered in HAL_CRC_Init() if InputDataFormat field is set
* to CRC_INPUT_FORMAT_UNDEFINED: the format MUST be defined by the user for
* the CRC APIs to provide a correct result */
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000)
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001)
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002)
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003)
#define CRC_INPUTDATA_FORMAT_UNDEFINED ((uint32_t)0x00000000U)
#define CRC_INPUTDATA_FORMAT_BYTES ((uint32_t)0x00000001U)
#define CRC_INPUTDATA_FORMAT_HALFWORDS ((uint32_t)0x00000002U)
#define CRC_INPUTDATA_FORMAT_WORDS ((uint32_t)0x00000003U)
/**
* @}
*/

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Extended CRC HAL module driver.
*
* This file provides firmware functions to manage the following
@ -23,7 +23,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_crc_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,7 +64,7 @@
/** @defgroup CRCEx_Input_Data_Inversion CRC Extended input data inversion modes
* @{
*/
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000)
#define CRC_INPUTDATA_INVERSION_NONE ((uint32_t)0x00000000U)
#define CRC_INPUTDATA_INVERSION_BYTE ((uint32_t)CRC_CR_REV_IN_0)
#define CRC_INPUTDATA_INVERSION_HALFWORD ((uint32_t)CRC_CR_REV_IN_1)
#define CRC_INPUTDATA_INVERSION_WORD ((uint32_t)CRC_CR_REV_IN)
@ -80,7 +80,7 @@
/** @defgroup CRCEx_Output_Data_Inversion CRC Extended output data inversion modes
* @{
*/
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000)
#define CRC_OUTPUTDATA_INVERSION_DISABLE ((uint32_t)0x00000000U)
#define CRC_OUTPUTDATA_INVERSION_ENABLE ((uint32_t)CRC_CR_REV_OUT)
#define IS_CRC_OUTPUTDATA_INVERSION_MODE(__MODE__) (((__MODE__) == CRC_OUTPUTDATA_INVERSION_DISABLE) || \

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief CRYP HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Cryptography (CRYP) peripheral:
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -103,7 +103,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined (STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup CRYP CRYP
* @brief CRYP HAL module driver.
* @{
@ -3815,7 +3815,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
/**
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

78
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined (STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -105,11 +105,11 @@ typedef struct
typedef enum
{
HAL_CRYP_STATE_RESET = 0x00, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03, /*!< CRYP timeout state */
HAL_CRYP_STATE_ERROR = 0x04 /*!< CRYP error state */
HAL_CRYP_STATE_RESET = 0x00U, /*!< CRYP not yet initialized or disabled */
HAL_CRYP_STATE_READY = 0x01U, /*!< CRYP initialized and ready for use */
HAL_CRYP_STATE_BUSY = 0x02U, /*!< CRYP internal processing is ongoing */
HAL_CRYP_STATE_TIMEOUT = 0x03U, /*!< CRYP timeout state */
HAL_CRYP_STATE_ERROR = 0x04U /*!< CRYP error state */
}HAL_CRYP_STATETypeDef;
/**
@ -123,9 +123,9 @@ typedef enum
typedef enum
{
HAL_CRYP_PHASE_READY = 0x01, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02, /*!< CRYP peripheral is in processing phase */
HAL_CRYP_PHASE_FINAL = 0x03 /*!< CRYP peripheral is in final phase
HAL_CRYP_PHASE_READY = 0x01U, /*!< CRYP peripheral is ready for initialization. */
HAL_CRYP_PHASE_PROCESS = 0x02U, /*!< CRYP peripheral is in processing phase */
HAL_CRYP_PHASE_FINAL = 0x03U /*!< CRYP peripheral is in final phase
This is relevant only with CCM and GCM modes */
}HAL_PhaseTypeDef;
@ -147,7 +147,7 @@ typedef struct
uint8_t *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
__IO uint16_t CrypInCount; /*!< Counter of inputed data */
__IO uint16_t CrypInCount; /*!< Counter of input data */
__IO uint16_t CrypOutCount; /*!< Counter of output data */
@ -180,7 +180,7 @@ typedef struct
/** @defgroup CRYP_Key_Size CRYP Key Size
* @{
*/
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000)
#define CRYP_KEYSIZE_128B ((uint32_t)0x00000000U)
#define CRYP_KEYSIZE_192B CRYP_CR_KEYSIZE_0
#define CRYP_KEYSIZE_256B CRYP_CR_KEYSIZE_1
/**
@ -190,7 +190,7 @@ typedef struct
/** @defgroup CRYP_Data_Type CRYP Data Type
* @{
*/
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000)
#define CRYP_DATATYPE_32B ((uint32_t)0x00000000U)
#define CRYP_DATATYPE_16B CRYP_CR_DATATYPE_0
#define CRYP_DATATYPE_8B CRYP_CR_DATATYPE_1
#define CRYP_DATATYPE_1B CRYP_CR_DATATYPE
@ -201,21 +201,21 @@ typedef struct
/** @defgroup CRYP_Exported_Constants_Group3 CRYP CRYP_AlgoModeDirection
* @{
*/
#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003C)
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000)
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004)
#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008)
#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000C)
#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010)
#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014)
#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018)
#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001C)
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020)
#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024)
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028)
#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002C)
#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030)
#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034)
#define CRYP_CR_ALGOMODE_DIRECTION ((uint32_t)0x0008003CU)
#define CRYP_CR_ALGOMODE_TDES_ECB_ENCRYPT ((uint32_t)0x00000000U)
#define CRYP_CR_ALGOMODE_TDES_ECB_DECRYPT ((uint32_t)0x00000004U)
#define CRYP_CR_ALGOMODE_TDES_CBC_ENCRYPT ((uint32_t)0x00000008U)
#define CRYP_CR_ALGOMODE_TDES_CBC_DECRYPT ((uint32_t)0x0000000CU)
#define CRYP_CR_ALGOMODE_DES_ECB_ENCRYPT ((uint32_t)0x00000010U)
#define CRYP_CR_ALGOMODE_DES_ECB_DECRYPT ((uint32_t)0x00000014U)
#define CRYP_CR_ALGOMODE_DES_CBC_ENCRYPT ((uint32_t)0x00000018U)
#define CRYP_CR_ALGOMODE_DES_CBC_DECRYPT ((uint32_t)0x0000001CU)
#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT ((uint32_t)0x00000020U)
#define CRYP_CR_ALGOMODE_AES_ECB_DECRYPT ((uint32_t)0x00000024U)
#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT ((uint32_t)0x00000028U)
#define CRYP_CR_ALGOMODE_AES_CBC_DECRYPT ((uint32_t)0x0000002CU)
#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT ((uint32_t)0x00000030U)
#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT ((uint32_t)0x00000034U)
/**
* @}
*/
@ -232,17 +232,17 @@ typedef struct
/** @defgroup CRYP_Exported_Constants_Group5 CRYP CRYP_Flags
* @{
*/
#define CRYP_FLAG_BUSY ((uint32_t)0x00000010) /*!< The CRYP core is currently
#define CRYP_FLAG_BUSY ((uint32_t)0x00000010U) /*!< The CRYP core is currently
processing a block of data
or a key preparation (for
AES decryption). */
#define CRYP_FLAG_IFEM ((uint32_t)0x00000001) /*!< Input FIFO is empty */
#define CRYP_FLAG_IFNF ((uint32_t)0x00000002) /*!< Input FIFO is not Full */
#define CRYP_FLAG_OFNE ((uint32_t)0x00000004) /*!< Output FIFO is not empty */
#define CRYP_FLAG_OFFU ((uint32_t)0x00000008) /*!< Output FIFO is Full */
#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002) /*!< Output FIFO service raw
#define CRYP_FLAG_IFEM ((uint32_t)0x00000001U) /*!< Input FIFO is empty */
#define CRYP_FLAG_IFNF ((uint32_t)0x00000002U) /*!< Input FIFO is not Full */
#define CRYP_FLAG_OFNE ((uint32_t)0x00000004U) /*!< Output FIFO is not empty */
#define CRYP_FLAG_OFFU ((uint32_t)0x00000008U) /*!< Output FIFO is Full */
#define CRYP_FLAG_OUTRIS ((uint32_t)0x01000002U) /*!< Output FIFO service raw
interrupt status */
#define CRYP_FLAG_INRIS ((uint32_t)0x01000001) /*!< Input FIFO service raw
#define CRYP_FLAG_INRIS ((uint32_t)0x01000001U) /*!< Input FIFO service raw
interrupt status */
/**
* @}
@ -301,7 +301,7 @@ typedef struct
* @retval The new state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
#define __HAL_CRYP_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 24)) == 0x01U)?((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)): \
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
@ -521,7 +521,7 @@ HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}

98
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Extended CRYP HAL module driver
* This file provides firmware functions to manage the following
* functionalities of CRYP extension peripheral:
@ -69,7 +69,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -102,7 +102,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined (STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup CRYPEx CRYPEx
* @brief CRYP Extension HAL module driver.
* @{
@ -534,10 +534,10 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
hcryp->Init.pScratch[bufferidx++] = 0xFF;
hcryp->Init.pScratch[bufferidx++] = 0xFE;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
headersize += 6;
}
/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
@ -1173,19 +1173,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *
/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(headersize < 65280)
{
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
headersize += 2;
}
else
{
/* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
hcryp->Init.pScratch[bufferidx++] = 0xFF;
hcryp->Init.pScratch[bufferidx++] = 0xFE;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
hcryp->Init.pScratch[bufferidx++] = 0xFFU;
hcryp->Init.pScratch[bufferidx++] = 0xFEU;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
headersize += 6;
}
/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
@ -1585,19 +1585,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(headersize < 65280)
{
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
headersize += 2;
}
else
{
/* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
hcryp->Init.pScratch[bufferidx++] = 0xFF;
hcryp->Init.pScratch[bufferidx++] = 0xFE;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
hcryp->Init.pScratch[bufferidx++] = 0xFFU;
hcryp->Init.pScratch[bufferidx++] = 0xFEU;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
headersize += 6;
}
/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
@ -2031,19 +2031,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_
/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(headersize < 65280)
{
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
headersize += 2;
}
else
{
/* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
hcryp->Init.pScratch[bufferidx++] = 0xFF;
hcryp->Init.pScratch[bufferidx++] = 0xFE;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
hcryp->Init.pScratch[bufferidx++] = 0xFFU;
hcryp->Init.pScratch[bufferidx++] = 0xFEU;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
headersize += 6;
}
/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
@ -2424,19 +2424,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(headersize < 65280)
{
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
headersize += 2;
}
else
{
/* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
hcryp->Init.pScratch[bufferidx++] = 0xFF;
hcryp->Init.pScratch[bufferidx++] = 0xFE;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
hcryp->Init.pScratch[bufferidx++] = 0xFFU;
hcryp->Init.pScratch[bufferidx++] = 0xFEU;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
headersize += 6;
}
/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
@ -2768,19 +2768,19 @@ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8
/* Check that the associated data (or header) length is lower than 2^16 - 2^8 = 65536 - 256 = 65280 */
if(headersize < 65280)
{
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFF);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize >> 8) & 0xFFU);
hcryp->Init.pScratch[bufferidx++] = (uint8_t) ((headersize) & 0xFFU);
headersize += 2;
}
else
{
/* Header is encoded as 0xff || 0xfe || [headersize]32, i.e., six octets */
hcryp->Init.pScratch[bufferidx++] = 0xFF;
hcryp->Init.pScratch[bufferidx++] = 0xFE;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ff;
hcryp->Init.pScratch[bufferidx++] = 0xFFU;
hcryp->Init.pScratch[bufferidx++] = 0xFEU;
hcryp->Init.pScratch[bufferidx++] = headersize & 0xff000000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x00ff0000U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x0000ff00U;
hcryp->Init.pScratch[bufferidx++] = headersize & 0x000000ffU;
headersize += 6;
}
/* Copy the header buffer in internal buffer "hcryp->Init.pScratch" */
@ -3032,7 +3032,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp)
/**
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

20
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_cryp_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined (STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -65,10 +65,10 @@
/** @defgroup CRYPEx_Exported_Constants_Group1 CRYP AlgoModeDirection
* @{
*/
#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000)
#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004)
#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008)
#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000C)
#define CRYP_CR_ALGOMODE_AES_GCM_ENCRYPT ((uint32_t)0x00080000U)
#define CRYP_CR_ALGOMODE_AES_GCM_DECRYPT ((uint32_t)0x00080004U)
#define CRYP_CR_ALGOMODE_AES_CCM_ENCRYPT ((uint32_t)0x00080008U)
#define CRYP_CR_ALGOMODE_AES_CCM_DECRYPT ((uint32_t)0x0008000CU)
/**
* @}
*/
@ -77,7 +77,7 @@
* @brief The phases are relevant only to AES-GCM and AES-CCM
* @{
*/
#define CRYP_PHASE_INIT ((uint32_t)0x00000000)
#define CRYP_PHASE_INIT ((uint32_t)0x00000000U)
#define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0
#define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1
#define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH
@ -206,7 +206,7 @@ void HAL_CRYPEx_GCMCCM_IRQHandler(CRYP_HandleTypeDef *hcryp);
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Digital to Analog Converter (DAC) peripheral:
@ -143,7 +143,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

46
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,11 +64,11 @@
*/
typedef enum
{
HAL_DAC_STATE_RESET = 0x00, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04 /*!< DAC error state */
HAL_DAC_STATE_RESET = 0x00U, /*!< DAC not yet initialized or disabled */
HAL_DAC_STATE_READY = 0x01U, /*!< DAC initialized and ready for use */
HAL_DAC_STATE_BUSY = 0x02U, /*!< DAC internal processing is ongoing */
HAL_DAC_STATE_TIMEOUT = 0x03U, /*!< DAC timeout state */
HAL_DAC_STATE_ERROR = 0x04U /*!< DAC error state */
}HAL_DAC_StateTypeDef;
/**
@ -113,10 +113,10 @@ typedef struct
/** @defgroup DAC_Error_Code DAC Error Code
* @{
*/
#define HAL_DAC_ERROR_NONE 0x00 /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01 /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02 /*!< DAC channel2 DAM underrun error */
#define HAL_DAC_ERROR_DMA 0x04 /*!< DMA error */
#define HAL_DAC_ERROR_NONE 0x00U /*!< No error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH1 0x01U /*!< DAC channel1 DAM underrun error */
#define HAL_DAC_ERROR_DMAUNDERRUNCH2 0x02U /*!< DAC channel2 DAM underrun error */
#define HAL_DAC_ERROR_DMA 0x04U /*!< DMA error */
/**
* @}
*/
@ -125,7 +125,7 @@ typedef struct
* @{
*/
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
#define DAC_TRIGGER_NONE ((uint32_t)0x00000000U) /*!< Conversion is automatic once the DAC1_DHRxxxx register
has been loaded, and not by external trigger */
#define DAC_TRIGGER_T2_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
#define DAC_TRIGGER_T4_TRGO ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
@ -143,7 +143,7 @@ typedef struct
/** @defgroup DAC_output_buffer DAC Output Buffer
* @{
*/
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000)
#define DAC_OUTPUTBUFFER_ENABLE ((uint32_t)0x00000000U)
#define DAC_OUTPUTBUFFER_DISABLE ((uint32_t)DAC_CR_BOFF1)
/**
* @}
@ -152,8 +152,8 @@ typedef struct
/** @defgroup DAC_Channel_selection DAC Channel Selection
* @{
*/
#define DAC_CHANNEL_1 ((uint32_t)0x00000000)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010)
#define DAC_CHANNEL_1 ((uint32_t)0x00000000U)
#define DAC_CHANNEL_2 ((uint32_t)0x00000010U)
/**
* @}
*/
@ -161,9 +161,9 @@ typedef struct
/** @defgroup DAC_data_alignment DAC Data Alignment
* @{
*/
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008)
#define DAC_ALIGN_12B_R ((uint32_t)0x00000000U)
#define DAC_ALIGN_12B_L ((uint32_t)0x00000004U)
#define DAC_ALIGN_8B_R ((uint32_t)0x00000008U)
/**
* @}
*/
@ -342,7 +342,7 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
/** @defgroup DAC_Private_Macros DAC Private Macros
* @{
*/
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0U)
#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
((ALIGN) == DAC_ALIGN_12B_L) || \
((ALIGN) == DAC_ALIGN_8B_R))
@ -365,19 +365,19 @@ void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008) + (__ALIGNMENT__))
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014) + (__ALIGNMENT__))
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
* @param __ALIGNMENT__: specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020) + (__ALIGNMENT__))
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
/**
* @}

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dac_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Extended DAC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DAC extension peripheral:
@ -25,7 +25,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dac_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DAC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -63,7 +63,7 @@
/** @defgroup DACEx_lfsrunmask_triangleamplitude DAC LFS Run Mask Triangle Amplitude
* @{
*/
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BIT0 ((uint32_t)0x00000000U) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
#define DAC_LFSRUNMASK_BITS1_0 ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS2_0 ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS3_0 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
@ -75,7 +75,7 @@
#define DAC_LFSRUNMASK_BITS9_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS10_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
#define DAC_LFSRUNMASK_BITS11_0 ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_1 ((uint32_t)0x00000000U) /*!< Select max triangle amplitude of 1 */
#define DAC_TRIANGLEAMPLITUDE_3 ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
#define DAC_TRIANGLEAMPLITUDE_7 ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
#define DAC_TRIANGLEAMPLITUDE_15 ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */

414
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@ -63,7 +63,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -105,11 +105,19 @@
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* 1s */
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */
#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */
#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma);
static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
/* Exported functions --------------------------------------------------------*/
@ -140,7 +148,7 @@ static void DCMI_DMAError(DMA_HandleTypeDef *hdma);
* the configuration information for DCMI.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if(hdcmi == NULL)
@ -150,60 +158,51 @@ __weak HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
/* Check function parameters */
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hdcmi->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_DCMI_MspInit(hdcmi);
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
DCMI_CR_LSM | DCMI_CR_OELS);
/* Set DCMI parameters */
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |
DCMI_CR_ESS);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate | \
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity | \
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode | \
hdcmi->Init.JPEGMode);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
hdcmi->Init.LineSelectStart);
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
}
/* Enable the Line interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
/* Enable the VSYNC interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
/* Enable the Frame capture complete interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Enable the Synchronization error interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
/* Enable the Overflow interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
/* Enable DCMI by setting DCMIEN bit */
__HAL_DCMI_ENABLE(hdcmi);
/* Enable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
@ -310,23 +309,30 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Process Locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Check the parameters */
assert_param(IS_DCMI_CAPTURE_MODE(DCMI_Mode));
/* Enable DCMI by setting DCMIEN bit */
__HAL_DCMI_ENABLE(hdcmi);
/* Configure the DCMI Mode */
hdcmi->Instance->CR &= ~(DCMI_CR_CM);
hdcmi->Instance->CR |= (uint32_t)(DCMI_Mode);
/* Set the DMA memory0 conversion complete callback */
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAConvCplt;
hdcmi->DMA_Handle->XferCpltCallback = DCMI_DMAXferCplt;
/* Set the DMA error callback */
hdcmi->DMA_Handle->XferErrorCallback = DCMI_DMAError;
/* Set the dma abort callback */
hdcmi->DMA_Handle->XferAbortCallback = NULL;
/* Reset transfer counters value */
hdcmi->XferCount = 0;
hdcmi->XferTransferNumber = 0;
if(Length <= 0xFFFF)
{
/* Enable the DMA Stream */
@ -335,7 +341,7 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
else /* DCMI_DOUBLE_BUFFER Mode */
{
/* Set the DMA memory1 conversion complete callback */
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAConvCplt;
hdcmi->DMA_Handle->XferM1CpltCallback = DCMI_DMAXferCplt;
/* Initialize transfer parameters */
hdcmi->XferCount = 1;
@ -359,9 +365,12 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
/* Start DMA multi buffer transfer */
HAL_DMAEx_MultiBufferStart_IT(hdcmi->DMA_Handle, (uint32_t)&hdcmi->Instance->DR, (uint32_t)pData, SecondMemAddress, hdcmi->XferSize);
}
/* Enable Capture */
DCMI->CR |= DCMI_CR_CAPTURE;
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
/* Release Lock */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return HAL_OK;
@ -375,36 +384,34 @@ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mo
*/
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
{
uint32_t tickstart = 0;
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
/* Lock the DCMI peripheral state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
__HAL_DCMI_DISABLE(hdcmi);
/* Disable Capture */
DCMI->CR &= ~(DCMI_CR_CAPTURE);
/* Get tick */
tickstart = HAL_GetTick();
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
/* Check if the DCMI capture effectively disabled */
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0)
do
{
if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DCMI_STOP)
if (count-- == 0)
{
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
status = HAL_TIMEOUT;
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
/* Disable the DCMI */
__HAL_DCMI_DISABLE(hdcmi);
/* Disable the DMA */
HAL_DMA_Abort(hdcmi->DMA_Handle);
@ -418,6 +425,78 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return status;
}
/**
* @brief Suspend DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi)
{
register uint32_t count = HAL_TIMEOUT_DCMI_STOP * (SystemCoreClock /8/1000);
HAL_StatusTypeDef status = HAL_OK;
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_BUSY)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_SUSPENDED;
/* Disable Capture */
hdcmi->Instance->CR &= ~(DCMI_CR_CAPTURE);
/* Check if the DCMI capture effectively disabled */
do
{
if (count-- == 0)
{
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_TIMEOUT;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_READY;
status = HAL_TIMEOUT;
break;
}
}
while((hdcmi->Instance->CR & DCMI_CR_CAPTURE) != 0);
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return status;
}
/**
* @brief Resume DCMI capture
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi)
{
/* Process locked */
__HAL_LOCK(hdcmi);
if(hdcmi->State == HAL_DCMI_STATE_SUSPENDED)
{
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable Capture */
hdcmi->Instance->CR |= DCMI_CR_CAPTURE;
}
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Return function status */
return HAL_OK;
}
@ -430,110 +509,80 @@ HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi)
*/
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi)
{
uint32_t isr_value = READ_REG(hdcmi->Instance->MISR);
/* Synchronization error interrupt management *******************************/
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_ERRRI) != RESET)
if((isr_value & DCMI_FLAG_ERRRI) == DCMI_FLAG_ERRRI)
{
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_ERR) != RESET)
{
/* Disable the Synchronization error interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_ERR);
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Abort the DMA Transfer */
HAL_DMA_Abort(hdcmi->DMA_Handle);
/* Synchronization error Callback */
HAL_DCMI_ErrorCallback(hdcmi);
}
/* Clear the Synchronization error flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_ERRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_SYNC;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Set the synchronization error callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Overflow interrupt management ********************************************/
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_OVFRI) != RESET)
if((isr_value & DCMI_FLAG_OVRRI) == DCMI_FLAG_OVRRI)
{
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_OVF) != RESET)
{
/* Disable the Overflow interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_OVF);
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVFRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVF;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Abort the DMA Transfer */
HAL_DMA_Abort(hdcmi->DMA_Handle);
/* Overflow Callback */
HAL_DCMI_ErrorCallback(hdcmi);
}
/* Clear the Overflow flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_OVRRI);
/* Update error code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_OVR;
/* Change DCMI state */
hdcmi->State = HAL_DCMI_STATE_ERROR;
/* Set the overflow callback */
hdcmi->DMA_Handle->XferAbortCallback = DCMI_DMAError;
/* Abort the DMA Transfer */
HAL_DMA_Abort_IT(hdcmi->DMA_Handle);
}
/* Line Interrupt management ************************************************/
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_LINERI) != RESET)
if((isr_value & DCMI_FLAG_LINERI) == DCMI_FLAG_LINERI)
{
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_LINE) != RESET)
{
/* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* Line interrupt Callback */
HAL_DCMI_LineEventCallback(hdcmi);
}
/* Clear the Line interrupt flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_LINERI);
/* Line interrupt Callback */
HAL_DCMI_LineEventCallback(hdcmi);
}
/* VSYNC interrupt management ***********************************************/
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_VSYNCRI) != RESET)
if((isr_value & DCMI_FLAG_VSYNCRI) == DCMI_FLAG_VSYNCRI)
{
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_VSYNC) != RESET)
{
/* Disable the VSYNC interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_VSYNC);
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* VSYNC Callback */
HAL_DCMI_VsyncEventCallback(hdcmi);
}
/* Clear the VSYNC flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_VSYNCRI);
/* VSYNC Callback */
HAL_DCMI_VsyncEventCallback(hdcmi);
}
/* End of Frame interrupt management ****************************************/
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
/* FRAME interrupt management ***********************************************/
if((isr_value & DCMI_FLAG_FRAMERI) == DCMI_FLAG_FRAMERI)
{
if(__HAL_DCMI_GET_IT_SOURCE(hdcmi, DCMI_IT_FRAME) != RESET)
{
/* Disable the End of Frame interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Clear the End of Frame flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* End of Frame Callback */
HAL_DCMI_FrameEventCallback(hdcmi);
/* When snapshot mode, disable Vsync, Error and Overrun interrupts */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
/* Disable the Line, Vsync, Error and Overrun interrupts */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_LINE | DCMI_IT_VSYNC | DCMI_IT_ERR | DCMI_IT_OVR);
}
/* Disable the Frame interrupt */
__HAL_DCMI_DISABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Clear the End of Frame flag */
__HAL_DCMI_CLEAR_FLAG(hdcmi, DCMI_FLAG_FRAMERI);
/* Frame Callback */
HAL_DCMI_FrameEventCallback(hdcmi);
}
}
@ -612,7 +661,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
[..] This section provides functions allowing to:
(+) Configure the CROP feature.
(+) Enable/Disable the CROP feature.
(+) Enable/Disable the JPEG feature.
(+) Set embedded synchronization delimiters unmasks.
@endverbatim
* @{
@ -628,7 +677,7 @@ __weak void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi)
* @param Y0: DCMI window Y offset
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
@ -643,8 +692,8 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
/* Configure CROP */
DCMI->CWSIZER = (XSize | (YSize << 16));
DCMI->CWSTRTR = (X0 | (Y0 << 16));
hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@ -661,7 +710,7 @@ HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, ui
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
@ -670,7 +719,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Disable DCMI Crop feature */
DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
hdcmi->Instance->CR &= ~(uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@ -687,7 +736,7 @@ HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi)
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi)
{
/* Process Locked */
__HAL_LOCK(hdcmi);
@ -696,7 +745,7 @@ HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi)
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Enable DCMI Crop feature */
DCMI->CR |= (uint32_t)DCMI_CR_CROP;
hdcmi->Instance->CR |= (uint32_t)DCMI_CR_CROP;
/* Change the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@ -762,12 +811,11 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi)
* the configuration information for the specified DMA module.
* @retval None
*/
static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
static void DCMI_DMAXferCplt(DMA_HandleTypeDef *hdma)
{
uint32_t tmp = 0;
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hdcmi->State= HAL_DCMI_STATE_READY;
if(hdcmi->XferCount != 0)
{
@ -800,14 +848,18 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
hdcmi->XferCount = hdcmi->XferTransferNumber;
}
if(__HAL_DCMI_GET_FLAG(hdcmi, DCMI_FLAG_FRAMERI) != RESET)
/* Check if the frame is transferred */
if(hdcmi->XferCount == hdcmi->XferTransferNumber)
{
/* Process Unlocked */
__HAL_UNLOCK(hdcmi);
/* FRAME Callback */
HAL_DCMI_FrameEventCallback(hdcmi);
}
/* Enable the Frame interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* When snapshot mode, set dcmi state to ready */
if((hdcmi->Instance->CR & DCMI_CR_CM) == DCMI_MODE_SNAPSHOT)
{
hdcmi->State= HAL_DCMI_STATE_READY;
}
}
}
/**
@ -818,9 +870,19 @@ static void DCMI_DMAConvCplt(DMA_HandleTypeDef *hdma)
*/
static void DCMI_DMAError(DMA_HandleTypeDef *hdma)
{
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
hdcmi->State= HAL_DCMI_STATE_READY;
HAL_DCMI_ErrorCallback(hdcmi);
DCMI_HandleTypeDef* hdcmi = ( DCMI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
if(hdcmi->DMA_Handle->ErrorCode != HAL_DMA_ERROR_FE)
{
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
/* Set DCMI Error Code */
hdcmi->ErrorCode |= HAL_DCMI_ERROR_DMA;
}
/* DCMI error Callback */
HAL_DCMI_ErrorCallback(hdcmi);
}
/**

240
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -45,11 +45,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/* Include DCMI HAL Extended module */
/* (include on top of file since DCMI structures are defined in extended file) */
#include "stm32f7xx_hal_dcmi_ex.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@ -68,13 +64,67 @@
*/
typedef enum
{
HAL_DCMI_STATE_RESET = 0x00, /*!< DCMI not yet initialized or disabled */
HAL_DCMI_STATE_READY = 0x01, /*!< DCMI initialized and ready for use */
HAL_DCMI_STATE_BUSY = 0x02, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04 /*!< DCMI error state */
HAL_DCMI_STATE_RESET = 0x00U, /*!< DCMI not yet initialized or disabled */
HAL_DCMI_STATE_READY = 0x01U, /*!< DCMI initialized and ready for use */
HAL_DCMI_STATE_BUSY = 0x02U, /*!< DCMI internal processing is ongoing */
HAL_DCMI_STATE_TIMEOUT = 0x03U, /*!< DCMI timeout state */
HAL_DCMI_STATE_ERROR = 0x04U, /*!< DCMI error state */
HAL_DCMI_STATE_SUSPENDED = 0x05U /*!< DCMI suspend state */
}HAL_DCMI_StateTypeDef;
/**
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
/**
* @brief DCMI Init structure definition
*/
typedef struct
{
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
This parameter can be a value of @ref DCMI_Synchronization_Mode */
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
This parameter can be a value of @ref DCMI_Capture_Rate */
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the line/frame start delimiter and the
line/frame end delimiter */
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_MODE_JPEG */
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
This parameter can be a value of @ref DCMI_Byte_Select_Mode */
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Byte_Select_Start */
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
This parameter can be a value of @ref DCMI_Line_Select_Mode */
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMI_Line_Select_Start */
}DCMI_InitTypeDef;
/**
* @brief DCMI handle Structure definition
*/
@ -113,10 +163,11 @@ typedef struct
/** @defgroup DCMI_Error_Code DCMI Error Code
* @{
*/
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DCMI_ERROR_OVF ((uint32_t)0x00000001) /*!< Overflow error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DCMI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DCMI_ERROR_OVR ((uint32_t)0x00000001U) /*!< Overrun error */
#define HAL_DCMI_ERROR_SYNC ((uint32_t)0x00000002U) /*!< Synchronization error */
#define HAL_DCMI_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_DCMI_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error */
/**
* @}
*/
@ -124,7 +175,7 @@ typedef struct
/** @defgroup DCMI_Capture_Mode DCMI Capture Mode
* @{
*/
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000) /*!< The received data are transferred continuously
#define DCMI_MODE_CONTINUOUS ((uint32_t)0x00000000U) /*!< The received data are transferred continuously
into the destination memory through the DMA */
#define DCMI_MODE_SNAPSHOT ((uint32_t)DCMI_CR_CM) /*!< Once activated, the interface waits for the start of
frame and then transfers a single frame through the DMA */
@ -135,7 +186,7 @@ typedef struct
/** @defgroup DCMI_Synchronization_Mode DCMI Synchronization Mode
* @{
*/
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000) /*!< Hardware synchronization data capture (frame/line start/stop)
#define DCMI_SYNCHRO_HARDWARE ((uint32_t)0x00000000U) /*!< Hardware synchronization data capture (frame/line start/stop)
is synchronized with the HSYNC/VSYNC signals */
#define DCMI_SYNCHRO_EMBEDDED ((uint32_t)DCMI_CR_ESS) /*!< Embedded synchronization data capture is synchronized with
synchronization codes embedded in the data flow */
@ -147,7 +198,7 @@ typedef struct
/** @defgroup DCMI_PIXCK_Polarity DCMI PIXCK Polarity
* @{
*/
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_FALLING ((uint32_t)0x00000000U) /*!< Pixel clock active on Falling edge */
#define DCMI_PCKPOLARITY_RISING ((uint32_t)DCMI_CR_PCKPOL) /*!< Pixel clock active on Rising edge */
/**
@ -157,7 +208,7 @@ typedef struct
/** @defgroup DCMI_VSYNC_Polarity DCMI VSYNC Polarity
* @{
*/
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Vertical synchronization active Low */
#define DCMI_VSPOLARITY_HIGH ((uint32_t)DCMI_CR_VSPOL) /*!< Vertical synchronization active High */
/**
@ -167,7 +218,7 @@ typedef struct
/** @defgroup DCMI_HSYNC_Polarity DCMI HSYNC Polarity
* @{
*/
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_LOW ((uint32_t)0x00000000U) /*!< Horizontal synchronization active Low */
#define DCMI_HSPOLARITY_HIGH ((uint32_t)DCMI_CR_HSPOL) /*!< Horizontal synchronization active High */
/**
@ -177,7 +228,7 @@ typedef struct
/** @defgroup DCMI_MODE_JPEG DCMI MODE JPEG
* @{
*/
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_DISABLE ((uint32_t)0x00000000U) /*!< Mode JPEG Disabled */
#define DCMI_JPEG_ENABLE ((uint32_t)DCMI_CR_JPEG) /*!< Mode JPEG Enabled */
/**
@ -187,7 +238,7 @@ typedef struct
/** @defgroup DCMI_Capture_Rate DCMI Capture Rate
* @{
*/
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000) /*!< All frames are captured */
#define DCMI_CR_ALL_FRAME ((uint32_t)0x00000000U) /*!< All frames are captured */
#define DCMI_CR_ALTERNATE_2_FRAME ((uint32_t)DCMI_CR_FCRC_0) /*!< Every alternate frame captured */
#define DCMI_CR_ALTERNATE_4_FRAME ((uint32_t)DCMI_CR_FCRC_1) /*!< One frame in 4 frames captured */
@ -198,7 +249,7 @@ typedef struct
/** @defgroup DCMI_Extended_Data_Mode DCMI Extended Data Mode
* @{
*/
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_8B ((uint32_t)0x00000000U) /*!< Interface captures 8-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_10B ((uint32_t)DCMI_CR_EDM_0) /*!< Interface captures 10-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_12B ((uint32_t)DCMI_CR_EDM_1) /*!< Interface captures 12-bit data on every pixel clock */
#define DCMI_EXTEND_DATA_14B ((uint32_t)(DCMI_CR_EDM_0 | DCMI_CR_EDM_1)) /*!< Interface captures 14-bit data on every pixel clock */
@ -210,7 +261,7 @@ typedef struct
/** @defgroup DCMI_Window_Coordinate DCMI Window Coordinate
* @{
*/
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFF) /*!< Window coordinate */
#define DCMI_WINDOW_COORDINATE ((uint32_t)0x3FFFU) /*!< Window coordinate */
/**
* @}
@ -219,7 +270,7 @@ typedef struct
/** @defgroup DCMI_Window_Height DCMI Window Height
* @{
*/
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFF) /*!< Window Height */
#define DCMI_WINDOW_HEIGHT ((uint32_t)0x1FFFU) /*!< Window Height */
/**
* @}
@ -228,11 +279,11 @@ typedef struct
/** @defgroup DCMI_interrupt_sources DCMI interrupt sources
* @{
*/
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE)
#define DCMI_IT_OVF ((uint32_t)DCMI_IER_OVF_IE)
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE)
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE)
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE)
#define DCMI_IT_FRAME ((uint32_t)DCMI_IER_FRAME_IE) /*!< Capture complete interrupt */
#define DCMI_IT_OVR ((uint32_t)DCMI_IER_OVR_IE) /*!< Overrun interrupt */
#define DCMI_IT_ERR ((uint32_t)DCMI_IER_ERR_IE) /*!< Synchronization error interrupt */
#define DCMI_IT_VSYNC ((uint32_t)DCMI_IER_VSYNC_IE) /*!< VSYNC interrupt */
#define DCMI_IT_LINE ((uint32_t)DCMI_IER_LINE_IE) /*!< Line interrupt */
/**
* @}
*/
@ -244,29 +295,71 @@ typedef struct
/**
* @brief DCMI SR register
*/
#define DCMI_FLAG_HSYNC ((uint32_t)0x2001)
#define DCMI_FLAG_VSYNC ((uint32_t)0x2002)
#define DCMI_FLAG_FNE ((uint32_t)0x2004)
#define DCMI_FLAG_HSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_HSYNC) /*!< HSYNC pin state (active line / synchronization between lines) */
#define DCMI_FLAG_VSYNC ((uint32_t)DCMI_SR_INDEX|DCMI_SR_VSYNC) /*!< VSYNC pin state (active frame / synchronization between frames) */
#define DCMI_FLAG_FNE ((uint32_t)DCMI_SR_INDEX|DCMI_SR_FNE) /*!< FIFO not empty flag */
/**
* @brief DCMI RISR register
* @brief DCMI RIS register
*/
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RISR_FRAME_RIS)
#define DCMI_FLAG_OVFRI ((uint32_t)DCMI_RISR_OVF_RIS)
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RISR_ERR_RIS)
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RISR_VSYNC_RIS)
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RISR_LINE_RIS)
#define DCMI_FLAG_FRAMERI ((uint32_t)DCMI_RIS_FRAME_RIS) /*!< Frame capture complete interrupt flag */
#define DCMI_FLAG_OVRRI ((uint32_t)DCMI_RIS_OVR_RIS) /*!< Overrun interrupt flag */
#define DCMI_FLAG_ERRRI ((uint32_t)DCMI_RIS_ERR_RIS) /*!< Synchronization error interrupt flag */
#define DCMI_FLAG_VSYNCRI ((uint32_t)DCMI_RIS_VSYNC_RIS) /*!< VSYNC interrupt flag */
#define DCMI_FLAG_LINERI ((uint32_t)DCMI_RIS_LINE_RIS) /*!< Line interrupt flag */
/**
* @brief DCMI MISR register
* @brief DCMI MIS register
*/
#define DCMI_FLAG_FRAMEMI ((uint32_t)0x1001)
#define DCMI_FLAG_OVFMI ((uint32_t)0x1002)
#define DCMI_FLAG_ERRMI ((uint32_t)0x1004)
#define DCMI_FLAG_VSYNCMI ((uint32_t)0x1008)
#define DCMI_FLAG_LINEMI ((uint32_t)0x1010)
#define DCMI_FLAG_FRAMEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_FRAME_MIS) /*!< DCMI Frame capture complete masked interrupt status */
#define DCMI_FLAG_OVRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_OVR_MIS ) /*!< DCMI Overrun masked interrupt status */
#define DCMI_FLAG_ERRMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_ERR_MIS ) /*!< DCMI Synchronization error masked interrupt status */
#define DCMI_FLAG_VSYNCMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_VSYNC_MIS) /*!< DCMI VSYNC masked interrupt status */
#define DCMI_FLAG_LINEMI ((uint32_t)DCMI_MIS_INDEX|DCMI_MIS_LINE_MIS ) /*!< DCMI Line masked interrupt status */
/**
* @}
*/
/** @defgroup DCMI_Byte_Select_Mode DCMI Byte Select Mode
* @{
*/
#define DCMI_BSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received data */
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
/**
* @}
*/
/** @defgroup DCMI_Byte_Select_Start DCMI Byte Select Start
* @{
*/
#define DCMI_OEBS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first data from the frame/line start, second one being dropped */
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
/**
* @}
*/
/** @defgroup DCMI_Line_Select_Mode DCMI Line Select Mode
* @{
*/
#define DCMI_LSM_ALL ((uint32_t)0x00000000U) /*!< Interface captures all received lines */
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
/**
* @}
*/
/** @defgroup DCMI_Line_Select_Start DCMI Line Select Start
* @{
*/
#define DCMI_OELS_ODD ((uint32_t)0x00000000U) /*!< Interface captures first line from the frame start, second one being dropped */
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
/**
* @}
*/
/**
* @}
*/
@ -298,20 +391,28 @@ typedef struct
/* Interrupt & Flag management */
/**
* @brief Get the DCMI pending flags.
* @brief Get the DCMI pending flag.
* @param __HANDLE__: DCMI handle
* @param __FLAG__: Get the specified flag.
* This parameter can be any combination of the following values:
* This parameter can be one of the following values (no combination allowed)
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
* @arg DCMI_FLAG_FNE: FIFO empty flag
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
* @arg DCMI_FLAG_OVFRI: Overflow flag mask
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
* @arg DCMI_FLAG_ERRRI: Synchronization error flag mask
* @arg DCMI_FLAG_VSYNCRI: VSYNC flag mask
* @arg DCMI_FLAG_LINERI: Line flag mask
* @arg DCMI_FLAG_FRAMEMI: DCMI Capture complete masked interrupt status
* @arg DCMI_FLAG_OVRMI: DCMI Overrun masked interrupt status
* @arg DCMI_FLAG_ERRMI: DCMI Synchronization error masked interrupt status
* @arg DCMI_FLAG_VSYNCMI: DCMI VSYNC masked interrupt status
* @arg DCMI_FLAG_LINEMI: DCMI Line masked interrupt status
* @retval The state of FLAG.
*/
#define __HAL_DCMI_GET_FLAG(__HANDLE__, __FLAG__)\
((((__FLAG__) & 0x3000) == 0x0)? ((__HANDLE__)->Instance->RISR & (__FLAG__)) :\
(((__FLAG__) & 0x2000) == 0x0)? ((__HANDLE__)->Instance->MISR & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
((((__FLAG__) & (DCMI_SR_INDEX|DCMI_MIS_INDEX)) == 0x0)? ((__HANDLE__)->Instance->RIS & (__FLAG__)) :\
(((__FLAG__) & DCMI_SR_INDEX) == 0x0)? ((__HANDLE__)->Instance->MIS & (__FLAG__)) : ((__HANDLE__)->Instance->SR & (__FLAG__)))
/**
* @brief Clear the DCMI pending flags.
@ -396,10 +497,14 @@ void HAL_DCMI_MspDeInit(DCMI_HandleTypeDef* hdcmi);
/* IO operation functions *****************************************************/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length);
HAL_StatusTypeDef HAL_DCMI_Stop(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Suspend(DCMI_HandleTypeDef* hdcmi);
HAL_StatusTypeDef HAL_DCMI_Resume(DCMI_HandleTypeDef* hdcmi);
void HAL_DCMI_ErrorCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi);
void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
/**
* @}
@ -409,9 +514,10 @@ void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi);
* @{
*/
/* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_DCMI_ConfigCROP(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCROP(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCROP(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize);
HAL_StatusTypeDef HAL_DCMI_EnableCrop(DCMI_HandleTypeDef *hdcmi);
HAL_StatusTypeDef HAL_DCMI_DisableCrop(DCMI_HandleTypeDef *hdcmi);
/**
* @}
*/
@ -432,7 +538,15 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DCMI_Private_Constants DCMI Private Constants
* @{
*/
#define DCMI_MIS_INDEX ((uint32_t)0x1000) /*!< DCMI MIS register index */
#define DCMI_SR_INDEX ((uint32_t)0x2000) /*!< DCMI SR register index */
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DCMI_Private_Macros DCMI Private Macros
* @{
@ -468,6 +582,20 @@ uint32_t HAL_DCMI_GetError(DCMI_HandleTypeDef *hdcmi);
#define IS_DCMI_WINDOW_HEIGHT(HEIGHT) ((HEIGHT) <= DCMI_WINDOW_HEIGHT)
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
((MODE) == DCMI_BSM_OTHER) || \
((MODE) == DCMI_BSM_ALTERNATE_4) || \
((MODE) == DCMI_BSM_ALTERNATE_2))
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
((POLARITY) == DCMI_OEBS_EVEN))
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
((MODE) == DCMI_LSM_ALTERNATE_2))
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
((POLARITY) == DCMI_OELS_EVEN))
/**
* @}
*/

165
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.c
View File

@ -2,29 +2,17 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @brief DCMI Extension HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of DCMI extension peripheral:
* + Extension features functions
*
@verbatim
==============================================================================
##### DCMI peripheral extension features #####
==============================================================================
[..] Support of Black and White cameras
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to manage the Black and White feature
@endverbatim
* @version V1.1.0
* @date 22-April-2016
* @brief Empty file; This file is no longer used to handle the Black&White
* feature. Its content is now moved to common files
* (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7
* family. It's just kept for compatibility reasons.
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -53,17 +41,6 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup DCMIEx DCMIEx
* @brief DCMI Extended HAL module driver
* @{
*/
#ifdef HAL_DCMI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
@ -71,131 +48,5 @@
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DCMIEx_Exported_Functions DCMIEx Exported Functions
* @{
*/
/** @defgroup DCMIEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DCMI
(+) De-initialize the DCMI
@endverbatim
* @{
*/
/**
* @brief Initializes the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle.
* @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Init(DCMI_HandleTypeDef *hdcmi)
{
/* Check the DCMI peripheral state */
if(hdcmi == NULL)
{
return HAL_ERROR;
}
/* Check function parameters */
assert_param(IS_DCMI_ALL_INSTANCE(hdcmi->Instance));
assert_param(IS_DCMI_PCKPOLARITY(hdcmi->Init.PCKPolarity));
assert_param(IS_DCMI_VSPOLARITY(hdcmi->Init.VSPolarity));
assert_param(IS_DCMI_HSPOLARITY(hdcmi->Init.HSPolarity));
assert_param(IS_DCMI_SYNCHRO(hdcmi->Init.SynchroMode));
assert_param(IS_DCMI_CAPTURE_RATE(hdcmi->Init.CaptureRate));
assert_param(IS_DCMI_EXTENDED_DATA(hdcmi->Init.ExtendedDataMode));
assert_param(IS_DCMI_MODE_JPEG(hdcmi->Init.JPEGMode));
assert_param(IS_DCMI_BYTE_SELECT_MODE(hdcmi->Init.ByteSelectMode));
assert_param(IS_DCMI_BYTE_SELECT_START(hdcmi->Init.ByteSelectStart));
assert_param(IS_DCMI_LINE_SELECT_MODE(hdcmi->Init.LineSelectMode));
assert_param(IS_DCMI_LINE_SELECT_START(hdcmi->Init.LineSelectStart));
if(hdcmi->State == HAL_DCMI_STATE_RESET)
{
/* Init the low level hardware */
HAL_DCMI_MspInit(hdcmi);
}
/* Change the DCMI state */
hdcmi->State = HAL_DCMI_STATE_BUSY;
/* Configures the HS, VS, DE and PC polarity */
hdcmi->Instance->CR &= ~(DCMI_CR_PCKPOL | DCMI_CR_HSPOL | DCMI_CR_VSPOL | DCMI_CR_EDM_0 |\
DCMI_CR_EDM_1 | DCMI_CR_FCRC_0 | DCMI_CR_FCRC_1 | DCMI_CR_JPEG |\
DCMI_CR_ESS | DCMI_CR_BSM_0 | DCMI_CR_BSM_1 | DCMI_CR_OEBS |\
DCMI_CR_LSM | DCMI_CR_OELS);
hdcmi->Instance->CR |= (uint32_t)(hdcmi->Init.SynchroMode | hdcmi->Init.CaptureRate |\
hdcmi->Init.VSPolarity | hdcmi->Init.HSPolarity |\
hdcmi->Init.PCKPolarity | hdcmi->Init.ExtendedDataMode |\
hdcmi->Init.JPEGMode | hdcmi->Init.ByteSelectMode |\
hdcmi->Init.ByteSelectStart | hdcmi->Init.LineSelectMode |\
hdcmi->Init.LineSelectStart);
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
DCMI->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |
((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << 8)|
((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << 16) |
((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << 24));
}
/* Enable the Line interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_LINE);
/* Enable the VSYNC interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_VSYNC);
/* Enable the Frame capture complete interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_FRAME);
/* Enable the Synchronization error interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_ERR);
/* Enable the Overflow interrupt */
__HAL_DCMI_ENABLE_IT(hdcmi, DCMI_IT_OVF);
/* Enable DCMI by setting DCMIEN bit */
__HAL_DCMI_ENABLE(hdcmi);
/* Update error code */
hdcmi->ErrorCode = HAL_DCMI_ERROR_NONE;
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_DCMI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

164
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dcmi_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DCMI Extension HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -39,175 +39,17 @@
#ifndef __STM32F7xx_HAL_DCMI_EX_H
#define __STM32F7xx_HAL_DCMI_EX_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup DCMIEx DCMIEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DCMIEx_Exported_Types DCMIEx Exported Types
* @{
*/
/**
* @brief DCMIEx Embedded Synchronisation CODE Init structure definition
*/
typedef struct
{
uint8_t FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
uint8_t LineStartCode; /*!< Specifies the code of the line start delimiter. */
uint8_t LineEndCode; /*!< Specifies the code of the line end delimiter. */
uint8_t FrameEndCode; /*!< Specifies the code of the frame end delimiter. */
}DCMI_CodesInitTypeDef;
/**
* @brief DCMI Init structure definition
*/
typedef struct
{
uint32_t SynchroMode; /*!< Specifies the Synchronization Mode: Hardware or Embedded.
This parameter can be a value of @ref DCMI_Synchronization_Mode */
uint32_t PCKPolarity; /*!< Specifies the Pixel clock polarity: Falling or Rising.
This parameter can be a value of @ref DCMI_PIXCK_Polarity */
uint32_t VSPolarity; /*!< Specifies the Vertical synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_VSYNC_Polarity */
uint32_t HSPolarity; /*!< Specifies the Horizontal synchronization polarity: High or Low.
This parameter can be a value of @ref DCMI_HSYNC_Polarity */
uint32_t CaptureRate; /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
This parameter can be a value of @ref DCMI_Capture_Rate */
uint32_t ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
This parameter can be a value of @ref DCMI_Extended_Data_Mode */
DCMI_CodesInitTypeDef SyncroCode; /*!< Specifies the code of the frame start delimiter. */
uint32_t JPEGMode; /*!< Enable or Disable the JPEG mode.
This parameter can be a value of @ref DCMI_MODE_JPEG */
uint32_t ByteSelectMode; /*!< Specifies the data to be captured by the interface
This parameter can be a value of @ref DCMIEx_Byte_Select_Mode */
uint32_t ByteSelectStart; /*!< Specifies if the data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMIEx_Byte_Select_Start */
uint32_t LineSelectMode; /*!< Specifies the line of data to be captured by the interface
This parameter can be a value of @ref DCMIEx_Line_Select_Mode */
uint32_t LineSelectStart; /*!< Specifies if the line of data to be captured by the interface is even or odd
This parameter can be a value of @ref DCMIEx_Line_Select_Start */
}DCMI_InitTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DCMIEx_Exported_Constants DCMIEx Exported Constants
* @{
*/
/** @defgroup DCMIEx_Byte_Select_Mode DCMIEx Byte Select Mode
* @{
*/
#define DCMI_BSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received data */
#define DCMI_BSM_OTHER ((uint32_t)DCMI_CR_BSM_0) /*!< Interface captures every other byte from the received data */
#define DCMI_BSM_ALTERNATE_4 ((uint32_t)DCMI_CR_BSM_1) /*!< Interface captures one byte out of four */
#define DCMI_BSM_ALTERNATE_2 ((uint32_t)(DCMI_CR_BSM_0 | DCMI_CR_BSM_1)) /*!< Interface captures two bytes out of four */
/**
* @}
*/
/** @defgroup DCMIEx_Byte_Select_Start DCMIEx Byte Select Start
* @{
*/
#define DCMI_OEBS_ODD ((uint32_t)0x00000000) /*!< Interface captures first data from the frame/line start, second one being dropped */
#define DCMI_OEBS_EVEN ((uint32_t)DCMI_CR_OEBS) /*!< Interface captures second data from the frame/line start, first one being dropped */
/**
* @}
*/
/** @defgroup DCMIEx_Line_Select_Mode DCMIEx Line Select Mode
* @{
*/
#define DCMI_LSM_ALL ((uint32_t)0x00000000) /*!< Interface captures all received lines */
#define DCMI_LSM_ALTERNATE_2 ((uint32_t)DCMI_CR_LSM) /*!< Interface captures one line out of two */
/**
* @}
*/
/** @defgroup DCMIEx_Line_Select_Start DCMIEx Line Select Start
* @{
*/
#define DCMI_OELS_ODD ((uint32_t)0x00000000) /*!< Interface captures first line from the frame start, second one being dropped */
#define DCMI_OELS_EVEN ((uint32_t)DCMI_CR_OELS) /*!< Interface captures second line from the frame start, first one being dropped */
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/** @defgroup DCMIEx_Private_Macros DCMIEx Private Macros
* @{
*/
#define IS_DCMI_BYTE_SELECT_MODE(MODE)(((MODE) == DCMI_BSM_ALL) || \
((MODE) == DCMI_BSM_OTHER) || \
((MODE) == DCMI_BSM_ALTERNATE_4) || \
((MODE) == DCMI_BSM_ALTERNATE_2))
#define IS_DCMI_BYTE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OEBS_ODD) || \
((POLARITY) == DCMI_OEBS_EVEN))
#define IS_DCMI_LINE_SELECT_MODE(MODE)(((MODE) == DCMI_LSM_ALL) || \
((MODE) == DCMI_LSM_ALTERNATE_2))
#define IS_DCMI_LINE_SELECT_START(POLARITY)(((POLARITY) == DCMI_OELS_ODD) || \
((POLARITY) == DCMI_OELS_EVEN))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_DCMI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

18
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_def.h
View File

@ -2,14 +2,14 @@
******************************************************************************
* @file stm32f7xx_hal_def.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -55,10 +55,10 @@
*/
typedef enum
{
HAL_OK = 0x00,
HAL_ERROR = 0x01,
HAL_BUSY = 0x02,
HAL_TIMEOUT = 0x03
HAL_OK = 0x00U,
HAL_ERROR = 0x01U,
HAL_BUSY = 0x02U,
HAL_TIMEOUT = 0x03U
} HAL_StatusTypeDef;
/**
@ -71,7 +71,7 @@ typedef enum
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
#define HAL_MAX_DELAY 0xFFFFFFFF
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
#define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == RESET)
@ -99,7 +99,7 @@ typedef enum
* HAL_PPP_MspInit() which will reconfigure the low level hardware.
* @retval None
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
#if (USE_RTOS == 1)
/* Reserved for future use */

3018
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.c Normal file
View File

File diff suppressed because it is too large Load Diff

710
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dfsdm.h Normal file
View File

@ -0,0 +1,710 @@
/**
******************************************************************************
* @file stm32f7xx_hal_dfsdm.h
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DFSDM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_DFSDM_H
#define __STM32F7xx_HAL_DFSDM_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup DFSDM
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Types DFSDM Exported Types
* @{
*/
/**
* @brief HAL DFSDM Channel states definition
*/
typedef enum
{
HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */
HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */
HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */
}HAL_DFSDM_Channel_StateTypeDef;
/**
* @brief DFSDM channel output clock structure definition
*/
typedef struct
{
FunctionalState Activation; /*!< Output clock enable/disable */
uint32_t Selection; /*!< Output clock is system clock or audio clock.
This parameter can be a value of @ref DFSDM_Channel_OuputClock */
uint32_t Divider; /*!< Output clock divider.
This parameter must be a number between Min_Data = 2 and Max_Data = 256 */
}DFSDM_Channel_OutputClockTypeDef;
/**
* @brief DFSDM channel input structure definition
*/
typedef struct
{
uint32_t Multiplexer; /*!< Input is external serial inputs or internal register.
This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */
uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register.
This parameter can be a value of @ref DFSDM_Channel_DataPacking */
uint32_t Pins; /*!< Input pins are taken from same or following channel.
This parameter can be a value of @ref DFSDM_Channel_InputPins */
}DFSDM_Channel_InputTypeDef;
/**
* @brief DFSDM channel serial interface structure definition
*/
typedef struct
{
uint32_t Type; /*!< SPI or Manchester modes.
This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */
uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point).
This parameter can be a value of @ref DFSDM_Channel_SpiClock */
}DFSDM_Channel_SerialInterfaceTypeDef;
/**
* @brief DFSDM channel analog watchdog structure definition
*/
typedef struct
{
uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order.
This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */
uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 32 */
}DFSDM_Channel_AwdTypeDef;
/**
* @brief DFSDM channel init structure definition
*/
typedef struct
{
DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */
DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */
DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */
DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */
int32_t Offset; /*!< DFSDM channel offset.
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
uint32_t RightBitShift; /*!< DFSDM channel right bit shift.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
}DFSDM_Channel_InitTypeDef;
/**
* @brief DFSDM channel handle structure definition
*/
typedef struct
{
DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */
DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */
HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */
}DFSDM_Channel_HandleTypeDef;
/**
* @brief HAL DFSDM Filter states definition
*/
typedef enum
{
HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */
HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */
HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */
HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */
HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */
HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */
}HAL_DFSDM_Filter_StateTypeDef;
/**
* @brief DFSDM filter regular conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous.
This parameter can be a value of @ref DFSDM_Filter_Trigger */
FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */
FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */
}DFSDM_Filter_RegularParamTypeDef;
/**
* @brief DFSDM filter injected conversion parameters structure definition
*/
typedef struct
{
uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous.
This parameter can be a value of @ref DFSDM_Filter_Trigger */
FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */
FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */
uint32_t ExtTrigger; /*!< External trigger.
This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */
uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both.
This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */
}DFSDM_Filter_InjectedParamTypeDef;
/**
* @brief DFSDM filter parameters structure definition
*/
typedef struct
{
uint32_t SincOrder; /*!< Sinc filter order.
This parameter can be a value of @ref DFSDM_Filter_SincOrder */
uint32_t Oversampling; /*!< Filter oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
uint32_t IntOversampling; /*!< Integrator oversampling ratio.
This parameter must be a number between Min_Data = 1 and Max_Data = 256 */
}DFSDM_Filter_FilterParamTypeDef;
/**
* @brief DFSDM filter init structure definition
*/
typedef struct
{
DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */
DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */
DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */
}DFSDM_Filter_InitTypeDef;
/**
* @brief DFSDM filter handle structure definition
*/
typedef struct
{
DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */
DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */
DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */
DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */
uint32_t RegularContMode; /*!< Regular conversion continuous mode */
uint32_t RegularTrigger; /*!< Trigger used for regular conversion */
uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */
uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */
FunctionalState InjectedScanMode; /*!< Injected scanning mode */
uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */
uint32_t InjConvRemaining; /*!< Injected conversions remaining */
HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */
uint32_t ErrorCode; /*!< DFSDM filter error code */
}DFSDM_Filter_HandleTypeDef;
/**
* @brief DFSDM filter analog watchdog parameters structure definition
*/
typedef struct
{
uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter.
This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */
uint32_t Channel; /*!< Analog watchdog channel selection.
This parameter can be a values combination of @ref DFSDM_Channel_Selection */
int32_t HighThreshold; /*!< High threshold for the analog watchdog.
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
int32_t LowThreshold; /*!< Low threshold for the analog watchdog.
This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */
uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event.
This parameter can be a values combination of @ref DFSDM_BreakSignals */
uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event.
This parameter can be a values combination of @ref DFSDM_BreakSignals */
}DFSDM_Filter_AwdParamTypeDef;
/**
* @}
*/
/* End of exported types -----------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants
* @{
*/
/** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection
* @{
*/
#define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM ((uint32_t)0x00000000U) /*!< Source for ouput clock is system clock */
#define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */
/**
* @}
*/
/** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer
* @{
*/
#define DFSDM_CHANNEL_EXTERNAL_INPUTS ((uint32_t)0x00000000U) /*!< Data are taken from external inputs */
#define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */
/**
* @}
*/
/** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing
* @{
*/
#define DFSDM_CHANNEL_STANDARD_MODE ((uint32_t)0x00000000U) /*!< Standard data packing mode */
#define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */
#define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */
/**
* @}
*/
/** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins
* @{
*/
#define DFSDM_CHANNEL_SAME_CHANNEL_PINS ((uint32_t)0x00000000U) /*!< Input from pins on same channel */
#define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */
/**
* @}
*/
/** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type
* @{
*/
#define DFSDM_CHANNEL_SPI_RISING ((uint32_t)0x00000000U) /*!< SPI with rising edge */
#define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */
#define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */
#define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */
/**
* @}
*/
/** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection
* @{
*/
#define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL ((uint32_t)0x00000000U) /*!< External SPI clock */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */
#define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */
/**
* @}
*/
/** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order
* @{
*/
#define DFSDM_CHANNEL_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
#define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */
#define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */
#define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */
/**
* @}
*/
/** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger
* @{
*/
#define DFSDM_FILTER_SW_TRIGGER ((uint32_t)0x00000000U) /*!< Software trigger */
#define DFSDM_FILTER_SYNC_TRIGGER ((uint32_t)0x00000001U) /*!< Synchronous with DFSDM_FLT0 */
#define DFSDM_FILTER_EXT_TRIGGER ((uint32_t)0x00000002U) /*!< External trigger (only for injected conversion) */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger
* @{
*/
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO ((uint32_t)0x00000000U) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM10_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \
DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \
DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
#define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \
DFSDM_FLTCR1_JEXTSEL_4) /*!< For DFSDM filter 0, 1, 2 and 3 */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge
* @{
*/
#define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */
#define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */
#define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */
/**
* @}
*/
/** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order
* @{
*/
#define DFSDM_FILTER_FASTSINC_ORDER ((uint32_t)0x00000000U) /*!< FastSinc filter type */
#define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */
#define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */
#define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */
#define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */
#define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */
/**
* @}
*/
/** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source
* @{
*/
#define DFSDM_FILTER_AWD_FILTER_DATA ((uint32_t)0x00000000U) /*!< From digital filter */
#define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */
/**
* @}
*/
/** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code
* @{
*/
#define DFSDM_FILTER_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define DFSDM_FILTER_ERROR_REGULAR_OVERRUN ((uint32_t)0x00000001U) /*!< Overrun occurs during regular conversion */
#define DFSDM_FILTER_ERROR_INJECTED_OVERRUN ((uint32_t)0x00000002U) /*!< Overrun occurs during injected conversion */
#define DFSDM_FILTER_ERROR_DMA ((uint32_t)0x00000003U) /*!< DMA error occurs */
/**
* @}
*/
/** @defgroup DFSDM_BreakSignals DFSDM break signals
* @{
*/
#define DFSDM_NO_BREAK_SIGNAL ((uint32_t)0x00000000U) /*!< No break signal */
#define DFSDM_BREAK_SIGNAL_0 ((uint32_t)0x00000001U) /*!< Break signal 0 */
#define DFSDM_BREAK_SIGNAL_1 ((uint32_t)0x00000002U) /*!< Break signal 1 */
#define DFSDM_BREAK_SIGNAL_2 ((uint32_t)0x00000004U) /*!< Break signal 2 */
#define DFSDM_BREAK_SIGNAL_3 ((uint32_t)0x00000008U) /*!< Break signal 3 */
/**
* @}
*/
/** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection
* @{
*/
/* DFSDM Channels ------------------------------------------------------------*/
/* The DFSDM channels are defined as follows:
- in 16-bit LSB the channel mask is set
- in 16-bit MSB the channel number is set
e.g. for channel 5 definition:
- the channel mask is 0x00000020 (bit 5 is set)
- the channel number 5 is 0x00050000
--> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */
#define DFSDM_CHANNEL_0 ((uint32_t)0x00000001U)
#define DFSDM_CHANNEL_1 ((uint32_t)0x00010002U)
#define DFSDM_CHANNEL_2 ((uint32_t)0x00020004U)
#define DFSDM_CHANNEL_3 ((uint32_t)0x00030008U)
#define DFSDM_CHANNEL_4 ((uint32_t)0x00040010U)
#define DFSDM_CHANNEL_5 ((uint32_t)0x00050020U)
#define DFSDM_CHANNEL_6 ((uint32_t)0x00060040U)
#define DFSDM_CHANNEL_7 ((uint32_t)0x00070080U)
/**
* @}
*/
/** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode
* @{
*/
#define DFSDM_CONTINUOUS_CONV_OFF ((uint32_t)0x00000000U) /*!< Conversion are not continuous */
#define DFSDM_CONTINUOUS_CONV_ON ((uint32_t)0x00000001U) /*!< Conversion are continuous */
/**
* @}
*/
/** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold
* @{
*/
#define DFSDM_AWD_HIGH_THRESHOLD ((uint32_t)0x00000000U) /*!< Analog watchdog high threshold */
#define DFSDM_AWD_LOW_THRESHOLD ((uint32_t)0x00000001U) /*!< Analog watchdog low threshold */
/**
* @}
*/
/**
* @}
*/
/* End of exported constants -------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros
* @{
*/
/** @brief Reset DFSDM channel handle state.
* @param __HANDLE__: DFSDM channel handle.
* @retval None
*/
#define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET)
/** @brief Reset DFSDM filter handle state.
* @param __HANDLE__: DFSDM filter handle.
* @retval None
*/
#define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
/**
* @}
*/
/* End of exported macros ----------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions
* @{
*/
/** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions
* @{
*/
/* Channel initialization and de-initialization functions *********************/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions
* @{
*/
/* Channel operation functions ************************************************/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout);
void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
/** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function
* @{
*/
/* Channel state function *****************************************************/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions
* @{
*/
/* Filter initialization and de-initialization functions *********************/
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions
* @{
*/
/* Filter control functions *********************/
HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel,
uint32_t ContinuousMode);
HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
uint32_t Channel);
/**
* @}
*/
/** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions
* @{
*/
/* Filter operation functions *********************/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
DFSDM_Filter_AwdParamTypeDef* awdParam);
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel);
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t* Channel);
uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout);
void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold);
void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
/** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions
* @{
*/
/* Filter state functions *****************************************************/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter);
/**
* @}
*/
/**
* @}
*/
/* End of exported functions -------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DFSDM_Private_Macros DFSDM Private Macros
* @{
*/
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \
((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO))
#define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2 <= (DIVIDER)) && ((DIVIDER) <= 256))
#define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \
((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER))
#define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \
((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \
((MODE) == DFSDM_CHANNEL_DUAL_MODE))
#define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \
((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS))
#define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \
((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \
((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \
((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING))
#define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \
((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING))
#define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \
((ORDER) == DFSDM_CHANNEL_SINC3_ORDER))
#define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 32))
#define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1F)
#define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFF)
#define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER))
#define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \
((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \
((TRIG) == DFSDM_FILTER_EXT_TRIGGER))
#define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2)|| \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2)|| \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM10_OC1) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \
((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) ||\
((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT))
#define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \
((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES))
#define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \
((ORDER) == DFSDM_FILTER_SINC5_ORDER))
#define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 1024))
#define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1 <= (RATIO)) && ((RATIO) <= 256))
#define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \
((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA))
#define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607))
#define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU)
#define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \
((CHANNEL) == DFSDM_CHANNEL_1) || \
((CHANNEL) == DFSDM_CHANNEL_2) || \
((CHANNEL) == DFSDM_CHANNEL_3) || \
((CHANNEL) == DFSDM_CHANNEL_4) || \
((CHANNEL) == DFSDM_CHANNEL_5) || \
((CHANNEL) == DFSDM_CHANNEL_6) || \
((CHANNEL) == DFSDM_CHANNEL_7))
#define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0) && ((CHANNEL) <= 0x000F00FFU))
#define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \
((MODE) == DFSDM_CONTINUOUS_CONV_ON))
/**
* @}
*/
/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_DFSDM_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

1029
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.c
View File

File diff suppressed because it is too large Load Diff

181
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dma.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -67,7 +67,7 @@
typedef struct
{
uint32_t Channel; /*!< Specifies the channel used for the specified stream.
This parameter can be a value of @ref DMA_Channel_selection */
This parameter can be a value of @ref DMAEx_Channel_selection */
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
from memory to memory or from peripheral to memory.
@ -119,17 +119,12 @@ typedef struct
*/
typedef enum
{
HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */
HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */
HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */
HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */
HAL_DMA_STATE_ERROR = 0x04U, /*!< DMA error state */
HAL_DMA_STATE_ABORT = 0x05U, /*!< DMA Abort state */
}HAL_DMA_StateTypeDef;
/**
@ -137,10 +132,24 @@ typedef enum
*/
typedef enum
{
HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */
HAL_DMA_HALF_TRANSFER = 0x01U, /*!< Half Transfer */
}HAL_DMA_LevelCompleteTypeDef;
/**
* @brief HAL DMA Error Code structure definition
*/
typedef enum
{
HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */
HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half Transfer */
HAL_DMA_XFER_M1CPLT_CB_ID = 0x02U, /*!< M1 Full Transfer */
HAL_DMA_XFER_M1HALFCPLT_CB_ID = 0x03U, /*!< M1 Half Transfer */
HAL_DMA_XFER_ERROR_CB_ID = 0x04U, /*!< Error */
HAL_DMA_XFER_ABORT_CB_ID = 0x05U, /*!< Abort */
HAL_DMA_XFER_ALL_CB_ID = 0x06U /*!< All */
}HAL_DMA_CallbackIDTypeDef;
/**
* @brief DMA handle Structure definition
*/
@ -154,18 +163,22 @@ typedef struct __DMA_HandleTypeDef
__IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
void *Parent; /*!< Parent object state */
void *Parent; /*!< Parent object state */
void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
void (* XferM1HalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Half complete Memory1 callback */
void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer Abort callback */
__IO uint32_t ErrorCode; /*!< DMA Error code */
__IO uint32_t ErrorCode; /*!< DMA Error code */
uint32_t StreamBaseAddress; /*!< DMA Stream Base Address */
uint32_t StreamIndex; /*!< DMA Stream Index */
@ -188,27 +201,14 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA Error Code
* @{
*/
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
/**
* @}
*/
/** @defgroup DMA_Channel_selection DMA Channel selection
* @brief DMA channel selection
* @{
*/
#define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
#define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
#define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
/**
* @}
*/
@ -217,7 +217,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA data transfer direction
* @{
*/
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
/**
@ -229,7 +229,7 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
/**
* @}
*/
@ -239,29 +239,27 @@ typedef struct __DMA_HandleTypeDef
* @{
*/
#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
/**
* @}
*/
/** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
* @brief DMA peripheral data size
* @{
*/
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
/**
* @}
*/
/** @defgroup DMA_Memory_data_size DMA Memory data size
* @brief DMA memory data size
* @{
*/
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
/**
@ -272,19 +270,18 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA mode
* @{
*/
#define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
/**
* @}
*/
/** @defgroup DMA_Priority_level DMA Priority level
* @brief DMA priority levels
* @{
*/
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
@ -292,12 +289,11 @@ typedef struct __DMA_HandleTypeDef
* @}
*/
/** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
* @brief DMA FIFO direct mode
* @{
*/
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
/**
* @}
@ -307,7 +303,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA FIFO level
* @{
*/
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
@ -319,7 +315,7 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA memory burst
* @{
*/
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
@ -327,15 +323,14 @@ typedef struct __DMA_HandleTypeDef
* @}
*/
/** @defgroup DMA_Peripheral_burst DMA Peripheral burst
* @brief DMA peripheral burst
* @{
*/
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
/**
* @}
*/
@ -348,7 +343,7 @@ typedef struct __DMA_HandleTypeDef
#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
#define DMA_IT_FE ((uint32_t)0x00000080)
#define DMA_IT_FE ((uint32_t)0x00000080U)
/**
* @}
*/
@ -357,26 +352,26 @@ typedef struct __DMA_HandleTypeDef
* @brief DMA flag definitions
* @{
*/
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
/**
* @}
*/
@ -563,7 +558,7 @@ typedef struct __DMA_HandleTypeDef
* @brief Enable the specified DMA Stream interrupts.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
* @arg DMA_IT_TE: Transfer error interrupt mask.
@ -578,7 +573,7 @@ typedef struct __DMA_HandleTypeDef
* @brief Disable the specified DMA Stream interrupts.
* @param __HANDLE__: DMA handle
* @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
* @arg DMA_IT_TE: Transfer error interrupt mask.
@ -660,8 +655,13 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
/**
* @}
*/
@ -692,20 +692,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
* @brief DMA private macros
* @{
*/
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
((CHANNEL) == DMA_CHANNEL_1) || \
((CHANNEL) == DMA_CHANNEL_2) || \
((CHANNEL) == DMA_CHANNEL_3) || \
((CHANNEL) == DMA_CHANNEL_4) || \
((CHANNEL) == DMA_CHANNEL_5) || \
((CHANNEL) == DMA_CHANNEL_6) || \
((CHANNEL) == DMA_CHANNEL_7))
#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
((DIRECTION) == DMA_MEMORY_TO_MEMORY))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x01U) && ((SIZE) < 0x10000U))
#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
((STATE) == DMA_PINC_DISABLE))

1415
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.c
View File

File diff suppressed because it is too large Load Diff

514
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma2d.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DMA2D HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -50,7 +50,7 @@
* @{
*/
/** @defgroup DMA2D DMA2D
/** @addtogroup DMA2D DMA2D
* @brief DMA2D HAL module driver
* @{
*/
@ -83,10 +83,10 @@ typedef struct
{
uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM */
uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode.
This parameter can be one value of @ref DMA2D_CLUT_CM. */
uint32_t Size; /*!< configures the DMA2D CLUT size.
uint32_t Size; /*!< Configures the DMA2D CLUT size.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
} DMA2D_CLUTCfgTypeDef;
@ -95,35 +95,67 @@ typedef struct
*/
typedef struct
{
uint32_t Mode; /*!< configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode */
uint32_t Mode; /*!< Configures the DMA2D transfer mode.
This parameter can be one value of @ref DMA2D_Mode. */
uint32_t ColorMode; /*!< configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Color_Mode */
uint32_t ColorMode; /*!< Configures the color format of the output image.
This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
uint32_t OutputOffset; /*!< Specifies the Offset value.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
#if defined (DMA2D_OPFCCR_AI)
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter.
This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
#endif /* DMA2D_OPFCCR_AI */
#if defined (DMA2D_OPFCCR_RBS)
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
for the output pixel format converter.
This parameter can be one value of @ref DMA2D_RB_Swap. */
#endif /* DMA2D_OPFCCR_RBS */
} DMA2D_InitTypeDef;
/**
* @brief DMA2D Layer structure definition
*/
typedef struct
{
uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset.
This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
This parameter can be one value of @ref DMA2D_Input_Color_Mode */
uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode.
This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
This parameter can be one value of @ref DMA2D_ALPHA_MODE */
uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode.
This parameter can be one value of @ref DMA2D_Alpha_Mode. */
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
in case of A8 or A4 color mode (ARGB).
Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
@note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
- InputAlpha[24:31] is the alpha value ALPHA[0:7]
- InputAlpha[16:23] is the red value RED[0:7]
- InputAlpha[8:15] is the green value GREEN[0:7]
- InputAlpha[0:7] is the blue value BLUE[0:7]. */
#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
uint32_t AlphaInverted; /*!< Select regular or inverted alpha value.
This parameter can be one value of @ref DMA2D_Alpha_Inverted.
This feature is only available on devices :
STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
This parameter can be one value of @ref DMA2D_RB_Swap
This feature is only available on devices :
STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
} DMA2D_LayerCfgTypeDef;
/**
@ -131,12 +163,12 @@ typedef struct
*/
typedef enum
{
HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */
HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */
HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */
}HAL_DMA2D_StateTypeDef;
/**
@ -144,21 +176,21 @@ typedef enum
*/
typedef struct __DMA2D_HandleTypeDef
{
DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */
DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */
void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */
DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
HAL_LockTypeDef Lock; /*!< DMA2D Lock */
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
__IO uint32_t ErrorCode; /*!< DMA2D Error code */
HAL_LockTypeDef Lock; /*!< DMA2D lock. */
__IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */
__IO uint32_t ErrorCode; /*!< DMA2D error code. */
} DMA2D_HandleTypeDef;
/**
* @}
@ -172,10 +204,11 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Error_Code DMA2D Error Code
* @{
*/
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
#define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002U) /*!< Configuration error */
#define HAL_DMA2D_ERROR_CAE ((uint32_t)0x00000004U) /*!< CLUT access error */
#define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
/**
* @}
*/
@ -183,135 +216,126 @@ typedef struct __DMA2D_HandleTypeDef
/** @defgroup DMA2D_Mode DMA2D Mode
* @{
*/
#define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
#define DMA2D_M2M ((uint32_t)0x00000000U) /*!< DMA2D memory to memory transfer mode */
#define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
#define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
#define DMA2D_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
/**
* @}
*/
/** @defgroup DMA2D_Color_Mode DMA2D Color Mode
/** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
* @{
*/
#define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
#define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
#define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
#define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
#define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */
#define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
#define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */
/**
* @}
*/
/** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
* @{
*/
#define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
/**
* @}
*/
/** @defgroup DMA2D_SIZE DMA2D SIZE
* @{
*/
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
/**
* @}
*/
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
/**
* @}
*/
/** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
* @{
*/
#define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
#define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
#define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
#define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
#define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
#define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
#define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
#define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
#define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
#define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
#define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
#define DMA2D_INPUT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 color mode */
#define DMA2D_INPUT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 color mode */
#define DMA2D_INPUT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 color mode */
#define DMA2D_INPUT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 color mode */
#define DMA2D_INPUT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 color mode */
#define DMA2D_INPUT_L8 ((uint32_t)0x00000005U) /*!< L8 color mode */
#define DMA2D_INPUT_AL44 ((uint32_t)0x00000006U) /*!< AL44 color mode */
#define DMA2D_INPUT_AL88 ((uint32_t)0x00000007U) /*!< AL88 color mode */
#define DMA2D_INPUT_L4 ((uint32_t)0x00000008U) /*!< L4 color mode */
#define DMA2D_INPUT_A8 ((uint32_t)0x00000009U) /*!< A8 color mode */
#define DMA2D_INPUT_A4 ((uint32_t)0x0000000AU) /*!< A4 color mode */
/**
* @}
*/
/** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
/** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
* @{
*/
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
#define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
#define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001U) /*!< Replace original alpha channel value by programmed alpha value */
#define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002U) /*!< Replace original alpha channel value by programmed alpha value
with original alpha channel value */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
/** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
* @{
*/
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
#define DMA2D_REGULAR_ALPHA ((uint32_t)0x00000000U) /*!< No modification of the alpha channel value */
#define DMA2D_INVERTED_ALPHA ((uint32_t)0x00000001U) /*!< Invert the alpha channel value */
/**
* @}
*/
#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
/** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
* @{
*/
#define DMA2D_RB_REGULAR ((uint32_t)0x00000000U) /*!< Select regular mode (RGB or ARGB) */
#define DMA2D_RB_SWAP ((uint32_t)0x00000001U) /*!< Select swap mode (BGR or ABGR) */
/**
* @}
*/
#endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS) */
/** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
* @{
*/
#define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 DMA2D CLUT color mode */
#define DMA2D_CCM_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 DMA2D CLUT color mode */
/**
* @}
*/
/** @defgroup DMA2D_Size_Clut DMA2D Size Clut
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
/**
* @}
*/
/** @defgroup DMA2D_DeadTime DMA2D DeadTime
* @{
*/
#define LINE_WATERMARK DMA2D_LWR_LW
/**
* @}
*/
/** @defgroup DMA2D_Interrupts DMA2D Interrupts
* @{
*/
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
/** @defgroup DMA2D_Flag DMA2D Flag
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
#define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
#define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
#define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
#define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
#define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
#define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
/**
* @}
*/
/** @defgroup DMA2D_Flags DMA2D Flags
* @{
*/
#define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
#define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
#define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
#define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
#define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
/**
* @}
*/
/** @defgroup DMA2D_Aliases DMA2D API Aliases
* @{
*/
#define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/**
* @}
*/
/* Exported macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
* @{
*/
@ -329,22 +353,16 @@ typedef struct __DMA2D_HandleTypeDef
*/
#define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
/**
* @brief Disable the DMA2D.
* @param __HANDLE__: DMA2D handle
* @retval None.
*/
#define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
/* Interrupt & Flag management */
/**
* @brief Get the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle
* @param __FLAG__: Get the specified flag.
* @param __FLAG__: flag to check.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
* @arg DMA2D_FLAG_CAE: C-LUT access error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
@ -353,13 +371,13 @@ typedef struct __DMA2D_HandleTypeDef
#define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/**
* @brief Clears the DMA2D pending flags.
* @brief Clear the DMA2D pending flags.
* @param __HANDLE__: DMA2D handle
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA2D_FLAG_CE: Configuration error flag
* @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
* @arg DMA2D_FLAG_CAE: C-LUT access error flag
* @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
* @arg DMA2D_FLAG_CAE: CLUT access error flag
* @arg DMA2D_FLAG_TW: Transfer Watermark flag
* @arg DMA2D_FLAG_TC: Transfer complete flag
* @arg DMA2D_FLAG_TE: Transfer error flag
@ -368,13 +386,13 @@ typedef struct __DMA2D_HandleTypeDef
#define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
/**
* @brief Enables the specified DMA2D interrupts.
* @brief Enable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
@ -383,13 +401,13 @@ typedef struct __DMA2D_HandleTypeDef
#define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disables the specified DMA2D interrupts.
* @brief Disable the specified DMA2D interrupts.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
@ -398,33 +416,48 @@ typedef struct __DMA2D_HandleTypeDef
#define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/**
* @brief Checks whether the specified DMA2D interrupt has occurred or not.
* @brief Check whether the specified DMA2D interrupt source is enabled or not.
* @param __HANDLE__: DMA2D handle
* @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA2D_IT_CE: Configuration error interrupt mask
* @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
* @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
* @arg DMA2D_IT_CAE: CLUT access error interrupt mask
* @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
* @arg DMA2D_IT_TC: Transfer complete interrupt mask
* @arg DMA2D_IT_TE: Transfer error interrupt mask
* @retval The state of INTERRUPT.
* @retval The state of INTERRUPT source.
*/
#define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
/** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
* @{
*/
/** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
* @{
*/
/* Initialization and de-initialization functions *******************************/
HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
* @{
*/
/* IO operation functions *******************************************************/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
@ -433,85 +466,146 @@ HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32
HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
* @{
*/
/* Peripheral Control functions *************************************************/
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
/**
* @}
*/
/** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
* @{
*/
/* Peripheral State functions ***************************************************/
HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Types DMA2D Private Types
* @{
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
* @{
*/
/** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
* @{
*/
#define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */
/**
* @}
*/
/** @defgroup DMA2D_Color_Value DMA2D Color Value
* @{
*/
#define DMA2D_COLOR_VALUE ((uint32_t)0x000000FFU) /*!< Color value mask */
/**
* @}
*/
/** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
* @{
*/
#define DMA2D_MAX_LAYER 2 /*!< DMA2D maximum number of layers */
/**
* @}
*/
/** @defgroup DMA2D_Offset DMA2D Offset
* @{
*/
#define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
/**
* @}
*/
/** @defgroup DMA2D_Size DMA2D Size
* @{
*/
#define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D number of pixels per line */
#define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of lines */
/**
* @}
*/
/** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
* @{
*/
#define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D CLUT size */
/**
* @}
*/
/**
* @}
*/
/* Private defines -------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Defines DMA2D Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup DMA2D_Private_Variables DMA2D Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup DMA2D_Private_Constants DMA2D Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMA2D_Private_Macros DMA2D Private Macros
* @{
*/
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
#define IS_DMA2D_LAYER(LAYER) ((LAYER) <= DMA2D_MAX_LAYER)
#define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
((MODE_ARGB) == DMA2D_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
#define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \
((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
#define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE)
#define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
#define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
#define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
((INPUT_CM) == CM_A4))
#define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \
((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \
((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \
((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \
((INPUT_CM) == DMA2D_INPUT_A4))
#define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
((AlphaMode) == DMA2D_COMBINE_ALPHA))
#define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
#define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
((RB_Swap) == DMA2D_RB_SWAP))
#define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
#define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
#define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
#define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
#define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
@ -522,24 +616,6 @@ uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
* @}
*/
/* Private functions prototypes ---------------------------------------------------------*/
/** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMA2D_Private_Functions DMA2D Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/

267
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief DMA Extension HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the DMA Extension peripheral:
@ -17,17 +17,17 @@
The DMA Extension HAL driver can be used as follows:
(+) Start a multi buffer transfer using the HAL_DMA_MultiBufferStart() function
for polling mode or HAL_DMA_MultiBufferStart_IT() for interrupt mode.
-@- In Memory-to-Memory transfer mode, Multi (Double) Buffer mode is not allowed.
-@- When Multi (Double) Buffer mode is enabled the, transfer is circular by default.
-@- When Multi (Double) Buffer mode is enabled, the transfer is circular by default.
-@- In Multi (Double) buffer mode, it is possible to update the base address for
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
the AHB memory port on the fly (DMA_SxM0AR or DMA_SxM1AR) when the stream is enabled.
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -79,40 +79,6 @@
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
/**
* @brief Set the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
hdma->Instance->PAR = DstAddress;
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
hdma->Instance->PAR = SrcAddress;
/* Configure DMA Stream destination address */
hdma->Instance->M0AR = DstAddress;
}
}
/**
* @}
*/
@ -126,7 +92,7 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
/** @addtogroup DMAEx_Exported_Functions_Group1
*
@verbatim
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
@ -154,39 +120,46 @@ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddres
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
hdma->State = HAL_DMA_STATE_BUSY_MEM0;
}
/* Current memory buffer used is Memory 1 */
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
{
hdma->State = HAL_DMA_STATE_BUSY_MEM1;
}
/* Check the parameters */
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Enable the double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
return HAL_OK;
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
status = HAL_ERROR;
}
else
{
/* Process Locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Enable the double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Return error status */
status = HAL_BUSY;
}
}
return status;
}
/**
@ -201,54 +174,66 @@ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t S
*/
HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength)
{
/* Process Locked */
__HAL_LOCK(hdma);
/* Current memory buffer used is Memory 0 */
if((hdma->Instance->CR & DMA_SxCR_CT) == 0)
{
hdma->State = HAL_DMA_STATE_BUSY_MEM0;
}
/* Current memory buffer used is Memory 1 */
else if((hdma->Instance->CR & DMA_SxCR_CT) != 0)
{
hdma->State = HAL_DMA_STATE_BUSY_MEM1;
}
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_DMA_BUFFER_SIZE(DataLength));
/* Disable the peripheral */
__HAL_DMA_DISABLE(hdma);
/* Enable the Double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Enable the transfer complete interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
/* Enable the Half transfer interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);
/* Enable the transfer Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
/* Enable the fifo Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_FE);
/* Enable the direct mode Error interrupt */
__HAL_DMA_ENABLE_IT(hdma, DMA_IT_DME);
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
return HAL_OK;
/* Memory-to-memory transfer not supported in double buffering mode */
if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY)
{
hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED;
return HAL_ERROR;
}
/* Process locked */
__HAL_LOCK(hdma);
if(HAL_DMA_STATE_READY == hdma->State)
{
/* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY;
/* Initialize the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
/* Enable the Double buffer mode */
hdma->Instance->CR |= (uint32_t)DMA_SxCR_DBM;
/* Configure DMA Stream destination address */
hdma->Instance->M1AR = SecondMemAddress;
/* Configure the source, destination address and the data length */
DMA_MultiBufferSetConfig(hdma, SrcAddress, DstAddress, DataLength);
/* Clear all flags */
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_DME_FLAG_INDEX(hdma));
__HAL_DMA_CLEAR_FLAG (hdma, __HAL_DMA_GET_FE_FLAG_INDEX(hdma));
/* Enable Common interrupts*/
hdma->Instance->CR |= DMA_IT_TC | DMA_IT_TE | DMA_IT_DME;
hdma->Instance->FCR |= DMA_IT_FE;
if((hdma->XferHalfCpltCallback != NULL) || (hdma->XferM1HalfCpltCallback != NULL))
{
hdma->Instance->CR |= DMA_IT_HT;
}
/* Enable the peripheral */
__HAL_DMA_ENABLE(hdma);
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdma);
/* Return error status */
status = HAL_BUSY;
}
return status;
}
/**
@ -277,7 +262,7 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
/* change the memory1 address */
hdma->Instance->M1AR = Address;
}
return HAL_OK;
}
@ -285,6 +270,48 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
* @}
*/
/**
* @}
*/
/** @addtogroup DMAEx_Private_Functions
* @{
*/
/**
* @brief Set the DMA Transfer parameter.
* @param hdma: pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @param SrcAddress: The source memory Buffer address
* @param DstAddress: The destination memory Buffer address
* @param DataLength: The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
{
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
/* Peripheral to Memory */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
hdma->Instance->PAR = DstAddress;
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
/* Memory to Peripheral */
else
{
/* Configure DMA Stream source address */
hdma->Instance->PAR = SrcAddress;
/* Configure DMA Stream destination address */
hdma->Instance->M0AR = DstAddress;
}
}
/**
* @}
*/

84
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dma_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -65,14 +65,52 @@
*/
typedef enum
{
MEMORY0 = 0x00, /*!< Memory 0 */
MEMORY1 = 0x01, /*!< Memory 1 */
MEMORY0 = 0x00U, /*!< Memory 0 */
MEMORY1 = 0x01U, /*!< Memory 1 */
}HAL_DMA_MemoryTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup DMA_Exported_Constants DMA Exported Constants
* @brief DMA Exported constants
* @{
*/
/** @defgroup DMAEx_Channel_selection DMA Channel selection
* @brief DMAEx channel selection
* @{
*/
#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */
#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */
#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/
#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/
#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/
#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/
#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/
#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup DMAEx_Exported_Functions DMAEx Exported Functions
@ -96,6 +134,42 @@ HAL_StatusTypeDef HAL_DMAEx_ChangeMemory(DMA_HandleTypeDef *hdma, uint32_t Addre
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup DMAEx_Private_Macros DMA Private Macros
* @brief DMAEx private macros
* @{
*/
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
((CHANNEL) == DMA_CHANNEL_1) || \
((CHANNEL) == DMA_CHANNEL_2) || \
((CHANNEL) == DMA_CHANNEL_3) || \
((CHANNEL) == DMA_CHANNEL_4) || \
((CHANNEL) == DMA_CHANNEL_5) || \
((CHANNEL) == DMA_CHANNEL_6) || \
((CHANNEL) == DMA_CHANNEL_7) || \
((CHANNEL) == DMA_CHANNEL_8) || \
((CHANNEL) == DMA_CHANNEL_9) || \
((CHANNEL) == DMA_CHANNEL_10) || \
((CHANNEL) == DMA_CHANNEL_11) || \
((CHANNEL) == DMA_CHANNEL_12) || \
((CHANNEL) == DMA_CHANNEL_13) || \
((CHANNEL) == DMA_CHANNEL_14) || \
((CHANNEL) == DMA_CHANNEL_15))
#else
#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
((CHANNEL) == DMA_CHANNEL_1) || \
((CHANNEL) == DMA_CHANNEL_2) || \
((CHANNEL) == DMA_CHANNEL_3) || \
((CHANNEL) == DMA_CHANNEL_4) || \
((CHANNEL) == DMA_CHANNEL_5) || \
((CHANNEL) == DMA_CHANNEL_6) || \
((CHANNEL) == DMA_CHANNEL_7))
#endif /* STM32F765xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup DMAEx_Private_Functions DMAEx Private Functions

2266
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.c Normal file
View File

File diff suppressed because it is too large Load Diff

1242
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_dsi.h Normal file
View File

File diff suppressed because it is too large Load Diff

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_eth.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

842
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_eth.h
View File

File diff suppressed because it is too large Load Diff

14
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@ -72,7 +72,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -118,8 +118,8 @@
/** @addtogroup FLASH_Private_Constants
* @{
*/
#define SECTOR_MASK ((uint32_t)0xFFFFFF07)
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000)/* 50 s */
#define SECTOR_MASK ((uint32_t)0xFFFFFF07U)
#define FLASH_TIMEOUT_VALUE ((uint32_t)50000U)/* 50 s */
/**
* @}
*/
@ -352,7 +352,7 @@ void HAL_FLASH_IRQHandler(void)
{
/* No more sectors to Erase, user callback can be called.*/
/* Reset Sector and stop Erase sectors procedure */
pFlash.Sector = temp = 0xFFFFFFFF;
pFlash.Sector = temp = 0xFFFFFFFFU;
/* FLASH EOP interrupt user callback */
HAL_FLASH_EndOfOperationCallback(temp);
/* Sector Erase procedure is completed */
@ -400,7 +400,7 @@ void HAL_FLASH_IRQHandler(void)
{
/* return the faulty sector */
temp = pFlash.Sector;
pFlash.Sector = 0xFFFFFFFF;
pFlash.Sector = 0xFFFFFFFFU;
break;
}
case FLASH_PROC_MASSERASE :

59
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_flash.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,7 +64,7 @@
*/
typedef enum
{
FLASH_PROC_NONE = 0,
FLASH_PROC_NONE = 0U,
FLASH_PROC_SECTERASE,
FLASH_PROC_MASSERASE,
FLASH_PROC_PROGRAM
@ -83,7 +83,7 @@ typedef struct
__IO uint8_t VoltageForErase; /* Internal variable to provide voltage range selected by user in IT context */
__IO uint32_t Sector; /* Internal variable to define the current sector which is erasing */
__IO uint32_t Address; /* Internal variable to save address selected for program */
HAL_LockTypeDef Lock; /* FLASH locking object */
@ -105,12 +105,12 @@ typedef struct
* @brief FLASH Error Code
* @{
*/
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002) /*!< Programming Sequence error */
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004) /*!< Programming Parallelism error */
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008) /*!< Programming Alignment error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010) /*!< Write protection error */
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020) /*!< Operation Error */
#define HAL_FLASH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_FLASH_ERROR_ERS ((uint32_t)0x00000002U) /*!< Programming Sequence error */
#define HAL_FLASH_ERROR_PGP ((uint32_t)0x00000004U) /*!< Programming Parallelism error */
#define HAL_FLASH_ERROR_PGA ((uint32_t)0x00000008U) /*!< Programming Alignment error */
#define HAL_FLASH_ERROR_WRP ((uint32_t)0x00000010U) /*!< Write protection error */
#define HAL_FLASH_ERROR_OPERATION ((uint32_t)0x00000020U) /*!< Operation Error */
/**
* @}
*/
@ -118,10 +118,10 @@ typedef struct
/** @defgroup FLASH_Type_Program FLASH Type Program
* @{
*/
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00) /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01) /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02) /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03) /*!< Program a double word (64-bit) at a specified address */
#define FLASH_TYPEPROGRAM_BYTE ((uint32_t)0x00U) /*!< Program byte (8-bit) at a specified address */
#define FLASH_TYPEPROGRAM_HALFWORD ((uint32_t)0x01U) /*!< Program a half-word (16-bit) at a specified address */
#define FLASH_TYPEPROGRAM_WORD ((uint32_t)0x02U) /*!< Program a word (32-bit) at a specified address */
#define FLASH_TYPEPROGRAM_DOUBLEWORD ((uint32_t)0x03U) /*!< Program a double word (64-bit) at a specified address */
/**
* @}
*/
@ -146,7 +146,7 @@ typedef struct
* @{
*/
#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of FLASH Operation Interrupt source */
#define FLASH_IT_ERR ((uint32_t)0x02000000) /*!< Error Interrupt source */
#define FLASH_IT_ERR ((uint32_t)0x02000000U) /*!< Error Interrupt source */
/**
* @}
*/
@ -154,11 +154,11 @@ typedef struct
/** @defgroup FLASH_Program_Parallelism FLASH Program Parallelism
* @{
*/
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000)
#define FLASH_PSIZE_BYTE ((uint32_t)0x00000000U)
#define FLASH_PSIZE_HALF_WORD ((uint32_t)FLASH_CR_PSIZE_0)
#define FLASH_PSIZE_WORD ((uint32_t)FLASH_CR_PSIZE_1)
#define FLASH_PSIZE_DOUBLE_WORD ((uint32_t)FLASH_CR_PSIZE)
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFF)
#define CR_PSIZE_MASK ((uint32_t)0xFFFFFCFFU)
/**
* @}
*/
@ -166,14 +166,29 @@ typedef struct
/** @defgroup FLASH_Keys FLASH Keys
* @{
*/
#define FLASH_KEY1 ((uint32_t)0x45670123)
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB)
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3B)
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7F)
#define FLASH_KEY1 ((uint32_t)0x45670123U)
#define FLASH_KEY2 ((uint32_t)0xCDEF89ABU)
#define FLASH_OPT_KEY1 ((uint32_t)0x08192A3BU)
#define FLASH_OPT_KEY2 ((uint32_t)0x4C5D6E7FU)
/**
* @}
*/
/** @defgroup FLASH_Sectors FLASH Sectors
* @{
*/
#define FLASH_SECTOR_0 ((uint32_t)0U) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1U) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2U) /*!< Sector Number 2 */
#define FLASH_SECTOR_3 ((uint32_t)3U) /*!< Sector Number 3 */
#define FLASH_SECTOR_4 ((uint32_t)4U) /*!< Sector Number 4 */
#define FLASH_SECTOR_5 ((uint32_t)5U) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6U) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7U) /*!< Sector Number 7 */
/**
* @}
*/
/**
* @}
*/

502
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@ -14,13 +14,13 @@
##### Flash Extension features #####
==============================================================================
[..] Comparing to other previous devices, the FLASH interface for STM32F727xx/437xx and
[..] Comparing to other previous devices, the FLASH interface for STM32F76xx/STM32F77xx
devices contains the following additional features
(+) Capacity up to 2 Mbyte with dual bank architecture supporting read-while-write
capability (RWW)
(+) Dual bank memory organization
(+) PCROP protection for all banks
(+) Dual boot mode
##### How to use this driver #####
==============================================================================
@ -39,18 +39,12 @@
(++) Set the Read protection Level
(++) Set the BOR level
(++) Program the user Option Bytes
(#) Advanced Option Bytes Programming functions: Use HAL_FLASHEx_AdvOBProgram() to :
(++) Extended space (bank 2) erase function
(++) Full FLASH space (2 Mo) erase (bank 1 and bank 2)
(++) Dual Boot activation
(++) Write protection configuration for bank 2
(++) PCROP protection configuration and control for both banks
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -117,11 +111,9 @@ extern FLASH_ProcessTypeDef pFlash;
* @{
*/
/* Option bytes control */
static void FLASH_MassErase(uint8_t VoltageRange);
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector);
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector);
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
static HAL_StatusTypeDef FLASH_OB_BOR_LevelConfig(uint8_t Level);
static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_t Address);
static uint32_t FLASH_OB_GetUser(void);
@ -130,6 +122,15 @@ static uint8_t FLASH_OB_GetRDP(void);
static uint32_t FLASH_OB_GetBOR(void);
static uint32_t FLASH_OB_GetBootAddress(uint32_t BootOption);
#if defined (FLASH_OPTCR_nDBANK)
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot);
#else
static void FLASH_MassErase(uint8_t VoltageRange);
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, uint32_t Iwdgstdby);
#endif /* FLASH_OPTCR_nDBANK */
extern HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/**
* @}
@ -182,13 +183,17 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
if(status == HAL_OK)
{
/*Initialization of SectorError variable*/
*SectorError = 0xFFFFFFFF;
*SectorError = 0xFFFFFFFFU;
if(pEraseInit->TypeErase == FLASH_TYPEERASE_MASSERASE)
{
/*Mass erase to be done*/
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
#if defined (FLASH_OPTCR_nDBANK)
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
#else
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
#endif /* FLASH_OPTCR_nDBANK */
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
@ -208,9 +213,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
/* If the erase operation is completed, disable the SER Bit */
FLASH->CR &= (~FLASH_CR_SER);
FLASH->CR &= SECTOR_MASK;
/* If the erase operation is completed, disable the SER Bit and SNB Bits */
CLEAR_BIT(FLASH->CR, (FLASH_CR_SER | FLASH_CR_SNB));
if(status != HAL_OK)
{
@ -259,7 +263,11 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
{
/*Mass erase to be done*/
pFlash.ProcedureOnGoing = FLASH_PROC_MASSERASE;
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
#if defined (FLASH_OPTCR_nDBANK)
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange, pEraseInit->Banks);
#else
FLASH_MassErase((uint8_t) pEraseInit->VoltageRange);
#endif /* FLASH_OPTCR_nDBANK */
}
else
{
@ -322,12 +330,23 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
/* USER configuration */
if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
{
#if defined (FLASH_OPTCR_nDBANK)
status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
pOBInit->USERConfig & OB_IWDG_SW,
pOBInit->USERConfig & OB_STOP_NO_RST,
pOBInit->USERConfig & OB_STDBY_NO_RST,
pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE,
pOBInit->USERConfig & OB_NDBANK_SINGLE_BANK,
pOBInit->USERConfig & OB_DUAL_BOOT_DISABLE);
#else
status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_WWDG_SW,
pOBInit->USERConfig & OB_IWDG_SW,
pOBInit->USERConfig & OB_STOP_NO_RST,
pOBInit->USERConfig & OB_STDBY_NO_RST,
pOBInit->USERConfig & OB_IWDG_STOP_ACTIVE,
pOBInit->USERConfig & OB_IWDG_STDBY_ACTIVE);
#endif /* FLASH_OPTCR_nDBANK */
}
/* BOR Level configuration */
@ -355,7 +374,7 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
}
/**
* @brief Get the Option byte configuration
* @brief Get the Option byte configuration
* @param pOBInit: pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
@ -384,11 +403,215 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
/*Get Boot Address when Boot pin = 1 */
pOBInit->BootAddr1 = FLASH_OB_GetBootAddress(OPTIONBYTE_BOOTADDR_1);
}
/**
* @}
*/
#if defined (FLASH_OPTCR_nDBANK)
/**
* @brief Full erase of FLASH memory sectors
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
* @arg VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
* @arg VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
* @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
* @param Banks: Banks to be erased
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Bank1 to be erased
* @arg FLASH_BANK_2: Bank2 to be erased
* @arg FLASH_BANK_BOTH: Bank1 and Bank2 to be erased
*
* @retval HAL Status
*/
static void FLASH_MassErase(uint8_t VoltageRange, uint32_t Banks)
{
/* Check the parameters */
assert_param(IS_VOLTAGERANGE(VoltageRange));
assert_param(IS_FLASH_BANK(Banks));
/* if the previous operation is completed, proceed to erase all sectors */
FLASH->CR &= CR_PSIZE_MASK;
if(Banks == FLASH_BANK_BOTH)
{
/* bank1 & bank2 will be erased*/
FLASH->CR |= FLASH_MER_BIT;
}
else if(Banks == FLASH_BANK_2)
{
/*Only bank2 will be erased*/
FLASH->CR |= FLASH_CR_MER2;
}
else
{
/*Only bank1 will be erased*/
FLASH->CR |= FLASH_CR_MER1;
}
FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
}
/**
* @brief Erase the specified FLASH memory sector
* @param Sector: FLASH sector to erase
* The value of this parameter depend on device used within the same series
* @param VoltageRange: The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
* @arg FLASH_VOLTAGE_RANGE_2: when the device voltage range is 2.1V to 2.7V,
* the operation will be done by half word (16-bit)
* @arg FLASH_VOLTAGE_RANGE_3: when the device voltage range is 2.7V to 3.6V,
* the operation will be done by word (32-bit)
* @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
* @retval None
*/
void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
{
uint32_t tmp_psize = 0;
/* Check the parameters */
assert_param(IS_FLASH_SECTOR(Sector));
assert_param(IS_VOLTAGERANGE(VoltageRange));
if(VoltageRange == FLASH_VOLTAGE_RANGE_1)
{
tmp_psize = FLASH_PSIZE_BYTE;
}
else if(VoltageRange == FLASH_VOLTAGE_RANGE_2)
{
tmp_psize = FLASH_PSIZE_HALF_WORD;
}
else if(VoltageRange == FLASH_VOLTAGE_RANGE_3)
{
tmp_psize = FLASH_PSIZE_WORD;
}
else
{
tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
}
/* Need to add offset of 4 when sector higher than FLASH_SECTOR_11 */
if(Sector > FLASH_SECTOR_11)
{
Sector += 4;
}
/* If the previous operation is completed, proceed to erase the sector */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= tmp_psize;
CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
FLASH->CR |= FLASH_CR_STRT;
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
}
/**
* @brief Return the FLASH Write Protection Option Bytes value.
* @retval uint32_t FLASH Write Protection Option Bytes value
*/
static uint32_t FLASH_OB_GetWRP(void)
{
/* Return the FLASH write protection Register value */
return ((uint32_t)(FLASH->OPTCR & 0x0FFF0000));
}
/**
* @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
* @param Wwdg: Selects the IWDG mode
* This parameter can be one of the following values:
* @arg OB_WWDG_SW: Software WWDG selected
* @arg OB_WWDG_HW: Hardware WWDG selected
* @param Iwdg: Selects the WWDG mode
* This parameter can be one of the following values:
* @arg OB_IWDG_SW: Software IWDG selected
* @arg OB_IWDG_HW: Hardware IWDG selected
* @param Stop: Reset event when entering STOP mode.
* This parameter can be one of the following values:
* @arg OB_STOP_NO_RST: No reset generated when entering in STOP
* @arg OB_STOP_RST: Reset generated when entering in STOP
* @param Stdby: Reset event when entering Standby mode.
* This parameter can be one of the following values:
* @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
* @param Iwdgstop: Independent watchdog counter freeze in Stop mode.
* This parameter can be one of the following values:
* @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP
* @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP
* @param Iwdgstdby: Independent watchdog counter freeze in standby mode.
* This parameter can be one of the following values:
* @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY
* @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY
* @param NDBank: Flash Single Bank mode enabled.
* This parameter can be one of the following values:
* @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank)
* @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode)
* @param NDBoot: Flash Dual boot mode disable.
* This parameter can be one of the following values:
* @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot
* @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint32_t Stop, uint32_t Stdby, uint32_t Iwdgstop, \
uint32_t Iwdgstdby, uint32_t NDBank, uint32_t NDBoot)
{
uint32_t useroptionmask = 0x00;
uint32_t useroptionvalue = 0x00;
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WWDG_SOURCE(Wwdg));
assert_param(IS_OB_IWDG_SOURCE(Iwdg));
assert_param(IS_OB_STOP_SOURCE(Stop));
assert_param(IS_OB_STDBY_SOURCE(Stdby));
assert_param(IS_OB_IWDG_STOP_FREEZE(Iwdgstop));
assert_param(IS_OB_IWDG_STDBY_FREEZE(Iwdgstdby));
assert_param(IS_OB_NDBANK(NDBank));
assert_param(IS_OB_NDBOOT(NDBoot));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
useroptionmask = (FLASH_OPTCR_WWDG_SW | FLASH_OPTCR_IWDG_SW | FLASH_OPTCR_nRST_STOP | \
FLASH_OPTCR_nRST_STDBY | FLASH_OPTCR_IWDG_STOP | FLASH_OPTCR_IWDG_STDBY | \
FLASH_OPTCR_nDBOOT | FLASH_OPTCR_nDBANK);
useroptionvalue = (Iwdg | Wwdg | Stop | Stdby | Iwdgstop | Iwdgstdby | NDBoot | NDBank);
/* Update User Option Byte */
MODIFY_REG(FLASH->OPTCR, useroptionmask, useroptionvalue);
}
return status;
}
/**
* @brief Return the FLASH User Option Byte value.
* @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
* nRST_STDBY(Bit7), nDBOOT(Bit28), nDBANK(Bit29), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
*/
static uint32_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return ((uint32_t)(FLASH->OPTCR & 0xF00000F0U));
}
#else
/**
* @brief Full erase of FLASH memory sectors
* @param VoltageRange: The device voltage range which defines the erase parallelism.
@ -412,7 +635,7 @@ static void FLASH_MassErase(uint8_t VoltageRange)
/* if the previous operation is completed, proceed to erase all sectors */
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_CR_MER;
FLASH->CR |= FLASH_CR_STRT | (VoltageRange <<8);
FLASH->CR |= FLASH_CR_STRT | ((uint32_t)VoltageRange <<8);
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
@ -473,100 +696,13 @@ void FLASH_Erase_Sector(uint32_t Sector, uint8_t VoltageRange)
}
/**
* @brief Enable the write protection of the desired bank1 or bank 2 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM7
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
* @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
* @arg OB_WRP_SECTOR_All
*
* @retval HAL FLASH State
* @brief Return the FLASH Write Protection Option Bytes value.
* @retval uint32_t FLASH Write Protection Option Bytes value
*/
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
static uint32_t FLASH_OB_GetWRP(void)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/*Write protection enabled on sectors */
FLASH->OPTCR &= (~WRPSector);
}
return status;
}
/**
* @brief Disable the write protection of the desired bank1 or bank 2 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
* @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7
* @arg OB_WRP_Sector_All
*
*
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Write protection disabled on sectors */
FLASH->OPTCR |= (WRPSector);
}
return status;
}
/**
* @brief Set the read protection level.
* @param Level: specifies the read protection level.
* This parameter can be one of the following values:
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_1: Read protection of the memory
* @arg OB_RDP_LEVEL_2: Full chip protection
*
* @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_RDP_LEVEL(Level));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
*(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
}
return status;
/* Return the FLASH write protection Register value */
return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
}
/**
@ -630,6 +766,119 @@ static HAL_StatusTypeDef FLASH_OB_UserConfig(uint32_t Wwdg, uint32_t Iwdg, uint3
}
/**
* @brief Return the FLASH User Option Byte value.
* @retval uint32_t FLASH User Option Bytes values: WWDG_SW(Bit4), IWDG_SW(Bit5), nRST_STOP(Bit6),
* nRST_STDBY(Bit7), IWDG_STDBY(Bit30) and IWDG_STOP(Bit31).
*/
static uint32_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
}
#endif /* FLASH_OPTCR_nDBANK */
/**
* @brief Enable the write protection of the desired bank1 or bank2 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM7
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
* @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
* or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
* or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
* @arg OB_WRP_SECTOR_All
*
* @retval HAL FLASH State
*/
static HAL_StatusTypeDef FLASH_OB_EnableWRP(uint32_t WRPSector)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/*Write protection enabled on sectors */
FLASH->OPTCR &= (~WRPSector);
}
return status;
}
/**
* @brief Disable the write protection of the desired bank1 or bank 2 sectors
*
* @note When the memory read protection level is selected (RDP level = 1),
* it is not possible to program or erase the flash sector i if CortexM4
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
*
* @param WRPSector: specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
* @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices)
* or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices)
* or a value between OB_WRP_DB_SECTOR_0 and OB_WRP_DB_SECTOR_23 (in Dual Bank mode for STM32F76xxx/STM32F77xxx devices)
* @arg OB_WRP_Sector_All
*
*
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_DisableWRP(uint32_t WRPSector)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_WRP_SECTOR(WRPSector));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
/* Write protection disabled on sectors */
FLASH->OPTCR |= (WRPSector);
}
return status;
}
/**
* @brief Set the read protection level.
* @param Level: specifies the read protection level.
* This parameter can be one of the following values:
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_1: Read protection of the memory
* @arg OB_RDP_LEVEL_2: Full chip protection
*
* @note WARNING: When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
*
* @retval HAL Status
*/
static HAL_StatusTypeDef FLASH_OB_RDP_LevelConfig(uint8_t Level)
{
HAL_StatusTypeDef status = HAL_OK;
/* Check the parameters */
assert_param(IS_OB_RDP_LEVEL(Level));
/* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation((uint32_t)FLASH_TIMEOUT_VALUE);
if(status == HAL_OK)
{
*(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = Level;
}
return status;
}
/**
* @brief Set the BOR Level.
* @param Level: specifies the Option Bytes BOR Reset Level.
@ -696,27 +945,6 @@ static HAL_StatusTypeDef FLASH_OB_BootAddressConfig(uint32_t BootOption, uint32_
return status;
}
/**
* @brief Return the FLASH User Option Byte value.
* @retval uint32_t FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
* and RST_STDBY(Bit2).
*/
static uint32_t FLASH_OB_GetUser(void)
{
/* Return the User Option Byte */
return ((uint32_t)(FLASH->OPTCR & 0xC00000F0));
}
/**
* @brief Return the FLASH Write Protection Option Bytes value.
* @retval uint32_t FLASH Write Protection Option Bytes value
*/
static uint32_t FLASH_OB_GetWRP(void)
{
/* Return the FLASH write protection Register value */
return ((uint32_t)(FLASH->OPTCR & 0x00FF0000));
}
/**
* @brief Returns the FLASH Read Protection level.
* @retval FlagStatus FLASH ReadOut Protection Status:

309
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_flash_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_flash_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of FLASH HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -67,6 +67,11 @@ typedef struct
uint32_t TypeErase; /*!< Mass erase or sector Erase.
This parameter can be a value of @ref FLASHEx_Type_Erase */
#if defined (FLASH_OPTCR_nDBANK)
uint32_t Banks; /*!< Select banks to erase when Mass erase is enabled.
This parameter must be a value of @ref FLASHEx_Banks */
#endif /* FLASH_OPTCR_nDBANK */
uint32_t Sector; /*!< Initial FLASH sector to erase when Mass erase is disabled
This parameter must be a value of @ref FLASHEx_Sectors */
@ -99,7 +104,8 @@ typedef struct
This parameter can be a value of @ref FLASHEx_BOR_Reset_Level */
uint32_t USERConfig; /*!< Program the FLASH User Option Byte: WWDG_SW / IWDG_SW / RST_STOP / RST_STDBY /
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY. */
IWDG_FREEZE_STOP / IWDG_FREEZE_SANDBY / nDBANK / nDBOOT.
nDBANK / nDBOOT are only available for STM32F76xxx/STM32F77xxx devices */
uint32_t BootAddr0; /*!< Boot base address when Boot pin = 0.
This parameter can be a value of @ref FLASHEx_Boot_Address */
@ -121,8 +127,8 @@ typedef struct
/** @defgroup FLASHEx_Type_Erase FLASH Type Erase
* @{
*/
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00) /*!< Sectors erase only */
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01) /*!< Flash Mass erase activation */
#define FLASH_TYPEERASE_SECTORS ((uint32_t)0x00U) /*!< Sectors erase only */
#define FLASH_TYPEERASE_MASSERASE ((uint32_t)0x01U) /*!< Flash Mass erase activation */
/**
* @}
*/
@ -130,10 +136,10 @@ typedef struct
/** @defgroup FLASHEx_Voltage_Range FLASH Voltage Range
* @{
*/
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00) /*!< Device operating range: 1.8V to 2.1V */
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01) /*!< Device operating range: 2.1V to 2.7V */
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02) /*!< Device operating range: 2.7V to 3.6V */
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
#define FLASH_VOLTAGE_RANGE_1 ((uint32_t)0x00U) /*!< Device operating range: 1.8V to 2.1V */
#define FLASH_VOLTAGE_RANGE_2 ((uint32_t)0x01U) /*!< Device operating range: 2.1V to 2.7V */
#define FLASH_VOLTAGE_RANGE_3 ((uint32_t)0x02U) /*!< Device operating range: 2.7V to 3.6V */
#define FLASH_VOLTAGE_RANGE_4 ((uint32_t)0x03U) /*!< Device operating range: 2.7V to 3.6V + External Vpp */
/**
* @}
*/
@ -141,8 +147,8 @@ typedef struct
/** @defgroup FLASHEx_WRP_State FLASH WRP State
* @{
*/
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00) /*!< Disable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01) /*!< Enable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_DISABLE ((uint32_t)0x00U) /*!< Disable the write protection of the desired bank 1 sectors */
#define OB_WRPSTATE_ENABLE ((uint32_t)0x01U) /*!< Enable the write protection of the desired bank 1 sectors */
/**
* @}
*/
@ -150,12 +156,12 @@ typedef struct
/** @defgroup FLASHEx_Option_Type FLASH Option Type
* @{
*/
#define OPTIONBYTE_WRP ((uint32_t)0x01) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08) /*!< BOR option byte configuration */
#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10) /*!< Boot 0 Address configuration */
#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20) /*!< Boot 1 Address configuration */
#define OPTIONBYTE_WRP ((uint32_t)0x01U) /*!< WRP option byte configuration */
#define OPTIONBYTE_RDP ((uint32_t)0x02U) /*!< RDP option byte configuration */
#define OPTIONBYTE_USER ((uint32_t)0x04U) /*!< USER option byte configuration */
#define OPTIONBYTE_BOR ((uint32_t)0x08U) /*!< BOR option byte configuration */
#define OPTIONBYTE_BOOTADDR_0 ((uint32_t)0x10U) /*!< Boot 0 Address configuration */
#define OPTIONBYTE_BOOTADDR_1 ((uint32_t)0x20U) /*!< Boot 1 Address configuration */
/**
* @}
*/
@ -163,9 +169,9 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASH Option Bytes Read Protection
* @{
*/
#define OB_RDP_LEVEL_0 ((uint8_t)0xAA)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCC) /*!< Warning: When enabling read protection level 2
#define OB_RDP_LEVEL_0 ((uint8_t)0xAAU)
#define OB_RDP_LEVEL_1 ((uint8_t)0x55U)
#define OB_RDP_LEVEL_2 ((uint8_t)0xCCU) /*!< Warning: When enabling read protection level 2
it s no more possible to go back to level 1 or 0 */
/**
* @}
@ -174,8 +180,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_WWatchdog FLASH Option Bytes WWatchdog
* @{
*/
#define OB_WWDG_SW ((uint32_t)0x10) /*!< Software WWDG selected */
#define OB_WWDG_HW ((uint32_t)0x00) /*!< Hardware WWDG selected */
#define OB_WWDG_SW ((uint32_t)0x10U) /*!< Software WWDG selected */
#define OB_WWDG_HW ((uint32_t)0x00U) /*!< Hardware WWDG selected */
/**
* @}
*/
@ -184,8 +190,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASH Option Bytes IWatchdog
* @{
*/
#define OB_IWDG_SW ((uint32_t)0x20) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint32_t)0x00) /*!< Hardware IWDG selected */
#define OB_IWDG_SW ((uint32_t)0x20U) /*!< Software IWDG selected */
#define OB_IWDG_HW ((uint32_t)0x00U) /*!< Hardware IWDG selected */
/**
* @}
*/
@ -193,8 +199,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASH Option Bytes nRST_STOP
* @{
*/
#define OB_STOP_NO_RST ((uint32_t)0x40) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint32_t)0x00) /*!< Reset generated when entering in STOP */
#define OB_STOP_NO_RST ((uint32_t)0x40U) /*!< No reset generated when entering in STOP */
#define OB_STOP_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STOP */
/**
* @}
*/
@ -202,8 +208,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASH Option Bytes nRST_STDBY
* @{
*/
#define OB_STDBY_NO_RST ((uint32_t)0x80) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint32_t)0x00) /*!< Reset generated when entering in STANDBY */
#define OB_STDBY_NO_RST ((uint32_t)0x80U) /*!< No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint32_t)0x00U) /*!< Reset generated when entering in STANDBY */
/**
* @}
*/
@ -211,8 +217,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_STOP FLASH IWDG Counter Freeze in STOP
* @{
*/
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000) /*!< IWDG counter active in STOP mode */
#define OB_IWDG_STOP_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STOP mode */
#define OB_IWDG_STOP_ACTIVE ((uint32_t)0x80000000U) /*!< IWDG counter active in STOP mode */
/**
* @}
*/
@ -220,8 +226,8 @@ typedef struct
/** @defgroup FLASHEx_Option_Bytes_IWDG_FREEZE_SANDBY FLASH IWDG Counter Freeze in STANDBY
* @{
*/
#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000) /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000) /*!< IWDG counter active in STANDBY mode */
#define OB_IWDG_STDBY_FREEZE ((uint32_t)0x00000000U) /*!< Freeze IWDG counter in STANDBY mode */
#define OB_IWDG_STDBY_ACTIVE ((uint32_t)0x40000000U) /*!< IWDG counter active in STANDBY mode */
/**
* @}
*/
@ -229,25 +235,47 @@ typedef struct
/** @defgroup FLASHEx_BOR_Reset_Level FLASH BOR Reset Level
* @{
*/
#define OB_BOR_LEVEL3 ((uint32_t)0x00) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint32_t)0x04) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint32_t)0x08) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint32_t)0x0C) /*!< Supply voltage ranges from 1.62 to 2.10 V */
#define OB_BOR_LEVEL3 ((uint32_t)0x00U) /*!< Supply voltage ranges from 2.70 to 3.60 V */
#define OB_BOR_LEVEL2 ((uint32_t)0x04U) /*!< Supply voltage ranges from 2.40 to 2.70 V */
#define OB_BOR_LEVEL1 ((uint32_t)0x08U) /*!< Supply voltage ranges from 2.10 to 2.40 V */
#define OB_BOR_OFF ((uint32_t)0x0CU) /*!< Supply voltage ranges from 1.62 to 2.10 V */
/**
* @}
*/
#if defined (FLASH_OPTCR_nDBOOT)
/** @defgroup FLASHEx_Option_Bytes_nDBOOT FLASH Option Bytes nDBOOT
* @{
*/
#define OB_DUAL_BOOT_DISABLE ((uint32_t)0x10000000U) /* !< Dual Boot disable. Boot according to boot address option */
#define OB_DUAL_BOOT_ENABLE ((uint32_t)0x00000000U) /* !< Dual Boot enable. Boot always from system memory if boot address in flash
(Dual bank Boot mode), or RAM if Boot address option in RAM */
/**
* @}
*/
#endif /* FLASH_OPTCR_nDBOOT */
#if defined (FLASH_OPTCR_nDBANK)
/** @defgroup FLASHEx_Option_Bytes_nDBank FLASH Single Bank or Dual Bank
* @{
*/
#define OB_NDBANK_SINGLE_BANK ((uint32_t)0x20000000U) /*!< NDBANK bit is set : Single Bank mode */
#define OB_NDBANK_DUAL_BANK ((uint32_t)0x00000000U) /*!< NDBANK bit is reset : Dual Bank mode */
/**
* @}
*/
#endif /* FLASH_OPTCR_nDBANK */
/** @defgroup FLASHEx_Boot_Address FLASH Boot Address
* @{
*/
#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000) /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040) /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080) /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000) /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000) /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004) /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013) /*!< Boot from SRAM2 (0x2004C000) */
#define OB_BOOTADDR_ITCM_RAM ((uint32_t)0x0000U) /*!< Boot from ITCM RAM (0x00000000) */
#define OB_BOOTADDR_SYSTEM ((uint32_t)0x0040U) /*!< Boot from System memory bootloader (0x00100000) */
#define OB_BOOTADDR_ITCM_FLASH ((uint32_t)0x0080U) /*!< Boot from Flash on ITCM interface (0x00200000) */
#define OB_BOOTADDR_AXIM_FLASH ((uint32_t)0x2000U) /*!< Boot from Flash on AXIM interface (0x08000000) */
#define OB_BOOTADDR_DTCM_RAM ((uint32_t)0x8000U) /*!< Boot from DTCM RAM (0x20000000) */
#define OB_BOOTADDR_SRAM1 ((uint32_t)0x8004U) /*!< Boot from SRAM1 (0x20010000) */
#define OB_BOOTADDR_SRAM2 ((uint32_t)0x8013U) /*!< Boot from SRAM2 (0x2004C000) */
/**
* @}
*/
@ -273,12 +301,28 @@ typedef struct
#define FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH Fifteen Latency cycles */
/**
* @}
*/
*/
#if defined (FLASH_OPTCR_nDBANK)
/** @defgroup FLASHEx_Banks FLASH Banks
* @{
*/
#define FLASH_BANK_1 ((uint32_t)0x01U) /*!< Bank 1 */
#define FLASH_BANK_2 ((uint32_t)0x02U) /*!< Bank 2 */
#define FLASH_BANK_BOTH ((uint32_t)(FLASH_BANK_1 | FLASH_BANK_2)) /*!< Bank1 and Bank2 */
/**
* @}
*/
#endif /* FLASH_OPTCR_nDBANK */
/** @defgroup FLASHEx_MassErase_bit FLASH Mass Erase bit
* @{
*/
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< MER bit to clear */
#if defined (FLASH_OPTCR_nDBANK)
#define FLASH_MER_BIT (FLASH_CR_MER1 | FLASH_CR_MER2) /*!< 2 MER bits */
#else
#define FLASH_MER_BIT (FLASH_CR_MER) /*!< only 1 MER bit */
#endif /* FLASH_OPTCR_nDBANK */
/**
* @}
*/
@ -286,41 +330,121 @@ typedef struct
/** @defgroup FLASHEx_Sectors FLASH Sectors
* @{
*/
#define FLASH_SECTOR_0 ((uint32_t)0) /*!< Sector Number 0 */
#define FLASH_SECTOR_1 ((uint32_t)1) /*!< Sector Number 1 */
#define FLASH_SECTOR_2 ((uint32_t)2) /*!< Sector Number 2 */
#define FLASH_SECTOR_3 ((uint32_t)3) /*!< Sector Number 3 */
#define FLASH_SECTOR_4 ((uint32_t)4) /*!< Sector Number 4 */
#define FLASH_SECTOR_5 ((uint32_t)5) /*!< Sector Number 5 */
#define FLASH_SECTOR_6 ((uint32_t)6) /*!< Sector Number 6 */
#define FLASH_SECTOR_7 ((uint32_t)7) /*!< Sector Number 7 */
#if (FLASH_SECTOR_TOTAL == 24)
#define FLASH_SECTOR_8 ((uint32_t)8U) /*!< Sector Number 8 */
#define FLASH_SECTOR_9 ((uint32_t)9U) /*!< Sector Number 9 */
#define FLASH_SECTOR_10 ((uint32_t)10U) /*!< Sector Number 10 */
#define FLASH_SECTOR_11 ((uint32_t)11U) /*!< Sector Number 11 */
#define FLASH_SECTOR_12 ((uint32_t)12U) /*!< Sector Number 12 */
#define FLASH_SECTOR_13 ((uint32_t)13U) /*!< Sector Number 13 */
#define FLASH_SECTOR_14 ((uint32_t)14U) /*!< Sector Number 14 */
#define FLASH_SECTOR_15 ((uint32_t)15U) /*!< Sector Number 15 */
#define FLASH_SECTOR_16 ((uint32_t)16U) /*!< Sector Number 16 */
#define FLASH_SECTOR_17 ((uint32_t)17U) /*!< Sector Number 17 */
#define FLASH_SECTOR_18 ((uint32_t)18U) /*!< Sector Number 18 */
#define FLASH_SECTOR_19 ((uint32_t)19U) /*!< Sector Number 19 */
#define FLASH_SECTOR_20 ((uint32_t)20U) /*!< Sector Number 20 */
#define FLASH_SECTOR_21 ((uint32_t)21U) /*!< Sector Number 21 */
#define FLASH_SECTOR_22 ((uint32_t)22U) /*!< Sector Number 22 */
#define FLASH_SECTOR_23 ((uint32_t)23U) /*!< Sector Number 23 */
#endif /* FLASH_SECTOR_TOTAL == 24 */
/**
* @}
*/
#if (FLASH_SECTOR_TOTAL == 24)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @note For Single Bank mode, use OB_WRP_SECTOR_x defines: In fact, in FLASH_OPTCR register,
* nWRP[11:0] bits contain the value of the write-protection option bytes for sectors 0 to 11.
* For Dual Bank mode, use OB_WRP_DB_SECTOR_x defines: In fact, in FLASH_OPTCR register,
* nWRP[11:0] bits are divided on two groups, one group dedicated for bank 1 and
* a second one dedicated for bank 2 (nWRP[i] activates Write protection on sector 2*i and 2*i+1).
* This behavior is applicable only for STM32F76xxx / STM32F77xxx devices.
* @{
*/
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000) /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000) /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000) /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000) /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000) /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000) /*!< Write protection of all Sectors */
/* Single Bank Sectors */
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Single Bank Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Single Bank Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Single Bank Sector2 */
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Single Bank Sector3 */
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Single Bank Sector4 */
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Single Bank Sector5 */
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Single Bank Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Single Bank Sector7 */
#define OB_WRP_SECTOR_8 ((uint32_t)0x01000000U) /*!< Write protection of Single Bank Sector8 */
#define OB_WRP_SECTOR_9 ((uint32_t)0x02000000U) /*!< Write protection of Single Bank Sector9 */
#define OB_WRP_SECTOR_10 ((uint32_t)0x04000000U) /*!< Write protection of Single Bank Sector10 */
#define OB_WRP_SECTOR_11 ((uint32_t)0x08000000U) /*!< Write protection of Single Bank Sector11 */
#define OB_WRP_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Single Bank Flash */
/* Dual Bank Sectors */
#define OB_WRP_DB_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector0 */
#define OB_WRP_DB_SECTOR_1 ((uint32_t)0x00010000U) /*!< Write protection of Dual Bank Sector1 */
#define OB_WRP_DB_SECTOR_2 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector2 */
#define OB_WRP_DB_SECTOR_3 ((uint32_t)0x00020000U) /*!< Write protection of Dual Bank Sector3 */
#define OB_WRP_DB_SECTOR_4 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector4 */
#define OB_WRP_DB_SECTOR_5 ((uint32_t)0x00040000U) /*!< Write protection of Dual Bank Sector5 */
#define OB_WRP_DB_SECTOR_6 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector6 */
#define OB_WRP_DB_SECTOR_7 ((uint32_t)0x00080000U) /*!< Write protection of Dual Bank Sector7 */
#define OB_WRP_DB_SECTOR_8 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector8 */
#define OB_WRP_DB_SECTOR_9 ((uint32_t)0x00100000U) /*!< Write protection of Dual Bank Sector9 */
#define OB_WRP_DB_SECTOR_10 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector10 */
#define OB_WRP_DB_SECTOR_11 ((uint32_t)0x00200000U) /*!< Write protection of Dual Bank Sector11 */
#define OB_WRP_DB_SECTOR_12 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector12 */
#define OB_WRP_DB_SECTOR_13 ((uint32_t)0x00400000U) /*!< Write protection of Dual Bank Sector13 */
#define OB_WRP_DB_SECTOR_14 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector14 */
#define OB_WRP_DB_SECTOR_15 ((uint32_t)0x00800000U) /*!< Write protection of Dual Bank Sector15 */
#define OB_WRP_DB_SECTOR_16 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector16 */
#define OB_WRP_DB_SECTOR_17 ((uint32_t)0x01000000U) /*!< Write protection of Dual Bank Sector17 */
#define OB_WRP_DB_SECTOR_18 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector18 */
#define OB_WRP_DB_SECTOR_19 ((uint32_t)0x02000000U) /*!< Write protection of Dual Bank Sector19 */
#define OB_WRP_DB_SECTOR_20 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector20 */
#define OB_WRP_DB_SECTOR_21 ((uint32_t)0x04000000U) /*!< Write protection of Dual Bank Sector21 */
#define OB_WRP_DB_SECTOR_22 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector22 */
#define OB_WRP_DB_SECTOR_23 ((uint32_t)0x08000000U) /*!< Write protection of Dual Bank Sector23 */
#define OB_WRP_DB_SECTOR_All ((uint32_t)0x0FFF0000U) /*!< Write protection of all Sectors for Dual Bank Flash */
/**
* @}
*/
#endif /* FLASH_SECTOR_TOTAL == 24 */
#if (FLASH_SECTOR_TOTAL == 8)
/** @defgroup FLASHEx_Option_Bytes_Write_Protection FLASH Option Bytes Write Protection
* @{
*/
#define OB_WRP_SECTOR_0 ((uint32_t)0x00010000U) /*!< Write protection of Sector0 */
#define OB_WRP_SECTOR_1 ((uint32_t)0x00020000U) /*!< Write protection of Sector1 */
#define OB_WRP_SECTOR_2 ((uint32_t)0x00040000U) /*!< Write protection of Sector2 */
#define OB_WRP_SECTOR_3 ((uint32_t)0x00080000U) /*!< Write protection of Sector3 */
#define OB_WRP_SECTOR_4 ((uint32_t)0x00100000U) /*!< Write protection of Sector4 */
#define OB_WRP_SECTOR_5 ((uint32_t)0x00200000U) /*!< Write protection of Sector5 */
#define OB_WRP_SECTOR_6 ((uint32_t)0x00400000U) /*!< Write protection of Sector6 */
#define OB_WRP_SECTOR_7 ((uint32_t)0x00800000U) /*!< Write protection of Sector7 */
#define OB_WRP_SECTOR_All ((uint32_t)0x00FF0000U) /*!< Write protection of all Sectors */
/**
* @}
*/
#endif /* FLASH_SECTOR_TOTAL == 8 */
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
* @{
*/
/**
* @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1)
* @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14].
* @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB)
* @retval The FLASH Boot Base Adress
*/
#define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup FLASHEx_Exported_Functions
* @{
@ -345,14 +469,6 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Constants FLASH Private Constants
* @{
*/
#define FLASH_SECTOR_TOTAL 8
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup FLASHEx_Private_Macros FLASH Private Macros
* @{
@ -376,13 +492,7 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#define IS_OPTIONBYTE(VALUE)(((VALUE) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER |\
OPTIONBYTE_BOR | OPTIONBYTE_BOOTADDR_0 | OPTIONBYTE_BOOTADDR_1)))
#define IS_OB_BOOT_ADDRESS(ADDRESS) (((ADDRESS) == OB_BOOTADDR_ITCM_RAM) || \
((ADDRESS) == OB_BOOTADDR_SYSTEM) || \
((ADDRESS) == OB_BOOTADDR_ITCM_FLASH) || \
((ADDRESS) == OB_BOOTADDR_AXIM_FLASH) || \
((ADDRESS) == OB_BOOTADDR_DTCM_RAM) || \
((ADDRESS) == OB_BOOTADDR_SRAM1) || \
((ADDRESS) == OB_BOOTADDR_SRAM2))
#define IS_OB_BOOT_ADDRESS(ADDRESS) ((ADDRESS) <= 0x8013)
#define IS_OB_RDP_LEVEL(LEVEL) (((LEVEL) == OB_RDP_LEVEL_0) ||\
((LEVEL) == OB_RDP_LEVEL_1) ||\
@ -422,14 +532,47 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
#define IS_FLASH_ADDRESS(ADDRESS) (((ADDRESS) >= FLASH_BASE) && ((ADDRESS) <= FLASH_END))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#define IS_FLASH_NBSECTORS(NBSECTORS) (((NBSECTORS) != 0U) && ((NBSECTORS) <= FLASH_SECTOR_TOTAL))
#if (FLASH_SECTOR_TOTAL == 8)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000) && ((SECTOR) != 0x00000000))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xFF00FFFF) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 8 */
#if (FLASH_SECTOR_TOTAL == 24)
#define IS_FLASH_SECTOR(SECTOR) (((SECTOR) == FLASH_SECTOR_0) || ((SECTOR) == FLASH_SECTOR_1) ||\
((SECTOR) == FLASH_SECTOR_2) || ((SECTOR) == FLASH_SECTOR_3) ||\
((SECTOR) == FLASH_SECTOR_4) || ((SECTOR) == FLASH_SECTOR_5) ||\
((SECTOR) == FLASH_SECTOR_6) || ((SECTOR) == FLASH_SECTOR_7) ||\
((SECTOR) == FLASH_SECTOR_8) || ((SECTOR) == FLASH_SECTOR_9) ||\
((SECTOR) == FLASH_SECTOR_10) || ((SECTOR) == FLASH_SECTOR_11) ||\
((SECTOR) == FLASH_SECTOR_12) || ((SECTOR) == FLASH_SECTOR_13) ||\
((SECTOR) == FLASH_SECTOR_14) || ((SECTOR) == FLASH_SECTOR_15) ||\
((SECTOR) == FLASH_SECTOR_16) || ((SECTOR) == FLASH_SECTOR_17) ||\
((SECTOR) == FLASH_SECTOR_18) || ((SECTOR) == FLASH_SECTOR_19) ||\
((SECTOR) == FLASH_SECTOR_20) || ((SECTOR) == FLASH_SECTOR_21) ||\
((SECTOR) == FLASH_SECTOR_22) || ((SECTOR) == FLASH_SECTOR_23))
#define IS_OB_WRP_SECTOR(SECTOR) ((((SECTOR) & (uint32_t)0xF000FFFFU) == 0x00000000U) && ((SECTOR) != 0x00000000U))
#endif /* FLASH_SECTOR_TOTAL == 24 */
#if defined (FLASH_OPTCR_nDBANK)
#define IS_OB_NDBANK(VALUE) (((VALUE) == OB_NDBANK_SINGLE_BANK) || \
((VALUE) == OB_NDBANK_DUAL_BANK))
#define IS_FLASH_BANK(BANK) (((BANK) == FLASH_BANK_1) || \
((BANK) == FLASH_BANK_2) || \
((BANK) == FLASH_BANK_BOTH))
#endif /* FLASH_OPTCR_nDBANK */
#if defined (FLASH_OPTCR_nDBOOT)
#define IS_OB_NDBOOT(VALUE) (((VALUE) == OB_DUAL_BOOT_DISABLE) || \
((VALUE) == OB_DUAL_BOOT_ENABLE))
#endif /* FLASH_OPTCR_nDBOOT */
/**
* @}

22
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief GPIO HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the General Purpose Input/Output (GPIO) peripheral:
@ -95,7 +95,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -141,15 +141,15 @@
/** @addtogroup GPIO_Private_Constants GPIO Private Constants
* @{
*/
#define GPIO_MODE ((uint32_t)0x00000003)
#define EXTI_MODE ((uint32_t)0x10000000)
#define GPIO_MODE_IT ((uint32_t)0x00010000)
#define GPIO_MODE_EVT ((uint32_t)0x00020000)
#define RISING_EDGE ((uint32_t)0x00100000)
#define FALLING_EDGE ((uint32_t)0x00200000)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010)
#define GPIO_MODE ((uint32_t)0x00000003U)
#define EXTI_MODE ((uint32_t)0x10000000U)
#define GPIO_MODE_IT ((uint32_t)0x00010000U)
#define GPIO_MODE_EVT ((uint32_t)0x00020000U)
#define RISING_EDGE ((uint32_t)0x00100000U)
#define FALLING_EDGE ((uint32_t)0x00200000U)
#define GPIO_OUTPUT_TYPE ((uint32_t)0x00000010U)
#define GPIO_NUMBER ((uint32_t)16)
#define GPIO_NUMBER ((uint32_t)16U)
/**
* @}
*/

80
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_gpio.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of GPIO HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -101,25 +101,25 @@ typedef enum
/** @defgroup GPIO_pins_define GPIO pins define
* @{
*/
#define GPIO_PIN_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFF) /* All pins selected */
#define GPIO_PIN_0 ((uint16_t)0x0001U) /* Pin 0 selected */
#define GPIO_PIN_1 ((uint16_t)0x0002U) /* Pin 1 selected */
#define GPIO_PIN_2 ((uint16_t)0x0004U) /* Pin 2 selected */
#define GPIO_PIN_3 ((uint16_t)0x0008U) /* Pin 3 selected */
#define GPIO_PIN_4 ((uint16_t)0x0010U) /* Pin 4 selected */
#define GPIO_PIN_5 ((uint16_t)0x0020U) /* Pin 5 selected */
#define GPIO_PIN_6 ((uint16_t)0x0040U) /* Pin 6 selected */
#define GPIO_PIN_7 ((uint16_t)0x0080U) /* Pin 7 selected */
#define GPIO_PIN_8 ((uint16_t)0x0100U) /* Pin 8 selected */
#define GPIO_PIN_9 ((uint16_t)0x0200U) /* Pin 9 selected */
#define GPIO_PIN_10 ((uint16_t)0x0400U) /* Pin 10 selected */
#define GPIO_PIN_11 ((uint16_t)0x0800U) /* Pin 11 selected */
#define GPIO_PIN_12 ((uint16_t)0x1000U) /* Pin 12 selected */
#define GPIO_PIN_13 ((uint16_t)0x2000U) /* Pin 13 selected */
#define GPIO_PIN_14 ((uint16_t)0x4000U) /* Pin 14 selected */
#define GPIO_PIN_15 ((uint16_t)0x8000U) /* Pin 15 selected */
#define GPIO_PIN_All ((uint16_t)0xFFFFU) /* All pins selected */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
#define GPIO_PIN_MASK ((uint32_t)0x0000FFFFU) /* PIN mask for assert test */
/**
* @}
*/
@ -134,21 +134,21 @@ typedef enum
* - Z : IO Direction mode (Input, Output, Alternate or Analog)
* @{
*/
#define GPIO_MODE_INPUT ((uint32_t)0x00000000) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_INPUT ((uint32_t)0x00000000U) /*!< Input Floating Mode */
#define GPIO_MODE_OUTPUT_PP ((uint32_t)0x00000001U) /*!< Output Push Pull Mode */
#define GPIO_MODE_OUTPUT_OD ((uint32_t)0x00000011U) /*!< Output Open Drain Mode */
#define GPIO_MODE_AF_PP ((uint32_t)0x00000002U) /*!< Alternate Function Push Pull Mode */
#define GPIO_MODE_AF_OD ((uint32_t)0x00000012U) /*!< Alternate Function Open Drain Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003) /*!< Analog Mode */
#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog Mode */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_IT_RISING ((uint32_t)0x10110000U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define GPIO_MODE_IT_FALLING ((uint32_t)0x10210000U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define GPIO_MODE_IT_RISING_FALLING ((uint32_t)0x10310000U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000) /*!< External Event Mode with Rising/Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING ((uint32_t)0x10120000U) /*!< External Event Mode with Rising edge trigger detection */
#define GPIO_MODE_EVT_FALLING ((uint32_t)0x10220000U) /*!< External Event Mode with Falling edge trigger detection */
#define GPIO_MODE_EVT_RISING_FALLING ((uint32_t)0x10320000U) /*!< External Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@ -157,10 +157,10 @@ typedef enum
* @brief GPIO Output Maximum frequency
* @{
*/
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002) /*!< Fast speed */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003) /*!< High speed */
#define GPIO_SPEED_FREQ_LOW ((uint32_t)0x00000000U) /*!< Low speed */
#define GPIO_SPEED_FREQ_MEDIUM ((uint32_t)0x00000001U) /*!< Medium speed */
#define GPIO_SPEED_FREQ_HIGH ((uint32_t)0x00000002U) /*!< Fast speed */
#define GPIO_SPEED_FREQ_VERY_HIGH ((uint32_t)0x00000003U) /*!< High speed */
/**
* @}
*/
@ -169,9 +169,9 @@ typedef enum
* @brief GPIO Pull-Up or Pull-Down Activation
* @{
*/
#define GPIO_NOPULL ((uint32_t)0x00000000) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002) /*!< Pull-down activation */
#define GPIO_NOPULL ((uint32_t)0x00000000U) /*!< No Pull-up or Pull-down activation */
#define GPIO_PULLUP ((uint32_t)0x00000001U) /*!< Pull-up activation */
#define GPIO_PULLDOWN ((uint32_t)0x00000002U) /*!< Pull-down activation */
/**
* @}
*/

278
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_gpio_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_gpio_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -68,128 +68,169 @@
/**
* @brief AF 0 selection
*/
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
#define GPIO_AF0_RTC_50Hz ((uint8_t)0x00U) /* RTC_50Hz Alternate Function mapping */
#define GPIO_AF0_MCO ((uint8_t)0x00U) /* MCO (MCO1 and MCO2) Alternate Function mapping */
#define GPIO_AF0_SWJ ((uint8_t)0x00U) /* SWJ (SWD and JTAG) Alternate Function mapping */
#define GPIO_AF0_TRACE ((uint8_t)0x00U) /* TRACE Alternate Function mapping */
/**
* @brief AF 1 selection
*/
#define GPIO_AF1_TIM1 ((uint8_t)0x01) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01) /* TIM2 Alternate Function mapping */
#define GPIO_AF1_TIM1 ((uint8_t)0x01U) /* TIM1 Alternate Function mapping */
#define GPIO_AF1_TIM2 ((uint8_t)0x01U) /* TIM2 Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF1_UART5 ((uint8_t)0x01U) /* UART5 Alternate Function mapping */
#define GPIO_AF1_I2C4 ((uint8_t)0x01U) /* I2C4 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 2 selection
*/
#define GPIO_AF2_TIM3 ((uint8_t)0x02) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02) /* TIM5 Alternate Function mapping */
#define GPIO_AF2_TIM3 ((uint8_t)0x02U) /* TIM3 Alternate Function mapping */
#define GPIO_AF2_TIM4 ((uint8_t)0x02U) /* TIM4 Alternate Function mapping */
#define GPIO_AF2_TIM5 ((uint8_t)0x02U) /* TIM5 Alternate Function mapping */
/**
* @brief AF 3 selection
*/
#define GPIO_AF3_TIM8 ((uint8_t)0x03) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03) /* TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03) /* TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03) /* TIM11 Alternate Function mapping */
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF3_CEC ((uint8_t)0x03) /* CEC Alternate Function mapping */
#define GPIO_AF3_TIM8 ((uint8_t)0x03U) /* TIM8 Alternate Function mapping */
#define GPIO_AF3_TIM9 ((uint8_t)0x03U) /* TIM9 Alternate Function mapping */
#define GPIO_AF3_TIM10 ((uint8_t)0x03U) /* TIM10 Alternate Function mapping */
#define GPIO_AF3_TIM11 ((uint8_t)0x03U) /* TIM11 Alternate Function mapping */
#define GPIO_AF3_LPTIM1 ((uint8_t)0x03U) /* LPTIM1 Alternate Function mapping */
#define GPIO_AF3_CEC ((uint8_t)0x03U) /* CEC Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF3_DFSDM1 ((uint8_t)0x03U) /* DFSDM1 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 4 selection
*/
#define GPIO_AF4_I2C1 ((uint8_t)0x04) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04) /* CEC Alternate Function mapping */
#define GPIO_AF4_I2C1 ((uint8_t)0x04U) /* I2C1 Alternate Function mapping */
#define GPIO_AF4_I2C2 ((uint8_t)0x04U) /* I2C2 Alternate Function mapping */
#define GPIO_AF4_I2C3 ((uint8_t)0x04U) /* I2C3 Alternate Function mapping */
#define GPIO_AF4_I2C4 ((uint8_t)0x04U) /* I2C4 Alternate Function mapping */
#define GPIO_AF4_CEC ((uint8_t)0x04U) /* CEC Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF4_USART1 ((uint8_t)0x04) /* USART1 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 5 selection
*/
#define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05) /* SPI6 Alternate Function mapping */
#define GPIO_AF5_SPI1 ((uint8_t)0x05U) /* SPI1 Alternate Function mapping */
#define GPIO_AF5_SPI2 ((uint8_t)0x05U) /* SPI2/I2S2 Alternate Function mapping */
#define GPIO_AF5_SPI3 ((uint8_t)0x05U) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF5_SPI4 ((uint8_t)0x05U) /* SPI4 Alternate Function mapping */
#define GPIO_AF5_SPI5 ((uint8_t)0x05U) /* SPI5 Alternate Function mapping */
#define GPIO_AF5_SPI6 ((uint8_t)0x05U) /* SPI6 Alternate Function mapping */
/**
* @brief AF 6 selection
*/
#define GPIO_AF6_SPI3 ((uint8_t)0x06) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06) /* SAI1 Alternate Function mapping */
#define GPIO_AF6_SPI3 ((uint8_t)0x06U) /* SPI3/I2S3 Alternate Function mapping */
#define GPIO_AF6_SAI1 ((uint8_t)0x06U) /* SAI1 Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF6_UART4 ((uint8_t)0x06U) /* UART4 Alternate Function mapping */
#define GPIO_AF6_DFSDM1 ((uint8_t)0x06U) /* DFSDM1 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 7 selection
*/
#define GPIO_AF7_USART1 ((uint8_t)0x07) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07) /* USART3 Alternate Function mapping */
#define GPIO_AF7_UART5 ((uint8_t)0x07) /* UART5 Alternate Function mapping */
#define GPIO_AF7_SPDIFRX ((uint8_t)0x07) /* SPDIF-RX Alternate Function mapping */
#define GPIO_AF7_SPI2 ((uint8_t)0x07) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07) /* SPI3 Alternate Function mapping */
#define GPIO_AF7_USART1 ((uint8_t)0x07U) /* USART1 Alternate Function mapping */
#define GPIO_AF7_USART2 ((uint8_t)0x07U) /* USART2 Alternate Function mapping */
#define GPIO_AF7_USART3 ((uint8_t)0x07U) /* USART3 Alternate Function mapping */
#define GPIO_AF7_UART5 ((uint8_t)0x07U) /* UART5 Alternate Function mapping */
#define GPIO_AF7_SPDIFRX ((uint8_t)0x07U) /* SPDIF-RX Alternate Function mapping */
#define GPIO_AF7_SPI2 ((uint8_t)0x07U) /* SPI2 Alternate Function mapping */
#define GPIO_AF7_SPI3 ((uint8_t)0x07U) /* SPI3 Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF7_SPI6 ((uint8_t)0x07U) /* SPI6 Alternate Function mapping */
#define GPIO_AF7_DFSDM1 ((uint8_t)0x07U) /* DFSDM1 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 8 selection
*/
#define GPIO_AF8_UART4 ((uint8_t)0x08) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08) /* UART5 Alternate Function mapping */
#define GPIO_AF8_USART6 ((uint8_t)0x08) /* USART6 Alternate Function mapping */
#define GPIO_AF8_UART7 ((uint8_t)0x08) /* UART7 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08) /* SPIDIF-RX Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08) /* SAI2 Alternate Function mapping */
#define GPIO_AF8_UART4 ((uint8_t)0x08U) /* UART4 Alternate Function mapping */
#define GPIO_AF8_UART5 ((uint8_t)0x08U) /* UART5 Alternate Function mapping */
#define GPIO_AF8_USART6 ((uint8_t)0x08U) /* USART6 Alternate Function mapping */
#define GPIO_AF8_UART7 ((uint8_t)0x08U) /* UART7 Alternate Function mapping */
#define GPIO_AF8_UART8 ((uint8_t)0x08U) /* UART8 Alternate Function mapping */
#define GPIO_AF8_SPDIFRX ((uint8_t)0x08U) /* SPIDIF-RX Alternate Function mapping */
#define GPIO_AF8_SAI2 ((uint8_t)0x08U) /* SAI2 Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF8_SPI6 ((uint8_t)0x08U) /* SPI6 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 9 selection
*/
#define GPIO_AF9_CAN1 ((uint8_t)0x09) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN2 ((uint8_t)0x09) /* CAN2 Alternate Function mapping */
#define GPIO_AF9_TIM12 ((uint8_t)0x09) /* TIM12 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09) /* QUADSPI Alternate Function mapping */
#if defined(STM32F746xx) || defined(STM32F756xx)
#define GPIO_AF9_LTDC ((uint8_t)0x09) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx */
#define GPIO_AF9_CAN1 ((uint8_t)0x09U) /* CAN1 Alternate Function mapping */
#define GPIO_AF9_CAN2 ((uint8_t)0x09U) /* CAN2 Alternate Function mapping */
#define GPIO_AF9_TIM12 ((uint8_t)0x09U) /* TIM12 Alternate Function mapping */
#define GPIO_AF9_TIM13 ((uint8_t)0x09U) /* TIM13 Alternate Function mapping */
#define GPIO_AF9_TIM14 ((uint8_t)0x09U) /* TIM14 Alternate Function mapping */
#define GPIO_AF9_QUADSPI ((uint8_t)0x09U) /* QUADSPI Alternate Function mapping */
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF9_LTDC ((uint8_t)0x09U) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F765xx) || defined(STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF9_FMC ((uint8_t)0x09U) /* FMC Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 10 selection
*/
#define GPIO_AF10_OTG_FS ((uint8_t)0xA) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0xA) /* OTG_HS Alternate Function mapping */
#define GPIO_AF10_QUADSPI ((uint8_t)0xA) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xA) /* SAI2 Alternate Function mapping */
#define GPIO_AF10_OTG_FS ((uint8_t)0xAU) /* OTG_FS Alternate Function mapping */
#define GPIO_AF10_OTG_HS ((uint8_t)0xAU) /* OTG_HS Alternate Function mapping */
#define GPIO_AF10_QUADSPI ((uint8_t)0xAU) /* QUADSPI Alternate Function mapping */
#define GPIO_AF10_SAI2 ((uint8_t)0xAU) /* SAI2 Alternate Function mapping */
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF10_DFSDM1 ((uint8_t)0x0AU) /* DFSDM1 Alternate Function mapping */
#define GPIO_AF10_SDMMC2 ((uint8_t)0x0AU) /* SDMMC2 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 11 selection
*/
#define GPIO_AF11_ETH ((uint8_t)0x0B) /* ETHERNET Alternate Function mapping */
#define GPIO_AF11_ETH ((uint8_t)0x0BU) /* ETHERNET Alternate Function mapping */
#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define GPIO_AF11_CAN3 ((uint8_t)0x0BU) /* CAN3 Alternate Function mapping */
#define GPIO_AF11_SDMMC2 ((uint8_t)0x0BU) /* SDMMC2 Alternate Function mapping */
#define GPIO_AF11_I2C4 ((uint8_t)0x0BU) /* I2C4 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 12 selection
*/
#define GPIO_AF12_FMC ((uint8_t)0xC) /* FMC Alternate Function mapping */
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xC) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xC) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_FMC ((uint8_t)0xCU) /* FMC Alternate Function mapping */
#define GPIO_AF12_OTG_HS_FS ((uint8_t)0xCU) /* OTG HS configured in FS, Alternate Function mapping */
#define GPIO_AF12_SDMMC1 ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
#if defined(STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define GPIO_AF12_MDIOS ((uint8_t)0xCU) /* SDMMC1 Alternate Function mapping */
#define GPIO_AF12_UART7 ((uint8_t)0xCU) /* UART7 Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 13 selection
*/
#define GPIO_AF13_DCMI ((uint8_t)0x0D) /* DCMI Alternate Function mapping */
#if defined(STM32F746xx) || defined(STM32F756xx)
#define GPIO_AF13_DCMI ((uint8_t)0x0DU) /* DCMI Alternate Function mapping */
#if defined (STM32F769xx) || defined (STM32F779xx)
#define GPIO_AF13_DSI ((uint8_t)0x0DU) /* DSI Alternate Function mapping */
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#if defined(STM32F746xx) || defined(STM32F756xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
#define GPIO_AF13_LTDC ((uint8_t)0x0DU) /* LTDC Alternate Function mapping */
/**
* @brief AF 14 selection
*/
#define GPIO_AF14_LTDC ((uint8_t)0x0E) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx */
#define GPIO_AF14_LTDC ((uint8_t)0x0EU) /* LCD-TFT Alternate Function mapping */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @brief AF 15 selection
*/
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0F) /* EVENTOUT Alternate Function mapping */
#define GPIO_AF15_EVENTOUT ((uint8_t)0x0FU) /* EVENTOUT Alternate Function mapping */
/**
@ -340,6 +381,101 @@
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
((AF) == GPIO_AF12_OTG_HS_FS) || ((AF) == GPIO_AF12_SDMMC1) || \
((AF) == GPIO_AF12_FMC) || ((AF) == GPIO_AF15_EVENTOUT))
#elif defined(STM32F767xx) || defined(STM32F777xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
((AF) == GPIO_AF10_OTG_FS) || ((AF) == GPIO_AF9_LTDC) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
((AF) == GPIO_AF14_LTDC))
#elif defined(STM32F769xx) || defined(STM32F779xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
((AF) == GPIO_AF9_LTDC) || ((AF) == GPIO_AF10_OTG_FS) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
((AF) == GPIO_AF14_LTDC) || ((AF) == GPIO_AF13_DSI))
#elif defined(STM32F765xx)
#define IS_GPIO_AF(AF) (((AF) == GPIO_AF0_RTC_50Hz) || ((AF) == GPIO_AF1_TIM1) || \
((AF) == GPIO_AF0_SWJ) || ((AF) == GPIO_AF0_TRACE) || \
((AF) == GPIO_AF0_MCO) || ((AF) == GPIO_AF1_TIM2) || \
((AF) == GPIO_AF2_TIM3) || ((AF) == GPIO_AF2_TIM4) || \
((AF) == GPIO_AF2_TIM5) || ((AF) == GPIO_AF3_TIM8) || \
((AF) == GPIO_AF3_TIM9) || ((AF) == GPIO_AF3_TIM10) || \
((AF) == GPIO_AF3_TIM11) || ((AF) == GPIO_AF3_LPTIM1) || \
((AF) == GPIO_AF3_CEC) || ((AF) == GPIO_AF4_CEC) || \
((AF) == GPIO_AF4_I2C1) || ((AF) == GPIO_AF4_I2C2) || \
((AF) == GPIO_AF4_I2C3) || ((AF) == GPIO_AF4_I2C4) || \
((AF) == GPIO_AF5_SPI1) || ((AF) == GPIO_AF5_SPI2) || \
((AF) == GPIO_AF5_SPI3) || ((AF) == GPIO_AF5_SPI4) || \
((AF) == GPIO_AF5_SPI5) || ((AF) == GPIO_AF5_SPI6) || \
((AF) == GPIO_AF6_SPI3) || ((AF) == GPIO_AF6_SAI1) || \
((AF) == GPIO_AF7_SPI3) || ((AF) == GPIO_AF7_SPI2) || \
((AF) == GPIO_AF7_USART1) || ((AF) == GPIO_AF7_USART2) || \
((AF) == GPIO_AF7_USART3) || ((AF) == GPIO_AF7_UART5) || \
((AF) == GPIO_AF7_SPDIFRX) || ((AF) == GPIO_AF8_SPDIFRX) || \
((AF) == GPIO_AF8_SAI2) || ((AF) == GPIO_AF8_USART6) || \
((AF) == GPIO_AF8_UART4) || ((AF) == GPIO_AF8_UART5) || \
((AF) == GPIO_AF8_UART7) || ((AF) == GPIO_AF8_UART8) || \
((AF) == GPIO_AF9_CAN1) || ((AF) == GPIO_AF9_CAN2) || \
((AF) == GPIO_AF9_TIM12) || ((AF) == GPIO_AF9_TIM12) || \
((AF) == GPIO_AF9_TIM14) || ((AF) == GPIO_AF9_QUADSPI) || \
((AF) == GPIO_AF10_OTG_HS) || ((AF) == GPIO_AF10_SAI2) || \
((AF) == GPIO_AF10_QUADSPI) || ((AF) == GPIO_AF11_ETH) || \
((AF) == GPIO_AF11_CAN3) || ((AF) == GPIO_AF12_OTG_HS_FS) || \
((AF) == GPIO_AF12_SDMMC1) || ((AF) == GPIO_AF12_FMC) || \
((AF) == GPIO_AF15_EVENTOUT) || ((AF) == GPIO_AF13_DCMI) || \
((AF) == GPIO_AF10_OTG_FS))
#endif /* STM32F756xx || STM32F746xx */
/**
* @}

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@ -68,7 +68,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -102,7 +102,7 @@
* @{
*/
#if defined(STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup HASH HASH
* @brief HASH HAL module driver.
@ -1869,7 +1869,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash)
/**
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}

32
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_hash.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined(STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -85,11 +85,11 @@ typedef struct
typedef enum
{
HAL_HASH_STATE_RESET = 0x00, /*!< HASH not yet initialized or disabled */
HAL_HASH_STATE_READY = 0x01, /*!< HASH initialized and ready for use */
HAL_HASH_STATE_BUSY = 0x02, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x03, /*!< HASH timeout state */
HAL_HASH_STATE_ERROR = 0x04 /*!< HASH error state */
HAL_HASH_STATE_RESET = 0x00U, /*!< HASH not yet initialized or disabled */
HAL_HASH_STATE_READY = 0x01U, /*!< HASH initialized and ready for use */
HAL_HASH_STATE_BUSY = 0x02U, /*!< HASH internal process is ongoing */
HAL_HASH_STATE_TIMEOUT = 0x03U, /*!< HASH timeout state */
HAL_HASH_STATE_ERROR = 0x04U /*!< HASH error state */
}HAL_HASH_StateTypeDef;
/**
@ -102,8 +102,8 @@ typedef enum
typedef enum
{
HAL_HASH_PHASE_READY = 0x01, /*!< HASH peripheral is ready for initialization */
HAL_HASH_PHASE_PROCESS = 0x02, /*!< HASH peripheral is in processing phase */
HAL_HASH_PHASE_READY = 0x01U, /*!< HASH peripheral is ready for initialization */
HAL_HASH_PHASE_PROCESS = 0x02U, /*!< HASH peripheral is in processing phase */
}HAL_HASHPhaseTypeDef;
/**
@ -156,7 +156,7 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group1 HASH Algorithm Selection
* @{
*/
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000) /*!< HASH function is SHA1 */
#define HASH_ALGOSELECTION_SHA1 ((uint32_t)0x0000U) /*!< HASH function is SHA1 */
#define HASH_ALGOSELECTION_SHA224 HASH_CR_ALGO_1 /*!< HASH function is SHA224 */
#define HASH_ALGOSELECTION_SHA256 HASH_CR_ALGO /*!< HASH function is SHA256 */
#define HASH_ALGOSELECTION_MD5 HASH_CR_ALGO_0 /*!< HASH function is MD5 */
@ -167,7 +167,7 @@ typedef struct
/** @defgroup HASH_Exported_Constants_Group2 HASH Algorithm Mode
* @{
*/
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000) /*!< Algorithm is HASH */
#define HASH_ALGOMODE_HASH ((uint32_t)0x00000000U) /*!< Algorithm is HASH */
#define HASH_ALGOMODE_HMAC HASH_CR_MODE /*!< Algorithm is HMAC */
/**
* @}
@ -176,7 +176,7 @@ typedef struct
/** @defgroup HASH_Data_Type HASH Data Type
* @{
*/
#define HASH_DATATYPE_32B ((uint32_t)0x0000) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_32B ((uint32_t)0x0000U) /*!< 32-bit data. No swapping */
#define HASH_DATATYPE_16B HASH_CR_DATATYPE_0 /*!< 16-bit data. Each half word is swapped */
#define HASH_DATATYPE_8B HASH_CR_DATATYPE_1 /*!< 8-bit data. All bytes are swapped */
#define HASH_DATATYPE_1B HASH_CR_DATATYPE /*!< 1-bit data. In the word all bits are swapped */
@ -188,7 +188,7 @@ typedef struct
* @brief HASH HMAC Long key used only for HMAC mode
* @{
*/
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
#define HASH_HMAC_KEYTYPE_SHORTKEY ((uint32_t)0x00000000U) /*!< HMAC Key is <= 64 bytes */
#define HASH_HMAC_KEYTYPE_LONGKEY HASH_CR_LKEY /*!< HMAC Key is > 64 bytes */
/**
* @}
@ -435,7 +435,7 @@ void HAL_HASH_ErrorCallback(HASH_HandleTypeDef *hhash);
/**
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@ -65,7 +65,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -98,7 +98,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined(STM32F756xx)
#if defined(STM32F756xx) || defined(STM32F777xx) || defined(STM32F779xx)
/** @defgroup HASHEx HASHEx
* @brief HASH Extension HAL module driver.
@ -1627,7 +1627,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t
/**
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hash_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of HASH HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,7 @@
extern "C" {
#endif
#if defined(STM32F756xx)
#if defined (STM32F756xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -185,7 +185,7 @@ void HAL_HASHEx_IRQHandler(HASH_HandleTypeDef *hhash);
/**
* @}
*/
#endif /* STM32F756xx */
#endif /* STM32F756xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

10
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -44,7 +44,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -1188,10 +1188,6 @@ static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
}
HAL_HCD_Connect_Callback(hhcd);
if(hhcd->Init.speed == HCD_SPEED_HIGH)
{
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
}
}
else
{

28
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_hcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -65,11 +65,11 @@
*/
typedef enum
{
HAL_HCD_STATE_RESET = 0x00,
HAL_HCD_STATE_READY = 0x01,
HAL_HCD_STATE_ERROR = 0x02,
HAL_HCD_STATE_BUSY = 0x03,
HAL_HCD_STATE_TIMEOUT = 0x04
HAL_HCD_STATE_RESET = 0x00U,
HAL_HCD_STATE_READY = 0x01U,
HAL_HCD_STATE_ERROR = 0x02U,
HAL_HCD_STATE_BUSY = 0x03U,
HAL_HCD_STATE_TIMEOUT = 0x04U
} HCD_StateTypeDef;
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
@ -109,9 +109,9 @@ typedef struct
/** @defgroup HCD_Speed HCD Speed
* @{
*/
#define HCD_SPEED_HIGH 0
#define HCD_SPEED_LOW 2
#define HCD_SPEED_FULL 3
#define HCD_SPEED_HIGH 0U
#define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3U
/**
* @}
*/
@ -119,8 +119,8 @@ typedef struct
/** @defgroup HCD_PHY_Module HCD PHY Module
* @{
*/
#define HCD_PHY_ULPI 1
#define HCD_PHY_EMBEDDED 2
#define HCD_PHY_ULPI 1U
#define HCD_PHY_EMBEDDED 2U
/**
* @}
*/
@ -139,7 +139,7 @@ typedef struct
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0)
#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)

4648
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.c
View File

File diff suppressed because it is too large Load Diff

515
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_I2C_H
@ -54,7 +54,7 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
* @{
*/
@ -73,22 +73,22 @@ typedef struct
This parameter can be a 7-bit or 10-bit address. */
uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
This parameter can be a value of @ref I2C_addressing_mode */
This parameter can be a value of @ref I2C_ADDRESSING_MODE */
uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected.
This parameter can be a value of @ref I2C_dual_addressing_mode */
This parameter can be a value of @ref I2C_DUAL_ADDRESSING_MODE */
uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected
This parameter can be a 7-bit address. */
uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_own_address2_masks */
uint32_t OwnAddress2Masks; /*!< Specifies the acknowledge mask address second device own address if dual addressing mode is selected
This parameter can be a value of @ref I2C_OWN_ADDRESS2_MASKS */
uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected.
This parameter can be a value of @ref I2C_general_call_addressing_mode */
This parameter can be a value of @ref I2C_GENERAL_CALL_ADDRESSING_MODE */
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_nostretch_mode */
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
}I2C_InitTypeDef;
@ -97,25 +97,82 @@ typedef struct
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
* @brief HAL State structure definition
* @note HAL I2C State value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : Abort (Abort user request on going)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP initialized and ready to use. HAL I2C Init function called)
* b4 (not used)
* x : Should be set to 0
* b3
* 0 : Ready or Busy (No Listen mode ongoing)
* 1 : Listen (IP in Address Listen Mode)
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* @{
*/
typedef enum
{
HAL_I2C_STATE_RESET = 0x00, /*!< I2C not yet initialized or disabled */
HAL_I2C_STATE_READY = 0x01, /*!< I2C initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x02, /*!< I2C internal process is ongoing */
HAL_I2C_STATE_MASTER_BUSY_TX = 0x12, /*!< Master Data Transmission process is ongoing */
HAL_I2C_STATE_MASTER_BUSY_RX = 0x22, /*!< Master Data Reception process is ongoing */
HAL_I2C_STATE_SLAVE_BUSY_TX = 0x32, /*!< Slave Data Transmission process is ongoing */
HAL_I2C_STATE_SLAVE_BUSY_RX = 0x42, /*!< Slave Data Reception process is ongoing */
HAL_I2C_STATE_MEM_BUSY_TX = 0x52, /*!< Memory Data Transmission process is ongoing */
HAL_I2C_STATE_MEM_BUSY_RX = 0x62, /*!< Memory Data Reception process is ongoing */
HAL_I2C_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_I2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_I2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
HAL_I2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_I2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_I2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_I2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
process is ongoing */
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
process is ongoing */
HAL_I2C_STATE_ABORT = 0x60, /*!< Abort user request ongoing */
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
}HAL_I2C_StateTypeDef;
/**
* @}
*/
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
* @note HAL I2C Mode value coding follow below described bitmap :
* b7 (not used)
* x : Should be set to 0
* b6
* 0 : None
* 1 : Memory (HAL I2C communication is in Memory Mode)
* b5
* 0 : None
* 1 : Slave (HAL I2C communication is in Slave Mode)
* b4
* 0 : None
* 1 : Master (HAL I2C communication is in Master Mode)
* b3-b2-b1-b0 (not used)
* xxxx : Should be set to 0000
* @{
*/
typedef enum
{
HAL_I2C_MODE_NONE = 0x00U, /*!< No I2C communication on going */
HAL_I2C_MODE_MASTER = 0x10U, /*!< I2C communication is in Master Mode */
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
}HAL_I2C_ModeTypeDef;
/**
* @}
*/
@ -123,45 +180,56 @@ typedef enum
/** @defgroup I2C_Error_Code_definition I2C Error Code definition
* @brief I2C Error Code definition
* @{
*/
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002) /*!< ARLO error */
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008) /*!< OVR error */
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040) /*!< Size Management error */
/**
*/
#define HAL_I2C_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_I2C_ERROR_BERR ((uint32_t)0x00000001U) /*!< BERR error */
#define HAL_I2C_ERROR_ARLO ((uint32_t)0x00000002U) /*!< ARLO error */
#define HAL_I2C_ERROR_AF ((uint32_t)0x00000004U) /*!< ACKF error */
#define HAL_I2C_ERROR_OVR ((uint32_t)0x00000008U) /*!< OVR error */
#define HAL_I2C_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
#define HAL_I2C_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
#define HAL_I2C_ERROR_SIZE ((uint32_t)0x00000040U) /*!< Size Management error */
#define HAL_I2C_ERROR_ABORT ((uint32_t)0x00000080U) /*!< Abort user request */
/**
* @}
*/
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
/** @defgroup I2C_handle_Structure_definition I2C handle Structure definition
* @brief I2C handle Structure definition
* @{
*/
typedef struct
typedef struct __I2C_HandleTypeDef
{
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_TypeDef *Instance; /*!< I2C registers base address */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
I2C_InitTypeDef Init; /*!< I2C communication parameters */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint8_t *pBuffPtr; /*!< Pointer to I2C transfer buffer */
uint16_t XferSize; /*!< I2C transfer size */
uint16_t XferSize; /*!< I2C transfer size */
__IO uint16_t XferCount; /*!< I2C transfer counter */
__IO uint16_t XferCount; /*!< I2C transfer counter */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
__IO uint32_t XferOptions; /*!< I2C sequantial transfer options, this parameter can
be a value of @ref I2C_XFEROPTIONS */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
HAL_LockTypeDef Lock; /*!< I2C locking object */
HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
__IO uint32_t ErrorCode; /*!< I2C Error code */
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
HAL_LockTypeDef Lock; /*!< I2C locking object */
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
__IO HAL_I2C_ModeTypeDef Mode; /*!< I2C communication mode */
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
}I2C_HandleTypeDef;
/**
* @}
@ -176,80 +244,101 @@ typedef struct
* @{
*/
/** @defgroup I2C_addressing_mode I2C addressing mode
/** @defgroup I2C_XFEROPTIONS I2C Sequential Transfer Options
* @{
*/
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001)
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002)
#define I2C_NO_OPTION_FRAME ((uint32_t)0xFFFF0000U)
#define I2C_FIRST_FRAME ((uint32_t)I2C_SOFTEND_MODE)
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
/**
* @}
*/
/** @defgroup I2C_dual_addressing_mode I2C dual addressing mode
/** @defgroup I2C_ADDRESSING_MODE I2C Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000)
#define I2C_ADDRESSINGMODE_7BIT ((uint32_t)0x00000001U)
#define I2C_ADDRESSINGMODE_10BIT ((uint32_t)0x00000002U)
/**
* @}
*/
/** @defgroup I2C_DUAL_ADDRESSING_MODE I2C Dual Addressing Mode
* @{
*/
#define I2C_DUALADDRESS_DISABLE ((uint32_t)0x00000000U)
#define I2C_DUALADDRESS_ENABLE I2C_OAR2_OA2EN
/**
* @}
*/
/** @defgroup I2C_own_address2_masks I2C own address2 masks
/** @defgroup I2C_OWN_ADDRESS2_MASKS I2C Own Address2 Masks
* @{
*/
#define I2C_OA2_NOMASK ((uint8_t)0x00)
#define I2C_OA2_MASK01 ((uint8_t)0x01)
#define I2C_OA2_MASK02 ((uint8_t)0x02)
#define I2C_OA2_MASK03 ((uint8_t)0x03)
#define I2C_OA2_MASK04 ((uint8_t)0x04)
#define I2C_OA2_MASK05 ((uint8_t)0x05)
#define I2C_OA2_MASK06 ((uint8_t)0x06)
#define I2C_OA2_MASK07 ((uint8_t)0x07)
#define I2C_OA2_NOMASK ((uint8_t)0x00U)
#define I2C_OA2_MASK01 ((uint8_t)0x01U)
#define I2C_OA2_MASK02 ((uint8_t)0x02U)
#define I2C_OA2_MASK03 ((uint8_t)0x03U)
#define I2C_OA2_MASK04 ((uint8_t)0x04U)
#define I2C_OA2_MASK05 ((uint8_t)0x05U)
#define I2C_OA2_MASK06 ((uint8_t)0x06U)
#define I2C_OA2_MASK07 ((uint8_t)0x07U)
/**
* @}
*/
/** @defgroup I2C_general_call_addressing_mode I2C general call addressing mode
/** @defgroup I2C_GENERAL_CALL_ADDRESSING_MODE I2C General Call Addressing Mode
* @{
*/
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000)
#define I2C_GENERALCALL_DISABLE ((uint32_t)0x00000000U)
#define I2C_GENERALCALL_ENABLE I2C_CR1_GCEN
/**
* @}
*/
/** @defgroup I2C_nostretch_mode I2C nostretch mode
/** @defgroup I2C_NOSTRETCH_MODE I2C No-Stretch Mode
* @{
*/
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000)
#define I2C_NOSTRETCH_DISABLE ((uint32_t)0x00000000U)
#define I2C_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH
/**
* @}
*/
/** @defgroup I2C_Memory_Address_Size I2C Memory Address Size
/** @defgroup I2C_MEMORY_ADDRESS_SIZE I2C Memory Address Size
* @{
*/
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002)
#define I2C_MEMADD_SIZE_8BIT ((uint32_t)0x00000001U)
#define I2C_MEMADD_SIZE_16BIT ((uint32_t)0x00000002U)
/**
* @}
*/
*/
/** @defgroup I2C_ReloadEndMode_definition I2C ReloadEndMode definition
/** @defgroup I2C_XferDirection I2C Transfer Direction
* @{
*/
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000)
#define I2C_DIRECTION_TRANSMIT ((uint32_t)0x00000000U)
#define I2C_DIRECTION_RECEIVE ((uint32_t)0x00000001U)
/**
* @}
*/
/** @defgroup I2C_StartStopMode_definition I2C StartStopMode definition
/** @defgroup I2C_RELOAD_END_MODE I2C Reload End Mode
* @{
*/
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000)
#define I2C_RELOAD_MODE I2C_CR2_RELOAD
#define I2C_AUTOEND_MODE I2C_CR2_AUTOEND
#define I2C_SOFTEND_MODE ((uint32_t)0x00000000U)
/**
* @}
*/
/** @defgroup I2C_START_STOP_MODE I2C Start or Stop Mode
* @{
*/
#define I2C_NO_STARTSTOP ((uint32_t)0x00000000U)
#define I2C_GENERATE_STOP I2C_CR2_STOP
#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
#define I2C_GENERATE_START_WRITE I2C_CR2_START
@ -270,7 +359,6 @@ typedef struct
#define I2C_IT_ADDRI I2C_CR1_ADDRIE
#define I2C_IT_RXI I2C_CR1_RXIE
#define I2C_IT_TXI I2C_CR1_TXIE
/**
* @}
*/
@ -308,122 +396,127 @@ typedef struct
* @{
*/
/** @brief Reset I2C handle state
* @param __HANDLE__: specifies the I2C Handle.
/** @brief Reset I2C handle state.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable the specified I2C interrupts.
* @param __HANDLE__: specifies the I2C Handle.
* @param __INTERRUPT__: specifies the interrupt source to enable.
/** @brief Enable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to enable.
* This parameter can be one of the following values:
* @arg I2C_IT_ERRI: Errors interrupt enable
* @arg I2C_IT_TCI: Transfer complete interrupt enable
* @arg I2C_IT_STOPI: STOP detection interrupt enable
* @arg I2C_IT_NACKI: NACK received interrupt enable
* @arg I2C_IT_ADDRI: Address match interrupt enable
* @arg I2C_IT_RXI: RX interrupt enable
* @arg I2C_IT_TXI: TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Disable the specified I2C interrupts.
* @param __HANDLE__: specifies the I2C Handle.
* @param __INTERRUPT__: specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg I2C_IT_ERRI: Errors interrupt enable
* @arg I2C_IT_TCI: Transfer complete interrupt enable
* @arg I2C_IT_STOPI: STOP detection interrupt enable
* @arg I2C_IT_NACKI: NACK received interrupt enable
* @arg I2C_IT_ADDRI: Address match interrupt enable
* @arg I2C_IT_RXI: RX interrupt enable
* @arg I2C_IT_TXI: TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
* @param __HANDLE__: specifies the I2C Handle.
* @param __INTERRUPT__: specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg I2C_IT_ERRI: Errors interrupt enable
* @arg I2C_IT_TCI: Transfer complete interrupt enable
* @arg I2C_IT_STOPI: STOP detection interrupt enable
* @arg I2C_IT_NACKI: NACK received interrupt enable
* @arg I2C_IT_ADDRI: Address match interrupt enable
* @arg I2C_IT_RXI: RX interrupt enable
* @arg I2C_IT_TXI: TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2C flag is set or not.
* @param __HANDLE__: specifies the I2C Handle.
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2C_FLAG_TXE: Transmit data register empty
* @arg I2C_FLAG_TXIS: Transmit interrupt status
* @arg I2C_FLAG_RXNE: Receive data register not empty
* @arg I2C_FLAG_ADDR: Address matched (slave mode)
* @arg I2C_FLAG_AF: Acknowledge failure received flag
* @arg I2C_FLAG_STOPF: STOP detection flag
* @arg I2C_FLAG_TC: Transfer complete (master mode)
* @arg I2C_FLAG_TCR: Transfer complete reload
* @arg I2C_FLAG_BERR: Bus error
* @arg I2C_FLAG_ARLO: Arbitration lost
* @arg I2C_FLAG_OVR: Overrun/Underrun
* @arg I2C_FLAG_PECERR: PEC error in reception
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
* @arg I2C_FLAG_ALERT: SMBus alert
* @arg I2C_FLAG_BUSY: Bus busy
* @arg I2C_FLAG_DIR: Transfer direction (slave mode)
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __FLAG__ (TRUE or FALSE).
* @retval None
*/
#define I2C_FLAG_MASK ((uint32_t)0x0001FFFF)
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
/** @brief Clears the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__: specifies the I2C Handle.
* @param __FLAG__: specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg I2C_FLAG_ADDR: Address matched (slave mode)
* @arg I2C_FLAG_AF: Acknowledge failure received flag
* @arg I2C_FLAG_STOPF: STOP detection flag
* @arg I2C_FLAG_BERR: Bus error
* @arg I2C_FLAG_ARLO: Arbitration lost
* @arg I2C_FLAG_OVR: Overrun/Underrun
* @arg I2C_FLAG_PECERR: PEC error in reception
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
* @arg I2C_FLAG_ALERT: SMBus alert
/** @brief Disable the specified I2C interrupt.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the interrupt source to disable.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = ((__FLAG__) & I2C_FLAG_MASK))
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg @ref I2C_IT_ERRI Errors interrupt enable
* @arg @ref I2C_IT_TCI Transfer complete interrupt enable
* @arg @ref I2C_IT_STOPI STOP detection interrupt enable
* @arg @ref I2C_IT_NACKI NACK received interrupt enable
* @arg @ref I2C_IT_ADDRI Address match interrupt enable
* @arg @ref I2C_IT_RXI RX interrupt enable
* @arg @ref I2C_IT_TXI TX interrupt enable
*
* @retval The new state of __INTERRUPT__ (SET or RESET).
*/
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified I2C flag is set or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_TXIS Transmit interrupt status
* @arg @ref I2C_FLAG_RXNE Receive data register not empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_TC Transfer complete (master mode)
* @arg @ref I2C_FLAG_TCR Transfer complete reload
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
* @arg @ref I2C_FLAG_BUSY Bus busy
* @arg @ref I2C_FLAG_DIR Transfer direction (slave mode)
*
* @retval The new state of __FLAG__ (SET or RESET).
*/
#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) ? SET : RESET)
/** @brief Clear the I2C pending flags which are cleared by writing 1 in a specific bit.
* @param __HANDLE__ specifies the I2C Handle.
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref I2C_FLAG_TXE Transmit data register empty
* @arg @ref I2C_FLAG_ADDR Address matched (slave mode)
* @arg @ref I2C_FLAG_AF Acknowledge failure received flag
* @arg @ref I2C_FLAG_STOPF STOP detection flag
* @arg @ref I2C_FLAG_BERR Bus error
* @arg @ref I2C_FLAG_ARLO Arbitration lost
* @arg @ref I2C_FLAG_OVR Overrun/Underrun
* @arg @ref I2C_FLAG_PECERR PEC error in reception
* @arg @ref I2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref I2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == I2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
/** @brief Enable the specified I2C peripheral.
* @param __HANDLE__: specifies the I2C Handle.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Disable the specified I2C peripheral.
* @param __HANDLE__: specifies the I2C Handle.
* @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
* @param __HANDLE__: specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
/**
* @}
*/
*/
/* Include I2C HAL Extension module */
/* Include I2C HAL Extended module */
#include "stm32f7xx_hal_i2c_ex.h"
/* Exported functions --------------------------------------------------------*/
@ -441,7 +534,7 @@ void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
*/
/** @addtogroup I2C_Exported_Functions_Group2 Input and Output operation functions
* @{
@ -464,6 +557,14 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pDa
HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
@ -473,11 +574,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
/**
* @}
*/
*/
/** @addtogroup IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
/** @addtogroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
*/
*/
/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
@ -485,18 +586,22 @@ void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode);
void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
/** @addtogroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
*/
/* Peripheral State and Errors functions *************************************/
/* Peripheral State, Mode and Error functions *********************************/
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
@ -506,7 +611,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
@ -522,49 +627,58 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
*/
#define IS_I2C_ADDRESSING_MODE(MODE) (((MODE) == I2C_ADDRESSINGMODE_7BIT) || \
((MODE) == I2C_ADDRESSINGMODE_10BIT))
((MODE) == I2C_ADDRESSINGMODE_10BIT))
#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLE) || \
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
((ADDRESS) == I2C_DUALADDRESS_ENABLE))
#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NOMASK) || \
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
((MASK) == I2C_OA2_MASK01) || \
((MASK) == I2C_OA2_MASK02) || \
((MASK) == I2C_OA2_MASK03) || \
((MASK) == I2C_OA2_MASK04) || \
((MASK) == I2C_OA2_MASK05) || \
((MASK) == I2C_OA2_MASK06) || \
((MASK) == I2C_OA2_MASK07))
#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLE) || \
((CALL) == I2C_GENERALCALL_ENABLE))
((CALL) == I2C_GENERALCALL_ENABLE))
#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLE) || \
((STRETCH) == I2C_NOSTRETCH_ENABLE))
((STRETCH) == I2C_NOSTRETCH_ENABLE))
#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
((SIZE) == I2C_MEMADD_SIZE_16BIT))
((SIZE) == I2C_MEMADD_SIZE_16BIT))
#define IS_TRANSFER_MODE(MODE) (((MODE) == I2C_RELOAD_MODE) || \
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
((MODE) == I2C_AUTOEND_MODE) || \
((MODE) == I2C_SOFTEND_MODE))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define IS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == I2C_GENERATE_STOP) || \
((REQUEST) == I2C_GENERATE_START_READ) || \
((REQUEST) == I2C_GENERATE_START_WRITE) || \
((REQUEST) == I2C_NO_STARTSTOP))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define IS_I2C_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == I2C_FIRST_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
((REQUEST) == I2C_LAST_FRAME))
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define I2C_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 16)
#define I2C_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16)
#define I2C_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
#define I2C_GET_OWN_ADDRESS1(__HANDLE__) ((__HANDLE__)->Instance->OAR1 & I2C_OAR1_OA1)
#define I2C_GET_OWN_ADDRESS2(__HANDLE__) ((__HANDLE__)->Instance->OAR2 & I2C_OAR2_OA2)
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
#define I2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
#define I2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define I2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == I2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
@ -586,7 +700,7 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
@ -595,4 +709,3 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
#endif /* __STM32F7xx_HAL_I2C_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

201
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.c
View File

@ -2,35 +2,39 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief I2C Extended HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
*
@verbatim
==============================================================================
##### I2C peripheral Extended features #####
==============================================================================
[..] Comparing to other previous devices, the I2C interface for STM32L4XX
[..] Comparing to other previous devices, the I2C interface for STM32F7XX
devices contains the following additional features
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
(+) Disable or enable wakeup from Stop mode
(+) Disable or enable Fast Mode Plus (available only for STM32F76xxx/STM32F77xxx
devices)
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to:
(#) Configure I2C Analog noise filter using the function HAL_I2CEx_ConfigAnalogFilter()
(#) Configure I2C Digital noise filter using the function HAL_I2CEx_ConfigDigitalFilter()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_I2CEx_EnableFastModePlus()
(++) HAL_I2CEx_DisbleFastModePlus()
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -54,8 +58,8 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@ -85,22 +89,23 @@
/** @defgroup I2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
*
@verbatim
@verbatim
===============================================================================
##### Extended features functions #####
===============================================================================
===============================================================================
[..] This section provides functions allowing to:
(+) Configure Noise Filters
(+) Configure Fast Mode Plus
@endverbatim
* @{
*/
/**
* @brief Configures I2C Analog noise filter.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter : new state of the Analog filter.
* @brief Configure I2C Analog noise filter.
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param AnalogFilter: New state of the Analog filter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter)
@ -109,41 +114,42 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Reset I2Cx ANOFF bit */
hi2c->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
/* Set analog filter bit*/
hi2c->Instance->CR1 |= AnalogFilter;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
/**
* @brief Configures I2C Digital noise filter.
* @param hi2c : pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter : Coefficient of digital noise filter between 0x00 and 0x0F.
* @brief Configure I2C Digital noise filter.
* @param hi2c: Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2Cx peripheral.
* @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
@ -154,49 +160,88 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
if((hi2c->State == HAL_I2C_STATE_BUSY) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_MASTER_BUSY_RX)
|| (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_TX) || (hi2c->State == HAL_I2C_STATE_SLAVE_BUSY_RX))
if(hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
hi2c->State = HAL_I2C_STATE_BUSY;
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
}
else
{
return HAL_BUSY;
}
/* Process Locked */
__HAL_LOCK(hi2c);
}
hi2c->State = HAL_I2C_STATE_BUSY;
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus: Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @retval None
*/
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Disable the selected I2C peripheral */
__HAL_I2C_DISABLE(hi2c);
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Get the old register value */
tmpreg = hi2c->Instance->CR1;
/* Reset I2Cx DNF bits [11:8] */
tmpreg &= ~(I2C_CR1_DNF);
/* Set I2Cx DNF coefficient */
tmpreg |= DigitalFilter << 8;
/* Store the new register value */
hi2c->Instance->CR1 = tmpreg;
__HAL_I2C_ENABLE(hi2c);
hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
return HAL_OK;
/* Enable fast mode plus driving capability for selected pin */
SET_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
}
/**
* @}
*/
* @brief Disable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus: Selects the pin.
* This parameter can be one of the @ref I2CEx_FastModePlus values
* @retval None
*/
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus)
{
/* Check the parameter */
assert_param(IS_I2C_FASTMODEPLUS(ConfigFastModePlus));
/* Enable SYSCFG clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
*/
/**
* @}
*/
#endif /* HAL_I2C_MODULE_ENABLED */
/**

93
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2c_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of I2C HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_I2C_EX_H
@ -44,7 +44,7 @@
#endif
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
@ -54,7 +54,7 @@
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup I2CEx_Exported_Constants I2CEx Exported Constants
@ -64,13 +64,32 @@
/** @defgroup I2CEx_Analog_Filter I2CEx Analog Filter
* @{
*/
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000)
#define I2C_ANALOGFILTER_ENABLE ((uint32_t)0x00000000U)
#define I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF
/**
* @}
*/
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{
*/
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
#define I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP
#define I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP
#define I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP
#define I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP
#define I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP
#define I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/
/**
* @}
*/
@ -81,6 +100,11 @@
/* Peripheral Control methods ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
* @{
@ -88,7 +112,7 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
/**
* @}
*/
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
@ -97,10 +121,45 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_ANALOGFILTER_ENABLE) || \
((FILTER) == I2C_ANALOGFILTER_DISABLE))
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C4) == I2C_FASTMODEPLUS_I2C4))
#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C3) == I2C_FASTMODEPLUS_I2C3))
#elif defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C2) == I2C_FASTMODEPLUS_I2C2))
#elif defined(SYSCFG_PMC_I2C1_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB9) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_I2C1) == I2C_FASTMODEPLUS_I2C1))
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
/**
* @}
*/
*/
/**
* @}
*/
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
@ -109,16 +168,16 @@ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_
/* Private functions are defined in stm32f7xx_hal_i2c_ex.c file */
/**
* @}
*/
/**
* @}
*/
*/
/**
* @}
*/
/**
* @}
*/
#ifdef __cplusplus
}
#endif

14
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -330,10 +330,10 @@ HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \
(uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \
(uint16_t)hi2s->Init.CPOL))));
/* Write to SPIx I2SCFGR */
hi2s->Instance->I2SCFGR = tmpreg;
hi2s->Instance->I2SCFGR = tmpreg;
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State= HAL_I2S_STATE_READY;
@ -1347,7 +1347,7 @@ static uint32_t I2S_GetClockFreq(I2S_HandleTypeDef *hi2s)
/* I2S_CLK_x : I2S Block Clock configuration for different clock sources selected */
switch(hi2s->Init.ClockSource)
{
case I2S_CLOCK_SYSCLK :
case I2S_CLOCK_PLL :
{
/* Configure the PLLI2S division factor */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */

94
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_i2s.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -91,14 +91,14 @@ typedef struct
*/
typedef enum
{
HAL_I2S_STATE_RESET = 0x00, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07 /*!< I2S error state */
HAL_I2S_STATE_RESET = 0x00U, /*!< I2S not yet initialized or disabled */
HAL_I2S_STATE_READY = 0x01U, /*!< I2S initialized and ready for use */
HAL_I2S_STATE_BUSY = 0x02U, /*!< I2S internal process is ongoing */
HAL_I2S_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */
HAL_I2S_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */
HAL_I2S_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */
HAL_I2S_STATE_TIMEOUT = 0x06U, /*!< I2S timeout state */
HAL_I2S_STATE_ERROR = 0x07U /*!< I2S error state */
}HAL_I2S_StateTypeDef;
@ -152,12 +152,12 @@ typedef struct
*@brief I2S Error Code
* @{
*/
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002) /*!< OVR error */
#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004) /*!< UDR error */
#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008) /*!< DMA transfer error */
#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010) /*!< Unknow Error error */
#define HAL_I2S_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_I2S_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_I2S_ERROR_OVR ((uint32_t)0x00000002U) /*!< OVR error */
#define HAL_I2S_ERROR_UDR ((uint32_t)0x00000004U) /*!< UDR error */
#define HAL_I2S_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
#define HAL_I2S_ERROR_UNKNOW ((uint32_t)0x00000010U) /*!< Unknow Error error */
/**
* @}
@ -165,8 +165,8 @@ typedef struct
/** @defgroup I2S_Clock_Source I2S Clock Source
* @{
*/
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001)
#define I2S_CLOCK_SYSCLK ((uint32_t)0x00000002)
#define I2S_CLOCK_EXTERNAL ((uint32_t)0x00000001U)
#define I2S_CLOCK_PLL ((uint32_t)0x00000002U)
/**
* @}
*/
@ -174,10 +174,10 @@ typedef struct
/** @defgroup I2S_Mode I2S Mode
* @{
*/
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000)
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100)
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200)
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300)
#define I2S_MODE_SLAVE_TX ((uint32_t)0x00000000U)
#define I2S_MODE_SLAVE_RX ((uint32_t)0x00000100U)
#define I2S_MODE_MASTER_TX ((uint32_t)0x00000200U)
#define I2S_MODE_MASTER_RX ((uint32_t)0x00000300U)
/**
* @}
*/
@ -185,11 +185,11 @@ typedef struct
/** @defgroup I2S_Standard I2S Standard
* @{
*/
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000)
#define I2S_STANDARD_MSB ((uint32_t)0x00000010)
#define I2S_STANDARD_LSB ((uint32_t)0x00000020)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030)
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0)
#define I2S_STANDARD_PHILIPS ((uint32_t)0x00000000U)
#define I2S_STANDARD_MSB ((uint32_t)0x00000010U)
#define I2S_STANDARD_LSB ((uint32_t)0x00000020U)
#define I2S_STANDARD_PCM_SHORT ((uint32_t)0x00000030U)
#define I2S_STANDARD_PCM_LONG ((uint32_t)0x000000B0U)
/**
* @}
*/
@ -197,10 +197,10 @@ typedef struct
/** @defgroup I2S_Data_Format I2S Data Format
* @{
*/
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000)
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001)
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003)
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005)
#define I2S_DATAFORMAT_16B ((uint32_t)0x00000000U)
#define I2S_DATAFORMAT_16B_EXTENDED ((uint32_t)0x00000001U)
#define I2S_DATAFORMAT_24B ((uint32_t)0x00000003U)
#define I2S_DATAFORMAT_32B ((uint32_t)0x00000005U)
/**
* @}
*/
@ -209,7 +209,7 @@ typedef struct
* @{
*/
#define I2S_MCLKOUTPUT_ENABLE ((uint32_t)SPI_I2SPR_MCKOE)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000)
#define I2S_MCLKOUTPUT_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -217,16 +217,16 @@ typedef struct
/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
* @{
*/
#define I2S_AUDIOFREQ_192K ((uint32_t)192000)
#define I2S_AUDIOFREQ_96K ((uint32_t)96000)
#define I2S_AUDIOFREQ_48K ((uint32_t)48000)
#define I2S_AUDIOFREQ_44K ((uint32_t)44100)
#define I2S_AUDIOFREQ_32K ((uint32_t)32000)
#define I2S_AUDIOFREQ_22K ((uint32_t)22050)
#define I2S_AUDIOFREQ_16K ((uint32_t)16000)
#define I2S_AUDIOFREQ_11K ((uint32_t)11025)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2)
#define I2S_AUDIOFREQ_192K ((uint32_t)192000U)
#define I2S_AUDIOFREQ_96K ((uint32_t)96000U)
#define I2S_AUDIOFREQ_48K ((uint32_t)48000U)
#define I2S_AUDIOFREQ_44K ((uint32_t)44100U)
#define I2S_AUDIOFREQ_32K ((uint32_t)32000U)
#define I2S_AUDIOFREQ_22K ((uint32_t)22050U)
#define I2S_AUDIOFREQ_16K ((uint32_t)16000U)
#define I2S_AUDIOFREQ_11K ((uint32_t)11025U)
#define I2S_AUDIOFREQ_8K ((uint32_t)8000U)
#define I2S_AUDIOFREQ_DEFAULT ((uint32_t)2U)
/**
* @}
*/
@ -235,7 +235,7 @@ typedef struct
/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
* @{
*/
#define I2S_CPOL_LOW ((uint32_t)0x00000000)
#define I2S_CPOL_LOW ((uint32_t)0x00000000U)
#define I2S_CPOL_HIGH ((uint32_t)SPI_I2SCFGR_CKPOL)
/**
* @}
@ -334,7 +334,7 @@ typedef struct
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->DR; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
@ -346,7 +346,7 @@ typedef struct
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
do{ \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
tmpreg = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg); \
} while(0)
@ -434,7 +434,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
* @{
*/
#define IS_I2S_CLOCKSOURCE(CLOCK) (((CLOCK) == I2S_CLOCK_EXTERNAL) || \
((CLOCK) == I2S_CLOCK_SYSCLK))
((CLOCK) == I2S_CLOCK_PLL))
#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX) || \
((MODE) == I2S_MODE_SLAVE_RX) || \

1834
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.c
View File

File diff suppressed because it is too large Load Diff

158
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_irda.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -89,18 +89,63 @@ typedef struct
}IRDA_InitTypeDef;
/**
* @brief HAL State structures definition
* @brief HAL IRDA State structures definition
* @note HAL IRDA State value is a combination of 2 different substates: gState and RxState.
* - gState contains IRDA state information related to global Handle management
* and also information related to Tx operations.
* gState value coding follow below described bitmap :
* b7-b6 Error information
* 00 : No Error
* 01 : (Not Used)
* 10 : Timeout
* 11 : Error
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized. HAL IRDA Init function already called)
* b4-b3 (not used)
* xx : Should be set to 00
* b2 Intrinsic process state
* 0 : Ready
* 1 : Busy (IP busy with some configuration or internal operations)
* b1 (not used)
* x : Should be set to 0
* b0 Tx state
* 0 : Ready (no Tx operation ongoing)
* 1 : Busy (Tx operation ongoing)
* - RxState contains information related to Rx operations.
* RxState value coding follow below described bitmap :
* b7-b6 (not used)
* xx : Should be set to 00
* b5 IP initilisation status
* 0 : Reset (IP not initialized)
* 1 : Init done (IP not initialized)
* b4-b2 (not used)
* xxx : Should be set to 000
* b1 Rx state
* 0 : Ready (no Rx operation ongoing)
* 1 : Busy (Rx operation ongoing)
* b0 (not used)
* x : Should be set to 0.
*/
typedef enum
{
HAL_IRDA_STATE_RESET = 0x00, /*!< Peripheral is not yet Initialized */
HAL_IRDA_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_IRDA_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
HAL_IRDA_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
HAL_IRDA_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
HAL_IRDA_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
HAL_IRDA_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_IRDA_STATE_ERROR = 0x04 /*!< Error */
HAL_IRDA_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized
Value is allowed for gState and RxState */
HAL_IRDA_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use
Value is allowed for gState and RxState */
HAL_IRDA_STATE_BUSY = 0x24U, /*!< An internal process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing
Value is allowed for gState only */
HAL_IRDA_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing
Value is allowed for RxState only */
HAL_IRDA_STATE_BUSY_TX_RX = 0x23U, /*!< Data Transmission and Reception process is ongoing
Not to be used for neither gState nor RxState.
Value is result of combination (Or) between gState and RxState values */
HAL_IRDA_STATE_TIMEOUT = 0xA0U, /*!< Timeout state
Value is allowed for gState only */
HAL_IRDA_STATE_ERROR = 0xE0U /*!< Error
Value is allowed for gState only */
}HAL_IRDA_StateTypeDef;
/**
@ -108,11 +153,11 @@ typedef enum
*/
typedef enum
{
IRDA_CLOCKSOURCE_PCLK1 = 0x00, /*!< PCLK1 clock source */
IRDA_CLOCKSOURCE_PCLK2 = 0x01, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x08 /*!< LSE clock source */
IRDA_CLOCKSOURCE_PCLK1 = 0x00U, /*!< PCLK1 clock source */
IRDA_CLOCKSOURCE_PCLK2 = 0x01U, /*!< PCLK2 clock source */
IRDA_CLOCKSOURCE_HSI = 0x02U, /*!< HSI clock source */
IRDA_CLOCKSOURCE_SYSCLK = 0x04U, /*!< SYSCLK clock source */
IRDA_CLOCKSOURCE_LSE = 0x08U /*!< LSE clock source */
}IRDA_ClockSourceTypeDef;
/**
@ -144,7 +189,12 @@ typedef struct
HAL_LockTypeDef Lock; /* Locking object */
__IO HAL_IRDA_StateTypeDef State; /* IRDA communication state */
__IO HAL_IRDA_StateTypeDef gState; /* IRDA state information related to global Handle management
and also related to Tx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO HAL_IRDA_StateTypeDef RxState; /* IRDA state information related to Rx operations.
This parameter can be a value of @ref HAL_IRDA_StateTypeDef */
__IO uint32_t ErrorCode; /* IRDA Error code */
@ -167,12 +217,12 @@ typedef struct
* @{
*/
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004) /*!< frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010) /*!< DMA transfer error */
#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */
#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */
#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */
#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */
#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */
/**
* @}
*/
@ -180,7 +230,7 @@ typedef struct
/** @defgroup IRDA_Parity IRDA Parity
* @{
*/
#define IRDA_PARITY_NONE ((uint32_t)0x0000)
#define IRDA_PARITY_NONE ((uint32_t)0x0000U)
#define IRDA_PARITY_EVEN ((uint32_t)USART_CR1_PCE)
#define IRDA_PARITY_ODD ((uint32_t)(USART_CR1_PCE | USART_CR1_PS))
/**
@ -201,7 +251,7 @@ typedef struct
/** @defgroup IRDA_Low_Power IRDA Low Power
* @{
*/
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000)
#define IRDA_POWERMODE_NORMAL ((uint32_t)0x0000U)
#define IRDA_POWERMODE_LOWPOWER ((uint32_t)USART_CR3_IRLP)
/**
* @}
@ -210,7 +260,7 @@ typedef struct
/** @defgroup IRDA_State IRDA State
* @{
*/
#define IRDA_STATE_DISABLE ((uint32_t)0x0000)
#define IRDA_STATE_DISABLE ((uint32_t)0x0000U)
#define IRDA_STATE_ENABLE ((uint32_t)USART_CR1_UE)
/**
* @}
@ -219,7 +269,7 @@ typedef struct
/** @defgroup IRDA_Mode IRDA Mode
* @{
*/
#define IRDA_MODE_DISABLE ((uint32_t)0x0000)
#define IRDA_MODE_DISABLE ((uint32_t)0x0000U)
#define IRDA_MODE_ENABLE ((uint32_t)USART_CR3_IREN)
/**
* @}
@ -228,7 +278,7 @@ typedef struct
/** @defgroup IRDA_One_Bit IRDA One Bit
* @{
*/
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000)
#define IRDA_ONE_BIT_SAMPLE_DISABLE ((uint32_t)0x00000000U)
#define IRDA_ONE_BIT_SAMPLE_ENABLE ((uint32_t)USART_CR3_ONEBIT)
/**
* @}
@ -237,7 +287,7 @@ typedef struct
/** @defgroup IRDA_DMA_Tx IRDA DMA Tx
* @{
*/
#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000)
#define IRDA_DMA_TX_DISABLE ((uint32_t)0x00000000U)
#define IRDA_DMA_TX_ENABLE ((uint32_t)USART_CR3_DMAT)
/**
* @}
@ -246,7 +296,7 @@ typedef struct
/** @defgroup IRDA_DMA_Rx IRDA DMA Rx
* @{
*/
#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000)
#define IRDA_DMA_RX_DISABLE ((uint32_t)0x0000U)
#define IRDA_DMA_RX_ENABLE ((uint32_t)USART_CR3_DMAR)
/**
* @}
@ -257,18 +307,18 @@ typedef struct
* - 0xXXXX : Flag mask in the ISR register
* @{
*/
#define IRDA_FLAG_REACK ((uint32_t)0x00400000)
#define IRDA_FLAG_TEACK ((uint32_t)0x00200000)
#define IRDA_FLAG_BUSY ((uint32_t)0x00010000)
#define IRDA_FLAG_ABRF ((uint32_t)0x00008000)
#define IRDA_FLAG_ABRE ((uint32_t)0x00004000)
#define IRDA_FLAG_TXE ((uint32_t)0x00000080)
#define IRDA_FLAG_TC ((uint32_t)0x00000040)
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020)
#define IRDA_FLAG_ORE ((uint32_t)0x00000008)
#define IRDA_FLAG_NE ((uint32_t)0x00000004)
#define IRDA_FLAG_FE ((uint32_t)0x00000002)
#define IRDA_FLAG_PE ((uint32_t)0x00000001)
#define IRDA_FLAG_REACK ((uint32_t)0x00400000U)
#define IRDA_FLAG_TEACK ((uint32_t)0x00200000U)
#define IRDA_FLAG_BUSY ((uint32_t)0x00010000U)
#define IRDA_FLAG_ABRF ((uint32_t)0x00008000U)
#define IRDA_FLAG_ABRE ((uint32_t)0x00004000U)
#define IRDA_FLAG_TXE ((uint32_t)0x00000080U)
#define IRDA_FLAG_TC ((uint32_t)0x00000040U)
#define IRDA_FLAG_RXNE ((uint32_t)0x00000020U)
#define IRDA_FLAG_ORE ((uint32_t)0x00000008U)
#define IRDA_FLAG_NE ((uint32_t)0x00000004U)
#define IRDA_FLAG_FE ((uint32_t)0x00000002U)
#define IRDA_FLAG_PE ((uint32_t)0x00000001U)
/**
* @}
*/
@ -283,11 +333,11 @@ typedef struct
* - ZZZZ : Flag position in the ISR register(4bits)
* @{
*/
#define IRDA_IT_PE ((uint16_t)0x0028)
#define IRDA_IT_TXE ((uint16_t)0x0727)
#define IRDA_IT_TC ((uint16_t)0x0626)
#define IRDA_IT_RXNE ((uint16_t)0x0525)
#define IRDA_IT_IDLE ((uint16_t)0x0424)
#define IRDA_IT_PE ((uint16_t)0x0028U)
#define IRDA_IT_TXE ((uint16_t)0x0727U)
#define IRDA_IT_TC ((uint16_t)0x0626U)
#define IRDA_IT_RXNE ((uint16_t)0x0525U)
#define IRDA_IT_IDLE ((uint16_t)0x0424U)
@ -298,14 +348,14 @@ typedef struct
* - 10: CR2 register
* - 11: CR3 register
*/
#define IRDA_IT_ERR ((uint16_t)0x0060)
#define IRDA_IT_ERR ((uint16_t)0x0060U)
/** Elements values convention: 0000ZZZZ00000000b
* - ZZZZ : Flag position in the ISR register(4bits)
*/
#define IRDA_IT_ORE ((uint16_t)0x0300)
#define IRDA_IT_NE ((uint16_t)0x0200)
#define IRDA_IT_FE ((uint16_t)0x0100)
#define IRDA_IT_ORE ((uint16_t)0x0300U)
#define IRDA_IT_NE ((uint16_t)0x0200U)
#define IRDA_IT_FE ((uint16_t)0x0100U)
/**
* @}
*/
@ -559,7 +609,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
/** @defgroup IRDA_Interruption_Mask IRDA Interruption Mask
* @{
*/
#define IRDA_IT_MASK ((uint16_t)0x001F)
#define IRDA_IT_MASK ((uint16_t)0x001FU)
/**
* @}
*/
@ -588,7 +638,7 @@ uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
((__PARITY__) == IRDA_PARITY_EVEN) || \
((__PARITY__) == IRDA_PARITY_ODD))
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00))
#define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == (uint32_t)0x00) && ((__MODE__) != (uint32_t)0x00U))
#define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
((__MODE__) == IRDA_POWERMODE_NORMAL))

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_irda_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_irda_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,7 +64,7 @@
* @{
*/
#define IRDA_WORDLENGTH_7B ((uint32_t)USART_CR1_M_1)
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000)
#define IRDA_WORDLENGTH_8B ((uint32_t)0x00000000U)
#define IRDA_WORDLENGTH_9B ((uint32_t)USART_CR1_M_0)
/**
* @}

358
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.c
View File

@ -2,90 +2,86 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief IWDG HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the Independent Watchdog (IWDG) peripheral:
* + Initialization and de-initialization functions
* + Initialization and Start functions
* + IO operation functions
* + Peripheral State functions
*
*
@verbatim
==============================================================================
##### IWDG Generic features #####
==============================================================================
[..]
[..]
(+) The IWDG can be started by either software or hardware (configurable
through option byte).
through option byte).
(+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
thus stays active even if the main clock fails.
Once the IWDG is started, the LSI is forced ON and cannot be disabled
(LSI cannot be disabled too), and the counter starts counting down from
the reset value of 0xFFF. When it reaches the end of count value (0x000)
a system reset is generated.
(+) The IWDG is clocked by Low-Speed clock (LSI) and thus stays active even
if the main clock fails.
(+) The IWDG counter should be refreshed at regular intervals, otherwise the
watchdog generates an MCU reset when the counter reaches 0.
(+) Once the IWDG is started, the LSI is forced ON and both can not be
disabled. The counter starts counting down from the reset value (0xFFF).
When it reaches the end of count value (0x000) a reset signal is
generated (IWDG reset).
(+) Whenever the key value 0x0000 AAAA is written in the IWDG_KR register,
the IWDG_RLR value is reloaded in the counter and the watchdog reset is
prevented.
(+) The IWDG is implemented in the VDD voltage domain that is still functional
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
reset occurs.
(+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32L4xx
The IWDG timeout may vary due to LSI frequency dispersion. STM32F7xx
devices provide the capability to measure the LSI frequency (LSI clock
connected internally to TIM16 CH1 input capture). The measured value
can be used to have an IWDG timeout with an acceptable accuracy.
##### How to use this driver #####
==============================================================================
[..]
If Window option is disabled
(+) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable write access to IWDG_PR, IWDG_RLR.
(++) Configure the IWDG prescaler, counter reload value.
This reload value will be loaded in the IWDG counter each time the counter
is reloaded, then the IWDG will start counting down from this value.
(+) Use IWDG using HAL_IWDG_Start() function to :
(++) Reload IWDG counter with value defined in the IWDG_RLR register.
(++) Start the IWDG, when the IWDG is used in software mode (no need
to enable the LSI, it will be enabled by hardware).
(+) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
[..]
if Window option is enabled:
(+) Use IWDG using HAL_IWDG_Start() function to enable IWDG downcounter
(+) Use IWDG using HAL_IWDG_Init() function to :
(++) Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
(++) Configure the IWDG prescaler, reload value and window value.
(+) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
[..]
(#) Use IWDG using HAL_IWDG_Init() function to :
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting.
(+) Enable write access to configuration register: IWDG_PR, IWDG_RLR &
IWDG_WINR.
(+) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value.
(+) wait for status flags to be reset"
(+) Depending on window parameter:
(++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit
function withy exact time base.
(++) Else modify Window register. This will automatically reload
watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular
intervals during normal operation to prevent an MCU reset, using
HAL_IWDG_Refresh() function.
*** IWDG HAL driver macros list ***
====================================
[..]
Below the list of most used macros in IWDG HAL driver.
Below the list of most used macros in IWDG HAL driver:
(+) __HAL_IWDG_START: Enable the IWDG peripheral
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register
(+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
(+) IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
(+) IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
(+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in
the reload register
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -119,61 +115,63 @@
* @{
*/
/** @defgroup IWDG IWDG HAL module driver
#ifdef HAL_IWDG_MODULE_ENABLED
/** @addtogroup IWDG
* @brief IWDG HAL module driver.
* @{
*/
#ifdef HAL_IWDG_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Defines IWDG Private Defines
* @{
*/
#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
/* Status register need 5 RC LSI divided by prescaler clock to be updated. With
higher prescaler (256), and according to LSI variation, we need to wait at
least 6 cycles so 48 ms. */
#define HAL_IWDG_DEFAULT_TIMEOUT 48u
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
/** @addtogroup IWDG_Exported_Functions
* @{
*/
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions.
/** @addtogroup IWDG_Exported_Functions_Group1
* @brief Initialization and Start functions.
*
@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
##### Initialization and Start functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters
in the IWDG_InitTypeDef and create the associated handle
(+) Manage Window option
(+) Initialize the IWDG MSP
(+) DeInitialize IWDG MSP
[..] This section provides functions allowing to:
(+) Initialize the IWDG according to the specified parameters in the
IWDG_InitTypeDef of associated handle.
(+) Manage Window option.
(+) Once initialization is performed in HAL_IWDG_Init function, Watchdog
is reloaded in order to exit function with correct time base.
@endverbatim
* @{
*/
/**
* @brief Initializes the IWDG according to the specified
* parameters in the IWDG_InitTypeDef and creates the associated handle.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* @brief Initialize the IWDG according to the specified parameters in the
* IWDG_InitTypeDef and start watchdog. Before exiting function,
* watchdog is refreshed in order to have correct time base.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
uint32_t tickstart;
/* Check the IWDG handle allocation */
if(hiwdg == NULL)
@ -182,230 +180,88 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
}
/* Check the parameters */
assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Check pending flag, if previous update not done, return error */
if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
&&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
&&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET))
{
return HAL_ERROR;
}
/* Enable IWDG. LSI is turned on automaticaly */
__HAL_IWDG_START(hiwdg);
if(hiwdg->State == HAL_IWDG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hiwdg->Lock = HAL_UNLOCKED;
/* Init the low level hardware */
HAL_IWDG_MspInit(hiwdg);
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers */
/* by writing 0x00005555 in KR */
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing
0x5555 in KR */
IWDG_ENABLE_WRITE_ACCESS(hiwdg);
/* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
MODIFY_REG(hiwdg->Instance->PR, (uint32_t)IWDG_PR_PR, hiwdg->Init.Prescaler);
MODIFY_REG(hiwdg->Instance->RLR, (uint32_t)IWDG_RLR_RL, hiwdg->Init.Reload);
/* Write to IWDG registers the Prescaler & Reload values to work with */
hiwdg->Instance->PR = hiwdg->Init.Prescaler;
hiwdg->Instance->RLR = hiwdg->Init.Reload;
/* check if window option is enabled */
if (((hiwdg->Init.Window) != IWDG_WINDOW_DISABLE) || ((hiwdg->Instance->WINR) != IWDG_WINDOW_DISABLE))
/* Check pending flag, if previous update not done, return timeout */
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while(hiwdg->Instance->SR != RESET)
{
tickstart = HAL_GetTick();
/* Wait for register to be updated */
while((uint32_t)(hiwdg->Instance->SR) != RESET)
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
return HAL_TIMEOUT;
}
return HAL_TIMEOUT;
}
/* Write to IWDG WINR the IWDG_Window value to compare with */
MODIFY_REG(hiwdg->Instance->WINR, (uint32_t)IWDG_WINR_WIN, hiwdg->Init.Window);
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* If window parameter is different than current value, modify window
register */
if(hiwdg->Instance->WINR != hiwdg->Init.Window)
{
/* Write to IWDG WINR the IWDG_Window value to compare with. In any case,
even if window feature is disabled, Watchdog will be reloaded by writing
windows register */
hiwdg->Instance->WINR = hiwdg->Init.Window;
}
else
{
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the IWDG MSP.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval None
*/
__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hiwdg);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_IWDG_MspInit could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @brief IO operation functions
/** @addtogroup IWDG_Exported_Functions_Group2
* @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Start the IWDG.
[..] This section provides functions allowing to:
(+) Refresh the IWDG.
@endverbatim
* @{
*/
/**
* @brief Starts the IWDG.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
/* Process locked */
__HAL_LOCK(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
/* Reload IWDG counter with value defined in the RLR register */
if ((hiwdg->Init.Window) == IWDG_WINDOW_DISABLE)
{
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
}
/* Start the IWDG peripheral */
__HAL_IWDG_START(hiwdg);
tickstart = HAL_GetTick();
/* Wait until PVU, RVU, WVU flag are RESET */
while( (__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
&&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
&&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_WVU) != RESET) )
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hiwdg);
return HAL_TIMEOUT;
}
}
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @brief Refreshes the IWDG.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* @brief Refresh the IWDG.
* @param hiwdg pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
{
uint32_t tickstart = 0;
/* Process Locked */
__HAL_LOCK(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_BUSY;
tickstart = HAL_GetTick();
/* Wait until RVU flag is RESET */
while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
{
if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
{
/* Set IWDG state */
hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
/* Process unlocked */
__HAL_UNLOCK(hiwdg);
return HAL_TIMEOUT;
}
}
/* Reload IWDG counter with value defined in the reload register */
__HAL_IWDG_RELOAD_COUNTER(hiwdg);
/* Change IWDG peripheral state */
hiwdg->State = HAL_IWDG_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hiwdg);
/* Return function status */
return HAL_OK;
}
/**
* @}
*/
/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
* @brief Peripheral State functions.
*
@verbatim
===============================================================================
##### Peripheral State functions #####
===============================================================================
[..]
This subsection permits to get in run-time the status of the peripheral.
@endverbatim
* @{
*/
/**
* @brief Returns the IWDG state.
* @param hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
* the configuration information for the specified IWDG module.
* @retval HAL state
*/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
{
return hiwdg->State;
}
/**
* @}
*/

119
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_iwdg.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_iwdg.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of IWDG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -33,7 +33,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_IWDG_H
@ -50,7 +50,7 @@
* @{
*/
/** @addtogroup IWDG
/** @defgroup IWDG IWDG
* @{
*/
@ -59,19 +59,6 @@
* @{
*/
/**
* @brief IWDG HAL State Structure definition
*/
typedef enum
{
HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
}HAL_IWDG_StateTypeDef;
/**
* @brief IWDG Init structure definition
*/
@ -97,10 +84,6 @@ typedef struct
IWDG_InitTypeDef Init; /*!< IWDG required parameters */
HAL_LockTypeDef Lock; /*!< IWDG Locking object */
__IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
}IWDG_HandleTypeDef;
/**
@ -115,21 +98,21 @@ typedef struct
/** @defgroup IWDG_Prescaler IWDG Prescaler
* @{
*/
#define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
#define IWDG_PRESCALER_4 0x00000000u /*!< IWDG prescaler set to 4 */
#define IWDG_PRESCALER_8 IWDG_PR_PR_0 /*!< IWDG prescaler set to 8 */
#define IWDG_PRESCALER_16 IWDG_PR_PR_1 /*!< IWDG prescaler set to 16 */
#define IWDG_PRESCALER_32 (IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 32 */
#define IWDG_PRESCALER_64 IWDG_PR_PR_2 /*!< IWDG prescaler set to 64 */
#define IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< IWDG prescaler set to 128 */
#define IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1) /*!< IWDG prescaler set to 256 */
/**
* @}
*/
/** @defgroup IWDG_Window IWDG Window
/** @defgroup IWDG_Window_option IWDG Window option
* @{
*/
#define IWDG_WINDOW_DISABLE ((uint32_t)0x00000FFF)
#define IWDG_WINDOW_DISABLE IWDG_WINR_WIN
/**
* @}
*/
@ -143,117 +126,83 @@ typedef struct
* @{
*/
/** @brief Reset IWDG handle state
* @param __HANDLE__: IWDG handle.
* @retval None
*/
#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
/**
* @brief Enables the IWDG peripheral.
* @brief Enable the IWDG peripheral.
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
/**
* @brief Reloads IWDG counter with value defined in the reload register
* (write access to IWDG_PR and IWDG_RLR registers disabled).
* @param __HANDLE__: IWDG handle
* @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled).
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
/**
* @brief Gets the selected IWDG's flag status.
* @param __HANDLE__: IWDG handle
* @param __FLAG__: specifies the flag to check.
* This parameter can be one of the following values:
* @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
* @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
* @arg IWDG_FLAG_WVU: Watchdog counter window value flag
* @retval The new state of __FLAG__ (TRUE or FALSE) .
*/
#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup IWDG_Exported_Functions
/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
* @{
*/
/** @addtogroup IWDG_Exported_Functions_Group1
/** @defgroup IWDG_Exported_Functions_Group1 Initialization and Start functions
* @{
*/
/* Initialization/de-initialization functions ********************************/
/* Initialization/Start functions ********************************************/
HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group2
/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions
* @{
*/
/* I/O operation functions ****************************************************/
HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/** @addtogroup IWDG_Exported_Functions_Group3
* @{
*/
/* Peripheral State functions ************************************************/
HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
/**
* @}
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @addtogroup IWDG_Private_Defines
/** @defgroup IWDG_Private_Constants IWDG Private Constants
* @{
*/
/**
* @brief IWDG Key Register BitMask
*/
#define IWDG_KEY_RELOAD ((uint32_t)0x0000AAAA) /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE ((uint32_t)0x0000CCCC) /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x00005555) /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x00000000) /*!< IWDG KR Write Access Disable */
/**
* @brief IWDG Flag definition
*/
#define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
#define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
#define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update flag */
#define IWDG_KEY_RELOAD 0x0000AAAAu /*!< IWDG Reload Counter Enable */
#define IWDG_KEY_ENABLE 0x0000CCCCu /*!< IWDG Peripheral Enable */
#define IWDG_KEY_WRITE_ACCESS_ENABLE 0x00005555u /*!< IWDG KR Write Access Enable */
#define IWDG_KEY_WRITE_ACCESS_DISABLE 0x00000000u /*!< IWDG KR Write Access Disable */
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup IWDG_Private_Macro IWDG Private Macros
/** @defgroup IWDG_Private_Macros IWDG Private Macros
* @{
*/
/**
* @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__: IWDG handle
* @retval None
*/
#define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
/**
* @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
* @param __HANDLE__: IWDG handle
* @retval None
*/
@ -277,14 +226,14 @@ HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
* @param __RELOAD__: IWDG reload value
* @retval None
*/
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL)
/**
* @brief Check IWDG window value.
* @param __WINDOW__: IWDG window value
* @retval None
*/
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0xFFF)
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/**
* @}

3403
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.c Normal file
View File

File diff suppressed because it is too large Load Diff

581
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_jpeg.h Normal file
View File

@ -0,0 +1,581 @@
/**
******************************************************************************
* @file stm32f7xx_hal_jpeg.h
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of JPEG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_JPEG_H
#define __STM32F7xx_HAL_JPEG_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup JPEG
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup JPEG_Exported_Types JPEG Exported Types
* @{
*/
/** @defgroup JPEG_Configuration_Structure_definition JPEG Configuration for encoding Structure definition
* @brief JPEG encoding configuration Structure definition
* @{
*/
typedef struct
{
uint8_t ColorSpace; /*!< Image Color space : gray-scale, YCBCR, RGB or CMYK
This parameter can be a value of @ref JPEG_ColorSpace_Type */
uint8_t ChromaSubsampling; /*!< Chroma Subsampling in case of YCBCR or CMYK color space, 0-> 4:4:4 , 1-> 4:2:2, 2 -> 4:1:1, 3 -> 4:2:0
This parameter can be a value of @ref JPEG_ChromaSubsampling_Type */
uint32_t ImageHeight; /*!< Image height : number of lines */
uint32_t ImageWidth; /*!< Image width : number of pixels per line */
uint8_t ImageQuality; /*!< Quality of the JPEG encoding : from 1 to 100 */
}JPEG_ConfTypeDef;
/**
* @}
*/
/** @defgroup HAL_JPEG_state_structure_definition HAL JPEG state structure definition
* @brief HAL JPEG State structure definition
* @{
*/
typedef enum
{
HAL_JPEG_STATE_RESET = 0x00U, /*!< JPEG not yet initialized or disabled */
HAL_JPEG_STATE_READY = 0x01U, /*!< JPEG initialized and ready for use */
HAL_JPEG_STATE_BUSY = 0x02U, /*!< JPEG internal processing is ongoing */
HAL_JPEG_STATE_BUSY_ENCODING = 0x03U, /*!< JPEG encoding processing is ongoing */
HAL_JPEG_STATE_BUSY_DECODING = 0x04U, /*!< JPEG decoding processing is ongoing */
HAL_JPEG_STATE_TIMEOUT = 0x05U, /*!< JPEG timeout state */
HAL_JPEG_STATE_ERROR = 0x06U /*!< JPEG error state */
}HAL_JPEG_STATETypeDef;
/**
* @}
*/
/** @defgroup JPEG_handle_Structure_definition JPEG handle Structure definition
* @brief JPEG handle Structure definition
* @{
*/
typedef struct
{
JPEG_TypeDef *Instance; /*!< JPEG peripheral register base address */
JPEG_ConfTypeDef Conf; /*!< Current JPEG encoding/decoding parameters */
uint8_t *pJpegInBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) input buffer */
uint8_t *pJpegOutBuffPtr; /*!< Pointer to JPEG processing (encoding, decoding,...) output buffer */
__IO uint32_t JpegInCount; /*!< Internal Counter of input data */
__IO uint32_t JpegOutCount; /*!< Internal Counter of output data */
uint32_t InDataLength; /*!< Input Buffer Length in Bytes */
uint32_t OutDataLength; /*!< Output Buffer Length in Bytes */
DMA_HandleTypeDef *hdmain; /*!< JPEG In DMA handle parameters */
DMA_HandleTypeDef *hdmaout; /*!< JPEG Out DMA handle parameters */
uint8_t CustomQuanTable; /*!< If set to ‘1’ specify that user customized quantization tables are used */
uint8_t *QuantTable0; /*!< Basic Quantization Table for component 0 */
uint8_t *QuantTable1; /*!< Basic Quantization Table for component 1 */
uint8_t *QuantTable2; /*!< Basic Quantization Table for component 2 */
uint8_t *QuantTable3; /*!< Basic Quantization Table for component 3 */
HAL_LockTypeDef Lock; /*!< JPEG locking object */
__IO HAL_JPEG_STATETypeDef State; /*!< JPEG peripheral state */
__IO uint32_t ErrorCode; /*!< JPEG Error code */
__IO uint32_t Context; /*!< JPEG Internal context */
}JPEG_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup JPEG_Exported_Constants JPEG Exported Constants
* @{
*/
/** @defgroup JPEG_Error_Code_definition JPEG Error Code definition
* @brief JPEG Error Code definition
* @{
*/
#define HAL_JPEG_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_JPEG_ERROR_HUFF_TABLE ((uint32_t)0x00000001U) /*!< HUffman Table programming error */
#define HAL_JPEG_ERROR_QUANT_TABLE ((uint32_t)0x00000002U) /*!< Quantization Table programming error */
#define HAL_JPEG_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_JPEG_ERROR_TIMEOUT ((uint32_t)0x00000008U) /*!< Timeout error */
/**
* @}
*/
/** @defgroup JPEG_Quantization_Table_Size JPEG Quantization Table Size
* @brief JPEG Quantization Table Size
* @{
*/
#define JPEG_QUANT_TABLE_SIZE ((uint32_t)64U)
/**
* @}
*/
/** @defgroup JPEG_ColorSpace_Type JPEG ColorSpace
* @brief JPEG Color Space
* @{
*/
#define JPEG_GRAYSCALE_COLORSPACE ((uint32_t)0x00000000U)
#define JPEG_YCBCR_COLORSPACE JPEG_CONFR1_COLORSPACE_0
#define JPEG_CMYK_COLORSPACE JPEG_CONFR1_COLORSPACE
/**
* @}
*/
/** @defgroup JPEG_ChromaSubsampling_Type JPEG Chrominance Sampling
* @brief JPEG Chrominance Sampling
* @{
*/
#define JPEG_444_SUBSAMPLING ((uint32_t)0x00000000U) /*!< Chroma Subsampling 4:4:4 */
#define JPEG_420_SUBSAMPLING ((uint32_t)0x00000001U) /*!< Chroma Subsampling 4:2:0 */
#define JPEG_422_SUBSAMPLING ((uint32_t)0x00000002U) /*!< Chroma Subsampling 4:2:2 */
/**
* @}
*/
/** @defgroup JPEG_ImageQuality JPEG Image Quality
* @brief JPEG Min and Max Image Quality
* @{
*/
#define JPEG_IMAGE_QUALITY_MIN ((uint32_t)1U) /*!< Minimum JPEG quality */
#define JPEG_IMAGE_QUALITY_MAX ((uint32_t)100U) /*!< Maximum JPEG quality */
/**
* @}
*/
/** @defgroup JPEG_Interrupt_configuration_definition JPEG Interrupt configuration definition
* @brief JPEG Interrupt definition
* @{
*/
#define JPEG_IT_IFT ((uint32_t)JPEG_CR_IFTIE) /*!< Input FIFO Threshold Interrupt */
#define JPEG_IT_IFNF ((uint32_t)JPEG_CR_IFNFIE) /*!< Input FIFO Not Full Interrupt */
#define JPEG_IT_OFT ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Threshold Interrupt */
#define JPEG_IT_OFNE ((uint32_t)JPEG_CR_OFTIE) /*!< Output FIFO Not Empty Interrupt */
#define JPEG_IT_EOC ((uint32_t)JPEG_CR_EOCIE) /*!< End of Conversion Interrupt */
#define JPEG_IT_HPD ((uint32_t)JPEG_CR_HPDIE) /*!< Header Parsing Done Interrupt */
/**
* @}
*/
/** @defgroup JPEG_Flag_definition JPEG Flag definition
* @brief JPEG Flags definition
* @{
*/
#define JPEG_FLAG_IFTF ((uint32_t)JPEG_SR_IFTF) /*!< Input FIFO is not full and is bellow its threshold flag */
#define JPEG_FLAG_IFNFF ((uint32_t)JPEG_SR_IFNFF) /*!< Input FIFO Not Full Flag, a data can be written */
#define JPEG_FLAG_OFTF ((uint32_t)JPEG_SR_OFTF) /*!< Output FIFO is not empty and has reach its threshold */
#define JPEG_FLAG_OFNEF ((uint32_t)JPEG_SR_OFNEF) /*!< Output FIFO is not empty, a data is available */
#define JPEG_FLAG_EOCF ((uint32_t)JPEG_SR_EOCF) /*!< JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
#define JPEG_FLAG_HPDF ((uint32_t)JPEG_SR_HPDF) /*!< JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
#define JPEG_FLAG_COF ((uint32_t)JPEG_SR_COF) /*!< JPEG Codec operation on going flag*/
#define JPEG_FLAG_ALL ((uint32_t)0x000000FEU) /*!< JPEG Codec All previous flag*/
/**
* @}
*/
/** @defgroup JPEG_PROCESS_PAUSE_RESUME_definition JPEG Process Pause Resume definition
* @brief JPEG process pause, resume definition
* @{
*/
#define JPEG_PAUSE_RESUME_INPUT ((uint32_t)0x00000001U) /*!< Pause/Resume Input FIFO Xfer*/
#define JPEG_PAUSE_RESUME_OUTPUT ((uint32_t)0x00000002U) /*!< Pause/Resume Output FIFO Xfer*/
#define JPEG_PAUSE_RESUME_INPUT_OUTPUT ((uint32_t)0x00000003U) /*!< Pause/Resume Input and Output FIFO Xfer*/
/**
* @}
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup JPEG_Exported_Macros JPEG Exported Macros
* @{
*/
/** @brief Reset JPEG handle state
* @param __HANDLE__: specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET)
/**
* @brief Enable the JPEG peripheral.
* @param __HANDLE__: specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN)
/**
* @brief Disable the JPEG peripheral.
* @param __HANDLE__: specifies the JPEG handle.
* @retval None
*/
#define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN)
/**
* @brief Check the specified JPEG status flag.
* @param __HANDLE__: specifies the JPEG handle.
* @param __FLAG__ : specifies the flag to check
* This parameter can be one of the following values:
* @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag
* @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written
* @arg JPEG_FLAG_OFTF : The output FIFO is not empty and has reach its threshold
* @arg JPEG_FLAG_OFNEF : The output FIFO is not empty, a data is available
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
* and the internal registers have been updated
* @arg JPEG_FLAG_COF : JPEG Codec operation on going flag
*
* @retval : __HAL_JPEG_GET_FLAG : returns The new state of __FLAG__ (TRUE or FALSE)
*/
#define __HAL_JPEG_GET_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)))
/**
* @brief Clear the specified JPEG status flag.
* @param __HANDLE__: specifies the JPEG handle.
* @param __FLAG__ : specifies the flag to clear
* This parameter can be one of the following values:
* @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process
* and than last data has been sent to the output FIFO
* @arg JPEG_FLAG_HPDF : JPEG Codec has finished the parsing of the headers
* @retval : None
*/
#define __HAL_JPEG_CLEAR_FLAG(__HANDLE__,__FLAG__) (((__HANDLE__)->Instance->CFR |= ((__FLAG__) & (JPEG_FLAG_EOCF | JPEG_FLAG_HPDF))))
/**
* @brief Enable Interrupt.
* @param __HANDLE__: specifies the JPEG handle.
* @param __INTERRUPT__ : specifies the interrupt to enable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @retval : No retrun
*/
#define __HAL_JPEG_ENABLE_IT(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__) )
/**
* @brief Disable Interrupt.
* @param __HANDLE__: specifies the JPEG handle.
* @param __INTERRUPT__ : specifies the interrupt to disable
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @note : To disable an IT we must use MODIFY_REG macro to avoid writing "1" to the FIFO flush bits
* located in the same IT enable register (CR register).
* @retval : No retrun
*/
#define __HAL_JPEG_DISABLE_IT(__HANDLE__,__INTERRUPT__) MODIFY_REG((__HANDLE__)->Instance->CR, (__INTERRUPT__), 0)
/**
* @brief Get Interrupt state.
* @param __HANDLE__: specifies the JPEG handle.
* @param __INTERRUPT__ : specifies the interrupt to check
* This parameter can be one of the following values:
* @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt
* @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
* @arg JPEG_IT_OFT : Output FIFO Threshold Interrupt
* @arg JPEG_IT_OFNE : Output FIFO Not empty Interrupt
* @arg JPEG_IT_EOC : End of Conversion Interrupt
* @arg JPEG_IT_HPD : Header Parsing Done Interrupt
*
* @retval : returns The new state of __INTERRUPT__ (Enabled or disabled)
*/
#define __HAL_JPEG_GET_IT_SOURCE(__HANDLE__,__INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup JPEG_Exported_Functions
* @{
*/
/** @addtogroup JPEG_Exported_Functions_Group1
* @{
*/
/* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_JPEG_Init(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DeInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspInit(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_MspDeInit(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group2
* @{
*/
/* Encoding/Decoding Configuration functions ********************************/
HAL_StatusTypeDef HAL_JPEG_ConfigEncoding(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pConf);
HAL_StatusTypeDef HAL_JPEG_GetInfo(JPEG_HandleTypeDef *hjpeg, JPEG_ConfTypeDef *pInfo);
HAL_StatusTypeDef HAL_JPEG_EnableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_DisableHeaderParsing(JPEG_HandleTypeDef *hjpeg);
HAL_StatusTypeDef HAL_JPEG_SetUserQuantTables(JPEG_HandleTypeDef *hjpeg, uint8_t *QTable0, uint8_t *QTable1, uint8_t *QTable2, uint8_t *QTable3);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group3
* @{
*/
/* JPEG processing functions **************************************/
HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout);
HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout);
HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Pause(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
HAL_StatusTypeDef HAL_JPEG_Resume(JPEG_HandleTypeDef *hjpeg, uint32_t XferSelection);
void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength);
void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength);
HAL_StatusTypeDef HAL_JPEG_Abort(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group4
* @{
*/
/* JPEG Decode/Encode callback functions ********************************************************/
void HAL_JPEG_InfoReadyCallback(JPEG_HandleTypeDef *hjpeg,JPEG_ConfTypeDef *pInfo);
void HAL_JPEG_EncodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_DecodeCpltCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_ErrorCallback(JPEG_HandleTypeDef *hjpeg);
void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData);
void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group5
* @{
*/
/* JPEG IRQ handler management ******************************************************/
void HAL_JPEG_IRQHandler(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/** @addtogroup JPEG_Exported_Functions_Group6
* @{
*/
/* Peripheral State and Error functions ************************************************/
HAL_JPEG_STATETypeDef HAL_JPEG_GetState(JPEG_HandleTypeDef *hjpeg);
uint32_t HAL_JPEG_GetError(JPEG_HandleTypeDef *hjpeg);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup JPEG_Private_Types JPEG Private Types
* @{
*/
/**
* @}
*/
/* Private defines -----------------------------------------------------------*/
/** @defgroup JPEG_Private_Defines JPEG Private Defines
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Variables JPEG Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Constants JPEG Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup JPEG_Private_Macros JPEG Private Macros
* @{
*/
/** @defgroup JPEG_IS_Definitions JPEG Private macros to check input parameters
* @{
*/
#define IS_JPEG_CHROMASUBSAMPLING(SUBSAMPLING) (((SUBSAMPLING) == JPEG_444_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_420_SUBSAMPLING) || \
((SUBSAMPLING) == JPEG_422_SUBSAMPLING))
#define IS_JPEG_IMAGE_QUALITY(NUMBER) (((NUMBER) >= JPEG_IMAGE_QUALITY_MIN) && ((NUMBER) <= JPEG_IMAGE_QUALITY_MAX))
#define IS_JPEG_COLORSPACE(COLORSPACE) (((COLORSPACE) == JPEG_GRAYSCALE_COLORSPACE) || \
((COLORSPACE) == JPEG_YCBCR_COLORSPACE) || \
((COLORSPACE) == JPEG_CMYK_COLORSPACE))
#define IS_JPEG_PAUSE_RESUME_STATE(VALUE) (((VALUE) == JPEG_PAUSE_RESUME_INPUT) || \
((VALUE) == JPEG_PAUSE_RESUME_OUTPUT)|| \
((VALUE) == JPEG_PAUSE_RESUME_INPUT_OUTPUT))
/**
* @}
*/
/**
* @}
*/
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup JPEG_Private_Functions_Prototypes JPEG Private Functions Prototypes
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup JPEG_Private_Functions JPEG Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_JPEG_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

34
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
@ -93,7 +93,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -1001,7 +1001,7 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Configure edge sensitivity for encoder mode */
/* Get the LPTIMx CFGR value */
tmpcfgr = hlptim->Instance->CFGR;
@ -1162,6 +1162,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
@ -1200,6 +1206,12 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@ -1295,6 +1307,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Enable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT();
/* Enable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();
/* If clock source is not ULPTIM clock and counter source is external, then it must not be prescaled */
if((hlptim->Init.Clock.Source != LPTIM_CLOCKSOURCE_ULPTIM) && (hlptim->Init.CounterSource == LPTIM_COUNTERSOURCE_EXTERNAL))
@ -1340,6 +1358,12 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Set the LPTIM state */
hlptim->State= HAL_LPTIM_STATE_BUSY;
/* Disable rising edge trigger on the LPTIM Wake-up Timer Exti line */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();
/* Disable EXTI Line interrupt on the LPTIM Wake-up Timer */
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT();
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
@ -1523,6 +1547,8 @@ void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
HAL_LPTIM_DirectionDownCallback(hlptim);
}
}
__HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG();
}
/**

135
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_lptim.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -60,6 +60,14 @@
* @{
*/
/** @defgroup LPTIM_WAKEUPTIMER_EXTILINE LPTIM WAKEUP Timer EXTI Line
* @{
*/
#define LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT ((uint32_t)EXTI_IMR_MR23) /*!< External interrupt line 23 Connected to the LPTIM EXTI Line */
/**
* @}
*/
/**
* @brief LPTIM Clock configuration definition
*/
@ -137,11 +145,11 @@ typedef struct
*/
typedef enum __HAL_LPTIM_StateTypeDef
{
HAL_LPTIM_STATE_RESET = 0x00, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04 /*!< Internal Process is ongoing */
HAL_LPTIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
HAL_LPTIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_LPTIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
HAL_LPTIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
HAL_LPTIM_STATE_ERROR = 0x04U /*!< Internal Process is ongoing */
}HAL_LPTIM_StateTypeDef;
/**
@ -173,7 +181,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Source LPTIM Clock Source
* @{
*/
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00)
#define LPTIM_CLOCKSOURCE_APBCLOCK_LPOSC ((uint32_t)0x00U)
#define LPTIM_CLOCKSOURCE_ULPTIM LPTIM_CFGR_CKSEL
/**
* @}
@ -182,7 +190,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Prescaler LPTIM Clock Prescaler
* @{
*/
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000)
#define LPTIM_PRESCALER_DIV1 ((uint32_t)0x000000U)
#define LPTIM_PRESCALER_DIV2 LPTIM_CFGR_PRESC_0
#define LPTIM_PRESCALER_DIV4 LPTIM_CFGR_PRESC_1
#define LPTIM_PRESCALER_DIV8 ((uint32_t)(LPTIM_CFGR_PRESC_0 | LPTIM_CFGR_PRESC_1))
@ -198,7 +206,7 @@ typedef struct
* @{
*/
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000)
#define LPTIM_OUTPUTPOLARITY_HIGH ((uint32_t)0x00000000U)
#define LPTIM_OUTPUTPOLARITY_LOW (LPTIM_CFGR_WAVPOL)
/**
* @}
@ -207,7 +215,7 @@ typedef struct
/** @defgroup LPTIM_Clock_Sample_Time LPTIM Clock Sample Time
* @{
*/
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define LPTIM_CLOCKSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_CLOCKSAMPLETIME_2TRANSITIONS LPTIM_CFGR_CKFLT_0
#define LPTIM_CLOCKSAMPLETIME_4TRANSITIONS LPTIM_CFGR_CKFLT_1
#define LPTIM_CLOCKSAMPLETIME_8TRANSITIONS LPTIM_CFGR_CKFLT
@ -219,7 +227,7 @@ typedef struct
* @{
*/
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000)
#define LPTIM_CLOCKPOLARITY_RISING ((uint32_t)0x00000000U)
#define LPTIM_CLOCKPOLARITY_FALLING LPTIM_CFGR_CKPOL_0
#define LPTIM_CLOCKPOLARITY_RISING_FALLING LPTIM_CFGR_CKPOL_1
/**
@ -229,8 +237,8 @@ typedef struct
/** @defgroup LPTIM_Trigger_Source LPTIM Trigger Source
* @{
*/
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFF)
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000)
#define LPTIM_TRIGSOURCE_SOFTWARE ((uint32_t)0x0000FFFFU)
#define LPTIM_TRIGSOURCE_0 ((uint32_t)0x00000000U)
#define LPTIM_TRIGSOURCE_1 ((uint32_t)LPTIM_CFGR_TRIGSEL_0)
#define LPTIM_TRIGSOURCE_2 LPTIM_CFGR_TRIGSEL_1
#define LPTIM_TRIGSOURCE_3 ((uint32_t)LPTIM_CFGR_TRIGSEL_0 | LPTIM_CFGR_TRIGSEL_1)
@ -253,7 +261,7 @@ typedef struct
/** @defgroup LPTIM_Trigger_Sample_Time LPTIM Trigger Sample Time
* @{
*/
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000)
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION ((uint32_t)0x00000000U)
#define LPTIM_TRIGSAMPLETIME_2TRANSITIONS LPTIM_CFGR_TRGFLT_0
#define LPTIM_TRIGSAMPLETIME_4TRANSITIONS LPTIM_CFGR_TRGFLT_1
#define LPTIM_TRIGSAMPLETIME_8TRANSITIONS LPTIM_CFGR_TRGFLT
@ -265,7 +273,7 @@ typedef struct
* @{
*/
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000)
#define LPTIM_UPDATE_IMMEDIATE ((uint32_t)0x00000000U)
#define LPTIM_UPDATE_ENDOFPERIOD LPTIM_CFGR_PRELOAD
/**
* @}
@ -275,7 +283,7 @@ typedef struct
* @{
*/
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000)
#define LPTIM_COUNTERSOURCE_INTERNAL ((uint32_t)0x00000000U)
#define LPTIM_COUNTERSOURCE_EXTERNAL LPTIM_CFGR_COUNTMODE
/**
* @}
@ -440,6 +448,89 @@ typedef struct
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Enable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_IT() (EXTI->IMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable event on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE() (EXTI->FTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE() (EXTI->FTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE() (EXTI->RTSR |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Disable rising edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE() (EXTI->RTSR &= ~(LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT))
/**
* @brief Enable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_RISING_EDGE();\
__HAL_LPTIM_WAKEUPTIMER_EXTI_ENABLE_FALLING_EDGE();\
}while(0)
/**
* @brief Disable rising & falling edge trigger on the LPTIM Wake-up Timer associated Exti line.
* This parameter can be:
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_FALLING_EDGE() do{__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_RISING_EDGE();\
__HAL_LPTIM_WAKEUPTIMER_EXTI_DISABLE_FALLING_EDGE();\
}while(0)
/**
* @brief Check whether the LPTIM Wake-up Timer associated Exti line interrupt flag is set or not.
* @retval Line Status.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GET_FLAG() (EXTI->PR & LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Clear the LPTIM Wake-up Timer associated Exti line flag.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_CLEAR_FLAG() (EXTI->PR = LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @brief Generate a Software interrupt on the LPTIM Wake-up Timer associated Exti line.
* @retval None.
*/
#define __HAL_LPTIM_WAKEUPTIMER_EXTI_GENERATE_SWIT() (EXTI->SWIER |= LPTIM_EXTI_LINE_WAKEUPTIMER_EVENT)
/**
* @}
*/
@ -610,13 +701,13 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
#define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \
((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL))
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFF)
#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((__AUTORELOAD__) <= 0x0000FFFFU)
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFF)
#define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFU)
#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFF)
#define IS_LPTIM_PERIOD(PERIOD) ((PERIOD) <= 0x0000FFFFU)
#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFF)
#define IS_LPTIM_PULSE(PULSE) ((PULSE) <= 0x0000FFFFU)
/**
* @}

726
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@ -43,6 +43,19 @@
for foreground or/and background layer using respectively the following
functions: HAL_LTDC_SetPixelFormat(), HAL_LTDC_SetAlpha(), HAL_LTDC_SetWindowSize(),
HAL_LTDC_SetWindowPosition(), HAL_LTDC_SetAddress.
(#) Variant functions with “_NoReload” post fix allows to set the LTDC configuration/settings without immediate reload.
This is useful in case when the program requires to modify serval LTDC settings (on one or both layers)
then applying(reload) these settings in one shot by calling the function “HAL_LTDC_Reload”
After calling the “_NoReload” functions to set different color/format/layer settings,
the program can call the function “HAL_LTDC_Reload” To apply(Reload) these settings.
Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType”
set to LTDC_RELOAD_IMMEDIATE if an immediate reload is required.
Function “HAL_LTDC_Reload” can be called with the parameter “ReloadType”
set to LTDC_RELOAD_VERTICAL_BLANKING if the reload should be done in the next vertical blanking period,
this option allows to avoid display flicker by applying the new settings during the vertical blanking period.
(#) To control LTDC state you can use the following function: HAL_LTDC_GetState()
@ -69,7 +82,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -102,7 +115,7 @@
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
#if defined (STM32F746xx) || defined (STM32F756xx)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @defgroup LTDC LTDC
* @brief LTDC HAL module driver
@ -381,6 +394,27 @@ void HAL_LTDC_IRQHandler(LTDC_HandleTypeDef *hltdc)
HAL_LTDC_LineEvenCallback(hltdc);
}
}
/* Register reload Interrupt management ***************************************/
if(__HAL_LTDC_GET_FLAG(hltdc, LTDC_FLAG_RR) != RESET)
{
if(__HAL_LTDC_GET_IT_SOURCE(hltdc, LTDC_IT_RR) != RESET)
{
/* Disable the register reload interrupt */
__HAL_LTDC_DISABLE_IT(hltdc, LTDC_IT_RR);
/* Clear the register reload flag */
__HAL_LTDC_CLEAR_FLAG(hltdc, LTDC_FLAG_RR);
/* Change LTDC state */
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
/* Register reload interrupt Callback */
HAL_LTDC_ReloadEventCallback(hltdc);
}
}
}
/**
@ -415,6 +449,22 @@ __weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
*/
}
/**
* @brief Reload Event callback.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
__weak void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_LTDC_ReloadEvenCallback could be implemented in the user file
*/
}
/**
* @}
*/
@ -741,7 +791,7 @@ HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc)
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable Dither by setting DTEN bit */
LTDC->GCR |= (uint32_t)LTDC_GCR_DTEN;
LTDC->GCR |= (uint32_t)LTDC_GCR_DEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@ -768,7 +818,7 @@ HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc)
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Disable Dither by setting DTEN bit */
LTDC->GCR &= ~(uint32_t)LTDC_GCR_DTEN;
LTDC->GCR &= ~(uint32_t)LTDC_GCR_DEN;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
@ -1029,7 +1079,81 @@ HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Addres
}
/**
* @brief Define the position of the line interrupt .
* @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
* larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
* want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
* will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
* Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
* configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
* @param LayerIdx: LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
uint32_t tmp = 0;
uint32_t pitchUpdate = 0;
uint32_t pixelFormat = 0;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4;
}
else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
tmp = 3;
}
else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
(pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
(pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
(pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2;
}
else
{
tmp = 1;
}
pitchUpdate = ((LinePitchInPixels * tmp) << 16);
/* Clear previously set standard pitch */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
/* Sets the Reload type as immediate update of LTDC pitch configured above */
LTDC->SRCR |= LTDC_SRCR_IMR;
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
/* Sets the Reload type as immediate update of LTDC pitch configured above */
LTDC->SRCR |= LTDC_SRCR_IMR;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Define the position of the line interrupt.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Line: Line Interrupt Position.
@ -1061,6 +1185,592 @@ HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t
return HAL_OK;
}
/**
* @brief LTDC configuration reload.
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param ReloadType: This parameter can be one of the following values :
* LTDC_RELOAD_IMMEDIATE : Immediate Reload
* LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType)
{
assert_param(IS_LTDC_RELAOD(ReloadType));
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Enable the Reload interrupt */
__HAL_LTDC_ENABLE_IT(hltdc, LTDC_IT_RR);
/* Apply Reload type */
hltdc->Instance->SRCR = ReloadType;
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Configure the LTDC Layer according to the specified without reloading
* parameters in the LTDC_InitTypeDef and create the associated handle.
* Variant of the function HAL_LTDC_ConfigLayer without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_PIXEL_FORMAT(pLayerCfg->PixelFormat));
assert_param(IS_LTDC_BLENDING_FACTOR1(pLayerCfg->BlendingFactor1));
assert_param(IS_LTDC_BLENDING_FACTOR2(pLayerCfg->BlendingFactor2));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
assert_param(IS_LTDC_ALPHA(pLayerCfg->Alpha0));
assert_param(IS_LTDC_CFBLL(pLayerCfg->ImageWidth));
assert_param(IS_LTDC_CFBLNBR(pLayerCfg->ImageHeight));
/* Copy new layer configuration into handle structure */
hltdc->LayerCfg[LayerIdx] = *pLayerCfg;
/* Configure the LTDC Layer */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Do not Sets the Reload */
/* Initialize the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Set the LTDC window size without reloading.
* Variant of the function HAL_LTDC_SetWindowSize without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param XSize: LTDC Pixel per line
* @param YSize: LTDC Line number
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Check the parameters (Layers parameters)*/
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
assert_param(IS_LTDC_CFBLL(XSize));
assert_param(IS_LTDC_CFBLNBR(YSize));
/* update horizontal start/stop */
pLayerCfg->WindowX0 = 0;
pLayerCfg->WindowX1 = XSize + pLayerCfg->WindowX0;
/* update vertical start/stop */
pLayerCfg->WindowY0 = 0;
pLayerCfg->WindowY1 = YSize + pLayerCfg->WindowY0;
/* Reconfigures the color frame buffer pitch in byte */
pLayerCfg->ImageWidth = XSize;
/* Reconfigures the frame buffer line number */
pLayerCfg->ImageHeight = YSize;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Set the LTDC window position without reloading.
* Variant of the function HAL_LTDC_SetWindowPosition without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param X0: LTDC window X offset
* @param Y0: LTDC window Y offset
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_HCONFIGST(pLayerCfg->WindowX0));
assert_param(IS_LTDC_HCONFIGSP(pLayerCfg->WindowX1));
assert_param(IS_LTDC_VCONFIGST(pLayerCfg->WindowY0));
assert_param(IS_LTDC_VCONFIGSP(pLayerCfg->WindowY1));
/* update horizontal start/stop */
pLayerCfg->WindowX0 = X0;
pLayerCfg->WindowX1 = X0 + pLayerCfg->ImageWidth;
/* update vertical start/stop */
pLayerCfg->WindowY0 = Y0;
pLayerCfg->WindowY1 = Y0 + pLayerCfg->ImageHeight;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the pixel format without reloading.
* Variant of the function HAL_LTDC_SetPixelFormat without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDfef structure that contains
* the configuration information for the LTDC.
* @param Pixelformat: new pixel format value.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
assert_param(IS_LTDC_PIXEL_FORMAT(Pixelformat));
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the pixel format */
pLayerCfg->PixelFormat = Pixelformat;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the layer alpha value without reloading.
* Variant of the function HAL_LTDC_SetAlpha without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Alpha: new alpha value.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_ALPHA(Alpha));
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the Alpha value */
pLayerCfg->Alpha = Alpha;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Reconfigure the frame buffer Address without reloading.
* Variant of the function HAL_LTDC_SetAddress without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param Address: new address value.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx)
{
LTDC_LayerCfgTypeDef *pLayerCfg;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Get layer configuration from handle structure */
pLayerCfg = &hltdc->LayerCfg[LayerIdx];
/* Reconfigure the Address */
pLayerCfg->FBStartAdress = Address;
/* Set LTDC parameters */
LTDC_SetConfig(hltdc, pLayerCfg, LayerIdx);
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Function used to reconfigure the pitch for specific cases where the attached LayerIdx buffer have a width that is
* larger than the one intended to be displayed on screen. Example of a buffer 800x480 attached to layer for which we
* want to read and display on screen only a portion 320x240 taken in the center of the buffer. The pitch in pixels
* will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
* Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
* configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* Variant of the function HAL_LTDC_SetPitch without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
* @param LayerIdx: LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
{
uint32_t tmp = 0;
uint32_t pitchUpdate = 0;
uint32_t pixelFormat = 0;
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* get LayerIdx used pixel format */
pixelFormat = hltdc->LayerCfg[LayerIdx].PixelFormat;
if(pixelFormat == LTDC_PIXEL_FORMAT_ARGB8888)
{
tmp = 4;
}
else if (pixelFormat == LTDC_PIXEL_FORMAT_RGB888)
{
tmp = 3;
}
else if((pixelFormat == LTDC_PIXEL_FORMAT_ARGB4444) || \
(pixelFormat == LTDC_PIXEL_FORMAT_RGB565) || \
(pixelFormat == LTDC_PIXEL_FORMAT_ARGB1555) || \
(pixelFormat == LTDC_PIXEL_FORMAT_AL88))
{
tmp = 2;
}
else
{
tmp = 1;
}
pitchUpdate = ((LinePitchInPixels * tmp) << 16);
/* Clear previously set standard pitch */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR &= ~LTDC_LxCFBLR_CFBP;
/* Set new line pitch value */
LTDC_LAYER(hltdc, LayerIdx)->CFBLR |= pitchUpdate;
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Configure the color keying without reloading.
* Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param RGBValue: the color key value
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Configures the default color values */
LTDC_LAYER(hltdc, LayerIdx)->CKCR &= ~(LTDC_LxCKCR_CKBLUE | LTDC_LxCKCR_CKGREEN | LTDC_LxCKCR_CKRED);
LTDC_LAYER(hltdc, LayerIdx)->CKCR = RGBValue;
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable the color keying without reloading.
* Variant of the function HAL_LTDC_EnableColorKeying without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Enable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_COLKEN;
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable the color keying without reloading.
* Variant of the function HAL_LTDC_DisableColorKeying without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Disable LTDC color keying by setting COLKEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_COLKEN;
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Enable the color lookup table without reloading.
* Variant of the function HAL_LTDC_EnableCLUT without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR |= (uint32_t)LTDC_LxCR_CLUTEN;
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @brief Disable the color lookup table without reloading.
* Variant of the function HAL_LTDC_DisableCLUT without immediate reload
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param LayerIdx: LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx)
{
/* Process locked */
__HAL_LOCK(hltdc);
/* Change LTDC peripheral state */
hltdc->State = HAL_LTDC_STATE_BUSY;
/* Check the parameters */
assert_param(IS_LTDC_LAYER(LayerIdx));
/* Disable LTDC color lookup table by setting CLUTEN bit */
LTDC_LAYER(hltdc, LayerIdx)->CR &= ~(uint32_t)LTDC_LxCR_CLUTEN;
/* Do not Sets the Reload */
/* Change the LTDC state*/
hltdc->State = HAL_LTDC_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hltdc);
return HAL_OK;
}
/**
* @}
*/
@ -1196,7 +1906,7 @@ static void LTDC_SetConfig(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLay
/**
* @}
*/
#endif /* STM32F746xx || STM32F756xx */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}

95
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of LTDC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -43,7 +43,8 @@
extern "C" {
#endif
#if defined(STM32F756xx) || defined(STM32F746xx)
#if defined (STM32F746xx) || defined (STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
@ -172,11 +173,11 @@ typedef struct
*/
typedef enum
{
HAL_LTDC_STATE_RESET = 0x00, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01, /*!< LTDC initialized and ready for use */
HAL_LTDC_STATE_BUSY = 0x02, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04 /*!< LTDC state error */
HAL_LTDC_STATE_RESET = 0x00U, /*!< LTDC not yet initialized or disabled */
HAL_LTDC_STATE_READY = 0x01U, /*!< LTDC initialized and ready for use */
HAL_LTDC_STATE_BUSY = 0x02U, /*!< LTDC internal process is ongoing */
HAL_LTDC_STATE_TIMEOUT = 0x03U, /*!< LTDC Timeout state */
HAL_LTDC_STATE_ERROR = 0x04U /*!< LTDC state error */
}HAL_LTDC_StateTypeDef;
/**
@ -209,10 +210,10 @@ typedef struct
/** @defgroup LTDC_Error_Code LTDC Error Code
* @{
*/
#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000) /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001) /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002) /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< LTDC Timeout error */
#define HAL_LTDC_ERROR_NONE ((uint32_t)0x00000000U) /*!< LTDC No error */
#define HAL_LTDC_ERROR_TE ((uint32_t)0x00000001U) /*!< LTDC Transfer error */
#define HAL_LTDC_ERROR_FU ((uint32_t)0x00000002U) /*!< LTDC FIFO Underrun */
#define HAL_LTDC_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< LTDC Timeout error */
/**
* @}
*/
@ -220,7 +221,7 @@ typedef struct
/** @defgroup LTDC_HS_POLARITY LTDC HS POLARITY
* @{
*/
#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000) /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Horizontal Synchronization is active low. */
#define LTDC_HSPOLARITY_AH LTDC_GCR_HSPOL /*!< Horizontal Synchronization is active high. */
/**
* @}
@ -229,7 +230,7 @@ typedef struct
/** @defgroup LTDC_VS_POLARITY LTDC VS POLARITY
* @{
*/
#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000) /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AL ((uint32_t)0x00000000U) /*!< Vertical Synchronization is active low. */
#define LTDC_VSPOLARITY_AH LTDC_GCR_VSPOL /*!< Vertical Synchronization is active high. */
/**
* @}
@ -238,7 +239,7 @@ typedef struct
/** @defgroup LTDC_DE_POLARITY LTDC DE POLARITY
* @{
*/
#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000) /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AL ((uint32_t)0x00000000U) /*!< Data Enable, is active low. */
#define LTDC_DEPOLARITY_AH LTDC_GCR_DEPOL /*!< Data Enable, is active high. */
/**
* @}
@ -247,7 +248,7 @@ typedef struct
/** @defgroup LTDC_PC_POLARITY LTDC PC POLARITY
* @{
*/
#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000) /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IPC ((uint32_t)0x00000000U) /*!< input pixel clock. */
#define LTDC_PCPOLARITY_IIPC LTDC_GCR_PCPOL /*!< inverted input pixel clock. */
/**
* @}
@ -265,7 +266,7 @@ typedef struct
/** @defgroup LTDC_BACK_COLOR LTDC BACK COLOR
* @{
*/
#define LTDC_COLOR ((uint32_t)0x000000FF) /*!< Color mask */
#define LTDC_COLOR ((uint32_t)0x000000FFU) /*!< Color mask */
/**
* @}
*/
@ -273,8 +274,8 @@ typedef struct
/** @defgroup LTDC_BlendingFactor1 LTDC Blending Factor1
* @{
*/
#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
#define LTDC_BLENDING_FACTOR1_CA ((uint32_t)0x00000400U) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR1_PAxCA ((uint32_t)0x00000600U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
@ -282,8 +283,8 @@ typedef struct
/** @defgroup LTDC_BlendingFactor2 LTDC Blending Factor2
* @{
*/
#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
#define LTDC_BLENDING_FACTOR2_CA ((uint32_t)0x00000005U) /*!< Blending factor : Cte Alpha */
#define LTDC_BLENDING_FACTOR2_PAxCA ((uint32_t)0x00000007U) /*!< Blending factor : Cte Alpha x Pixel Alpha*/
/**
* @}
*/
@ -291,14 +292,14 @@ typedef struct
/** @defgroup LTDC_Pixelformat LTDC Pixel format
* @{
*/
#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001) /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002) /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005) /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006) /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007) /*!< AL88 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB8888 ((uint32_t)0x00000000U) /*!< ARGB8888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB888 ((uint32_t)0x00000001U) /*!< RGB888 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_RGB565 ((uint32_t)0x00000002U) /*!< RGB565 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB1555 ((uint32_t)0x00000003U) /*!< ARGB1555 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_ARGB4444 ((uint32_t)0x00000004U) /*!< ARGB4444 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_L8 ((uint32_t)0x00000005U) /*!< L8 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL44 ((uint32_t)0x00000006U) /*!< AL44 LTDC pixel format */
#define LTDC_PIXEL_FORMAT_AL88 ((uint32_t)0x00000007U) /*!< AL88 LTDC pixel format */
/**
* @}
*/
@ -345,6 +346,15 @@ typedef struct
* @}
*/
/** @defgroup LTDC_Reload_Type LTDC Reload Type
* @{
*/
#define LTDC_RELOAD_IMMEDIATE LTDC_SRCR_IMR /*!< Immediate Reload */
#define LTDC_RELOAD_VERTICAL_BLANKING LTDC_SRCR_VBR /*!< Vertical Blanking Reload */
/**
* @}
*/
/**
* @}
*/
@ -467,6 +477,12 @@ typedef struct
/**
* @}
*/
#if defined (STM32F769xx) || defined (STM32F779xx)
/* Include LTDC HAL Extension module */
#include "stm32f7xx_hal_ltdc_ex.h"
#endif /* STM32F769xx) | STM32F779xx */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup LTDC_Exported_Functions
* @{
@ -481,6 +497,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc);
void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc);
void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
@ -504,6 +521,7 @@ HAL_StatusTypeDef HAL_LTDC_SetWindowPosition(LTDC_HandleTypeDef *hltdc, uint32_t
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigCLUT(LTDC_HandleTypeDef *hltdc, uint32_t *pCLUT, uint32_t CLUTSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
@ -513,6 +531,20 @@ HAL_StatusTypeDef HAL_LTDC_DisableCLUT(LTDC_HandleTypeDef *hltdc, uint32_t Layer
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line);
HAL_StatusTypeDef HAL_LTDC_EnableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_DisableDither(LTDC_HandleTypeDef *hltdc);
HAL_StatusTypeDef HAL_LTDC_Reload(LTDC_HandleTypeDef *hltdc, uint32_t ReloadType);
HAL_StatusTypeDef HAL_LTDC_ConfigLayer_NoReload(LTDC_HandleTypeDef *hltdc, LTDC_LayerCfgTypeDef *pLayerCfg, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowSize_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t XSize, uint32_t YSize, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetWindowPosition_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t X0, uint32_t Y0, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPixelFormat_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Pixelformat, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAlpha_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Alpha, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetAddress_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t Address, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_ConfigColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t RGBValue, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableColorKeying_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_EnableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
HAL_StatusTypeDef HAL_LTDC_DisableCLUT_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LayerIdx);
/**
* @}
*/
@ -599,6 +631,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
#define IS_LTDC_CFBLL(CFBLL) ((CFBLL) <= LTDC_COLOR_FRAME_BUFFER)
#define IS_LTDC_CFBLNBR(CFBLNBR) ((CFBLNBR) <= LTDC_LINE_NUMBER)
#define IS_LTDC_LIPOS(LIPOS) ((LIPOS) <= 0x7FF)
#define IS_LTDC_RELAOD(RELOADTYPE) (((RELOADTYPE) == LTDC_RELOAD_IMMEDIATE) || ((RELOADTYPE) == LTDC_SRCR_VBR))
/**
* @}
*/
@ -615,7 +648,7 @@ uint32_t HAL_LTDC_GetError(LTDC_HandleTypeDef *hltdc);
/**
* @}
*/
#endif /* STM32F746xx || STM32F756xx */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

164
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.c Normal file
View File

@ -0,0 +1,164 @@
/**
******************************************************************************
* @file stm32f7xx_hal_ltdc_ex.c
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief LTDC Extension HAL module driver.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup LTDCEx LTDCEx
* @brief LTDC HAL module driver
* @{
*/
#ifdef HAL_LTDC_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
/** @defgroup LTDCEx_Exported_Functions_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the LTDC
@endverbatim
* @{
*/
#if defined (STM32F769xx) || defined (STM32F779xx)
/**
* @brief Retrieve common parameters from DSI Video mode configuration structure
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
* the DSI video mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (VidCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (VidCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (VidCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = VidCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = VidCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = VidCfg->HSPolarity << 29; */
/* Retrieve vertical timing parameters from DSI */
hltdc->Init.VerticalSync = VidCfg->VerticalSyncActive - 1;
hltdc->Init.AccumulatedVBP = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch - 1;
hltdc->Init.AccumulatedActiveH = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive - 1;
hltdc->Init.TotalHeigh = VidCfg->VerticalSyncActive + VidCfg->VerticalBackPorch + VidCfg->VerticalActive + VidCfg->VerticalFrontPorch - 1;
return HAL_OK;
}
/**
* @brief Retrieve common parameters from DSI Adapted command mode configuration structure
* @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @note The implementation of this function is taking into account the LTDC
* polarities inversion as described in the current LTDC specification
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg)
{
/* Retrieve signal polarities from DSI */
/* The following polarities are inverted:
LTDC_DEPOLARITY_AL <-> LTDC_DEPOLARITY_AH
LTDC_VSPOLARITY_AL <-> LTDC_VSPOLARITY_AH
LTDC_HSPOLARITY_AL <-> LTDC_HSPOLARITY_AH)*/
/* Note 1 : Code in line w/ Current LTDC specification */
hltdc->Init.DEPolarity = (CmdCfg->DEPolarity == DSI_DATA_ENABLE_ACTIVE_HIGH) ? LTDC_DEPOLARITY_AL : LTDC_DEPOLARITY_AH;
hltdc->Init.VSPolarity = (CmdCfg->VSPolarity == DSI_VSYNC_ACTIVE_HIGH) ? LTDC_VSPOLARITY_AL : LTDC_VSPOLARITY_AH;
hltdc->Init.HSPolarity = (CmdCfg->HSPolarity == DSI_HSYNC_ACTIVE_HIGH) ? LTDC_HSPOLARITY_AL : LTDC_HSPOLARITY_AH;
/* Note 2: Code to be used in case LTDC polarities inversion updated in the specification */
/* hltdc->Init.DEPolarity = CmdCfg->DEPolarity << 29;
hltdc->Init.VSPolarity = CmdCfg->VSPolarity << 29;
hltdc->Init.HSPolarity = CmdCfg->HSPolarity << 29; */
return HAL_OK;
}
#endif /*STM32F769xx | STM32F779xx */
/**
* @}
*/
/**
* @}
*/
#endif /* HAL_LTCD_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

151
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_ltdc_ex.h Normal file
View File

@ -0,0 +1,151 @@
/**
******************************************************************************
* @file stm32f7xx_hal_ltdc_ex.h
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of LTDC HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_LTDC_EX_H
#define __STM32F7xx_HAL_LTDC_EX_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (STM32F769xx) || defined (STM32F779xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
#include "stm32f7xx_hal_dsi.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup LTDCEx
* @{
*/
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Constants LTDCEx Exported Constants
* @{
*/
/**
* @}
*/
/* Exported macro ------------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Macros LTDC Exported Macros
* @{
*/
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup LTDCEx_Exported_Functions LTDC Extended Exported Functions
* @{
*/
HAL_StatusTypeDef HAL_LTDC_StructInitFromVideoConfig(LTDC_HandleTypeDef* hltdc, DSI_VidCfgTypeDef *VidCfg);
HAL_StatusTypeDef HAL_LTDC_StructInitFromAdaptedCommandConfig(LTDC_HandleTypeDef* hltdc, DSI_CmdCfgTypeDef *CmdCfg);
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup LTDCEx_Private_Types LTDCEx Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup LTDCEx_Private_Variables LTDCEx Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup LTDCEx_Private_Constants LTDCEx Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup LTDCEx_Private_Macros LTDCEx Private Macros
* @{
*/
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup LTDCEx_Private_Functions LTDCEx Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /*STM32F769xx | STM32F779xx */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_LTDC_EX_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

629
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.c Normal file
View File

@ -0,0 +1,629 @@
/**
******************************************************************************
* @file stm32f7xx_hal_mdios.c
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief MDIOS HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities of the MDIOS Peripheral.
* + Initialization and de-initialization functions
* + IO operation functions
* + Peripheral Control functions
*
*
@verbatim
===============================================================================
##### How to use this driver #####
===============================================================================
[..]
The MDIOS HAL driver can be used as follow:
(#) Declare a MDIOS_HandleTypeDef handle structure.
(#) Initialize the MDIOS low level resources by implementing the HAL_MDIOS_MspInit() API:
(##) Enable the MDIOS interface clock.
(##) MDIOS pins configuration:
(+++) Enable clocks for the MDIOS GPIOs.
(+++) Configure the MDIOS pins as alternate function.
(##) NVIC configuration if you need to use interrupt process:
(+++) Configure the MDIOS interrupt priority.
(+++) Enable the NVIC MDIOS IRQ handle.
(#) Program the Port Address and the Preamble Check in the Init structure.
(#) Initialize the MDIOS registers by calling the HAL_MDIOS_Init() API.
(#) Perform direct slave read/write operations using the following APIs:
(##) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(##) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
(#) Get the Master read/write operations flags using the following APIs:
(##) Bit map of DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(##) Bit map of DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
(#) Clear the read/write flags using the following APIs:
(##) Clear read flags of a set of registers: HAL_MDIOS_ClearReadRegAddress()
(##) Clear write flags of a set of registers: HAL_MDIOS_ClearWriteRegAddress()
(#) Enable interrupts on events using HAL_MDIOS_EnableEvents(), when called
the MDIOS will generate an interrupt in the following cases:
(##) a DINn register written by the Master
(##) a DOUTn register read by the Master
(##) an error occur
(@) A callback is executed for each genereted interrupt, so the driver provide the following
HAL_MDIOS_WriteCpltCallback(), HAL_MDIOS_ReadCpltCallback() and HAL_MDIOS_ErrorCallback()
(@) HAL_MDIOS_IRQHandler() must be called from the MDIOS IRQ Handler, to handle the interrupt
and execute the previous callbacks
(#) Reset the MDIOS peripheral and all related ressources by calling the HAL_MDIOS_DeInit() API.
(##) HAL_MDIOS_MspDeInit() must be implemented to reset low level ressources
(GPIO, Clocks, NVIC configuration ...)
@endverbatim
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @defgroup MDIOS MDIOS
* @brief HAL MDIOS module driver
* @{
*/
#ifdef HAL_MDIOS_MODULE_ENABLED
#if defined (MDIOS)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
#define MDIOS_PORT_ADDRESS_SHIFT ((uint32_t)8)
#define MDIOS_ALL_REG_FLAG ((uint32_t)0xFFFFFFFFU)
#define MDIOS_ALL_ERRORS_FLAG ((uint32_t)(MDIOS_SR_PERF | MDIOS_SR_SERF | MDIOS_SR_TERF))
#define MDIOS_DIN_BASE_ADDR (MDIOS_BASE + 0x100)
#define MDIOS_DOUT_BASE_ADDR (MDIOS_BASE + 0x180)
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
* @{
*/
/** @defgroup MDIOS_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
##### Initialization and Configuration functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to initialize the MDIOS
(+) The following parameters can be configured:
(++) Port Address
(++) Preamble Check
@endverbatim
* @{
*/
/**
* @brief Initializes the MDIOS according to the specified parameters in
* the MDIOS_InitTypeDef and creates the associated handle .
* @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
* the configuration information for MDIOS module
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios)
{
uint32_t tmpcr = 0;
/* Check the MDIOS handle allocation */
if(hmdios == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
assert_param(IS_MDIOS_PORTADDRESS(hmdios->Init.PortAddress));
assert_param(IS_MDIOS_PREAMBLECHECK(hmdios->Init.PreambleCheck));
/* Process Locked */
__HAL_LOCK(hmdios);
if(hmdios->State == HAL_MDIOS_STATE_RESET)
{
/* Init the low level hardware */
HAL_MDIOS_MspInit(hmdios);
}
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
/* Get the MDIOS CR value */
tmpcr = hmdios->Instance->CR;
/* Clear PORT_ADDRESS, DPC and EN bits */
tmpcr &= ((uint32_t)~(MDIOS_CR_EN | MDIOS_CR_DPC | MDIOS_CR_PORT_ADDRESS));
/* Set MDIOS control parametrs and enable the peripheral */
tmpcr |= (uint32_t)(((hmdios->Init.PortAddress) << MDIOS_PORT_ADDRESS_SHIFT) |\
(hmdios->Init.PreambleCheck) | \
(MDIOS_CR_EN));
/* Write the MDIOS CR */
hmdios->Instance->CR = tmpcr;
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_READY;
/* Release Lock */
__HAL_UNLOCK(hmdios);
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the MDIOS peripheral.
* @param hmdios: MDIOS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
{
/* Check the MDIOS handle allocation */
if(hmdios == NULL)
{
return HAL_ERROR;
}
/* Check the parameters */
assert_param(IS_MDIOS_ALL_INSTANCE(hmdios->Instance));
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_BUSY;
/* Disable the Peripheral */
__HAL_MDIOS_DISABLE(hmdios);
/* DeInit the low level hardware */
HAL_MDIOS_MspDeInit(hmdios);
/* Change the MDIOS state */
hmdios->State = HAL_MDIOS_STATE_RESET;
/* Release Lock */
__HAL_UNLOCK(hmdios);
/* Return function status */
return HAL_OK;
}
/**
* @brief MDIOS MSP Init
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspInit can be implemented in the user file
*/
}
/**
* @brief MDIOS MSP DeInit
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_MspDeInit can be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup MDIOS_Exported_Functions_Group2 IO operation functions
* @brief MDIOS Read/Write functions
*
@verbatim
===============================================================================
##### IO operation functions #####
===============================================================================
This subsection provides a set of functions allowing to manage the MDIOS
read and write operations.
(#) APIs that allow to the MDIOS to read/write from/to the
values of one of the DINn/DOUTn registers:
(+) Read the value of a DINn register: HAL_MDIOS_ReadReg()
(+) Write a value to a DOUTn register: HAL_MDIOS_WriteReg()
(#) APIs that provide if there are some Slave registres have been
read or written by the Master:
(+) DOUTn registers read by Master: HAL_MDIOS_GetReadRegAddress()
(+) DINn registers written by Master : HAL_MDIOS_GetWrittenRegAddress()
(#) APIs that Clear the read/write flags:
(+) Clear read registers flags: HAL_MDIOS_ClearReadRegAddress()
(+) Clear write registers flags: HAL_MDIOS_ClearWriteRegAddress()
(#) A set of Callbacks are provided:
(+) HAL_MDIOS_WriteCpltCallback()
(+) HAL_MDIOS_ReadCpltCallback()
(+) HAL_MDIOS_ErrorCallback()
@endverbatim
* @{
*/
/**
* @brief Writes to an MDIOS output register
* @param hmdios: mdios handle
* @param RegNum: MDIOS input register number
* @param Data: Data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Get the addr of output register to be written by the MDIOS */
tmpreg = MDIOS_DOUT_BASE_ADDR + (4 * RegNum);
/* Write to DOUTn register */
*((uint32_t *)tmpreg) = Data;
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Reads an MDIOS input register
* @param hmdios: mdios handle
* @param RegNum: MDIOS input register number
* @param pData: pointer to Data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
{
uint32_t tmpreg;
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Get the addr of input register to be read by the MDIOS */
tmpreg = MDIOS_DIN_BASE_ADDR + (4 * RegNum);
/* Read DINn register */
*pData = (uint16_t)(*((uint32_t *)tmpreg));
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Gets Written registers by MDIO master
* @param hmdios: mdios handle
* @retval bit map of written registers addresses
*/
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
{
return hmdios->Instance->WRFR;
}
/**
* @brief Gets Read registers by MDIO master
* @param hmdios: mdios handle
* @retval bit map of read registers addresses
*/
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
{
return hmdios->Instance->RDFR;
}
/**
* @brief Clears Write registers flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Clear write registers flags */
hmdios->Instance->CWRFR |= (RegNum);
/* Release Lock */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Clears Read register flag
* @param hmdios: mdios handle
* @param RegNum: registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
{
/* Check the parameters */
assert_param(IS_MDIOS_REGISTER(RegNum));
/* Process Locked */
__HAL_LOCK(hmdios);
/* Clear read registers flags */
hmdios->Instance->CRDFR |= (RegNum);
/* Release Lock */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief Enables Events for MDIOS peripheral
* @param hmdios: mdios handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
{
/* Process Locked */
__HAL_LOCK(hmdios);
/* Enable MDIOS interrupts: Register Write, Register Read and Error ITs */
__HAL_MDIOS_ENABLE_IT(hmdios, (MDIOS_IT_WRITE | MDIOS_IT_READ | MDIOS_IT_ERROR));
/* Process Unlocked */
__HAL_UNLOCK(hmdios);
return HAL_OK;
}
/**
* @brief This function handles MDIOS interrupt request.
* @param hmdios: MDIOS handle
* @retval None
*/
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
{
/* Write Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_WRITE) != RESET)
{
/* Write register flag */
if(HAL_MDIOS_GetWrittenRegAddress(hmdios) != RESET)
{
/* Write callback function */
HAL_MDIOS_WriteCpltCallback(hmdios);
/* Clear write register flag */
HAL_MDIOS_ClearWriteRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
}
}
/* Read Register Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_READ) != RESET)
{
/* Read register flag */
if(HAL_MDIOS_GetReadRegAddress(hmdios) != RESET)
{
/* Read callback function */
HAL_MDIOS_ReadCpltCallback(hmdios);
/* Clear read register flag */
HAL_MDIOS_ClearReadRegAddress(hmdios, MDIOS_ALL_REG_FLAG);
}
}
/* Error Interrupt enabled ? */
if(__HAL_MDIOS_GET_IT_SOURCE(hmdios, MDIOS_IT_ERROR) != RESET)
{
/* All Errors Flag */
if(__HAL_MDIOS_GET_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG) !=RESET)
{
/* Error Callback */
HAL_MDIOS_ErrorCallback(hmdios);
/* Clear errors flag */
__HAL_MDIOS_CLEAR_ERROR_FLAG(hmdios, MDIOS_ALL_ERRORS_FLAG);
}
}
/* check MDIOS WAKEUP exti flag */
if(__HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() != RESET)
{
/* MDIOS WAKEUP interrupt user callback */
HAL_MDIOS_WakeUpCallback(hmdios);
/* Clear MDIOS WAKEUP Exti pending bit */
__HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG();
}
}
/**
* @brief Write Complete Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_WriteCpltCallback can be implemented in the user file
*/
}
/**
* @brief Read Complete Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ReadCpltCallback can be implemented in the user file
*/
}
/**
* @brief Error Callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function should not be modified, when the callback is needed,
the HAL_MDIOS_ErrorCallback can be implemented in the user file
*/
}
/**
* @brief MDIOS WAKEUP interrupt callback
* @param hmdios: mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hmdios);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_MDIOS_WakeUpCallback could be implemented in the user file
*/
}
/**
* @}
*/
/** @defgroup MDIOS_Exported_Functions_Group3 Peripheral Control functions
* @brief MDIOS control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
[..]
This subsection provides a set of functions allowing to control the MDIOS.
(+) HAL_MDIOS_GetState() API, helpful to check in run-time the state.
(+) HAL_MDIOS_GetError() API, returns the errors occured during data transfer.
@endverbatim
* @{
*/
/**
* @brief Gets MDIOS error flags
* @param hmdios: mdios handle
* @retval bit map of occured errors
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
{
/* return errors flags on status register */
return hmdios->Instance->SR;
}
/**
* @brief Return the MDIOS HAL state
* @param hmdios: mdios handle
* @retval MDIOS state
*/
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
{
/* Return MDIOS state */
return hmdios->State;
}
/**
* @}
*/
/**
* @}
*/
#endif /* MDIOS */
#endif /* HAL_MDIOS_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

537
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_mdios.h Normal file
View File

@ -0,0 +1,537 @@
/**
******************************************************************************
* @file stm32f7xx_hal_mdios.h
* @author MCD Application Team
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of MDIOS HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_MDIOS_H
#define __STM32F7xx_HAL_MDIOS_H
#ifdef __cplusplus
extern "C" {
#endif
#if defined (MDIOS)
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
/** @addtogroup MDIOS
* @{
*/
/* Exported types ------------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Types MDIOS Exported Types
* @{
*/
/** @defgroup MDIOS_Exported_Types_Group1 MDIOS State structures definition
* @{
*/
typedef enum
{
HAL_MDIOS_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */
HAL_MDIOS_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
HAL_MDIOS_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */
HAL_MDIOS_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
}HAL_MDIOS_StateTypeDef;
/**
* @}
*/
/** @defgroup MDIOS_Exported_Types_Group2 MDIOS Init Structure definition
* @{
*/
typedef struct
{
uint32_t PortAddress; /*!< Specifies the MDIOS port address.
This parameter can be a value from 0 to 31 */
uint32_t PreambleCheck; /*!< Specifies whether the preamble check is enabled or disabled.
This parameter can be a value of @ref MDIOS_Preamble_Check */
}MDIOS_InitTypeDef;
/**
* @}
*/
/** @defgroup MDIOS_Exported_Types_Group4 MDIOS handle Structure definition
* @{
*/
typedef struct
{
MDIOS_TypeDef *Instance; /*!< Register base address */
MDIOS_InitTypeDef Init; /*!< MDIOS Init Structure */
__IO HAL_MDIOS_StateTypeDef State; /*!< MDIOS communication state */
HAL_LockTypeDef Lock; /*!< MDIOS Lock */
}MDIOS_HandleTypeDef;
/**
* @}
*/
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Constants MDIOS Exported Constants
* @{
*/
/** @defgroup MDIOS_Preamble_Check MDIOS Preamble Check
* @{
*/
#define MDIOS_PREAMBLE_CHECK_ENABLE ((uint32_t)0x00000000U)
#define MDIOS_PREAMBLE_CHECK_DISABLE MDIOS_CR_DPC
/**
* @}
*/
/** @defgroup MDIOS_Input_Output_Registers_Definitions MDIOS Input Output Registers Definitions
* @{
*/
#define MDIOS_REG0 ((uint32_t)0x00000000U)
#define MDIOS_REG1 ((uint32_t)0x00000001U)
#define MDIOS_REG2 ((uint32_t)0x00000002U)
#define MDIOS_REG3 ((uint32_t)0x00000003U)
#define MDIOS_REG4 ((uint32_t)0x00000004U)
#define MDIOS_REG5 ((uint32_t)0x00000005U)
#define MDIOS_REG6 ((uint32_t)0x00000006U)
#define MDIOS_REG7 ((uint32_t)0x00000007U)
#define MDIOS_REG8 ((uint32_t)0x00000008U)
#define MDIOS_REG9 ((uint32_t)0x00000009U)
#define MDIOS_REG10 ((uint32_t)0x0000000AU)
#define MDIOS_REG11 ((uint32_t)0x0000000BU)
#define MDIOS_REG12 ((uint32_t)0x0000000CU)
#define MDIOS_REG13 ((uint32_t)0x0000000DU)
#define MDIOS_REG14 ((uint32_t)0x0000000EU)
#define MDIOS_REG15 ((uint32_t)0x0000000FU)
#define MDIOS_REG16 ((uint32_t)0x00000010U)
#define MDIOS_REG17 ((uint32_t)0x00000011U)
#define MDIOS_REG18 ((uint32_t)0x00000012U)
#define MDIOS_REG19 ((uint32_t)0x00000013U)
#define MDIOS_REG20 ((uint32_t)0x00000014U)
#define MDIOS_REG21 ((uint32_t)0x00000015U)
#define MDIOS_REG22 ((uint32_t)0x00000016U)
#define MDIOS_REG23 ((uint32_t)0x00000017U)
#define MDIOS_REG24 ((uint32_t)0x00000018U)
#define MDIOS_REG25 ((uint32_t)0x00000019U)
#define MDIOS_REG26 ((uint32_t)0x0000001AU)
#define MDIOS_REG27 ((uint32_t)0x0000001BU)
#define MDIOS_REG28 ((uint32_t)0x0000001CU)
#define MDIOS_REG29 ((uint32_t)0x0000001DU)
#define MDIOS_REG30 ((uint32_t)0x0000001EU)
#define MDIOS_REG31 ((uint32_t)0x0000001FU)
/**
* @}
*/
/** @defgroup MDIOS_Registers_Flags MDIOS Registers Flags
* @{
*/
#define MDIOS_REG0_FLAG ((uint32_t)0x00000001U)
#define MDIOS_REG1_FLAG ((uint32_t)0x00000002U)
#define MDIOS_REG2_FLAG ((uint32_t)0x00000004U)
#define MDIOS_REG3_FLAG ((uint32_t)0x00000008U)
#define MDIOS_REG4_FLAG ((uint32_t)0x00000010U)
#define MDIOS_REG5_FLAG ((uint32_t)0x00000020U)
#define MDIOS_REG6_FLAG ((uint32_t)0x00000040U)
#define MDIOS_REG7_FLAG ((uint32_t)0x00000080U)
#define MDIOS_REG8_FLAG ((uint32_t)0x00000100U)
#define MDIOS_REG9_FLAG ((uint32_t)0x00000200U)
#define MDIOS_REG10_FLAG ((uint32_t)0x00000400U)
#define MDIOS_REG11_FLAG ((uint32_t)0x00000800U)
#define MDIOS_REG12_FLAG ((uint32_t)0x00001000U)
#define MDIOS_REG13_FLAG ((uint32_t)0x00002000U)
#define MDIOS_REG14_FLAG ((uint32_t)0x00004000U)
#define MDIOS_REG15_FLAG ((uint32_t)0x00008000U)
#define MDIOS_REG16_FLAG ((uint32_t)0x00010000U)
#define MDIOS_REG17_FLAG ((uint32_t)0x00020000U)
#define MDIOS_REG18_FLAG ((uint32_t)0x00040000U)
#define MDIOS_REG19_FLAG ((uint32_t)0x00080000U)
#define MDIOS_REG20_FLAG ((uint32_t)0x00100000U)
#define MDIOS_REG21_FLAG ((uint32_t)0x00200000U)
#define MDIOS_REG22_FLAG ((uint32_t)0x00400000U)
#define MDIOS_REG23_FLAG ((uint32_t)0x00800000U)
#define MDIOS_REG24_FLAG ((uint32_t)0x01000000U)
#define MDIOS_REG25_FLAG ((uint32_t)0x02000000U)
#define MDIOS_REG26_FLAG ((uint32_t)0x04000000U)
#define MDIOS_REG27_FLAG ((uint32_t)0x08000000U)
#define MDIOS_REG28_FLAG ((uint32_t)0x10000000U)
#define MDIOS_REG29_FLAG ((uint32_t)0x20000000U)
#define MDIOS_REG30_FLAG ((uint32_t)0x40000000U)
#define MDIOS_REG31_FLAG ((uint32_t)0x80000000U)
#define MDIOS_ALLREG_FLAG ((uint32_t)0xFFFFFFFFU)
/**
* @}
*/
/** @defgroup MDIOS_Interrupt_sources Interrupt Sources
* @{
*/
#define MDIOS_IT_WRITE MDIOS_CR_WRIE
#define MDIOS_IT_READ MDIOS_CR_RDIE
#define MDIOS_IT_ERROR MDIOS_CR_EIE
/**
* @}
*/
/** @defgroup MDIOS_Interrupt_Flags MDIOS Interrupt Flags
* @{
*/
#define MDIOS_TURNAROUND_ERROR_FLAG MDIOS_SR_TERF
#define MDIOS_START_ERROR_FLAG MDIOS_SR_SERF
#define MDIOS_PREAMBLE_ERROR_FLAG MDIOS_SR_PERF
/**
* @}
*/
/** @defgroup MDIOS_Wakeup_Line MDIOS Wakeup Line
* @{
*/
#define MDIOS_WAKEUP_EXTI_LINE ((uint32_t)0x01000000) /* !< EXTI Line 24 */
/**
* @}
*/
/**
* @}
*/
/* Exported macros -----------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Macros MDIOS Exported Macros
* @{
*/
/** @brief Reset MDIOS handle state
* @param __HANDLE__: MDIOS handle.
* @retval None
*/
#define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET)
/**
* @brief Enable/Disable the MDIOS peripheral.
* @param __HANDLE__: specifies the MDIOS handle.
* @retval None
*/
#define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN)
#define __HAL_MDIOS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~MDIOS_CR_EN)
/**
* @brief Enable the MDIOS device interrupt.
* @param __HANDLE__: specifies the MDIOS handle.
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
* @arg MDIOS_IT_ERROR: Error interrupt
* @retval None
*/
#define __HAL_MDIOS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
/**
* @brief Disable the MDIOS device interrupt.
* @param __HANDLE__: specifies the MDIOS handle.
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
* @arg MDIOS_IT_ERROR: Error interrupt
* @retval None
*/
#define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
/** @brief Set MDIOS slave get write register flag
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__: specifies the write register flag
* @retval The state of write flag
*/
#define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__))
/** @brief MDIOS slave get read register flag
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__: specifies the read register flag
* @retval The state of read flag
*/
#define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__))
/** @brief MDIOS slave get interrupt
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__ : specifies the Error flag.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
* @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
* @retval The state of the error flag
*/
#define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__))
/** @brief MDIOS slave clear interrupt
* @param __HANDLE__: specifies the MDIOS handle.
* @param __FLAG__ : specifies the Error flag.
* This parameter can be one or a combination of the following values:
* @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt
* @arg MDIOS_START_ERROR_FLAG: Register read interrupt
* @arg MDIOS_PREAMBLE_ERROR_FLAG: Error interrupt
* @retval none
*/
#define __HAL_MDIOS_CLEAR_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR) |= (__FLAG__)
/**
* @brief Checks whether the specified MDIOS interrupt is set or not.
* @param __HANDLE__: specifies the MDIOS handle.
* @param __INTERRUPT__ : specifies the MDIOS interrupt sources
* This parameter can be one or a combination of the following values:
* @arg MDIOS_IT_WRITE: Register write interrupt
* @arg MDIOS_IT_READ: Register read interrupt
* @arg MDIOS_IT_ERROR: Error interrupt
* @retval The state of the interrupt source
*/
#define __HAL_MDIOS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
/**
* @brief Enable the MDIOS WAKEUP Exti Line.
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_IT() (EXTI->IMR |= (MDIOS_WAKEUP_EXTI_LINE))
/**
* @brief Disable the MDIOS WAKEUP Exti Line.
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_IT() (EXTI->IMR &= ~(MDIOS_WAKEUP_EXTI_LINE))
/**
* @brief Enable event on MDIOS WAKEUP Exti Line.
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_EVENT() (EXTI->EMR |= (MDIOS_WAKEUP_EXTI_LINE))
/**
* @brief Disable event on MDIOS WAKEUP Exti Line.
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(MDIOS_WAKEUP_EXTI_LINE))
/**
* @brief checks whether the specified MDIOS WAKEUP Exti interrupt flag is set or not.
* @retval EXTI MDIOS WAKEUP Line Status.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_GET_FLAG() (EXTI->PR & (MDIOS_WAKEUP_EXTI_LINE))
/**
* @brief Clear the MDIOS WAKEUP Exti flag.
* @retval None.
*/
#define __HAL_MDIOS_WAKEUP_EXTI_CLEAR_FLAG() (EXTI->PR = (MDIOS_WAKEUP_EXTI_LINE))
/**
* @brief Enables rising edge trigger to the MDIOS External interrupt line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE
/**
* @brief Disables the rising edge trigger to the MDIOS External interrupt line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
/**
* @brief Enables falling edge trigger to the MDIOS External interrupt line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (MDIOS_WAKEUP_EXTI_LINE)
/**
* @brief Disables falling edge trigger to the MDIOS External interrupt line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
/**
* @brief Enables rising/falling edge trigger to the MDIOS External interrupt line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= MDIOS_WAKEUP_EXTI_LINE;\
EXTI->FTSR |= MDIOS_WAKEUP_EXTI_LINE
/**
* @brief Disables rising/falling edge trigger to the MDIOS External interrupt line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(MDIOS_WAKEUP_EXTI_LINE);\
EXTI->FTSR &= ~(MDIOS_WAKEUP_EXTI_LINE)
/**
* @brief Generates a Software interrupt on selected EXTI line.
* @retval None
*/
#define __HAL_MDIOS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (MDIOS_WAKEUP_EXTI_LINE))
/**
* @}
*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup MDIOS_Exported_Functions MDIOS Exported Functions
* @{
*/
/** @addtogroup MDIOS_Exported_Functions_Group1
* @{
*/
HAL_StatusTypeDef HAL_MDIOS_Init(MDIOS_HandleTypeDef *hmdios);
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios);
/**
* @}
*/
/** @addtogroup MDIOS_Exported_Functions_Group2
* @{
*/
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data);
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData);
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios);
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios);
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum);
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios);
void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios);
/**
* @}
*/
/** @addtogroup MDIOS_Exported_Functions_Group3
* @{
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios);
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/** @defgroup MDIOS_Private_Types MDIOS Private Types
* @{
*/
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Variables MDIOS Private Variables
* @{
*/
/**
* @}
*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Constants MDIOS Private Constants
* @{
*/
/**
* @}
*/
/* Private macros ------------------------------------------------------------*/
/** @defgroup MDIOS_Private_Macros MDIOS Private Macros
* @{
*/
#define IS_MDIOS_PORTADDRESS(__ADDR__) ((__ADDR__) < 32)
#define IS_MDIOS_REGISTER(__REGISTER__) ((__REGISTER__) < 32)
#define IS_MDIOS_PREAMBLECHECK(__PREAMBLECHECK__) (((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_ENABLE) || \
((__PREAMBLECHECK__) == MDIOS_PREAMBLE_CHECK_DISABLE))
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup MDIOS_Private_Functions MDIOS Private Functions
* @{
*/
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
#endif /* MDIOS */
#ifdef __cplusplus
}
#endif
#endif /* __STM32F7xx_HAL_MDIOS_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

537
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nand.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -316,6 +316,7 @@ __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand)
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
{
__IO uint32_t data = 0;
__IO uint32_t data1 = 0;
uint32_t deviceAddress = 0;
/* Process Locked */
@ -324,7 +325,7 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
return HAL_BUSY;
}
/* Identify the device address */
@ -335,16 +336,33 @@ HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pN
/* Send Read ID command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_READID;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
/* Read the electronic signature from NAND flash */
if (hnand->Init.MemoryDataWidth == FMC_NAND_PCC_MEM_BUS_WIDTH_8)
{
data = *(__IO uint32_t *)deviceAddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
}
else
{
data = *(__IO uint32_t *)deviceAddress;
data1 = *((__IO uint32_t *)deviceAddress + 4);
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Third_Id = ADDR_1ST_CYCLE(data1);
pNAND_ID->Fourth_Id = ADDR_3RD_CYCLE(data1);
}
/* Read the electronic signature from NAND flash */
data = *(__IO uint32_t *)deviceAddress;
/* Return the data read */
pNAND_ID->Maker_Id = ADDR_1ST_CYCLE(data);
pNAND_ID->Device_Id = ADDR_2ND_CYCLE(data);
pNAND_ID->Third_Id = ADDR_3RD_CYCLE(data);
pNAND_ID->Fourth_Id = ADDR_4TH_CYCLE(data);
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
@ -395,7 +413,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
}
/**
* @brief Read Page(s) from NAND memory block
* @brief Read Page(s) from NAND memory block (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@ -403,7 +421,104 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand)
* @param NumPageToRead : number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0;
uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
deviceAddress = NAND_DEVICE;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* NAND raw address calculation */
nandAddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) read loop */
while((NumPageToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
{
/* update the buffer size */
size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesRead);
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
/* Get Data into Buffer */
for(; index < size; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
}
}
else
{
/* Get Data into Buffer */
for(; index < size; index++)
{
*(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
}
}
/* Increment read pages number */
numPagesRead++;
/* Decrement pages to read */
NumPageToRead--;
/* Increment the NAND address */
nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Read Page(s) from NAND memory block (16-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to destination read buffer
* @param NumPageToRead : number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
{
__IO uint32_t index = 0;
uint32_t deviceAddress = 0, size = 0, numPagesRead = 0, nandAddress = 0;
@ -434,24 +549,30 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
/* Send read page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
/* Get Data into Buffer */
for(index = 0; index < size; index++)
for(; index < size; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
*(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
}
/* Increment read pages number */
@ -462,7 +583,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
/* Increment the NAND address */
nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
}
/* Update the NAND controller state */
@ -472,11 +592,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Write Page(s) to NAND memory block
* @brief Write Page(s) to NAND memory block (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@ -484,7 +603,7 @@ HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressType
* @param NumPageToWrite : number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
@ -516,11 +635,16 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
@ -530,15 +654,28 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
/* Write data to memory */
for(index = 0; index < size; index++)
if (hnand->Init.MemoryDataWidth == FMC_NAND_MEM_BUS_WIDTH_8)
{
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
__DSB();
/* Write data to memory */
for(; index < size; index++)
{
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
__DSB();
}
}
else
{
/* Write data to memory */
for(; index < size; index++)
{
*(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
__DSB();
}
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
@ -572,7 +709,109 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
}
/**
* @brief Read Spare area(s) from NAND memory
* @brief Write Page(s) to NAND memory block (16-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumPageToWrite : number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
uint32_t deviceAddress = 0, size = 0, numPagesWritten = 0, nandAddress = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
deviceAddress = NAND_DEVICE;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* NAND raw address calculation */
nandAddress = ARRAY_ADDRESS(pAddress, hnand);
/* Page(s) write loop */
while((NumPageToWrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.PageSize) * (hnand->Info.ZoneSize))))
{
/* update the buffer size */
size = (hnand->Info.PageSize) + ((hnand->Info.PageSize) * numPagesWritten);
/* Send write page command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_A;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
/* Write data to memory */
for(; index < size; index++)
{
*(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
/* Get tick */
tickstart = HAL_GetTick();
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Increment written pages number */
numPagesWritten++;
/* Decrement pages to write */
NumPageToWrite--;
/* Increment the NAND address */
nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize * 8));
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Read Spare area(s) from NAND memory (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@ -580,7 +819,7 @@ HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTyp
* @param NumSpareAreaToRead: Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0;
uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
@ -605,29 +844,34 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
/* Spare area(s) read loop */
while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
{
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
/* Get Data into Buffer */
for(index = 0; index < size; index++)
for(; index < size; index++)
{
*(uint8_t *)pBuffer++ = *(uint8_t *)deviceAddress;
}
@ -652,7 +896,92 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
}
/**
* @brief Write Spare area(s) to NAND memory
* @brief Read Spare area(s) from NAND memory (16-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer: pointer to source buffer to write
* @param NumSpareAreaToRead: Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
{
__IO uint32_t index = 0;
uint32_t deviceAddress = 0, size = 0, numSpareAreaRead = 0, nandAddress = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
deviceAddress = NAND_DEVICE;
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* NAND raw address calculation */
nandAddress = ARRAY_ADDRESS(pAddress, hnand);
/* Spare area(s) read loop */
while((NumSpareAreaToRead != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaRead);
/* Send read spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_TRUE1;
__DSB();
/* Get Data into Buffer */
for(; index < size; index++)
{
*(uint16_t *)pBuffer++ = *(uint16_t *)deviceAddress;
}
/* Increment read spare areas number */
numSpareAreaRead++;
/* Decrement spare areas to read */
NumSpareAreaToRead--;
/* Increment the NAND address */
nandAddress = (uint32_t)(nandAddress + (hnand->Info.SpareAreaSize));
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory (8-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
@ -660,7 +989,7 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addres
* @param NumSpareAreaTowrite : number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
@ -686,17 +1015,21 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Spare area(s) write loop */
while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
{
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
@ -707,7 +1040,7 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
}
/* Write data to memory */
for(index = 0; index < size; index++)
for(; index < size; index++)
{
*(__IO uint8_t *)deviceAddress = *(uint8_t *)pBuffer++;
__DSB();
@ -743,7 +1076,107 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_Addre
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
/**
* @brief Write Spare area(s) to NAND memory (16-bits addressing)
* @param hnand: pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @param pAddress : pointer to NAND address structure
* @param pBuffer : pointer to source buffer to write
* @param NumSpareAreaTowrite : number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
{
__IO uint32_t index = 0;
uint32_t tickstart = 0;
uint32_t deviceAddress = 0, size = 0, numSpareAreaWritten = 0, nandAddress = 0;
/* Process Locked */
__HAL_LOCK(hnand);
/* Check the NAND controller state */
if(hnand->State == HAL_NAND_STATE_BUSY)
{
return HAL_BUSY;
}
/* Identify the device address */
deviceAddress = NAND_DEVICE;
/* Update the FMC_NAND controller state */
hnand->State = HAL_NAND_STATE_BUSY;
/* NAND raw address calculation */
nandAddress = ARRAY_ADDRESS(pAddress, hnand);
/* Spare area(s) write loop */
while((NumSpareAreaTowrite != 0) && (nandAddress < ((hnand->Info.BlockSize) * (hnand->Info.SpareAreaSize) * (hnand->Info.ZoneSize))))
{
/* update the buffer size */
size = (hnand->Info.SpareAreaSize) + ((hnand->Info.SpareAreaSize) * numSpareAreaWritten);
/* Send write Spare area command sequence */
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_AREA_C;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE0;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = 0x00;
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(nandAddress);
__DSB();
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(nandAddress);
__DSB();
/* for 512 and 1 GB devices, 4th cycle is required */
if(hnand->Info.BlockNbr >= 1024)
{
*(__IO uint8_t *)((uint32_t)(deviceAddress | ADDR_AREA)) = ADDR_4TH_CYCLE(nandAddress);
__DSB();
}
/* Write data to memory */
for(; index < size; index++)
{
*(__IO uint16_t *)deviceAddress = *(uint16_t *)pBuffer++;
__DSB();
}
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
{
/* Get tick */
tickstart = HAL_GetTick();
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
}
}
/* Increment written spare areas number */
numSpareAreaWritten++;
/* Decrement spare areas to write */
NumSpareAreaTowrite--;
/* Increment the NAND address */
nandAddress = (uint32_t)(nandAddress + (hnand->Info.PageSize));
}
/* Update the NAND controller state */
hnand->State = HAL_NAND_STATE_READY;
/* Process unlocked */
__HAL_UNLOCK(hnand);
return HAL_OK;
}
@ -775,9 +1208,11 @@ HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTy
/* Send Erase block command sequence */
*(__IO uint8_t *)((uint32_t)(DeviceAddress | CMD_AREA)) = NAND_CMD_ERASE0;
__DSB();
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_1ST_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_2ND_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();
*(__IO uint8_t *)((uint32_t)(DeviceAddress | ADDR_AREA)) = ADDR_3RD_CYCLE(ARRAY_ADDRESS(pAddress, hnand));
__DSB();

67
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nand.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_nand.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of NAND HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -65,10 +65,10 @@
*/
typedef enum
{
HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */
HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */
HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */
HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */
}HAL_NAND_StateTypeDef;
/**
@ -179,10 +179,15 @@ void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
/* IO operation functions ****************************************************/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
@ -223,33 +228,33 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
/** @defgroup NAND_Private_Constants NAND Private Constants
* @{
*/
#define NAND_DEVICE ((uint32_t)0x80000000)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
#define NAND_DEVICE ((uint32_t)0x80000000U)
#define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U)
#define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
#define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
#define NAND_CMD_AREA_A ((uint8_t)0x00)
#define NAND_CMD_AREA_B ((uint8_t)0x01)
#define NAND_CMD_AREA_C ((uint8_t)0x50)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30)
#define NAND_CMD_AREA_A ((uint8_t)0x00U)
#define NAND_CMD_AREA_B ((uint8_t)0x01U)
#define NAND_CMD_AREA_C ((uint8_t)0x50U)
#define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U)
#define NAND_CMD_WRITE0 ((uint8_t)0x80)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10)
#define NAND_CMD_ERASE0 ((uint8_t)0x60)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0)
#define NAND_CMD_READID ((uint8_t)0x90)
#define NAND_CMD_STATUS ((uint8_t)0x70)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7A)
#define NAND_CMD_RESET ((uint8_t)0xFF)
#define NAND_CMD_WRITE0 ((uint8_t)0x80U)
#define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U)
#define NAND_CMD_ERASE0 ((uint8_t)0x60U)
#define NAND_CMD_ERASE1 ((uint8_t)0xD0U)
#define NAND_CMD_READID ((uint8_t)0x90U)
#define NAND_CMD_STATUS ((uint8_t)0x70U)
#define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU)
#define NAND_CMD_RESET ((uint8_t)0xFFU)
/* NAND memory status */
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
#define NAND_BUSY ((uint32_t)0x00000000)
#define NAND_ERROR ((uint32_t)0x00000001)
#define NAND_READY ((uint32_t)0x00000040)
#define NAND_VALID_ADDRESS ((uint32_t)0x00000100U)
#define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U)
#define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U)
#define NAND_BUSY ((uint32_t)0x00000000U)
#define NAND_ERROR ((uint32_t)0x00000001U)
#define NAND_READY ((uint32_t)0x00000040U)
/**
* @}
*/

98
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_nor.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@ -55,7 +55,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -137,6 +137,16 @@
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/** @defgroup NOR_Private_Variables NOR Private Variables
* @{
*/
static uint32_t uwNORMemoryDataWidth = NOR_MEMORY_8B;
/**
* @}
*/
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup NOR_Exported_Functions NOR Exported Functions
@ -194,6 +204,16 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
/* Enable the NORSRAM device */
__FMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);
/* Initialize NOR Memory Data Width*/
if (hnor->Init.MemoryDataWidth == FMC_NORSRAM_MEM_BUS_WIDTH_8)
{
uwNORMemoryDataWidth = NOR_MEMORY_8B;
}
else
{
uwNORMemoryDataWidth = NOR_MEMORY_16B;
}
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -333,15 +353,15 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read ID command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_AUTO_SELECT);
/* Read the NOR IDs */
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, MC_ADDRESS);
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE1_ADDR);
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE2_ADDR);
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, DEVICE_CODE3_ADDR);
pNOR_ID->Manufacturer_Code = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, MC_ADDRESS);
pNOR_ID->Device_Code1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE1_ADDR);
pNOR_ID->Device_Code2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE2_ADDR);
pNOR_ID->Device_Code3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, DEVICE_CODE3_ADDR);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -443,9 +463,9 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
/* Read the data */
*pData = *(__IO uint32_t *)(uint32_t)pAddress;
@ -502,9 +522,9 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
hnor->State = HAL_NOR_STATE_BUSY;
/* Send program data command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_PROGRAM);
/* Write the data */
NOR_WRITE(pAddress, *pData);
@ -562,9 +582,9 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read data command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_READ_RESET);
/* Read buffer */
while( uwBufferSize > 0)
@ -634,12 +654,12 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
lastloadedaddress = (uint32_t)(uwAddress);
/* Issue unlock command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
/* Write Buffer Load Command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, uwAddress), (uwBufferSize - 1));
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), NOR_CMD_DATA_BUFFER_AND_PROG);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, uwAddress), (uwBufferSize - 1));
/* Load Data into NOR Buffer */
while(p_currentaddress <= p_endaddress)
@ -707,11 +727,11 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
hnor->State = HAL_NOR_STATE_BUSY;
/* Send block erase command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE((uint32_t)(BlockAddress + Address), NOR_CMD_DATA_BLOCK_ERASE);
/* Check the NOR memory status and update the controller state */
@ -766,12 +786,12 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
hnor->State = HAL_NOR_STATE_BUSY;
/* Send NOR chip erase command sequence */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST), NOR_CMD_DATA_FIRST);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SECOND), NOR_CMD_DATA_SECOND);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_THIRD), NOR_CMD_DATA_CHIP_BLOCK_ERASE_THIRD);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FOURTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FOURTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIFTH), NOR_CMD_DATA_CHIP_BLOCK_ERASE_FIFTH);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_SIXTH), NOR_CMD_DATA_CHIP_ERASE);
/* Check the NOR memory status and update the controller state */
hnor->State = HAL_NOR_STATE_READY;
@ -824,13 +844,13 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
hnor->State = HAL_NOR_STATE_BUSY;
/* Send read CFI query command */
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
NOR_WRITE(NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, NOR_CMD_ADDRESS_FIRST_CFI), NOR_CMD_DATA_CFI);
/* read the NOR CFI information */
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI2_ADDRESS);
pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI3_ADDRESS);
pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, NOR_MEMORY_8B, CFI4_ADDRESS);
pNOR_CFI->CFI_1 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI1_ADDRESS);
pNOR_CFI->CFI_2 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI2_ADDRESS);
pNOR_CFI->CFI_3 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI3_ADDRESS);
pNOR_CFI->CFI_4 = *(__IO uint16_t *) NOR_ADDR_SHIFT(deviceaddress, uwNORMemoryDataWidth, CFI4_ADDRESS);
/* Check the NOR controller state */
hnor->State = HAL_NOR_STATE_READY;

50
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_nor.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_nor.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -65,11 +65,11 @@
*/
typedef enum
{
HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
HAL_NOR_STATE_RESET = 0x00U, /*!< NOR not yet initialized or disabled */
HAL_NOR_STATE_READY = 0x01U, /*!< NOR initialized and ready for use */
HAL_NOR_STATE_BUSY = 0x02U, /*!< NOR internal processing is ongoing */
HAL_NOR_STATE_ERROR = 0x03U, /*!< NOR error state */
HAL_NOR_STATE_PROTECTED = 0x04U /*!< NOR NORSRAM device write protected */
}HAL_NOR_StateTypeDef;
/**
@ -77,7 +77,7 @@ typedef enum
*/
typedef enum
{
HAL_NOR_STATUS_SUCCESS = 0,
HAL_NOR_STATUS_SUCCESS = 0U,
HAL_NOR_STATUS_ONGOING,
HAL_NOR_STATUS_ERROR,
HAL_NOR_STATUS_TIMEOUT
@ -224,29 +224,29 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @{
*/
/* NOR device IDs addresses */
#define MC_ADDRESS ((uint16_t)0x0000)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
#define MC_ADDRESS ((uint16_t)0x0000U)
#define DEVICE_CODE1_ADDR ((uint16_t)0x0001U)
#define DEVICE_CODE2_ADDR ((uint16_t)0x000EU)
#define DEVICE_CODE3_ADDR ((uint16_t)0x000FU)
/* NOR CFI IDs addresses */
#define CFI1_ADDRESS ((uint16_t)0x61)
#define CFI2_ADDRESS ((uint16_t)0x62)
#define CFI3_ADDRESS ((uint16_t)0x63)
#define CFI4_ADDRESS ((uint16_t)0x64)
#define CFI1_ADDRESS ((uint16_t)0x61U)
#define CFI2_ADDRESS ((uint16_t)0x62U)
#define CFI3_ADDRESS ((uint16_t)0x63U)
#define CFI4_ADDRESS ((uint16_t)0x64U)
/* NOR operation wait timeout */
#define NOR_TMEOUT ((uint16_t)0xFFFF)
#define NOR_TMEOUT ((uint16_t)0xFFFFU)
/* NOR memory data width */
#define NOR_MEMORY_8B ((uint8_t)0x0)
#define NOR_MEMORY_16B ((uint8_t)0x1)
#define NOR_MEMORY_8B ((uint8_t)0x0U)
#define NOR_MEMORY_16B ((uint8_t)0x1U)
/* NOR memory device read/write start address */
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
#define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000U)
#define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000U)
#define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000U)
#define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000U)
/**
* @}
*/
@ -263,7 +263,7 @@ HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Addres
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? \
((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)? \
((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))): \
((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))

82
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -45,7 +45,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -316,8 +316,9 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t i = 0, ep_intr = 0, epint = 0, epnum = 0;
uint32_t fifoemptymsk = 0, temp = 0;
USB_OTG_EPTypeDef *ep;
USB_OTG_EPTypeDef *ep = NULL;
uint32_t hclk = 200000000;
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
@ -527,7 +528,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* setup EP0 to receive SETUP packets */
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
@ -547,7 +548,74 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
hpcd->Instance->GUSBCFG |= (uint32_t)((USBD_FS_TRDT_VALUE << 10) & USB_OTG_GUSBCFG_TRDT);
/* The USBTRD is configured according to the tables below, depending on AHB frequency
used by application. In the low AHB frequency range it is used to stretch enough the USB response
time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
if((hclk >= 14200000)&&(hclk < 15000000))
{
/* hclk Clock Range between 14.2-15 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 15000000)&&(hclk < 16000000))
{
/* hclk Clock Range between 15-16 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 16000000)&&(hclk < 17200000))
{
/* hclk Clock Range between 16-17.2 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 17200000)&&(hclk < 18500000))
{
/* hclk Clock Range between 17.2-18.5 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 18500000)&&(hclk < 20000000))
{
/* hclk Clock Range between 18.5-20 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 20000000)&&(hclk < 21800000))
{
/* hclk Clock Range between 20-21.8 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 21800000)&&(hclk < 24000000))
{
/* hclk Clock Range between 21.8-24 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 24000000)&&(hclk < 27700000))
{
/* hclk Clock Range between 24-27.7 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
}
else if((hclk >= 27700000)&&(hclk < 32000000))
{
/* hclk Clock Range between 27.7-32 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
}
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-200 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
}
}
HAL_PCD_ResetCallback(hpcd);

54
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,20 +64,20 @@
*/
typedef enum
{
HAL_PCD_STATE_RESET = 0x00,
HAL_PCD_STATE_READY = 0x01,
HAL_PCD_STATE_ERROR = 0x02,
HAL_PCD_STATE_BUSY = 0x03,
HAL_PCD_STATE_TIMEOUT = 0x04
HAL_PCD_STATE_RESET = 0x00U,
HAL_PCD_STATE_READY = 0x01U,
HAL_PCD_STATE_ERROR = 0x02U,
HAL_PCD_STATE_BUSY = 0x03U,
HAL_PCD_STATE_TIMEOUT = 0x04U
} PCD_StateTypeDef;
/* Device LPM suspend state */
typedef enum
{
LPM_L0 = 0x00, /* on */
LPM_L1 = 0x01, /* LPM L1 sleep */
LPM_L2 = 0x02, /* suspend */
LPM_L3 = 0x03, /* off */
LPM_L0 = 0x00U, /* on */
LPM_L1 = 0x01U, /* LPM L1 sleep */
LPM_L2 = 0x02U, /* suspend */
LPM_L3 = 0x03U, /* off */
}PCD_LPM_StateTypeDef;
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
@ -118,9 +118,9 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed
* @{
*/
#define PCD_SPEED_HIGH 0
#define PCD_SPEED_HIGH_IN_FULL 1
#define PCD_SPEED_FULL 2
#define PCD_SPEED_HIGH 0U
#define PCD_SPEED_HIGH_IN_FULL 1U
#define PCD_SPEED_FULL 2U
/**
* @}
*/
@ -128,8 +128,8 @@ typedef struct
/** @defgroup PCD_PHY_Module PCD PHY Module
* @{
*/
#define PCD_PHY_ULPI 1
#define PCD_PHY_EMBEDDED 2
#define PCD_PHY_ULPI 1U
#define PCD_PHY_EMBEDDED 2U
/**
* @}
*/
@ -138,10 +138,10 @@ typedef struct
* @{
*/
#ifndef USBD_HS_TRDT_VALUE
#define USBD_HS_TRDT_VALUE 9
#define USBD_HS_TRDT_VALUE 9U
#endif /* USBD_HS_TRDT_VALUE */
#ifndef USBD_FS_TRDT_VALUE
#define USBD_FS_TRDT_VALUE 5
#define USBD_FS_TRDT_VALUE 5U
#endif /* USBD_HS_TRDT_VALUE */
/**
@ -172,16 +172,16 @@ typedef struct
#define __HAL_PCD_IS_PHY_SUSPENDED(__HANDLE__) ((*(__IO uint32_t *)((uint32_t)((__HANDLE__)->Instance) + USB_OTG_PCGCCTL_BASE))&0x10)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0C)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE ((uint32_t)0x08U)
#define USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE ((uint32_t)0x0CU)
#define USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE ((uint32_t)0x10U)
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define USB_OTG_HS_WAKEUP_EXTI_LINE ((uint32_t)0x00100000U) /*!< External interrupt line 20 Connected to the USB HS EXTI Line */
#define USB_OTG_FS_WAKEUP_EXTI_LINE ((uint32_t)0x00040000U) /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -59,7 +59,7 @@
/* Private functions ---------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @defgroup PCDEx_Exported_Functions PCD Extended Exported Functions
/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/

12
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pcd_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_pcd_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -56,14 +56,14 @@
/* Exported types ------------------------------------------------------------*/
typedef enum
{
PCD_LPM_L0_ACTIVE = 0x00, /* on */
PCD_LPM_L1_ACTIVE = 0x01, /* LPM L1 sleep */
PCD_LPM_L0_ACTIVE = 0x00U, /* on */
PCD_LPM_L1_ACTIVE = 0x01U, /* LPM L1 sleep */
}PCD_LPM_MsgTypeDef;
/* Exported constants --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
/** @addtogroup PCDEx_Exported_Functions PCD Extended Exported Functions
/** @addtogroup PCDEx_Exported_Functions PCDEx Exported Functions
* @{
*/
/** @addtogroup PCDEx_Exported_Functions_Group1 Peripheral Control functions

14
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@ -13,7 +13,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -63,10 +63,10 @@
/** @defgroup PWR_PVD_Mode_Mask PWR PVD Mode Mask
* @{
*/
#define PVD_MODE_IT ((uint32_t)0x00010000)
#define PVD_MODE_EVT ((uint32_t)0x00020000)
#define PVD_RISING_EDGE ((uint32_t)0x00000001)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002)
#define PVD_MODE_IT ((uint32_t)0x00010000U)
#define PVD_MODE_EVT ((uint32_t)0x00020000U)
#define PVD_RISING_EDGE ((uint32_t)0x00000001U)
#define PVD_FALLING_EDGE ((uint32_t)0x00000002U)
/**
* @}
*/

36
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of PWR HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -101,13 +101,13 @@ typedef struct
/** @defgroup PWR_PVD_Mode PWR PVD Mode
* @{
*/
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000U) /*!< basic mode is used */
#define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001U) /*!< External Interrupt Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002U) /*!< External Interrupt Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003U) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001U) /*!< Event Mode with Rising edge trigger detection */
#define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002U) /*!< Event Mode with Falling edge trigger detection */
#define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003U) /*!< Event Mode with Rising/Falling edge trigger detection */
/**
* @}
*/
@ -115,7 +115,7 @@ typedef struct
/** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
* @{
*/
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
#define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000U)
#define PWR_LOWPOWERREGULATOR_ON PWR_CR1_LPDS
/**
* @}
@ -124,8 +124,8 @@ typedef struct
/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
* @{
*/
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
#define PWR_SLEEPENTRY_WFI ((uint8_t)0x01U)
#define PWR_SLEEPENTRY_WFE ((uint8_t)0x02U)
/**
* @}
*/
@ -133,8 +133,8 @@ typedef struct
/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
* @{
*/
#define PWR_STOPENTRY_WFI ((uint8_t)0x01)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02)
#define PWR_STOPENTRY_WFI ((uint8_t)0x01U)
#define PWR_STOPENTRY_WFE ((uint8_t)0x02U)
/**
* @}
*/
@ -181,7 +181,7 @@ typedef struct
* @retval None
*/
#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) do { \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
MODIFY_REG(PWR->CR1, PWR_CR1_VOS, (__REGULATOR__)); \
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
@ -364,7 +364,7 @@ void HAL_PWR_DisableSEVOnPend(void);
/** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
* @{
*/
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
#define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_IM16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
/**
* @}
*/
@ -380,8 +380,6 @@ void HAL_PWR_DisableSEVOnPend(void);
/** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
* @{
*/
#define IS_PWR_WAKEUP_POLARITY(POLARITY) (((POLARITY) == PWR_POLARITY_RISINGEDGE) || \
((POLARITY) == PWR_POLARITY_FALLINGEDGE))
#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \

14
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -156,6 +156,10 @@ HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void)
/* Enable Backup regulator */
PWR->CSR1 |= PWR_CSR1_BRE;
/* Workaround for the following hardware bug: */
/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
PWR->CSR1 |= PWR_CSR1_EIWUP;
/* Get tick */
tickstart = HAL_GetTick();
@ -181,6 +185,10 @@ HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void)
/* Disable Backup regulator */
PWR->CSR1 &= (uint32_t)~((uint32_t)PWR_CSR1_BRE);
/* Workaround for the following hardware bug: */
/* Id 19: PWR : No STANDBY wake-up when Back-up RAM enabled (ref. Errata Sheet p23) */
PWR->CSR1 |= PWR_CSR1_EIWUP;
/* Get tick */
tickstart = HAL_GetTick();

8
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_pwr_ex.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_pwr_ex.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -99,7 +99,7 @@
*/
#define PWR_FLAG_ODRDY PWR_CSR1_ODRDY
#define PWR_FLAG_ODSWRDY PWR_CSR1_ODSWRDY
#define PWR_FLAG_UDRDY PWR_CSR1_UDSWRDY
#define PWR_FLAG_UDRDY PWR_CSR1_UDRDY
/**
* @}
*/

937
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.c
View File

File diff suppressed because it is too large Load Diff

101
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_qspi.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_qspi.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of QSPI HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -100,14 +100,15 @@ typedef struct
*/
typedef enum
{
HAL_QSPI_STATE_RESET = 0x00, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01, /*!< Peripheral initialized and ready for use */
HAL_QSPI_STATE_BUSY = 0x02, /*!< Peripheral in indirect mode and busy */
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82, /*!< Peripheral in memory mapped mode ongoing */
HAL_QSPI_STATE_ERROR = 0x04 /*!< Peripheral in error */
HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */
HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */
HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */
HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */
HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */
HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */
HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */
HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */
HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */
}HAL_QSPI_StateTypeDef;
/**
@ -207,10 +208,11 @@ typedef struct
/** @defgroup QSPI_ErrorCode QSPI Error Code
* @{
*/
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
#define HAL_QSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
#define HAL_QSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */
#define HAL_QSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */
#define HAL_QSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */
/**
* @}
*/
@ -218,7 +220,7 @@ typedef struct
/** @defgroup QSPI_SampleShifting QSPI Sample Shifting
* @{
*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!<No clock cycle shift to sample data*/
#define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/
/**
* @}
@ -227,7 +229,7 @@ typedef struct
/** @defgroup QSPI_ChipSelectHighTime QSPI Chip Select High Time
* @{
*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_1_CYCLE ((uint32_t)0x00000000U) /*!<nCS stay high for at least 1 clock cycle between commands*/
#define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/
#define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/
@ -242,7 +244,7 @@ typedef struct
/** @defgroup QSPI_ClockMode QSPI Clock Mode
* @{
*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!<Clk stays low while nCS is released*/
#define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/
/**
* @}
@ -251,7 +253,7 @@ typedef struct
/** @defgroup QSPI_Flash_Select QSPI Flash Select
* @{
*/
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000)
#define QSPI_FLASH_ID_1 ((uint32_t)0x00000000U)
#define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL)
/**
* @}
@ -261,7 +263,7 @@ typedef struct
* @{
*/
#define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM)
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000)
#define QSPI_DUALFLASH_DISABLE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -269,7 +271,7 @@ typedef struct
/** @defgroup QSPI_AddressSize QSPI Address Size
* @{
*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000) /*!<8-bit address*/
#define QSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!<8-bit address*/
#define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/
#define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/
#define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/
@ -280,7 +282,7 @@ typedef struct
/** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size
* @{
*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!<8-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/
#define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/
@ -291,7 +293,7 @@ typedef struct
/** @defgroup QSPI_InstructionMode QSPI Instruction Mode
* @{
*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000) /*!<No instruction*/
#define QSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!<No instruction*/
#define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/
#define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/
#define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/
@ -302,7 +304,7 @@ typedef struct
/** @defgroup QSPI_AddressMode QSPI Address Mode
* @{
*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000) /*!<No address*/
#define QSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!<No address*/
#define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/
#define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/
#define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/
@ -313,7 +315,7 @@ typedef struct
/** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode
* @{
*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!<No alternate bytes*/
#define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/
#define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/
#define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/
@ -335,7 +337,7 @@ typedef struct
/** @defgroup QSPI_DdrMode QSPI Ddr Mode
* @{
*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_DISABLE ((uint32_t)0x00000000U) /*!<Double data rate mode disabled*/
#define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/
/**
* @}
@ -344,7 +346,7 @@ typedef struct
/** @defgroup QSPI_DdrHoldHalfCycle QSPI Ddr HoldHalfCycle
* @{
*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_ANALOG_DELAY ((uint32_t)0x00000000U) /*!<Delay the data output using analog delay in DDR mode*/
#define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by 1/2 clock cycle in DDR mode*/
/**
* @}
@ -353,7 +355,7 @@ typedef struct
/** @defgroup QSPI_SIOOMode QSPI SIOO Mode
* @{
*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!<Send instruction on every transaction*/
#define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/
/**
* @}
@ -362,7 +364,7 @@ typedef struct
/** @defgroup QSPI_MatchMode QSPI Match Mode
* @{
*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!<AND match mode between unmasked bits*/
#define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/
/**
* @}
@ -371,7 +373,7 @@ typedef struct
/** @defgroup QSPI_AutomaticStop QSPI Automatic Stop
* @{
*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!<AutoPolling stops only with abort or QSPI disabling*/
#define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/
/**
* @}
@ -380,7 +382,7 @@ typedef struct
/** @defgroup QSPI_TimeOutActivation QSPI TimeOut Activation
* @{
*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!<Timeout counter disabled, nCS remains active*/
#define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/
/**
* @}
@ -389,12 +391,12 @@ typedef struct
/** @defgroup QSPI_Flags QSPI Flags
* @{
*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
#define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/
#define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/
#define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/
#define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/
#define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/
#define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/
/**
* @}
*/
@ -565,6 +567,7 @@ HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_Comm
*/
/* Callback functions in non-blocking modes ***********************************/
void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi);
/* QSPI indirect mode */
@ -587,24 +590,16 @@ void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi);
* @{
*/
/* Peripheral Control and State functions ************************************/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi);
uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi);
HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi);
void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout);
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold);
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi);
/**
* @}
*/
/**
* @}
*/
/* Private types -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private constants ---------------------------------------------------------*/
/** @defgroup QSPI_Private_Constants QSPI Private Constants
* @{
*/
/**
* @}
@ -755,7 +750,7 @@ void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Ti
((FLAG) == QSPI_FLAG_TC) || \
((FLAG) == QSPI_FLAG_TE))
#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFF) == 0x00000000) && ((IT) != 0x00000000))
#define IS_QSPI_IT(IT) ((((IT) & (uint32_t)0xFFE0FFFFU) == 0x00000000U) && ((IT) != 0x00000000U))
/**
* @}
*/

300
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
@ -56,7 +56,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -119,7 +119,6 @@
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
*/
const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
@ -227,7 +226,7 @@ void HAL_RCC_DeInit(void)
/* Reset PLLCFGR register */
CLEAR_REG(RCC->PLLCFGR);
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
/* Reset PLLI2SCFGR register */
CLEAR_REG(RCC->PLLI2SCFGR);
@ -238,6 +237,9 @@ void HAL_RCC_DeInit(void)
/* Disable all interrupts */
CLEAR_REG(RCC->CIR);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HSI_VALUE;
}
/**
@ -246,9 +248,15 @@ void HAL_RCC_DeInit(void)
* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
* supported by this function. User should request a transition to LSE Off
* first and then LSE On or LSE Bypass.
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
@ -271,21 +279,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
else
{
/* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
__HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
@ -450,21 +443,6 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
}
/* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
__HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@ -530,11 +508,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PLLM,
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ);
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
RCC_OscInitStruct->PLL.PLLM | \
(RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
(((RCC_OscInitStruct->PLL.PLLP >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
(RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
@ -605,14 +583,14 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
/* To correctly read data from FLASH memory, the number of wait states (LATENCY)
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
/* Increasing the CPU frequency */
if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
@ -626,161 +604,87 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
return HAL_ERROR;
}
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
}
/* Decreasing the CPU frequency */
else
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
/*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/*------------------------- SYSCLK Configuration -------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
{
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
/* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
return HAL_ERROR;
}
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
/* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
}
}
/* HSI is selected as System Clock Source */
else
{
/* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
return HAL_ERROR;
}
}
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
/* Get Start Tick*/
tickstart = HAL_GetTick();
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
{
if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/* Decreasing the number of wait states because of lower CPU frequency */
if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
@ -790,7 +694,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
{
return HAL_ERROR;
}
}
}
/*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
@ -806,6 +710,9 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
}
/* Update the SystemCoreClock global variable */
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
@ -1005,15 +912,12 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
/**
* @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
*
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
uint32_t HAL_RCC_GetHCLKFreq(void)
{
SystemCoreClock = HAL_RCC_GetSysClockFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
return SystemCoreClock;
}
@ -1026,7 +930,7 @@ uint32_t HAL_RCC_GetHCLKFreq(void)
uint32_t HAL_RCC_GetPCLK1Freq(void)
{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq() >> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
}
/**
@ -1038,7 +942,7 @@ uint32_t HAL_RCC_GetPCLK1Freq(void)
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
return (HAL_RCC_GetHCLKFreq()>> APBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
}
/**

325
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -45,6 +45,10 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal_def.h"
/* Include RCC HAL Extended module */
/* (include on top of file since RCC structures are defined in extended file) */
#include "stm32f7xx_hal_rcc_ex.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
@ -60,31 +64,6 @@
* @{
*/
/**
* @brief RCC PLL configuration structure definition
*/
typedef struct
{
uint32_t PLLState; /*!< The new state of the PLL.
This parameter can be a value of @ref RCC_PLL_Config */
uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
This parameter must be a value of @ref RCC_PLL_Clock_Source */
uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
This parameter must be a number between Min_Data = 100 and Max_Data = 432 */
uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDMMC and RNG clocks.
This parameter must be a number between Min_Data = 2 and Max_Data = 15 */
}RCC_PLLInitTypeDef;
/**
* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
@ -102,7 +81,7 @@ typedef struct
uint32_t HSIState; /*!< The new state of the HSI.
This parameter can be a value of @ref RCC_HSI_Config */
uint32_t HSICalibrationValue; /*!< The calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
uint32_t LSIState; /*!< The new state of the LSI.
@ -146,11 +125,11 @@ typedef struct
/** @defgroup RCC_Oscillator_Type Oscillator Type
* @{
*/
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000U)
#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001U)
#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002U)
#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004U)
#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008U)
/**
* @}
*/
@ -158,7 +137,7 @@ typedef struct
/** @defgroup RCC_HSE_Config RCC HSE Config
* @{
*/
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_OFF ((uint32_t)0x00000000U)
#define RCC_HSE_ON RCC_CR_HSEON
#define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON))
/**
@ -168,7 +147,7 @@ typedef struct
/** @defgroup RCC_LSE_Config RCC LSE Config
* @{
*/
#define RCC_LSE_OFF ((uint32_t)0x00000000)
#define RCC_LSE_OFF ((uint32_t)0x00000000U)
#define RCC_LSE_ON RCC_BDCR_LSEON
#define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON))
/**
@ -178,8 +157,10 @@ typedef struct
/** @defgroup RCC_HSI_Config RCC HSI Config
* @{
*/
#define RCC_HSI_OFF ((uint32_t)0x00000000)
#define RCC_HSI_OFF ((uint32_t)0x00000000U)
#define RCC_HSI_ON RCC_CR_HSION
#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10U) /* Default HSI calibration trimming value */
/**
* @}
*/
@ -187,7 +168,7 @@ typedef struct
/** @defgroup RCC_LSI_Config RCC LSI Config
* @{
*/
#define RCC_LSI_OFF ((uint32_t)0x00000000)
#define RCC_LSI_OFF ((uint32_t)0x00000000U)
#define RCC_LSI_ON RCC_CSR_LSION
/**
* @}
@ -196,9 +177,9 @@ typedef struct
/** @defgroup RCC_PLL_Config RCC PLL Config
* @{
*/
#define RCC_PLL_NONE ((uint32_t)0x00000000)
#define RCC_PLL_OFF ((uint32_t)0x00000001)
#define RCC_PLL_ON ((uint32_t)0x00000002)
#define RCC_PLL_NONE ((uint32_t)0x00000000U)
#define RCC_PLL_OFF ((uint32_t)0x00000001U)
#define RCC_PLL_ON ((uint32_t)0x00000002U)
/**
* @}
*/
@ -206,10 +187,10 @@ typedef struct
/** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
* @{
*/
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
#define RCC_PLLP_DIV2 ((uint32_t)0x00000002U)
#define RCC_PLLP_DIV4 ((uint32_t)0x00000004U)
#define RCC_PLLP_DIV6 ((uint32_t)0x00000006U)
#define RCC_PLLP_DIV8 ((uint32_t)0x00000008U)
/**
* @}
*/
@ -226,10 +207,10 @@ typedef struct
/** @defgroup RCC_System_Clock_Type RCC System Clock Type
* @{
*/
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001U)
#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002U)
#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004U)
#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008U)
/**
* @}
*/
@ -286,38 +267,38 @@ typedef struct
/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
* @{
*/
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300U)
#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300U)
#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300U)
#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300U)
#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300U)
#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300U)
#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300U)
#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300U)
#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300U)
#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300U)
#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300U)
#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300U)
#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300U)
#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300U)
#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300U)
#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300U)
#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300U)
/**
* @}
*/
@ -327,8 +308,8 @@ typedef struct
/** @defgroup RCC_MCO_Index RCC MCO Index
* @{
*/
#define RCC_MCO1 ((uint32_t)0x00000000)
#define RCC_MCO2 ((uint32_t)0x00000001)
#define RCC_MCO1 ((uint32_t)0x00000000U)
#define RCC_MCO2 ((uint32_t)0x00000001U)
/**
* @}
*/
@ -336,7 +317,7 @@ typedef struct
/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
* @{
*/
#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000U)
#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
@ -347,7 +328,7 @@ typedef struct
/** @defgroup RCC_MCO2_Clock_Source RCC MCO2 Clock Source
* @{
*/
#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000U)
#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
@ -358,7 +339,7 @@ typedef struct
/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
* @{
*/
#define RCC_MCODIV_1 ((uint32_t)0x00000000)
#define RCC_MCODIV_1 ((uint32_t)0x00000000U)
#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
@ -370,14 +351,14 @@ typedef struct
/** @defgroup RCC_Interrupt RCC Interrupt
* @{
*/
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40)
#define RCC_IT_CSS ((uint8_t)0x80)
#define RCC_IT_LSIRDY ((uint8_t)0x01U)
#define RCC_IT_LSERDY ((uint8_t)0x02U)
#define RCC_IT_HSIRDY ((uint8_t)0x04U)
#define RCC_IT_HSERDY ((uint8_t)0x08U)
#define RCC_IT_PLLRDY ((uint8_t)0x10U)
#define RCC_IT_PLLI2SRDY ((uint8_t)0x20U)
#define RCC_IT_PLLSAIRDY ((uint8_t)0x40U)
#define RCC_IT_CSS ((uint8_t)0x80U)
/**
* @}
*/
@ -392,24 +373,24 @@ typedef struct
* @{
*/
/* Flags in the CR register */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3C)
#define RCC_FLAG_HSIRDY ((uint8_t)0x21U)
#define RCC_FLAG_HSERDY ((uint8_t)0x31U)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39U)
#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3BU)
#define RCC_FLAG_PLLSAIRDY ((uint8_t)0x3CU)
/* Flags in the BDCR register */
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSERDY ((uint8_t)0x41U)
/* Flags in the CSR register */
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_BORRST ((uint8_t)0x79)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61U)
#define RCC_FLAG_BORRST ((uint8_t)0x79U)
#define RCC_FLAG_PINRST ((uint8_t)0x7AU)
#define RCC_FLAG_PORRST ((uint8_t)0x7BU)
#define RCC_FLAG_SFTRST ((uint8_t)0x7CU)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7DU)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7EU)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7FU)
/**
* @}
*/
@ -417,7 +398,7 @@ typedef struct
/** @defgroup RCC_LSEDrive_Configuration RCC LSE Drive configurations
* @{
*/
#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000U)
#define RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1
#define RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0
#define RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV
@ -442,7 +423,7 @@ typedef struct
* @{
*/
#define __HAL_RCC_CRC_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
@ -450,7 +431,7 @@ typedef struct
} while(0)
#define __HAL_RCC_DMA1_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
@ -472,7 +453,7 @@ typedef struct
* @{
*/
#define __HAL_RCC_WWDG_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
@ -480,7 +461,7 @@ typedef struct
} while(0)
#define __HAL_RCC_PWR_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
@ -501,7 +482,7 @@ typedef struct
* @{
*/
#define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00; \
__IO uint32_t tmpreg; \
SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
/* Delay after an RCC peripheral clock enabling */ \
tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
@ -563,11 +544,11 @@ typedef struct
* @brief Force or release AHB peripheral reset.
* @{
*/
#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
#define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
#define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00U)
#define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
#define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
/**
@ -578,11 +559,11 @@ typedef struct
* @brief Force or release APB1 peripheral reset.
* @{
*/
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
/**
@ -593,10 +574,10 @@ typedef struct
* @brief Force or release APB2 peripheral reset.
* @{
*/
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
#define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00U)
#define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
/**
@ -714,7 +695,7 @@ typedef struct
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
* @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
* This parameter must be a number between 0 and 0x1F.
* (default is RCC_HSICALIBRATION_DEFAULT).
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
@ -744,17 +725,20 @@ typedef struct
* @{
*/
/**
* @brief Macro to configure the External High Speed oscillator (__HSE__).
* @brief Macro to configure the External High Speed oscillator (HSE).
* @note Transitions HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this macro. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
* is stable and can be used to clock the PLL and/or system clock.
* @note HSE state can not be changed if it is used directly or through the
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
* function.
* @param __STATE__: specifies the new state of the HSE.
* This parameter can be one of the following values:
* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
@ -762,24 +746,27 @@ typedef struct
* @arg RCC_HSE_ON: turn ON the HSE oscillator.
* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
*/
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
if((__STATE__) == RCC_HSE_ON) \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else if((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
} \
#define __HAL_RCC_HSE_CONFIG(__STATE__) \
do { \
if ((__STATE__) == RCC_HSE_ON) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else if ((__STATE__) == RCC_HSE_OFF) \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
else if ((__STATE__) == RCC_HSE_BYPASS) \
{ \
SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
SET_BIT(RCC->CR, RCC_CR_HSEON); \
} \
else \
{ \
CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
} \
} while(0)
/**
* @}
@ -791,7 +778,7 @@ typedef struct
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
* @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
* this domain after reset, you have to enable write access using
@ -809,12 +796,15 @@ typedef struct
*/
#define __HAL_RCC_LSE_CONFIG(__STATE__) \
do { \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
if((__STATE__) == RCC_LSE_ON) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
} \
else if((__STATE__) == RCC_LSE_OFF) \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
else if((__STATE__) == RCC_LSE_BYPASS) \
{ \
SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
@ -822,8 +812,8 @@ typedef struct
} \
else \
{ \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
} \
} while(0)
/**
@ -892,39 +882,6 @@ typedef struct
*/
#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
* @param __RCC_PLLSource__: specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
* @param __PLLM__: specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
* This parameter must be a number between Min_Data = 100 and Max_Data = 432.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 100 and 432 MHz.
* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
* the System clock frequency.
* @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
* correctly.
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
(RCC->PLLCFGR = (0x20000000 | (__PLLM__) | ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | (__RCC_PLLSource__) | \
((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
@ -1099,7 +1056,7 @@ typedef struct
* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
*/
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
@ -1216,9 +1173,9 @@ void HAL_RCC_CSSCallback(void);
* @{
*/
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
@ -1232,7 +1189,7 @@ void HAL_RCC_CSSCallback(void);
#define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
#define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
#define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
#define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
/**
* @}
*/

462
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@ -12,7 +12,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -114,12 +114,12 @@
* parameters in the RCC_PeriphCLKInitTypeDef.
* @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, SAI, LTDC RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
* clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
*
* @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
* the RTC clock source; in this case the Backup domain will be reset in
* order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) and RCC_BDCR register are set to their reset values.
* the backup registers) are set to their reset values.
*
* @retval HAL status
*/
@ -200,38 +200,44 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/*------------------------------------ RTC configuration --------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait for Backup domain Write protection disable */
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
{
if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
/* Reset the Backup domain only if the RTC Clock source selection is modified */
if((RCC->BDCR & RCC_BDCR_RTCSEL) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL))
/* Reset the Backup domain only if the RTC Clock source selection is modified */
tmpreg0 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg0 != 0x00000000U) && (tmpreg0 != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
/* Store the content of BDCR register before the reset of Backup Domain */
tmpreg0 = (RCC->BDCR & ~(RCC_BDCR_RTCSEL));
/* RTC Clock selection can be changed only if the Backup Domain is reset */
__HAL_RCC_BACKUPRESET_FORCE();
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg0;
/* If LSE is selected as RTC clock source, wait for LSE reactivation */
if (HAL_IS_BIT_SET(tmpreg0, RCC_BDCR_LSERDY))
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
@ -245,8 +251,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
}
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*------------------------------------ TIM configuration --------------------------------------*/
@ -406,12 +412,13 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
}
/*-------------------------------------- LTDC Configuration -----------------------------------*/
#if defined(STM32F756xx) || defined(STM32F746xx)
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC)
{
pllsaiused = 1;
}
#endif /* STM32F756xx || STM32F746xx */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- LPTIM1 Configuration -----------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
{
@ -431,7 +438,39 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the SDMMC1 clock source */
__HAL_RCC_SDMMC1_CONFIG(PeriphClkInit->Sdmmc1ClockSelection);
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/*------------------------------------- SDMMC2 Configuration ------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDMMC2) == RCC_PERIPHCLK_SDMMC2)
{
/* Check the parameters */
assert_param(IS_RCC_SDMMC2CLKSOURCE(PeriphClkInit->Sdmmc2ClockSelection));
/* Configure the SDMMC2 clock source */
__HAL_RCC_SDMMC2_CONFIG(PeriphClkInit->Sdmmc2ClockSelection);
}
/*------------------------------------- DFSDM1 Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1) == RCC_PERIPHCLK_DFSDM1)
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1CLKSOURCE(PeriphClkInit->Dfsdm1ClockSelection));
/* Configure the DFSDM1 interface clock source */
__HAL_RCC_DFSDM1_CONFIG(PeriphClkInit->Dfsdm1ClockSelection);
}
/*------------------------------------- DFSDM AUDIO Configuration -------------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM1_AUDIO) == RCC_PERIPHCLK_DFSDM1_AUDIO)
{
/* Check the parameters */
assert_param(IS_RCC_DFSDM1AUDIOCLKSOURCE(PeriphClkInit->Dfsdm1AudioClockSelection));
/* Configure the DFSDM interface clock source */
__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*-------------------------------------- PLLI2S Configuration ---------------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S or SPDIF-RX */
if((plli2sused == 1) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
@ -598,7 +637,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, tmpreg0, tmpreg1);
}
#if defined(STM32F756xx) || defined(STM32F746xx)
#if defined(STM32F746xx) || defined(STM32F756xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/*---------------------------- LTDC configuration -------------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{
@ -617,7 +656,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
}
#endif /* STM32F756xx || STM32F746xx */
#endif /* STM32F746xx || STM32F756xx || STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
@ -648,7 +687,21 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tempreg = 0;
/* Set all possible values for the extended clock type parameter------------*/
/* Set all possible values for the extended clock type parameter------------*/
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_I2C4 |\
RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 |\
RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_USART1 |\
RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 |\
RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 |\
RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2 |\
RCC_PERIPHCLK_DFSDM1 | RCC_PERIPHCLK_DFSDM1_AUDIO;
#else
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_LPTIM1 |\
RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
@ -660,7 +713,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
RCC_PERIPHCLK_USART6 | RCC_PERIPHCLK_UART7 |\
RCC_PERIPHCLK_UART8 | RCC_PERIPHCLK_SDMMC1 |\
RCC_PERIPHCLK_CLK48;
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Get the PLLI2S Clock configuration -----------------------------------------------*/
PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
@ -733,9 +786,20 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Get the CK48 clock configuration -----------------------------------------------*/
PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
/* Get the SDMMC clock configuration -----------------------------------------------*/
/* Get the SDMMC1 clock configuration -----------------------------------------------*/
PeriphClkInit->Sdmmc1ClockSelection = __HAL_RCC_GET_SDMMC1_SOURCE();
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/* Get the SDMMC2 clock configuration -----------------------------------------------*/
PeriphClkInit->Sdmmc2ClockSelection = __HAL_RCC_GET_SDMMC2_SOURCE();
/* Get the DFSDM clock configuration -----------------------------------------------*/
PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
/* Get the DFSDM AUDIO clock configuration -----------------------------------------------*/
PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Get the RTC Clock configuration -----------------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
@ -830,6 +894,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
case RCC_DCKCFGR1_SAI1SEL: /* HSI or HSE is the clock source for SAI*/
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the main PLL Source is HSI */
frequency = HSI_VALUE;
}
else
{
/* In Case the main PLL Source is HSE */
frequency = HSE_VALUE;
}
break;
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
default :
{
break;
@ -897,6 +977,22 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = EXTERNAL_CLOCK_VALUE;
break;
}
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
case RCC_DCKCFGR1_SAI2SEL: /* HSI or HSE is the clock source for SAI2 */
{
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the main PLL Source is HSI */
frequency = HSI_VALUE;
}
else
{
/* In Case the main PLL Source is HSE */
frequency = HSE_VALUE;
}
break;
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
default :
{
break;
@ -906,6 +1002,324 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
return frequency;
}
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
/**
* @brief Initializes the RCC Oscillators according to the specified parameters in the
* RCC_OscInitTypeDef.
* @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
* supported by this function. User should request a transition to LSE Off
* first and then LSE On or LSE Bypass.
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this function. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
/*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
}
else
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
}
/*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
{
return HAL_ERROR;
}
/* Otherwise, just the calibration is allowed */
else
{
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
}
else
{
/* Check the HSI State */
if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
{
/* Enable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_ENABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
else
{
/* Disable the Internal High Speed oscillator (HSI). */
__HAL_RCC_HSI_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
}
/*------------------------------ LSI Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
{
/* Check the parameters */
assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
/* Check the LSI State */
if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
while((PWR->CR1 & PWR_CR1_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
if((RCC_OscInitStruct->LSEState) != RCC_LSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
{
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
assert_param(IS_RCC_PLLM_VALUE(RCC_OscInitStruct->PLL.PLLM));
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
RCC_OscInitStruct->PLL.PLLM,
RCC_OscInitStruct->PLL.PLLN,
RCC_OscInitStruct->PLL.PLLP,
RCC_OscInitStruct->PLL.PLLQ,
RCC_OscInitStruct->PLL.PLLR);
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
/* Get Start Tick*/
tickstart = HAL_GetTick();
/* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
}
}
}
else
{
return HAL_ERROR;
}
}
return HAL_OK;
}
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
*/

864
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rcc_ex.h
View File

File diff suppressed because it is too large Load Diff

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rng.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@ -29,7 +29,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

16
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rng.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_rng.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -66,11 +66,11 @@
*/
typedef enum
{
HAL_RNG_STATE_RESET = 0x00, /*!< RNG not yet initialized or disabled */
HAL_RNG_STATE_READY = 0x01, /*!< RNG initialized and ready for use */
HAL_RNG_STATE_BUSY = 0x02, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04 /*!< RNG error state */
HAL_RNG_STATE_RESET = 0x00U, /*!< RNG not yet initialized or disabled */
HAL_RNG_STATE_READY = 0x01U, /*!< RNG initialized and ready for use */
HAL_RNG_STATE_BUSY = 0x02U, /*!< RNG internal process is ongoing */
HAL_RNG_STATE_TIMEOUT = 0x03U, /*!< RNG timeout state */
HAL_RNG_STATE_ERROR = 0x04U /*!< RNG error state */
}HAL_RNG_StateTypeDef;

13
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@ -109,7 +109,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -581,6 +581,9 @@ HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim
/* Get subseconds values from the correspondent registers*/
sTime->SubSeconds = (uint32_t)(hrtc->Instance->SSR);
/* Get SecondFraction structure field from the corresponding register field*/
sTime->SecondFraction = (uint32_t)(hrtc->Instance->PRER & RTC_PRER_PREDIV_S);
/* Get the TR register */
tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK);
@ -626,9 +629,9 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat
hrtc->State = HAL_RTC_STATE_BUSY;
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
if((Format == RTC_FORMAT_BIN) && ((sDate->Month & 0x10U) == 0x10U))
{
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10U)) + (uint8_t)0x0AU);
}
assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));

143
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.h
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,11 +64,11 @@
*/
typedef enum
{
HAL_RTC_STATE_RESET = 0x00, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04 /*!< RTC error state */
HAL_RTC_STATE_RESET = 0x00U, /*!< RTC not yet initialized or disabled */
HAL_RTC_STATE_READY = 0x01U, /*!< RTC initialized and ready for use */
HAL_RTC_STATE_BUSY = 0x02U, /*!< RTC process is ongoing */
HAL_RTC_STATE_TIMEOUT = 0x03U, /*!< RTC timeout state */
HAL_RTC_STATE_ERROR = 0x04U /*!< RTC error state */
}HAL_RTCStateTypeDef;
@ -111,8 +111,15 @@ typedef struct
uint8_t Seconds; /*!< Specifies the RTC Time Seconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint32_t SubSeconds; /*!< Specifies the RTC Time SubSeconds.
This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
uint32_t SubSeconds; /*!< Specifies the RTC_SSR RTC Sub Second register content.
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity */
uint32_t SecondFraction; /*!< Specifies the range or granularity of Sub Second register content
corresponding to Synchronous pre-scaler factor value (PREDIV_S)
This parameter corresponds to a time unit range between [0-1] Second
with [1 Sec / SecondFraction +1] granularity.
This field will be used only by HAL_RTC_GetTime function */
uint8_t TimeFormat; /*!< Specifies the RTC AM/PM Time.
This parameter can be a value of @ref RTC_AM_PM_Definitions */
@ -195,8 +202,8 @@ typedef struct
/** @defgroup RTC_Hour_Formats RTC Hour Formats
* @{
*/
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040)
#define RTC_HOURFORMAT_24 ((uint32_t)0x00000000U)
#define RTC_HOURFORMAT_12 ((uint32_t)0x00000040U)
/**
* @}
*/
@ -205,8 +212,8 @@ typedef struct
/** @defgroup RTC_Output_Polarity_Definitions RTC Output Polarity Definitions
* @{
*/
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000)
#define RTC_OUTPUT_POLARITY_HIGH ((uint32_t)0x00000000U)
#define RTC_OUTPUT_POLARITY_LOW ((uint32_t)0x00100000U)
/**
* @}
*/
@ -214,7 +221,7 @@ typedef struct
/** @defgroup RTC_Output_Type_ALARM_OUT RTC Output Type ALARM OUT
* @{
*/
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000)
#define RTC_OUTPUT_TYPE_OPENDRAIN ((uint32_t)0x00000000U)
#define RTC_OUTPUT_TYPE_PUSHPULL ((uint32_t)RTC_OR_ALARMTYPE) /* 0x00000008 */
/**
* @}
@ -223,8 +230,8 @@ typedef struct
/** @defgroup RTC_AM_PM_Definitions RTC AM PM Definitions
* @{
*/
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40)
#define RTC_HOURFORMAT12_AM ((uint8_t)0x00U)
#define RTC_HOURFORMAT12_PM ((uint8_t)0x40U)
/**
* @}
*/
@ -232,9 +239,9 @@ typedef struct
/** @defgroup RTC_DayLightSaving_Definitions RTC DayLight Saving Definitions
* @{
*/
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000)
#define RTC_DAYLIGHTSAVING_SUB1H ((uint32_t)0x00020000U)
#define RTC_DAYLIGHTSAVING_ADD1H ((uint32_t)0x00010000U)
#define RTC_DAYLIGHTSAVING_NONE ((uint32_t)0x00000000U)
/**
* @}
*/
@ -242,8 +249,8 @@ typedef struct
/** @defgroup RTC_StoreOperation_Definitions RTC Store Operation Definitions
* @{
*/
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000)
#define RTC_STOREOPERATION_RESET ((uint32_t)0x00000000U)
#define RTC_STOREOPERATION_SET ((uint32_t)0x00040000U)
/**
* @}
*/
@ -251,8 +258,8 @@ typedef struct
/** @defgroup RTC_Input_parameter_format_definitions RTC Input Parameter Format Definitions
* @{
*/
#define RTC_FORMAT_BIN ((uint32_t)0x000000000)
#define RTC_FORMAT_BCD ((uint32_t)0x000000001)
#define RTC_FORMAT_BIN ((uint32_t)0x00000000U)
#define RTC_FORMAT_BCD ((uint32_t)0x00000001U)
/**
* @}
*/
@ -261,18 +268,18 @@ typedef struct
* @{
*/
/* Coded in BCD format */
#define RTC_MONTH_JANUARY ((uint8_t)0x01)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02)
#define RTC_MONTH_MARCH ((uint8_t)0x03)
#define RTC_MONTH_APRIL ((uint8_t)0x04)
#define RTC_MONTH_MAY ((uint8_t)0x05)
#define RTC_MONTH_JUNE ((uint8_t)0x06)
#define RTC_MONTH_JULY ((uint8_t)0x07)
#define RTC_MONTH_AUGUST ((uint8_t)0x08)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12)
#define RTC_MONTH_JANUARY ((uint8_t)0x01U)
#define RTC_MONTH_FEBRUARY ((uint8_t)0x02U)
#define RTC_MONTH_MARCH ((uint8_t)0x03U)
#define RTC_MONTH_APRIL ((uint8_t)0x04U)
#define RTC_MONTH_MAY ((uint8_t)0x05U)
#define RTC_MONTH_JUNE ((uint8_t)0x06U)
#define RTC_MONTH_JULY ((uint8_t)0x07U)
#define RTC_MONTH_AUGUST ((uint8_t)0x08U)
#define RTC_MONTH_SEPTEMBER ((uint8_t)0x09U)
#define RTC_MONTH_OCTOBER ((uint8_t)0x10U)
#define RTC_MONTH_NOVEMBER ((uint8_t)0x11U)
#define RTC_MONTH_DECEMBER ((uint8_t)0x12U)
/**
* @}
*/
@ -280,13 +287,13 @@ typedef struct
/** @defgroup RTC_WeekDay_Definitions RTC WeekDay Definitions
* @{
*/
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07)
#define RTC_WEEKDAY_MONDAY ((uint8_t)0x01U)
#define RTC_WEEKDAY_TUESDAY ((uint8_t)0x02U)
#define RTC_WEEKDAY_WEDNESDAY ((uint8_t)0x03U)
#define RTC_WEEKDAY_THURSDAY ((uint8_t)0x04U)
#define RTC_WEEKDAY_FRIDAY ((uint8_t)0x05U)
#define RTC_WEEKDAY_SATURDAY ((uint8_t)0x06U)
#define RTC_WEEKDAY_SUNDAY ((uint8_t)0x07U)
/**
* @}
*/
@ -294,8 +301,8 @@ typedef struct
/** @defgroup RTC_AlarmDateWeekDay_Definitions RTC Alarm Date WeekDay Definitions
* @{
*/
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000)
#define RTC_ALARMDATEWEEKDAYSEL_DATE ((uint32_t)0x00000000U)
#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY ((uint32_t)0x40000000U)
/**
* @}
*/
@ -303,12 +310,12 @@ typedef struct
/** @defgroup RTC_AlarmMask_Definitions RTC Alarm Mask Definitions
* @{
*/
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000)
#define RTC_ALARMMASK_NONE ((uint32_t)0x00000000U)
#define RTC_ALARMMASK_DATEWEEKDAY RTC_ALRMAR_MSK4
#define RTC_ALARMMASK_HOURS RTC_ALRMAR_MSK3
#define RTC_ALARMMASK_MINUTES RTC_ALRMAR_MSK2
#define RTC_ALARMMASK_SECONDS RTC_ALRMAR_MSK1
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080)
#define RTC_ALARMMASK_ALL ((uint32_t)0x80808080U)
/**
* @}
*/
@ -325,38 +332,38 @@ typedef struct
/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions RTC Alarm Sub Seconds Masks Definitions
* @{
*/
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked.
#define RTC_ALARMSUBSECONDMASK_ALL ((uint32_t)0x00000000U) /*!< All Alarm SS fields are masked.
There is no comparison on sub seconds
for Alarm */
#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_1 ((uint32_t)0x01000000U) /*!< SS[14:1] are don't care in Alarm
comparison. Only SS[0] is compared. */
#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_2 ((uint32_t)0x02000000U) /*!< SS[14:2] are don't care in Alarm
comparison. Only SS[1:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_3 ((uint32_t)0x03000000U) /*!< SS[14:3] are don't care in Alarm
comparison. Only SS[2:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_4 ((uint32_t)0x04000000U) /*!< SS[14:4] are don't care in Alarm
comparison. Only SS[3:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_5 ((uint32_t)0x05000000U) /*!< SS[14:5] are don't care in Alarm
comparison. Only SS[4:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_6 ((uint32_t)0x06000000U) /*!< SS[14:6] are don't care in Alarm
comparison. Only SS[5:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_7 ((uint32_t)0x07000000U) /*!< SS[14:7] are don't care in Alarm
comparison. Only SS[6:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_8 ((uint32_t)0x08000000U) /*!< SS[14:8] are don't care in Alarm
comparison. Only SS[7:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_9 ((uint32_t)0x09000000U) /*!< SS[14:9] are don't care in Alarm
comparison. Only SS[8:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_10 ((uint32_t)0x0A000000U) /*!< SS[14:10] are don't care in Alarm
comparison. Only SS[9:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_11 ((uint32_t)0x0B000000U) /*!< SS[14:11] are don't care in Alarm
comparison. Only SS[10:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_12 ((uint32_t)0x0C000000U) /*!< SS[14:12] are don't care in Alarm
comparison.Only SS[11:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14_13 ((uint32_t)0x0D000000U) /*!< SS[14:13] are don't care in Alarm
comparison. Only SS[12:0] are compared */
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm
#define RTC_ALARMSUBSECONDMASK_SS14 ((uint32_t)0x0E000000U) /*!< SS[14] is don't care in Alarm
comparison.Only SS[13:0] are compared */
#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match
#define RTC_ALARMSUBSECONDMASK_NONE ((uint32_t)0x0F000000U) /*!< SS[14:0] are compared and must match
to activate alarm. */
/**
* @}
@ -690,14 +697,14 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
* @{
*/
/* Masks Definition */
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7F)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3F)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFF)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5F)
#define RTC_TR_RESERVED_MASK ((uint32_t)0x007F7F7FU)
#define RTC_DR_RESERVED_MASK ((uint32_t)0x00FFFF3FU)
#define RTC_INIT_MASK ((uint32_t)0xFFFFFFFFU)
#define RTC_RSF_MASK ((uint32_t)0xFFFFFF5FU)
#define RTC_TIMEOUT_VALUE 1000
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_MR17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
#define RTC_EXTI_LINE_ALARM_EVENT ((uint32_t)EXTI_IMR_IM17) /*!< External interrupt line 17 Connected to the RTC Alarm event */
/**
* @}
*/

6
hal/targets/cmsis/TARGET_STM/TARGET_STM32F7/stm32f7xx_hal_rtc_ex.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.c
* @author MCD Application Team
* @version V1.0.4
* @date 09-December-2015
* @version V1.1.0
* @date 22-April-2016
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@ -70,7 +70,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

Some files were not shown because too many files have changed in this diff Show More