diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_adc.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_adc.c index da7990a72f..0facc0385a 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_adc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_adc.c @@ -280,9 +280,8 @@ #define ADC_STAB_DELAY_US ((uint32_t) 1U) /* Delay for temperature sensor stabilization time. */ -/* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */ /* Unit: us */ -#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U) +#define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 20000U) /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_crc.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_crc.c index e43a42313a..98e0cc21a3 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_crc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_crc.c @@ -422,7 +422,14 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t return temp; } +#if __GNUC__ +# define MAY_ALIAS __attribute__ ((__may_alias__)) +#else +# define MAY_ALIAS +#endif +typedef __IO uint8_t MAY_ALIAS uint8_io_t; +typedef __IO uint16_t MAY_ALIAS uint16_io_t; /** * @} @@ -487,16 +494,16 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ { if (BufferLength%4U == 1U) { - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i]; + *(uint8_io_t*) (&hcrc->Instance->DR) = pBuffer[4U*i]; } if (BufferLength%4U == 2U) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U]; + *(uint16_io_t*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U]; } if (BufferLength%4U == 3U) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U]; - *(uint8_t volatile*) (&hcrc->Instance->DR) = pBuffer[4U*i+2U]; + *(uint16_io_t*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4U*i]<<8U) | (uint32_t)pBuffer[4U*i+1U]; + *(uint8_io_t*) (&hcrc->Instance->DR) = pBuffer[4U*i+2U]; } } @@ -525,7 +532,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3 } if ((BufferLength%2U) != 0U) { - *(uint16_t volatile*) (&hcrc->Instance->DR) = pBuffer[2U*i]; + *(uint16_io_t*) (&hcrc->Instance->DR) = pBuffer[2U*i]; } /* Return the CRC computed value */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_i2c.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_i2c.c index 2d1ccc8a68..0f6f34f1dc 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_i2c.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_i2c.c @@ -2607,12 +2607,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + // MBED commit 23926a2418 /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) - { - xferrequest = I2C_NO_STARTSTOP; - } + //if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX) + //{ + // xferrequest = I2C_NO_STARTSTOP; + //} /* Send Slave Address and set NBYTES to write */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -2680,12 +2681,13 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, xfermode = hi2c->XferOptions; } + // MBED commit 23926a2418 /* If transfer direction not change, do not generate Restart Condition */ /* Mean Previous state is same as current state */ - if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) - { - xferrequest = I2C_NO_STARTSTOP; - } + //if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX) + //{ + // xferrequest = I2C_NO_STARTSTOP; + //} /* Send Slave Address and set NBYTES to read */ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest); @@ -3444,7 +3446,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint { /* Call I2C Slave Sequential complete process */ I2C_ITSlaveSequentialCplt(hi2c); - } + } } else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET)) { @@ -3510,7 +3512,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui /* Set corresponding Error Code */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; - + /* No need to generate STOP, it is automatically done */ /* But enable STOP interrupt, to treat it */ /* Error callback will be send during stop flag treatment */ @@ -3528,7 +3530,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui { /* Recover Slave address */ devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD); - + /* Prepare the new XferSize to transfer */ if (hi2c->XferCount > MAX_NBYTE_SIZE) { @@ -3564,7 +3566,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE); } } - else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) + else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET)) { /* Call I2C Master complete process */ I2C_ITMasterCplt(hi2c, ITFlags); @@ -3605,7 +3607,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - + /* Set ErrorCode corresponding to a Non-Acknowledge */ hi2c->ErrorCode |= HAL_I2C_ERROR_AF; } @@ -4208,7 +4210,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) { /* Disable all interrupts */ I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT); - + /* If state is an abort treatment on goind, don't change state */ /* This change will be do later */ if (hi2c->State != HAL_I2C_STATE_ABORT) @@ -4261,7 +4263,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode) else if (hi2c->State == HAL_I2C_STATE_ABORT) { hi2c->State = HAL_I2C_STATE_READY; - + /* Process Unlocked */ __HAL_UNLOCK(hi2c); diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_rcc.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_rcc.c index d846f73c4c..8b08c3ee2b 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_rcc.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_rcc.c @@ -787,7 +787,19 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) } else { - return HAL_ERROR; + /* MBED patch - ST internal ticket 42806 */ + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLDIV) != RCC_OscInitStruct->PLL.PLLDIV) { + return HAL_ERROR; + } + + if (READ_BIT(RCC->CFGR, RCC_CFGR_PLLMUL) != RCC_OscInitStruct->PLL.PLLMUL) { + return HAL_ERROR; + } + /* MBED patch - ST internal ticket 42806 */ } } diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_spi.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_spi.c index 45615e2f10..3bd1f6db3c 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_spi.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_spi.c @@ -167,16 +167,32 @@ * @{ */ #define SPI_TIMEOUT_VALUE 10U +#define SPI_DEFAULT_TIMEOUT 100U // MBED commit 64a037cc /* Private macro -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/ -static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi); -static void SPI_TxISR(SPI_HandleTypeDef *hspi); -static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi); -static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi); -static void SPI_RxISR(SPI_HandleTypeDef *hspi); +// MBED commit 64a037cc +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart); +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi); +#if (USE_SPI_CRC != 0U) +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi); +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi); +#endif /* USE_SPI_CRC */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi); +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi); +static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart); static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma); static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma); static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma); @@ -1011,7 +1027,17 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->TxISR = &SPI_TxISR; + // MBED commit 64a037cc + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->TxISR = SPI_TxISR_16BIT; + } + else + { + hspi->TxISR = SPI_TxISR_8BIT; + } + hspi->pTxBuffPtr = pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1085,7 +1111,16 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->RxISR = &SPI_RxISR; + // MBED commit 64a037cc + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = SPI_RxISR_16BIT; + } + else + { + hspi->RxISR = SPI_RxISR_8BIT; + } hspi->pRxBuffPtr = pData; hspi->RxXferSize = Size; hspi->RxXferCount = Size ; @@ -1176,16 +1211,27 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Configure communication */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->TxISR = &SPI_TxISR; hspi->pTxBuffPtr = pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; - hspi->RxISR = &SPI_2LinesRxISR; hspi->pRxBuffPtr = pRxData; hspi->RxXferSize = Size; hspi->RxXferCount = Size; + // MBED commit 64a037cc + /* Set the function for IT treatment */ + if(hspi->Init.DataSize > SPI_DATASIZE_8BIT ) + { + hspi->RxISR = SPI_2linesRxISR_16BIT; + hspi->TxISR = SPI_2linesTxISR_16BIT; + } + else + { + hspi->RxISR = SPI_2linesRxISR_8BIT; + hspi->TxISR = SPI_2linesTxISR_8BIT; + } + /* Reset CRC Calculation */ if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) { @@ -1193,7 +1239,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p } /* Enable TXE, RXNE and ERR interrupt */ - __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); // MBED patch: Send next byte in hardware register only after previous one is read /* Process Unlocked */ __HAL_UNLOCK(hspi); @@ -1205,6 +1251,11 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p __HAL_SPI_ENABLE(hspi); } + /* MBED patch: Send next byte in hardware register only after previous one is read + Start 1st byte transmission (function is the same than for ISR), further transmissions will be trigger by RX interrupt */ + hspi->TxISR(hspi); + + return HAL_OK; } else @@ -1604,6 +1655,14 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi) if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET)) { hspi->RxISR(hspi); + /* MBED patch Send next byte in hardware register only after previous one is read to avoid overrun */ + if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) { + if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET) && (hspi->TxXferCount != 0U)) + { + hspi->TxISR(hspi); + } + } + return; } @@ -1814,251 +1873,12 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) /** * @} */ - -/** - * @} - */ - - /** @addtogroup SPI_Private * @{ */ - - /** - * @brief Interrupt Handler to close Tx transfer - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_TxCloseIRQHandler(SPI_HandleTypeDef *hspi) -{ - /* Wait until TXE flag is set to send data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Disable TXE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); - - /* Disable ERR interrupt if Receive process is finished */ - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET) - { - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); - - /* Wait until Busy flag is reset before disabling SPI */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Clear OVERUN flag in 2 Lines communication mode because received is not read */ - if(hspi->Init.Direction == SPI_DIRECTION_2LINES) - { - __HAL_SPI_CLEAR_OVRFLAG(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - /* Check if we are in Tx or in Rx/Tx Mode */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxCpltCallback(hspi); - } - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - /* Call Error call back in case of Error */ - HAL_SPI_ErrorCallback(hspi); - } - } -} - -/** - * @brief Interrupt Handler to transmit amount of data in no-blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_TxISR(SPI_HandleTypeDef *hspi) -{ - /* Transmit data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - hspi->Instance->DR = (*hspi->pTxBuffPtr++); - } - /* Transmit data in 16 Bit mode */ - else - { - hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr); - hspi->pTxBuffPtr+=2U; - } - hspi->TxXferCount--; - - if(hspi->TxXferCount == 0U) - { - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* calculate and transfer CRC on Tx line */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - SPI_TxCloseIRQHandler(hspi); - } -} - -/** - * @brief Interrupt Handler to close Rx transfer - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_RxCloseIRQHandler(SPI_HandleTypeDef *hspi) -{ - __IO uint16_t tmpreg = 0U; - - if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) - { - /* Wait until RXNE flag is set to read CRC data */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Read CRC to reset RXNE flag */ - tmpreg = hspi->Instance->DR; - UNUSED(tmpreg); /* avoid warning on tmpreg affectation with some compiler */ - - /* Wait until RXNE flag is reset */ - if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); - } - - /* Check if CRC error occurred */ - if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) - { - SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - - /* Reset CRC Calculation */ - SPI_RESET_CRC(hspi); - } - } - - /* Disable RXNE interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE)); - - /* if Transmit process is finished */ - if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET) - { - /* Disable ERR interrupt */ - __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR)); - - if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) - { - /* Disable SPI peripheral */ - __HAL_SPI_DISABLE(hspi); - } - - /* Check if Errors has been detected during transfer */ - if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) - { - /* Check if we are in Rx or in Rx/Tx Mode */ - if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX) - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_TxRxCpltCallback(hspi); - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - HAL_SPI_RxCpltCallback(hspi); - } - } - else - { - /* Set state to READY before run the Callback Complete */ - hspi->State = HAL_SPI_STATE_READY; - /* Call Error call back in case of Error */ - HAL_SPI_ErrorCallback(hspi); - } - } -} - -/** - * @brief Interrupt Handler to receive amount of data in 2Lines mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_2LinesRxISR(SPI_HandleTypeDef *hspi) -{ - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2U; - } - hspi->RxXferCount--; - - if(hspi->RxXferCount==0U) - { - SPI_RxCloseIRQHandler(hspi); - } -} - -/** - * @brief Interrupt Handler to receive amount of data in no-blocking mode - * @param hspi: pointer to a SPI_HandleTypeDef structure that contains - * the configuration information for SPI module. - * @retval void - */ -static void SPI_RxISR(SPI_HandleTypeDef *hspi) -{ - /* Receive data in 8 Bit mode */ - if(hspi->Init.DataSize == SPI_DATASIZE_8BIT) - { - (*hspi->pRxBuffPtr++) = hspi->Instance->DR; - } - /* Receive data in 16 Bit mode */ - else - { - *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; - hspi->pRxBuffPtr+=2U; - } - hspi->RxXferCount--; - - /* Enable CRC Transmission */ - if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) - { - /* Set CRC Next to calculate CRC on Rx side */ - SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); - } - - if(hspi->RxXferCount == 0U) - { - SPI_RxCloseIRQHandler(hspi); - } -} +// MBED commit 64a037cc /** * @brief DMA SPI transmit process complete callback @@ -2405,6 +2225,603 @@ static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(SPI_HandleTypeDef *hspi, uin * @} */ +/** + * @} + */ + +// MBED commit 64a037cc +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 8bit mode */ + *hspi->pRxBuffPtr++ = *((__IO uint8_t *)&hspi->Instance->DR); + hspi->RxXferCount--; + + /* check end of the reception */ + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if(hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t *)&hspi->Instance->DR); + + /* To avoid GCC warning */ + + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + if(hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + /* check the end of the transmission */ + if(hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if(hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +/** + * @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_2linesRxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + if(hspi->TxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + /* Receive data in 16 Bit mode */ + __IO uint16_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = hspi->Instance->DR; + + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE); + + SPI_CloseRxTx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + /* Enable CRC Transmission */ + if(hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + return; + } +#endif /* USE_SPI_CRC */ + + /* Disable TXE interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_TXE); + + if(hspi->RxXferCount == 0U) + { + SPI_CloseRxTx_ISR(hspi); + } + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 8-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint8_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = *((__IO uint8_t*)&hspi->Instance->DR); + + /* To avoid GCC warning */ + UNUSED(tmpreg); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the receive 8-bit in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *hspi->pRxBuffPtr++ = (*(__IO uint8_t *)&hspi->Instance->DR); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_8BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +#if (USE_SPI_CRC != 0U) +/** + * @brief Manage the CRC 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) +{ + __IO uint16_t tmpreg = 0U; + + /* Read data register to flush CRC */ + tmpreg = hspi->Instance->DR; + + /* To avoid GCC warning */ + UNUSED(tmpreg); + + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + SPI_CloseRx_ISR(hspi); +} +#endif /* USE_SPI_CRC */ + +/** + * @brief Manage the 16-bit receive in Interrupt context. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + *((uint16_t *)hspi->pRxBuffPtr) = hspi->Instance->DR; + hspi->pRxBuffPtr += sizeof(uint16_t); + hspi->RxXferCount--; + +#if (USE_SPI_CRC != 0U) + /* Enable CRC Transmission */ + if((hspi->RxXferCount == 1U) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE)) + { + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + + if(hspi->RxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + hspi->RxISR = SPI_RxISR_16BITCRC; + return; + } +#endif /* USE_SPI_CRC */ + SPI_CloseRx_ISR(hspi); + } +} + +/** + * @brief Handle the data 8-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) +{ + *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr++); + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle the data 16-bit transmit in Interrupt mode. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) +{ + /* Transmit data in 16 Bit mode */ + hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->pTxBuffPtr += sizeof(uint16_t); + hspi->TxXferCount--; + + if(hspi->TxXferCount == 0U) + { +#if (USE_SPI_CRC != 0U) + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + /* Enable CRC Transmission */ + SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT); + } +#endif /* USE_SPI_CRC */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE)); + SPI_CloseTx_ISR(hspi); + } +} + +/** + * @brief Handle SPI Communication Timeout. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Flag: SPI flag to check + * @param State: flag state to check + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart) +{ + while((hspi->Instance->SR & Flag) != State) + { + if(Timeout != HAL_MAX_DELAY) + { + if((Timeout == 0U) || ((HAL_GetTick()-Tickstart) >= Timeout)) + { + /* Disable the SPI and reset the CRC: the CRC value should be cleared + on both master and slave sides in order to resynchronize the master + and slave for their respective CRC calculation */ + + /* Disable TXE, RXNE and ERR interrupts for the interrupt process */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); + + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Reset CRC Calculation */ + if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLE) + { + SPI_RESET_CRC(hspi); + } + + hspi->State= HAL_SPI_STATE_READY; + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + + return HAL_TIMEOUT; + } + } + } + + return HAL_OK; +} + +/** + * @brief Handle to check BSY flag before start a new transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @param Timeout: Timeout duration + * @param Tickstart: tick start value + * @retval HAL status + */ +static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart) +{ + /* Control the BSY flag */ + if(SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, Timeout, Tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + return HAL_TIMEOUT; + } + return HAL_OK; +} + +/** + * @brief Handle the end of the RXTX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRxTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000); + /* Init tickstart for timeout managment*/ + tickstart = HAL_GetTick(); + + /* Disable ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, SPI_IT_ERR); + + /* Wait until TXE flag is set */ + do + { + if(count-- == 0) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + } + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Check the end of the transaction */ + if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart)!=HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + hspi->State = HAL_SPI_STATE_READY; + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { +#endif /* USE_SPI_CRC */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + if(hspi->State == HAL_SPI_STATE_BUSY_RX) + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_RxCpltCallback(hspi); + } + else + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_TxRxCpltCallback(hspi); + } + } + else + { + hspi->State = HAL_SPI_STATE_READY; + HAL_SPI_ErrorCallback(hspi); + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the RX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseRx_ISR(SPI_HandleTypeDef *hspi) +{ + /* Disable RXNE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); + + /* Check the end of the transaction */ + if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY))) + { + /* Disable SPI peripheral */ + __HAL_SPI_DISABLE(hspi); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + hspi->State = HAL_SPI_STATE_READY; + +#if (USE_SPI_CRC != 0U) + /* Check if CRC error occurred */ + if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); + __HAL_SPI_CLEAR_CRCERRFLAG(hspi); + HAL_SPI_ErrorCallback(hspi); + } + else + { +#endif /* USE_SPI_CRC */ + if(hspi->ErrorCode == HAL_SPI_ERROR_NONE) + { + HAL_SPI_RxCpltCallback(hspi); + } + else + { + HAL_SPI_ErrorCallback(hspi); + } +#if (USE_SPI_CRC != 0U) + } +#endif /* USE_SPI_CRC */ +} + +/** + * @brief Handle the end of the TX transaction. + * @param hspi: pointer to a SPI_HandleTypeDef structure that contains + * the configuration information for SPI module. + * @retval None + */ +static void SPI_CloseTx_ISR(SPI_HandleTypeDef *hspi) +{ + uint32_t tickstart = 0U; + __IO uint32_t count = SPI_DEFAULT_TIMEOUT * (SystemCoreClock / 24 / 1000); + + /* Init tickstart for timeout management*/ + tickstart = HAL_GetTick(); + + /* Wait until TXE flag is set */ + do + { + if(count-- == 0) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + break; + } + } + while((hspi->Instance->SR & SPI_FLAG_TXE) == RESET); + + /* Disable TXE and ERR interrupt */ + __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); + + /* Check Busy flag */ + if(SPI_CheckFlag_BSY(hspi, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + { + SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG); + } + + /* Clear overrun flag in 2 Lines communication mode because received is not read */ + if(hspi->Init.Direction == SPI_DIRECTION_2LINES) + { + __HAL_SPI_CLEAR_OVRFLAG(hspi); + } + + hspi->State = HAL_SPI_STATE_READY; + if(hspi->ErrorCode != HAL_SPI_ERROR_NONE) + { + HAL_SPI_ErrorCallback(hspi); + } + else + { + HAL_SPI_TxCpltCallback(hspi); + } +} + /** * @} */ diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tim.c b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tim.c index a431331ded..bf38663fc9 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tim.c +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tim.c @@ -394,11 +394,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat /* Check the parameters */ assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((pData == 0U ) && (Length > 0U)) { @@ -765,11 +765,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U ) && (Length > 0U)) { @@ -1243,11 +1243,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe /* Check the parameters */ assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if(((uint32_t)pData == 0U ) && (Length > 0U)) { @@ -1714,11 +1714,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((pData == 0U ) && (Length > 0U)) { @@ -2505,11 +2505,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch /* Check the parameters */ assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) { @@ -3227,11 +3227,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((BurstBuffer == 0U ) && (BurstLength > 0U)) { @@ -3429,11 +3429,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_LENGTH(BurstLength)); - if((htim->State == HAL_TIM_STATE_BUSY)) + if(htim->State == HAL_TIM_STATE_BUSY) { return HAL_BUSY; } - else if((htim->State == HAL_TIM_STATE_READY)) + else if(htim->State == HAL_TIM_STATE_READY) { if((BurstBuffer == 0U ) && (BurstLength > 0U)) { diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tsc.h b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tsc.h index cacef337c7..c27cd2ebab 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tsc.h +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_hal_tsc.h @@ -38,12 +38,11 @@ #ifndef __STM32L0xx_TSC_H #define __STM32L0xx_TSC_H +#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) + #ifdef __cplusplus extern "C" { #endif - -#if !defined (STM32L011xx) && !defined (STM32L021xx) && !defined (STM32L031xx) && !defined (STM32L041xx) && !defined (STM32L051xx) && !defined (STM32L061xx) && !defined (STM32L071xx) && !defined (STM32L081xx) - /* Includes ------------------------------------------------------------------*/ #include "stm32l0xx_hal_def.h" diff --git a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_ll_spi.h b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_ll_spi.h index f4c79a3fb6..19c9951bb7 100644 --- a/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_ll_spi.h +++ b/targets/TARGET_STM/TARGET_STM32L0/STM32Cube_FW/STM32L0xx_HAL_Driver/stm32l0xx_ll_spi.h @@ -1119,6 +1119,14 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) *((__IO uint8_t *)&SPIx->DR) = TxData; } +#if __GNUC__ +# define MAY_ALIAS __attribute__ ((__may_alias__)) +#else +# define MAY_ALIAS +#endif + +typedef __IO uint16_t MAY_ALIAS uint16_io_t; + /** * @brief Write 16-Bits in the data register * @rmtoll DR DR LL_SPI_TransmitData16 @@ -1128,7 +1136,7 @@ __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) */ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) { - *((__IO uint16_t *)&SPIx->DR) = TxData; + *((uint16_io_t*)&SPIx->DR) = TxData; } /**