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Merge branch 'master' of https://github.com/mbedmicro/mbed into dev_nucleo_f303k8 

Conflicts:
	workspace_tools/host_tests/host_test.py
pull/1346/head
dbestm 2015-09-28 14:23:53 +02:00
parent 0fb5d52a8c cc65d391ef
commit d7ab336a2b
514 changed files with 62791 additions and 29835 deletions
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2
README.md
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@ -68,6 +68,7 @@ STMicroelectronics:
* [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F)
* [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F)
* [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F)
* [Nucleo-L476RG](https://developer.mbed.org/platforms/ST-Nucleo-L476RG/) (Cortex-M4F)
* STM32F4XX (Cortex-M4F)
* STM32F3XX (Cortex-M4F)
* STM32F0-Discovery (Cortex-M0)
@ -76,6 +77,7 @@ STMicroelectronics:
* STM32F4-Discovery (Cortex-M4F)
* STM32F429-Discovery (Cortex-M4F)
* STM32L0-Discovery (Cortex-M0+)
* [STM32L4-Discovery](https://developer.mbed.org/platforms/ST-Discovery-L476VG/) (Cortex-M4F)
* [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F)

769
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h Normal file
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@ -0,0 +1,769 @@
/**************************************************************************//**
* @file CMSDK_BEID.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_BEID Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef CMSDK_BEID_H
#define CMSDK_BEID_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */
UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
#define __CM3_REV 0x0201 /* Core revision r2p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include <core_cm3.h> /* Processor and core peripherals */
#include "system_CMSDK_BEID.h" /* System Header */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef;
/* CMSDK_UART DATA Register Definitions */
#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
/*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
} CMSDK_TIMER_TypeDef;
/* CMSDK_TIMER CTRL Register Definitions */
#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
uint32_t RESERVED0;
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
uint32_t RESERVED1[945];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
/*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2];
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
};
uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
/*------------- System Control (SYSCON) --------------------------------------*/
typedef struct
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
uint32_t RESERVED0[3];
__IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
__IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
uint32_t RESERVED1[2];
__IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
__IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
uint32_t RESERVED2[2];
__IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
__IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
__IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
__IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
__IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
__IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
uint32_t RESERVED3[10];
__IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
__IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
__IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
__IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
__IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
__IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
uint32_t RESERVED4[2];
__IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
__IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
__IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
__IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
__IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
__IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
uint32_t RESERVED5[2];
__IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
__IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
__IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
__IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
__IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
__IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
__IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
__IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
__O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
__IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
uint32_t RESERVED6[2];
__IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
__IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
__I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
uint32_t RESERVED7[1];
__IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
__IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
__IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
} CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0
#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
/*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
uint32_t RESERVED0[3];
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef;
#define PL230_DMA_CHNL_BITS 0
#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
/*------------------- Watchdog ----------------------------------------------*/
typedef struct
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM )
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* Peripheral and SRAM base address */
#define CMSDK_FLASH_BASE (0x00000000UL)
#define CMSDK_SRAM_BASE (0x20000000UL)
#define CMSDK_PERIPH_BASE (0x40000000UL)
#define CMSDK_RAM_BASE (0x20000000UL)
#define CMSDK_APB_BASE (0x40000000UL)
#define CMSDK_AHB_BASE (0x40010000UL)
/* APB peripherals */
#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
/* ================================================================================ */
/* ================ Peripheral declaration ================ */
/* ================================================================================ */
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
#ifdef __cplusplus
}
#endif
#endif /* CMSDK_BEID_H */

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/*
* Copyright:
* ----------------------------------------------------------------
* This confidential and proprietary software may be used only as
* authorised by a licensing agreement from ARM Limited
* (C) COPYRIGHT 2014 ARM Limited
* ALL RIGHTS RESERVED
* The entire notice above must be reproduced on all authorised
* copies and copies may only be made to the extent permitted
* by a licensing agreement from ARM Limited.
* ----------------------------------------------------------------
* File: smm_mps2.h
* Release: Version 1.0
* ----------------------------------------------------------------
*/
#ifndef __SMM_MPS2_H
#define __SMM_MPS2_H
#include "peripherallink.h" /* device specific header file */
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
// [1:0] : LEDs
uint32_t RESERVED1[1];
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
// [31:2] : Reserved
// [1:0] : Buttons
uint32_t RESERVED2[1];
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
// Increments when 32-bit prescale counter reach zero
uint32_t RESERVED3[1];
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
// [3] : CLCD_RESET
// [2] : RESERVED
// [1] : SPI_nSS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef;
// MISC register bit definitions
#define CLCD_CS_Pos 0
#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
#define SPI_nSS_Pos 1
#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
#define CLCD_RESET_Pos 3
#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
#define CLCD_RS_Pos 4
#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
#define CLCD_RD_Pos 5
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
// [31:8] : Reserved
// [7:0] : MCC LEDs
uint32_t RESERVED0[1];
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
// [31:8] : Reserved
// [7:0] : These bits indicate state of the MCC switches
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
// [31:4] : Reserved
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
uint32_t RESERVED1[35];
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
// [31] : Start (generates interrupt on write to this bit)
// [30] : R/W access
// [29:26] : Reserved
// [25:20] : Function value
// [19:12] : Reserved
// [11:0] : Device (value of 0/1/2 for supported clocks)
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
// [31:2] : Reserved
// [1] : Error
// [0] : Complete
__IO uint32_t RESERVED2[20];
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [15:1] : Reserved
// [0] : This bit indicates if all enabled DLLs are locked
uint32_t RESERVED3[957];
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
// [31:24] : FPGA build number
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [19:11] : Reserved
// [10] : if “1” SCC_SW register has been implemented
// [9] : if “1” SCC_LED register has been implemented
// [8] : if “1” DLL lock register has been implemented
// [7:0] : number of SCC configuration register
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
// [31:24] : Implementer ID: 0x41 = ARM
// [23:20] : Application note IP variant number
// [19:16] : IP Architecture: 0x4 =AHB
// [15:4] : Primary part number: 386 = AN386
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef;
/******************************************************************************/
/* SSP Peripheral declaration */
/******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved
// [15:8] : Serial clock rate
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [5:4] : Frame format
// [3:0] : Data Size Select
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
// [31:4] : Reserved
// [3] : Slave-mode output disable
// [2] : Master or slave mode select
// [1] : Synchronous serial port enable
// [0] : Loop back mode
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
// [31:16] : Reserved
// [15:0] : Transmit/Receive FIFO
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
// [31:5] : Reserved
// [4] : PrimeCell SSP busy flag
// [3] : Receive FIFO full
// [2] : Receive FIFO not empty
// [1] : Transmit FIFO not full
// [0] : Transmit FIFO empty
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
// [31:8] : Reserved
// [8:0] : Clock prescale divisor
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
// [31:4] : Reserved
// [3] : Transmit FIFO interrupt mask
// [2] : Receive FIFO interrupt mask
// [1] : Receive timeout interrupt mask
// [0] : Receive overrun interrupt mask
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
// [31:4] : Reserved
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
// [31:4] : Reserved
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
// [31:2] : Reserved
// [1] : Clears the SSPRTINTR interrupt
// [0] : Clears the SSPRORINTR interrupt
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
// [31:2] : Reserved
// [1] : Transmit DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef;
// SSP_CR0 Control register 0
#define SSP_CR0_DSS_Pos 0 // Data Size Select
#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
#define SSP_CR0_FRF_Pos 4 // Frame Format Select
#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
// SSP_CR1 Control register 1
#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
#define SSP_CR1_SSE_Pos 1 // Serial port enable
#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
#define SSP_CR1_MS_Pos 2 // Master or Slave mode
#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
// SSP_SR Status register
#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
#define SSP_SR_RFF_Pos 3 // Receive FIFO full
#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
#define SSP_SR_BSY_Pos 4 // Busy
#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
// SSP_CPSR Clock prescale register
#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
// SSPRIS Raw interrupt status register
#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
// SSPMIS Masked interrupt status register
#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
// SSPICR Interrupt clear register
#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
// SSPDMACR DMA control register
#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
/******************************************************************************/
/* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
#define SCL 1 << 0
/******************************************************************************/
/* Audio I2S Peripheral declaration */
/******************************************************************************/
typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable
// <0=> TX disabled
// <1=> TX enabled
// <o.1> TX IRQ Enable
// <0=> TX IRQ disabled
// <1=> TX IRQ enabled
// <o.2> RX Enable
// <0=> RX disabled
// <1=> RX enabled
// <o.3> RX IRQ Enable
// <0=> RX IRQ disabled
// <1=> RX IRQ enabled
// <o.10..8> TX Buffer Water Level
// <0=> / IRQ triggers when any space available
// <1=> / IRQ triggers when more than 1 space available
// <2=> / IRQ triggers when more than 2 space available
// <3=> / IRQ triggers when more than 3 space available
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
// <2=> / IRQ triggers when less than 2 space available
// <3=> / IRQ triggers when less than 3 space available
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
// <o.17> Audio Codec reset
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
// <1=> TX buffer empty
// <o.3> TX Buffer Full
// <0=> TX buffer not full
// <1=> TX buffer full
// <o.4> RX Buffer Empty
// <0=> RX buffer have data
// <1=> RX buffer empty
// <o.5> RX Buffer Full
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN
// <0=> Normal operation
// <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT
// <o.1> SCLK
// <o.2> LRCK
// <o.3> IRQOUT
} MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0
#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
#define I2S_CONTROL_TXIRQEN_Pos 1
#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
#define I2S_CONTROL_RXEN_Pos 2
#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
#define I2S_CONTROL_RXIRQEN_Pos 3
#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
#define I2S_CONTROL_TXWLVL_Pos 8
#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
#define I2S_CONTROL_RXWLVL_Pos 12
#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
/* FIFO reset*/
#define I2S_CONTROL_FIFORST_Pos 16
#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
/* Codec reset*/
#define I2S_CONTROL_CODECRST_Pos 17
#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
#define I2S_STATUS_TXIRQ_Pos 0
#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
#define I2S_STATUS_RXIRQ_Pos 1
#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
#define I2S_STATUS_TXEmpty_Pos 2
#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
#define I2S_STATUS_TXFull_Pos 3
#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
#define I2S_STATUS_RXEmpty_Pos 4
#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
#define I2S_STATUS_RXFull_Pos 5
#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
#define I2S_ERROR_TXERR_Pos 0
#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
#define I2S_ERROR_RXERR_Pos 1
#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
/******************************************************************************/
/* SMSC9220 Register Definitions */
/******************************************************************************/
typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef;
// SMSC9220 MAC Registers Indices
#define SMSC9220_MAC_CR 0x1
#define SMSC9220_MAC_ADDRH 0x2
#define SMSC9220_MAC_ADDRL 0x3
#define SMSC9220_MAC_HASHH 0x4
#define SMSC9220_MAC_HASHL 0x5
#define SMSC9220_MAC_MII_ACC 0x6
#define SMSC9220_MAC_MII_DATA 0x7
#define SMSC9220_MAC_FLOW 0x8
#define SMSC9220_MAC_VLAN1 0x9
#define SMSC9220_MAC_VLAN2 0xA
#define SMSC9220_MAC_WUFF 0xB
#define SMSC9220_MAC_WUCSR 0xC
// SMSC9220 PHY Registers Indices
#define SMSC9220_PHY_BCONTROL 0x0
#define SMSC9220_PHY_BSTATUS 0x1
#define SMSC9220_PHY_ID1 0x2
#define SMSC9220_PHY_ID2 0x3
#define SMSC9220_PHY_ANEG_ADV 0x4
#define SMSC9220_PHY_ANEG_LPA 0x5
#define SMSC9220_PHY_ANEG_EXP 0x6
#define SMSC9220_PHY_MCONTROL 0x17
#define SMSC9220_PHY_MSTATUS 0x18
#define SMSC9220_PHY_CSINDICATE 0x27
#define SMSC9220_PHY_INTSRC 0x29
#define SMSC9220_PHY_INTMASK 0x30
#define SMSC9220_PHY_CS 0x31
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
#define MPS2_SSP0_BASE (0x40020000ul) /* User SSP Base Address */
#define MPS2_SSP1_BASE (0x40021000ul) /* CLCD SSP Base Address */
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Audio Interface I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Audio Interface I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
#else
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
//******************************************************************************/
/* General MACRO Definitions */
/******************************************************************************/
//#define DEBUG
//#ifdef DEBUG
// #define debug(...) printf(__VA_ARGS__)
//#else
// #define debug(...)
//#endif // ifdef DEBUG
// Bit control macros
//#define HW_REG(base,offset) *((volatile unsigned int *)((base) + (offset)))
#define CREATE_MASK(msb, lsb) (((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
#define MASK_BITS(arg, msb, lsb) ((arg) & CREATE_MASK(msb, lsb))
#define EXTRACT_BITS(arg, msb, lsb) (MASK_BITS(arg, msb, lsb) >> (lsb))
#define INSERT_BITS(arg, msb, lsb, value) \
((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb)))
#define MASK_FIELD(arg, field) MASK_BITS(arg, field##_MSB, field##_LSB)
#define EXTRACT_FIELD(arg, field) EXTRACT_BITS(arg, field##_MSB, field##_LSB)
#define INSERT_FIELD(arg, field, value) INSERT_BITS(arg, field##_MSB, field##_LSB, value)
#define SET_BIT(arg, bit) ((arg) |= (1 << (bit)))
#define CLEAR_BIT(arg, bit) ((arg) &= ~(1 << (bit)))
#define TEST_BIT(arg, bit) ((arg) & (1 << (bit)))
#ifndef NoOfElements
#define NoOfElements(array) (sizeof(array) / sizeof(array[0]))
#endif
#endif /* __SMM_MPS2_H */

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libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 +0 { ; load address = execution address
*.o (RESET, +FIRST)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 +0 { ; RW data
.ANY (+RW +ZI)
}
}

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;/**************************************************************************//**
; * @file startup_CMSDK_CM3.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM3 Device
; * @version V3.02
; * @date 15. November 2013
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2013 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UARTRX0_Handler [WEAK]
EXPORT UARTTX0_Handler [WEAK]
EXPORT UARTRX1_Handler [WEAK]
EXPORT UARTTX1_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
EXPORT PORT1_COMB_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
EXPORT SPI_Handler [WEAK]
EXPORT UARTOVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
EXPORT PORT0_3_Handler [WEAK]
EXPORT PORT0_4_Handler [WEAK]
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
UARTRX1_Handler
UARTTX1_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
SPI_Handler
UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC1768 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "CMSDK_BEID.h"
#include "SMM_MPS2.h"
#include "cmsis_nvic.h"
#endif

30
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/* mbed Microcontroller Library - cmsis_nvic for LCP1768
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

26
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h Normal file
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/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

34
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/*-----------------------------------------------------------------------------
* Name: Device.h
* Purpose: Include the correct device header file
*-----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* This software is supplied "AS IS" without warranties of any kind.
*
* Copyright (c) 2013 KEIL - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
#ifndef __DEVICE_H
#define __DEVICE_H
#if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */
#elif defined CMSDK_BEID
#include "CMSDK_BEID.h" /* device specific header file */
#else
#warning "no appropriate header file found!"
#endif
#endif /* __DEVICE_H */

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/**************************************************************************//**
* @file system_CMSDK_BEID.c
* @brief CMSIS Device System Source File for
* CMSDK_M3 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "CMSDK_BEID.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (50000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
// Enable AHB and APB clock
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO
CMSDK_SYSCON->APBCLKCFG0SET = 0x37; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER
}

75
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h Normal file
View File

@ -0,0 +1,75 @@
/**************************************************************************//**
* @file system_CMSDK_BEID.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_BEID Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_CMSDK_BEID_H
#define SYSTEM_CMSDK_BEID_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_BEID_H */

9
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld
View File

@ -3,8 +3,7 @@ OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
@ -13,8 +12,7 @@ MEMORY
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
SECTIONS {
.text :
{
. = ALIGN(4);
@ -82,7 +80,8 @@ SECTIONS
_edvectors = .;
} > ram
.relocate : AT (_etext)
.relocate :
AT (_etext)
{
. = ALIGN(4);
_srelocate = .;

9
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld
View File

@ -3,8 +3,7 @@ OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
@ -13,8 +12,7 @@ MEMORY
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
SECTIONS {
.text :
{
. = ALIGN(4);
@ -82,7 +80,8 @@ SECTIONS
_edvectors = .;
} > ram
.relocate : AT (_etext)
.relocate :
AT (_etext)
{
. = ALIGN(4);
_srelocate = .;

5
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c
View File

@ -42,7 +42,10 @@
#include "samr21.h"
typedef void (*intfunc) (void);
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
typedef union {
intfunc __fun;
void * __ptr;
} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -130,8 +129,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -127,8 +126,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -127,8 +126,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -125,8 +124,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -130,8 +129,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -127,8 +126,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -127,8 +126,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -125,8 +124,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -130,8 +129,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -130,8 +129,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -132,8 +131,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -129,8 +128,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -132,8 +131,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -129,8 +128,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -132,8 +131,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -134,8 +133,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -132,8 +131,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -134,8 +133,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -134,8 +133,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -134,8 +133,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -134,8 +133,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h
View File

@ -93,8 +93,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -134,8 +133,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e16a.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e17a.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21e18a.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g16a.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g17a.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/samr21g18a.h
View File

@ -90,8 +90,7 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
@ -131,8 +130,7 @@ typedef enum IRQn
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;

19
libraries/mbed/targets/cmsis/TARGET_NXP/TARGET_LPC176X/TOOLCHAIN_GCC_CR/LPC1768.ld
View File

@ -8,7 +8,8 @@ MEMORY
/* Define each memory region */
MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
RamAHB_USB (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x4000 /* 16k */
RamAHB_Eth (rwx) : ORIGIN = 0x20080000, LENGTH = 0x4000 /* 16k */
}
/* Define a symbol for the top of each memory region */
@ -110,11 +111,11 @@ SECTIONS
*(.data.$RAM2*)
*(.data.$RamAHB32*)
. = ALIGN(4) ;
} > RamAHB32 AT>MFlash512
} > RamAHB_USB AT>MFlash512
/* MAIN DATA SECTION */
.uninit_RESERVED : ALIGN(4)
.uninit_RESERVED(NOLOAD) : ALIGN(4)
{
KEEP(*(.bss.$RESERVED*))
} > RamLoc32
@ -130,15 +131,21 @@ SECTIONS
} > RamLoc32 AT>MFlash512
.bss_RAM2 : ALIGN(4)
.bss_RAM2(NOLOAD) : ALIGN(4)
{
*(.bss.$RAM2*)
*(.bss.$RamAHB32*)
*(AHBSRAM0)
. = ALIGN(4) ;
} > RamAHB32
} > RamAHB_USB
.bss_RAM3(NOLOAD) : ALIGN(4)
{
*(AHBSRAM1)
. = ALIGN(4) ;
} > RamAHB_Eth
/* MAIN BSS SECTION */
.bss : ALIGN(4)
.bss(NOLOAD) : ALIGN(4)
{
_bss = .;
*(.bss*)

6
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/pl310.c
View File

@ -1,8 +1,8 @@
/**************************************************************************//**
* @file pl310.c
* @brief Implementation of pl310 functions
* @brief Implementation of PL310 PrimeCell Level 2 Cache Controller functions
* @version
* @date 11 June 2013
* @date 3 December 2014
*
* @note
*
@ -80,7 +80,7 @@ void PL310_CleanInvAllByWay (void)
assoc = 8;
PL310->CLEAN_INV_WAY = (1 << assoc) - 1;
while(PL310->CLEAN_INV_WAY && ((1 << assoc) - 1)); //poll invalidate
while(PL310->CLEAN_INV_WAY & ((1 << assoc) - 1)); //poll invalidate
PL310_Sync();
}

167
libraries/mbed/targets/cmsis/TARGET_RENESAS/TARGET_RZ_A1H/system_MBRZA1H.c
View File

@ -1,14 +1,14 @@
/**************************************************************************//**
* @file system_MBRZA1H.c
* @brief CMSIS Device System Source File for
* ARMCA9 Device Series
* ARM Cortex-A9 Device Series
* @version V1.00
* @date 19 Sept 2013
* @date 09 January 2015
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
/* Copyright (c) 2011 - 2015 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
@ -50,9 +50,9 @@ void FPUEnable(void);
#endif
uint32_t IRQNestLevel;
unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
#if defined(__ARMCC_VERSION)
/**
* Initialize the cache.
*
@ -61,6 +61,7 @@ uint32_t IRQNestLevel;
*
* @brief Initialise caches. Requires PL1, so implemented as an SVC in case threads are USR mode.
*/
#if defined(__ARMCC_VERSION)
#pragma push
#pragma arm
@ -189,7 +190,7 @@ void SystemInit (void)
//Fault Status Register (IFSR/DFSR) definitions
#define FSR_ALIGNMENT_FAULT 0x01 //DFSR only. Fault on first lookup
#define FSR_INSTRUCTION_CACHE_MAINTAINANCE 0x04 //DFSR only - async/external
#define FSR_INSTRUCTION_CACHE_MAINTENANCE 0x04 //DFSR only - async/external
#define FSR_SYNC_EXT_TTB_WALK_FIRST 0x0c //sync/external
#define FSR_SYNC_EXT_TTB_WALK_SECOND 0x0e //sync/external
#define FSR_SYNC_PARITY_TTB_WALK_FIRST 0x1c //sync/external
@ -223,7 +224,7 @@ void CDAbtHandler(uint32_t DFSR, uint32_t DFAR, uint32_t LR) {
//Your code here. Value in DFAR is invalid for some fault statuses.
case FSR_ALIGNMENT_FAULT:
case FSR_INSTRUCTION_CACHE_MAINTAINANCE:
case FSR_INSTRUCTION_CACHE_MAINTENANCE:
case FSR_SYNC_EXT_TTB_WALK_FIRST:
case FSR_SYNC_EXT_TTB_WALK_SECOND:
case FSR_TRANSLATION_FAULT_FIRST:
@ -278,21 +279,36 @@ void CPAbtHandler(uint32_t IFSR, uint32_t IFAR, uint32_t LR) {
}
//returns amount to decrement lr by
//this will be 0 when we have emulated the instruction and simply want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in arm (state == 4)
//this will be 0 when we have emulated the instruction and want to execute the next instruction
//this will be 2 when we have performed some maintenance and want to retry the instruction in Thumb (state == 2)
//this will be 4 when we have performed some maintenance and want to retry the instruction in ARM (state == 4)
uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
const unsigned int THUMB = 2;
const unsigned int ARM = 4;
//Lazy VFP/NEON initialisation and switching
if ((state == ARM && ((opcode & 0x0C000000)) >> 26 == 0x03) ||
(state == THUMB && ((opcode & 0xEC000000)) >> 26 == 0x3B)) {
if (((opcode & 0x00000E00) >> 9) == 5) { //fp instruction?
// (ARM ARM section A7.5) VFP data processing instruction?
// (ARM ARM section A7.6) VFP/NEON register load/store instruction?
// (ARM ARM section A7.8) VFP/NEON register data transfer instruction?
// (ARM ARM section A7.9) VFP/NEON 64-bit register data transfer instruction?
if ((state == ARM && ((opcode & 0x0C000000) >> 26 == 0x03)) ||
(state == THUMB && ((opcode & 0xEC000000) >> 26 == 0x3B))) {
if (((opcode & 0x00000E00) >> 9) == 5) {
FPUEnable();
return state;
}
}
// (ARM ARM section A7.4) NEON data processing instruction?
if ((state == ARM && ((opcode & 0xFE000000) >> 24 == 0xF2)) ||
(state == THUMB && ((opcode & 0xEF000000) >> 24 == 0xEF)) ||
// (ARM ARM section A7.7) NEON load/store instruction?
(state == ARM && ((opcode >> 24) == 0xF4)) ||
(state == THUMB && ((opcode >> 24) == 0xF9))) {
FPUEnable();
return state;
}
//Add code here for other Undef cases
while(1);
}
@ -304,18 +320,22 @@ uint32_t CUndefHandler(uint32_t opcode, uint32_t state, uint32_t LR) {
__asm void FPUEnable(void) {
ARM
//Permit access to VFP registers by modifying CPACR
//Permit access to VFP/NEON, registers by modifying CPACR
MRC p15,0,R1,c1,c0,2
ORR R1,R1,#0x00F00000
MCR p15,0,R1,c1,c0,2
//Enable VFP
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
ISB
//Enable VFP/NEON
VMRS R1,FPEXC
ORR R1,R1,#0x40000000
VMSR FPEXC,R1
//Initialise VFP registers to 0
//Initialise VFP/NEON registers to 0
MOV R2,#0
//Initialise D16 registers to 0
VMOV D0, R2,R2
VMOV D1, R2,R2
VMOV D2, R2,R2
@ -332,7 +352,23 @@ __asm void FPUEnable(void) {
VMOV D13,R2,R2
VMOV D14,R2,R2
VMOV D15,R2,R2
//Initialise D32 registers to 0
VMOV D16,R2,R2
VMOV D17,R2,R2
VMOV D18,R2,R2
VMOV D19,R2,R2
VMOV D20,R2,R2
VMOV D21,R2,R2
VMOV D22,R2,R2
VMOV D23,R2,R2
VMOV D24,R2,R2
VMOV D25,R2,R2
VMOV D26,R2,R2
VMOV D27,R2,R2
VMOV D28,R2,R2
VMOV D29,R2,R2
VMOV D30,R2,R2
VMOV D31,R2,R2
//Initialise FPSCR to a known state
VMRS R2,FPSCR
LDR R3,=0x00086060 //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
@ -344,40 +380,71 @@ __asm void FPUEnable(void) {
#pragma pop
#elif defined(__GNUC__)
void FPUEnable(void)
{
__asm__ __volatile__ (
".align 2 \n\t"
".arm \n\t"
"mrc p15,0,r1,c1,c0,2 \n\t"
"orr r1,r1,#0x00f00000 \n\t"
"mcr p15,0,r1,c1,c0,2 \n\t"
"vmrs r1,fpexc \n\t"
"orr r1,r1,#0x40000000 \n\t"
"vmsr fpexc,r1 \n\t"
"mov r2,#0 \n\t"
"vmov d0, r2,r2 \n\t"
"vmov d1, r2,r2 \n\t"
"vmov d2, r2,r2 \n\t"
"vmov d3, r2,r2 \n\t"
"vmov d4, r2,r2 \n\t"
"vmov d5, r2,r2 \n\t"
"vmov d6, r2,r2 \n\t"
"vmov d7, r2,r2 \n\t"
"vmov d8, r2,r2 \n\t"
"vmov d9, r2,r2 \n\t"
"vmov d10,r2,r2 \n\t"
"vmov d11,r2,r2 \n\t"
"vmov d12,r2,r2 \n\t"
"vmov d13,r2,r2 \n\t"
"vmov d14,r2,r2 \n\t"
"vmov d15,r2,r2 \n\t"
"vmrs r2,fpscr \n\t"
"ldr r3,=0x00086060 \n\t"
"and r2,r2,r3 \n\t"
"vmsr fpscr,r2 \n\t"
"bx lr \n\t"
);
void FPUEnable(void) {
__asm__ (
".ARM;"
//Permit access to VFP/NEON, registers by modifying CPACR
"MRC p15,0,R1,c1,c0,2;"
"ORR R1,R1,#0x00F00000;"
"MCR p15,0,R1,c1,c0,2;"
//Ensure that subsequent instructions occur in the context of VFP/NEON access permitted
"ISB;"
//Enable VFP/NEON
"VMRS R1,FPEXC;"
"ORR R1,R1,#0x40000000;"
"VMSR FPEXC,R1;"
//Initialise VFP/NEON registers to 0
"MOV R2,#0;"
//Initialise D16 registers to 0
"VMOV D0, R2,R2;"
"VMOV D1, R2,R2;"
"VMOV D2, R2,R2;"
"VMOV D3, R2,R2;"
"VMOV D4, R2,R2;"
"VMOV D5, R2,R2;"
"VMOV D6, R2,R2;"
"VMOV D7, R2,R2;"
"VMOV D8, R2,R2;"
"VMOV D9, R2,R2;"
"VMOV D10,R2,R2;"
"VMOV D11,R2,R2;"
"VMOV D12,R2,R2;"
"VMOV D13,R2,R2;"
"VMOV D14,R2,R2;"
"VMOV D15,R2,R2;"
//Initialise D32 registers to 0
"VMOV D16,R2,R2;"
"VMOV D17,R2,R2;"
"VMOV D18,R2,R2;"
"VMOV D19,R2,R2;"
"VMOV D20,R2,R2;"
"VMOV D21,R2,R2;"
"VMOV D22,R2,R2;"
"VMOV D23,R2,R2;"
"VMOV D24,R2,R2;"
"VMOV D25,R2,R2;"
"VMOV D26,R2,R2;"
"VMOV D27,R2,R2;"
"VMOV D28,R2,R2;"
"VMOV D29,R2,R2;"
"VMOV D30,R2,R2;"
"VMOV D31,R2,R2;"
//Initialise FPSCR to a known state
"VMRS R2,FPSCR;"
"LDR R3,=0x00086060;" //Mask off all bits that do not have to be preserved. Non-preserved bits can/should be zero.
"AND R2,R2,R3;"
"VMSR FPSCR,R2;"
//"BX LR;"
:
:
:"r1", "r2", "r3");
return;
}
#else
#endif

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.c
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -33,10 +33,10 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
static unsigned char vtor_remap = 0; // To keep track that the vectors remap is done
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
// To keep track that the vectors remap is done
static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/cmsis_nvic.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

296
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f051x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f051x8.h
* @author MCD Application Team
* @version V2.1.0
* @date 03-Oct-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F051x4/STM32F051x6/STM32F051x8 devices Peripheral Access
* Layer Header File.
*
@ -15,7 +15,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -60,7 +60,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@ -290,8 +289,6 @@ typedef struct
__IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
__IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
__IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
__IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
__IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
}OB_TypeDef;
/**
@ -369,6 +366,7 @@ typedef struct
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@ -390,7 +388,6 @@ typedef struct
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@ -426,24 +423,15 @@ typedef struct
typedef struct
{
__IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
uint16_t RESERVED0; /*!< Reserved, 0x02 */
__IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
uint16_t RESERVED1; /*!< Reserved, 0x06 */
__IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
uint16_t RESERVED2; /*!< Reserved, 0x0A */
__IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
uint16_t RESERVED3; /*!< Reserved, 0x0E */
__IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
uint16_t RESERVED4; /*!< Reserved, 0x12 */
__IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
uint16_t RESERVED5; /*!< Reserved, 0x16 */
__IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
uint16_t RESERVED6; /*!< Reserved, 0x1A */
__IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
uint16_t RESERVED7; /*!< Reserved, 0x1E */
__IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
uint16_t RESERVED8; /*!< Reserved, 0x22 */
__IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
__IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
__IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
__IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
__IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
__IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
__IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
__IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
__IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
}SPI_TypeDef;
/**
@ -535,6 +523,7 @@ typedef struct
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@ -556,6 +545,7 @@ typedef struct
#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
@ -642,7 +632,6 @@ typedef struct
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
/**
* @}
*/
@ -782,7 +771,6 @@ typedef struct
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
/******************************************************************************/
/* */
/* HDMI-CEC (CEC) */
@ -841,7 +829,6 @@ typedef struct
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
@ -889,24 +876,24 @@ typedef struct
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@ -929,7 +916,6 @@ typedef struct
/******************* Bit definition for CRC_INIT register *******************/
#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
/******************************************************************************/
/* */
/* Digital to Analog Converter (DAC) */
@ -1266,8 +1252,8 @@ typedef struct
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@ -1302,12 +1288,13 @@ typedef struct
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@ -2181,16 +2168,6 @@ typedef struct
#define RCC_CFGR3_CECSW_HSI_DIV244 ((uint32_t)0x00000000) /*!< HSI clock divided by 244 selected as HDMI CEC entry clock source */
#define RCC_CFGR3_CECSW_LSE ((uint32_t)0x00000040) /*!< LSE clock selected as HDMI CEC entry clock source */
/*!< USART2 Clock source selection */
#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
/******************* Bit definition for RCC_CR2 register *******************/
#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
@ -2566,6 +2543,7 @@ typedef struct
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
@ -2578,173 +2556,174 @@ typedef struct
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@ -3503,7 +3482,9 @@ typedef struct
((INSTANCE) == GPIOD) || \
((INSTANCE) == GPIOF))
/****************************** GPIO Lock Instances ****************************/
#define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB))
#define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
((INSTANCE) == GPIOB))
@ -3767,7 +3748,6 @@ typedef struct
/****************** UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)

34
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.1.0
* @date 03-Oct-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,16 +64,23 @@
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F0)
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
!defined (STM32F031x6) && !defined (STM32F038xx) && \
!defined (STM32F042x6) && !defined (STM32F048xx) && \
!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
!defined (STM32F051x8) && !defined (STM32F058xx) && \
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && \
!defined (STM32F091xC) && !defined (STM32F098xx)
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F031x6 */ /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
@ -82,9 +89,12 @@
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
#define STM32F051x8 /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
#endif
@ -102,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.1.0
* @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
@ -137,6 +147,10 @@
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
@ -147,6 +161,8 @@
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif

69
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.1.0
* @date 03-Oct-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -107,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/**
* @}
*/
@ -135,6 +136,7 @@
updated automatically.
*/
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
@ -191,15 +193,31 @@ void SystemInit(void)
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
#if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xB)
/* Reset USART2SW[1:0] USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FFAC;
#else
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
#elif defined (STM32F051x8) || defined (STM32F058xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
#elif defined (STM32F042x6) || defined (STM32F048xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
#elif defined (STM32F070x6) || defined (STM32F070xB)
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
/* Set default USB clock to PLLCLK, since there is no HSI48 */
RCC->CFGR3 |= (uint32_t)0x00000080;
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
@ -207,14 +225,6 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the Cube driver */
SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
HAL_Init();
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
}
/**
@ -289,13 +299,17 @@ void SystemCoreClockUpdate (void)
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
default: /* HSI used as system clock */
@ -350,17 +364,24 @@ void SetSysClock(void)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
//Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
// Select HSE oscillator as PLL source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
RCC_OscInitStruct.HSI48State = 0; // not used
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
@ -378,6 +399,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
return 0; // FAIL
}
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
return 1; // OK
}
#endif
@ -410,6 +433,8 @@ uint8_t SetSysClock_PLL_HSI(void)
return 0; // FAIL
}
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
return 1; // OK
}

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/system_stm32f0xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.1.0
* @date 03-Oct-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

47
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/TOOLCHAIN_IAR/stm32f030x8.icf
View File

@ -1,31 +1,34 @@
/* [ROM = 64kb = 0x10000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_end__ = 0x0800FFFF;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0800FFFF;
/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 45 vectors = 180 bytes (0xB4) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
define symbol __NVIC_end__ = 0x200000B7; /* Add 4 more bytes to be aligned on 8 bytes */
define symbol __region_RAM_start__ = 0x200000B8;
define symbol __region_RAM_end__ = 0x20001FFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000B8; /* Add 4 more bytes after NVIC section to be aligned on 8 bytes */
define symbol __ICFEDIT_region_RAM_end__ = 0x20001FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x800;
/**** End of ICF editor section. ###ICF###*/
/* Memory regions */
define memory mem with size = 4G;
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x400;
define symbol __size_heap__ = 0x800;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing = zeros { readwrite };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__intvec_start__ { readonly section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, block STACKHEAP };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

230
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f030x8.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f030x8.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
*
* This file contains:
@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@ -242,8 +241,6 @@ typedef struct
__IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
__IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
__IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
__IO uint16_t WRP2; /*!< FLASH option byte write protection 2, Address offset: 0x0C */
__IO uint16_t WRP3; /*!< FLASH option byte write protection 3, Address offset: 0x0E */
}OB_TypeDef;
/**
@ -321,6 +318,7 @@ typedef struct
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@ -342,7 +340,6 @@ typedef struct
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@ -410,7 +407,6 @@ typedef struct
__IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
}TIM_TypeDef;
/**
* @brief Universal Synchronous Asynchronous Receiver Transmitter
*/
@ -451,6 +447,7 @@ typedef struct
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@ -545,7 +542,6 @@ typedef struct
#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
/**
* @}
*/
@ -681,7 +677,6 @@ typedef struct
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
@ -994,8 +989,8 @@ typedef struct
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@ -1030,12 +1025,13 @@ typedef struct
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@ -1560,6 +1556,7 @@ typedef struct
/******************* Bit definition for PWR_CSR register *******************/
#define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
#define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
#define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
#define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
@ -1873,16 +1870,6 @@ typedef struct
#define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
#define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
/*!< USART2 Clock source selection */
#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
#define RCC_CFGR3_USART2SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_SYSCLK ((uint32_t)0x00010000) /*!< System clock selected as USART2 clock source */
#define RCC_CFGR3_USART2SW_LSE ((uint32_t)0x00020000) /*!< LSE oscillator clock used as USART2 clock source */
#define RCC_CFGR3_USART2SW_HSI ((uint32_t)0x00030000) /*!< HSI oscillator clock used as USART2 clock source */
/******************* Bit definition for RCC_CR2 register *******************/
#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
@ -2240,6 +2227,7 @@ typedef struct
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
@ -2252,173 +2240,174 @@ typedef struct
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@ -2724,7 +2713,6 @@ typedef struct
#define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
#define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
/******************************************************************************/
/* */
/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
@ -2958,6 +2946,7 @@ typedef struct
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@ -3168,7 +3157,6 @@ typedef struct
/****************** UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/****************************** WWDG Instances ********************************/
#define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)

17
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,6 +64,13 @@
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F0)
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.0
* @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\

44
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -107,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/**
* @}
*/
@ -192,7 +193,7 @@ void SystemInit(void)
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
#if defined (STM32F072xB) || defined (STM32F078xB)
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@ -224,14 +225,6 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the Cube driver */
SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
HAL_Init();
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
}
/**
@ -306,9 +299,9 @@ void SystemCoreClockUpdate (void)
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@ -362,7 +355,7 @@ void SetSysClock(void)
}
// Output clock on MCO pin(PA8) for debugging purpose
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_NODIV); // 48 MHz
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
@ -371,17 +364,24 @@ void SetSysClock(void)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
//Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
// Select HSE oscillator as PLL source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
RCC_OscInitStruct.HSI48State = 0; // not used
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
@ -399,6 +399,8 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
return 0; // FAIL
}
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
return 1; // OK
}
#endif
@ -431,6 +433,8 @@ uint8_t SetSysClock_PLL_HSI(void)
return 0; // FAIL
}
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
return 1; // OK
}

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F030R8/system_stm32f0xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

226
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s Normal file
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@ -0,0 +1,226 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f031x6.s
;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
EXPORT __initial_sp
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20001000 ; Top of RAM
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
EXPORT __heap_base
EXPORT __heap_limit
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit EQU (__initial_sp - Stack_Size)
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

45
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/stm32f0xx.sct Normal file
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@ -0,0 +1,45 @@
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2014, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of STMicroelectronics nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; 32KB FLASH (0x8000) + 4KB RAM (0x1000)
LR_IROM1 0x08000000 0x8000 { ; load region size_region
ER_IROM1 0x08000000 0x8000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 44 vectors = 176 bytes (0xB0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xB0) (0x1000-0xB0) { ; RW data
.ANY (+RW +ZI)
}
}

56
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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@ -0,0 +1,56 @@
/* mbed Microcontroller Library - stackheap
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

199
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s Normal file
View File

@ -0,0 +1,199 @@
;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f031x6.s
;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == Reset_Handler
;* - Set the vector table entries with the exceptions ISR address
;* - Branches to __main in the C library (which eventually
;* calls main()).
;* After Reset the CortexM0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;* <<< Use Configuration Wizard in Context Menu >>>
;*******************************************************************************
;
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;
;*******************************************************************************
__initial_sp EQU 0x20001000 ; Top of RAM
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset handler routine
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT WWDG_IRQHandler [WEAK]
EXPORT PVD_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT RCC_IRQHandler [WEAK]
EXPORT EXTI0_1_IRQHandler [WEAK]
EXPORT EXTI2_3_IRQHandler [WEAK]
EXPORT EXTI4_15_IRQHandler [WEAK]
EXPORT DMA1_Channel1_IRQHandler [WEAK]
EXPORT DMA1_Channel2_3_IRQHandler [WEAK]
EXPORT DMA1_Channel4_5_IRQHandler [WEAK]
EXPORT ADC1_IRQHandler [WEAK]
EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK]
EXPORT TIM1_CC_IRQHandler [WEAK]
EXPORT TIM2_IRQHandler [WEAK]
EXPORT TIM3_IRQHandler [WEAK]
EXPORT TIM14_IRQHandler [WEAK]
EXPORT TIM16_IRQHandler [WEAK]
EXPORT TIM17_IRQHandler [WEAK]
EXPORT I2C1_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT USART1_IRQHandler [WEAK]
WWDG_IRQHandler
PVD_IRQHandler
RTC_IRQHandler
FLASH_IRQHandler
RCC_IRQHandler
EXTI0_1_IRQHandler
EXTI2_3_IRQHandler
EXTI4_15_IRQHandler
DMA1_Channel1_IRQHandler
DMA1_Channel2_3_IRQHandler
DMA1_Channel4_5_IRQHandler
ADC1_IRQHandler
TIM1_BRK_UP_TRG_COM_IRQHandler
TIM1_CC_IRQHandler
TIM2_IRQHandler
TIM3_IRQHandler
TIM14_IRQHandler
TIM16_IRQHandler
TIM17_IRQHandler
I2C1_IRQHandler
SPI1_IRQHandler
USART1_IRQHandler
B .
ENDP
ALIGN
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

45
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@ -0,0 +1,45 @@
; Scatter-Loading Description File
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; Copyright (c) 2014, STMicroelectronics
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
;
; 1. Redistributions of source code must retain the above copyright notice,
; this list of conditions and the following disclaimer.
; 2. Redistributions in binary form must reproduce the above copyright notice,
; this list of conditions and the following disclaimer in the documentation
; and/or other materials provided with the distribution.
; 3. Neither the name of STMicroelectronics nor the names of its contributors
; may be used to endorse or promote products derived from this software
; without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; 32KB FLASH (0x8000) + 4KB RAM (0x1000)
LR_IROM1 0x08000000 0x8000 { ; load region size_region
ER_IROM1 0x08000000 0x8000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; 44 vectors = 176 bytes (0xB0) to be reserved in RAM
RW_IRAM1 (0x20000000+0xB0) (0x1000-0xB0) { ; RW data
.ANY (+RW +ZI)
}
}

56
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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/* mbed Microcontroller Library - stackheap
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

153
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/STM32F031X6.ld Normal file
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/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 32k
RAM (xrw) : ORIGIN = 0x200000B0, LENGTH = 4k - 0x0B0
}
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
* _estack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
_sidata = .;
.data : AT (__etext)
{
__data_start__ = .;
_sdata = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
_edata = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
_sbss = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
_ebss = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

279
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s Normal file
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/**
******************************************************************************
* @file startup_stm32f031x6.s
* @author MCD Application Team
* @version V2.2.2
* @date 26-June-2015
* @brief STM32F031x4/STM32F031x6 devices vector table for Atollic TrueSTUDIO toolchain.
* This module performs:
* - Set the initial SP
* - Set the initial PC == Reset_Handler,
* - Set the vector table entries with the exceptions ISR address
* - Branches to main in the C library (which eventually
* calls main()).
* After Reset the Cortex-M0 processor is in Thread mode,
* priority is Privileged, and the Stack is set to Main.
******************************************************************************
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
.syntax unified
.cpu cortex-m0
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
ldr r0, =_estack
mov sp, r0 /* set stack pointer */
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2]
adds r2, r2, #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the clock system intitialization function.*/
bl SystemInit
/* Call static constructors */
bl __libc_init_array
/* Call the application's entry point.*/
// bl main
bl _start
LoopForever:
b LoopForever
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M0. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word 0
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler /* Window WatchDog */
.word PVD_IRQHandler /* PVD through EXTI Line detect */
.word RTC_IRQHandler /* RTC through the EXTI line */
.word FLASH_IRQHandler /* FLASH */
.word RCC_IRQHandler /* RCC */
.word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */
.word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */
.word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */
.word 0 /* Reserved */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */
.word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */
.word ADC1_IRQHandler /* ADC1 */
.word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word TIM14_IRQHandler /* TIM14 */
.word 0 /* Reserved */
.word TIM16_IRQHandler /* TIM16 */
.word TIM17_IRQHandler /* TIM17 */
.word I2C1_IRQHandler /* I2C1 */
.word 0 /* Reserved */
.word SPI1_IRQHandler /* SPI1 */
.word 0 /* Reserved */
.word USART1_IRQHandler /* USART1 */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
.word 0 /* Reserved */
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak WWDG_IRQHandler
.thumb_set WWDG_IRQHandler,Default_Handler
.weak PVD_IRQHandler
.thumb_set PVD_IRQHandler,Default_Handler
.weak RTC_IRQHandler
.thumb_set RTC_IRQHandler,Default_Handler
.weak FLASH_IRQHandler
.thumb_set FLASH_IRQHandler,Default_Handler
.weak RCC_IRQHandler
.thumb_set RCC_IRQHandler,Default_Handler
.weak EXTI0_1_IRQHandler
.thumb_set EXTI0_1_IRQHandler,Default_Handler
.weak EXTI2_3_IRQHandler
.thumb_set EXTI2_3_IRQHandler,Default_Handler
.weak EXTI4_15_IRQHandler
.thumb_set EXTI4_15_IRQHandler,Default_Handler
.weak DMA1_Channel1_IRQHandler
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
.weak DMA1_Channel2_3_IRQHandler
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
.weak DMA1_Channel4_5_IRQHandler
.thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
.weak TIM1_CC_IRQHandler
.thumb_set TIM1_CC_IRQHandler,Default_Handler
.weak TIM2_IRQHandler
.thumb_set TIM2_IRQHandler,Default_Handler
.weak TIM3_IRQHandler
.thumb_set TIM3_IRQHandler,Default_Handler
.weak TIM14_IRQHandler
.thumb_set TIM14_IRQHandler,Default_Handler
.weak TIM16_IRQHandler
.thumb_set TIM16_IRQHandler,Default_Handler
.weak TIM17_IRQHandler
.thumb_set TIM17_IRQHandler,Default_Handler
.weak I2C1_IRQHandler
.thumb_set I2C1_IRQHandler,Default_Handler
.weak SPI1_IRQHandler
.thumb_set SPI1_IRQHandler,Default_Handler
.weak USART1_IRQHandler
.thumb_set USART1_IRQHandler,Default_Handler
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

272
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;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
;* File Name : startup_stm32f031x6.s
;* Author : MCD Application Team
;* Version : V2.2.2
;* Date : 26-June-2015
;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
;* - Set the initial PC == __iar_program_start,
;* - Set the vector table entries with the exceptions ISR
;* address,
;* - Branches to main in the C library (which eventually
;* calls main()).
;* After Reset the Cortex-M0 processor is in Thread mode,
;* priority is Privileged, and the Stack is set to Main.
;*******************************************************************************
;*
;* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
;*
;* Redistribution and use in source and binary forms, with or without modification,
;* are permitted provided that the following conditions are met:
;* 1. Redistributions of source code must retain the above copyright notice,
;* this list of conditions and the following disclaimer.
;* 2. Redistributions in binary form must reproduce the above copyright notice,
;* this list of conditions and the following disclaimer in the documentation
;* and/or other materials provided with the distribution.
;* 3. Neither the name of STMicroelectronics nor the names of its contributors
;* may be used to endorse or promote products derived from this software
;* without specific prior written permission.
;*
;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*
;*******************************************************************************
;
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; The vector table is normally located at address 0.
; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
; The name "__vector_table" has special meaning for C-SPY:
; it is where the SP start value is found, and the NVIC vector
; table register (VTOR) is initialized to this address if != 0.
;
; Cortex-M version
;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION CSTACK:DATA:NOROOT(3)
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
EXTERN SystemInit
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD WWDG_IRQHandler ; Window Watchdog
DCD PVD_IRQHandler ; PVD through EXTI Line detect
DCD RTC_IRQHandler ; RTC through EXTI Line
DCD FLASH_IRQHandler ; FLASH
DCD RCC_IRQHandler ; RCC
DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1
DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3
DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15
DCD 0 ; Reserved
DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3
DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5
DCD ADC1_IRQHandler ; ADC1
DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation
DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
DCD TIM2_IRQHandler ; TIM2
DCD TIM3_IRQHandler ; TIM3
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD TIM14_IRQHandler ; TIM14
DCD 0 ; Reserved
DCD TIM16_IRQHandler ; TIM16
DCD TIM17_IRQHandler ; TIM17
DCD I2C1_IRQHandler ; I2C1
DCD 0 ; Reserved
DCD SPI1_IRQHandler ; SPI1
DCD 0 ; Reserved
DCD USART1_IRQHandler ; USART1
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK Reset_Handler
SECTION .text:CODE:NOROOT:REORDER(2)
Reset_Handler
LDR R0, =SystemInit
BLX R0
LDR R0, =__iar_program_start
BX R0
PUBWEAK NMI_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:NOROOT:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK RTC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RTC_IRQHandler
B RTC_IRQHandler
PUBWEAK FLASH_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI0_1_IRQHandler
B EXTI0_1_IRQHandler
PUBWEAK EXTI2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI2_3_IRQHandler
B EXTI2_3_IRQHandler
PUBWEAK EXTI4_15_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
EXTI4_15_IRQHandler
B EXTI4_15_IRQHandler
PUBWEAK DMA1_Channel1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel1_IRQHandler
B DMA1_Channel1_IRQHandler
PUBWEAK DMA1_Channel2_3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel2_3_IRQHandler
B DMA1_Channel2_3_IRQHandler
PUBWEAK DMA1_Channel4_5_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
DMA1_Channel4_5_IRQHandler
B DMA1_Channel4_5_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_BRK_UP_TRG_COM_IRQHandler
B TIM1_BRK_UP_TRG_COM_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM14_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM14_IRQHandler
B TIM14_IRQHandler
PUBWEAK TIM16_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM16_IRQHandler
B TIM16_IRQHandler
PUBWEAK TIM17_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
TIM17_IRQHandler
B TIM17_IRQHandler
PUBWEAK I2C1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
I2C1_IRQHandler
B I2C1_IRQHandler
PUBWEAK SPI1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK USART1_IRQHandler
SECTION .text:CODE:NOROOT:REORDER(1)
USART1_IRQHandler
B USART1_IRQHandler
END
;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

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/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x08007FFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000B0;
define symbol __ICFEDIT_region_RAM_end__ = 0x20000FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x400;
define symbol __ICFEDIT_size_heap__ = 0x200;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "stm32f0xx.h"
#include "cmsis_nvic.h"
#endif

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
// To keep track that the vectors remap is done
static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
vtor_remap = 1; // The vectors remap is done
}
// Set the vector
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];
}

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
// STM32F031K6
// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
// MCU Peripherals: 28 vectors = 112 bytes from 0x40 to 0xAF
// Total: 44 vectors = 176 bytes (0xB0) to be reserved in RAM
#define NVIC_NUM_VECTORS 44
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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/**
******************************************************************************
* @file hal_tick.c
* @author MCD Application Team
* @brief Initialization of HAL tick
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "hal_tick.h"
TIM_HandleTypeDef TimMasterHandle;
uint32_t PreviousVal = 0;
void us_ticker_irq_handler(void);
void timer_irq_handler(void) {
// Channel 1 for mbed timeout
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
us_ticker_irq_handler();
}
// Channel 2 for HAL tick
if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
__HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
if ((val - PreviousVal) >= HAL_TICK_DELAY) {
// Increment HAL variable
HAL_IncTick();
// Prepare next interrupt
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
PreviousVal = val;
#if 0 // For DEBUG only
HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
#endif
}
}
}
// Reconfigure the HAL tick using a standard timer instead of systick.
HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
// Enable timer clock
TIM_MST_RCC;
// Reset timer
TIM_MST_RESET_ON;
TIM_MST_RESET_OFF;
// Update the SystemCoreClock variable
SystemCoreClockUpdate();
// Configure time base
TimMasterHandle.Instance = TIM_MST;
TimMasterHandle.Init.Period = 0xFFFFFFFF;
TimMasterHandle.Init.Prescaler = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 µs tick
TimMasterHandle.Init.ClockDivision = 0;
TimMasterHandle.Init.CounterMode = TIM_COUNTERMODE_UP;
TimMasterHandle.Init.RepetitionCounter = 0;
HAL_TIM_OC_Init(&TimMasterHandle);
NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
NVIC_EnableIRQ(TIM_MST_IRQ);
// Channel 1 for mbed timeout
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
// Channel 2 for HAL tick
HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
__HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
__HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
#if 0 // For DEBUG only
__GPIOB_CLK_ENABLE();
GPIO_InitTypeDef GPIO_InitStruct;
GPIO_InitStruct.Pin = GPIO_PIN_6;
GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
GPIO_InitStruct.Pull = GPIO_PULLUP;
GPIO_InitStruct.Speed = GPIO_SPEED_FAST;
HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
#endif
return HAL_OK;
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file hal_tick.h
* @author MCD Application Team
* @brief Initialization of HAL tick
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __HAL_TICK_H
#define __HAL_TICK_H
#ifdef __cplusplus
extern "C" {
#endif
#include "stm32f0xx.h"
#include "cmsis_nvic.h"
#define TIM_MST TIM2
#define TIM_MST_IRQ TIM2_IRQn
#define TIM_MST_RCC __TIM2_CLK_ENABLE()
#define TIM_MST_RESET_ON __TIM2_FORCE_RESET()
#define TIM_MST_RESET_OFF __TIM2_RELEASE_RESET()
#define HAL_TICK_DELAY (1000) // 1 ms
#ifdef __cplusplus
}
#endif
#endif // __HAL_TICK_H
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F0xx device used in the target application
* - To use or not the peripheral’s drivers in application code(i.e.
* code will be based on direct access to peripheral’s registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx
* @{
*/
#ifndef __STM32F0xx_H
#define __STM32F0xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
/** @addtogroup Library_configuration_section
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F0)
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
#if !defined (STM32F030x6) && !defined (STM32F030x8) && \
!defined (STM32F031x6) && !defined (STM32F038xx) && \
!defined (STM32F042x6) && !defined (STM32F048xx) && !defined (STM32F070x6) && \
!defined (STM32F051x8) && !defined (STM32F058xx) && \
!defined (STM32F071xB) && !defined (STM32F072xB) && !defined (STM32F078xx) && !defined (STM32F070xB) && \
!defined (STM32F091xC) && !defined (STM32F098xx) && !defined (STM32F030xC)
/* #define STM32F030x6 */ /*!< STM32F030x4, STM32F030x6 Devices (STM32F030xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F030x8 */ /*!< STM32F030x8 Devices (STM32F030xx microcontrollers where the Flash memory is 64 Kbytes) */
#define STM32F031x6 /*!< STM32F031x4, STM32F031x6 Devices (STM32F031xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F038xx */ /*!< STM32F038xx Devices (STM32F038xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F042x6 */ /*!< STM32F042x4, STM32F042x6 Devices (STM32F042xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F048x6 */ /*!< STM32F048xx Devices (STM32F042xx microcontrollers where the Flash memory is 32 Kbytes) */
/* #define STM32F051x8 */ /*!< STM32F051x4, STM32F051x6, STM32F051x8 Devices (STM32F051xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes) */
/* #define STM32F058xx */ /*!< STM32F058xx Devices (STM32F058xx microcontrollers where the Flash memory is 64 Kbytes) */
/* #define STM32F070x6 */ /*!< STM32F070x6 Devices (STM32F070x6 microcontrollers where the Flash memory ranges between 16 and 32 Kbytes) */
/* #define STM32F070xB */ /*!< STM32F070xB Devices (STM32F070xB microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F071xB */ /*!< STM32F071x8, STM32F071xB Devices (STM32F071xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F072xB */ /*!< STM32F072x8, STM32F072xB Devices (STM32F072xx microcontrollers where the Flash memory ranges between 64 and 128 Kbytes) */
/* #define STM32F078xx */ /*!< STM32F078xx Devices (STM32F078xx microcontrollers where the Flash memory is 128 Kbytes) */
/* #define STM32F030xC */ /*!< STM32F030xC Devices (STM32F030xC microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F091xC */ /*!< STM32F091xC Devices (STM32F091xx microcontrollers where the Flash memory is 256 Kbytes) */
/* #define STM32F098xx */ /*!< STM32F098xx Devices (STM32F098xx microcontrollers where the Flash memory is 256 Kbytes) */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
|(__CMSIS_DEVICE_HAL_VERSION_RC))
/**
* @}
*/
/** @addtogroup Device_Included
* @{
*/
#if defined(STM32F030x6)
#include "stm32f030x6.h"
#elif defined(STM32F030x8)
#include "stm32f030x8.h"
#elif defined(STM32F031x6)
#include "stm32f031x6.h"
#elif defined(STM32F038xx)
#include "stm32f038xx.h"
#elif defined(STM32F042x6)
#include "stm32f042x6.h"
#elif defined(STM32F048xx)
#include "stm32f048xx.h"
#elif defined(STM32F051x8)
#include "stm32f051x8.h"
#elif defined(STM32F058xx)
#include "stm32f058xx.h"
#elif defined(STM32F070x6)
#include "stm32f070x6.h"
#elif defined(STM32F070xB)
#include "stm32f070xb.h"
#elif defined(STM32F071xB)
#include "stm32f071xb.h"
#elif defined(STM32F072xB)
#include "stm32f072xb.h"
#elif defined(STM32F078xx)
#include "stm32f078xx.h"
#elif defined(STM32F091xC)
#include "stm32f091xc.h"
#elif defined(STM32F098xx)
#include "stm32f098xx.h"
#elif defined(STM32F030xC)
#include "stm32f030xc.h"
#else
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
/**
* @}
*/
/** @addtogroup Exported_types
* @{
*/
typedef enum
{
RESET = 0,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
DISABLE = 0,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
ERROR = 0,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
/** @addtogroup Exported_macros
* @{
*/
#define SET_BIT(REG, BIT) ((REG) |= (BIT))
#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
#define READ_BIT(REG, BIT) ((REG) & (BIT))
#define CLEAR_REG(REG) ((REG) = (0x0))
#define WRITE_REG(REG, VAL) ((REG) = (VAL))
#define READ_REG(REG) ((REG))
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
/**
* @}
*/
#if defined (USE_HAL_DRIVER)
#include "stm32f0xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
}
#endif /* __cplusplus */
#endif /* __STM32F0xx_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
* user application:
* - SystemInit(): This function is called at startup just after reset and
* before branch to main program. This call is made inside
* the "startup_stm32f0xx.s" file.
*
* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
* by the user application to setup the SysTick
* timer or configure other parameters.
*
* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
* be called whenever the core clock is changed
* during program execution.
*
* 2. After each device reset the HSI (8 MHz) is used as system clock source.
* Then SystemInit() function is called, in "startup_stm32f0xx.s" file, to
* configure the system clock before to branch to main program.
*
* 3. This file configures the system clock as follows:
*=============================================================================
* System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
* | (external 8 MHz clock) | (internal 48 MHz)
* | 2- PLL_HSE_XTAL |
* | (external 8 MHz xtal) |
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 48 | 48
*-----------------------------------------------------------------------------
* AHBCLK (MHz) | 48 | 48
*-----------------------------------------------------------------------------
* APB1CLK (MHz) | 48 | 48
*-----------------------------------------------------------------------------
* USB capable (48 MHz precise clock) | YES | YES
*=============================================================================
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx_system
* @{
*/
/** @addtogroup STM32F0xx_System_Private_Includes
* @{
*/
#include "stm32f0xx.h"
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_TypesDefinitions
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Defines
* @{
*/
#if !defined (HSE_VALUE)
#define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSE_VALUE */
#if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Macros
* @{
*/
/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
#define USE_PLL_HSE_EXTC (1) /* Use external clock */
#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Variables
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock there is no need to
call the 2 first functions listed above, since SystemCoreClock variable is
updated automatically.
*/
uint32_t SystemCoreClock = 48000000;
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_FunctionPrototypes
* @{
*/
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
#endif
uint8_t SetSysClock_PLL_HSI(void);
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Private_Functions
* @{
*/
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
* @param None
* @retval None
*/
void SystemInit(void)
{
/* Reset the RCC clock configuration to the default reset state ------------*/
/* Set HSION bit */
RCC->CR |= (uint32_t)0x00000001;
#if defined (STM32F051x8) || defined (STM32F058x8)
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE and MCOSEL[2:0] bits */
RCC->CFGR &= (uint32_t)0xF8FFB80C;
#else
/* Reset SW[1:0], HPRE[3:0], PPRE[2:0], ADCPRE, MCOSEL[2:0], MCOPRE[2:0] and PLLNODIV bits */
RCC->CFGR &= (uint32_t)0x08FFB80C;
#endif /* STM32F051x8 or STM32F058x8 */
/* Reset HSEON, CSSON and PLLON bits */
RCC->CR &= (uint32_t)0xFEF6FFFF;
/* Reset HSEBYP bit */
RCC->CR &= (uint32_t)0xFFFBFFFF;
/* Reset PLLSRC, PLLXTPRE and PLLMUL[3:0] bits */
RCC->CFGR &= (uint32_t)0xFFC0FFFF;
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFCEAC;
#elif defined (STM32F091xC) || defined (STM32F098xx)
/* Reset USART3SW[1:0], USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFF0FEAC;
#elif defined (STM32F030x6) || defined (STM32F030x8) || defined (STM32F031x6) || defined (STM32F038xx) || defined (STM32F030xC)
/* Reset USART1SW[1:0], I2C1SW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEEC;
#elif defined (STM32F051x8) || defined (STM32F058xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFEAC;
#elif defined (STM32F042x6) || defined (STM32F048xx)
/* Reset USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE2C;
#elif defined (STM32F070x6) || defined (STM32F070xB)
/* Reset USART1SW[1:0], I2C1SW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFFFE6C;
/* Set default USB clock to PLLCLK, since there is no HSI48 */
RCC->CFGR3 |= (uint32_t)0x00000080;
#else
#warning "No target selected"
#endif
/* Reset HSI14 bit */
RCC->CR2 &= (uint32_t)0xFFFFFFFE;
/* Disable all interrupts */
RCC->CIR = 0x00000000;
}
/**
* @brief Update SystemCoreClock variable according to Clock Register Values.
* The SystemCoreClock variable contains the core clock (HCLK), it can
* be used by the user application to setup the SysTick timer or configure
* other parameters.
*
* @note Each time the core clock (HCLK) changes, this function must be called
* to update SystemCoreClock variable value. Otherwise, any configuration
* based on this variable will be incorrect.
*
* @note - The system frequency computed by this function is not the real
* frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
*
* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
*
* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
*
* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
* or HSI_VALUE(*) multiplied/divided by the PLL factors.
*
* (*) HSI_VALUE is a constant defined in stm32f0xx_hal.h file (default value
* 8 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
*
* (**) HSE_VALUE is a constant defined in stm32f0xx_hal.h file (default value
* 8 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
*
* - The result of this function could be not correct when using fractional
* value for HSE crystal.
*
* @param None
* @retval None
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, predivfactor = 0;
/* Get SYSCLK source -------------------------------------------------------*/
tmp = RCC->CFGR & RCC_CFGR_SWS;
switch (tmp)
{
case RCC_CFGR_SWS_HSI: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
case RCC_CFGR_SWS_HSE: /* HSE used as system clock */
SystemCoreClock = HSE_VALUE;
break;
case RCC_CFGR_SWS_PLL: /* PLL used as system clock */
/* Get PLL clock source and multiplication factor ----------------------*/
pllmull = RCC->CFGR & RCC_CFGR_PLLMUL;
pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
predivfactor = (RCC->CFGR2 & RCC_CFGR2_PREDIV) + 1;
if (pllsource == RCC_CFGR_PLLSRC_HSE_PREDIV)
{
/* HSE used as PLL clock source : SystemCoreClock = HSE/PREDIV * PLLMUL */
SystemCoreClock = (HSE_VALUE/predivfactor) * pllmull;
}
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F091xC) || defined(STM32F098xx)
else if (pllsource == RCC_CFGR_PLLSRC_HSI48_PREDIV)
{
/* HSI48 used as PLL clock source : SystemCoreClock = HSI48/PREDIV * PLLMUL */
SystemCoreClock = (HSI48_VALUE/predivfactor) * pllmull;
}
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
/* HSI used as PLL clock source : SystemCoreClock = HSI/2 * PLLMUL */
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
#endif /* STM32F042x6 || STM32F048xx || STM32F070x6 ||
STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB ||
STM32F091xC || STM32F098xx || STM32F030xC */
}
break;
default: /* HSI used as system clock */
SystemCoreClock = HSI_VALUE;
break;
}
/* Compute HCLK clock frequency ----------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}
/**
* @brief Configures the System clock source, PLL Multiplier and Divider factors,
* AHB/APBx prescalers and Flash settings
* @note This function should be called only once the RCC clock configuration
* is reset to the default reset state (done in SystemInit() function).
* @param None
* @retval None
*/
void SetSysClock(void)
{
/* 1- Try to start with HSE and external clock */
#if USE_PLL_HSE_EXTC != 0
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
/* 2- If fail try to start with HSE and external xtal */
#if USE_PLL_HSE_XTAL != 0
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
/* 3- If fail start with HSI clock */
if (SetSysClock_PLL_HSI() == 0)
{
while(1)
{
// [TODO] Put something here to tell the user that a problem occured...
}
}
}
}
// Output clock on MCO pin(PA8) for debugging purpose
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 48 MHz
}
#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
//Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
// Select HSE oscillator as PLL source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0; // FAIL
}
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 8/2 = 4 MHz
return 1; // OK
}
#endif
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
// Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
// Select PLL as system clock source and configure the HCLK and PCLK1 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 48 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 48 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 48 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0; // FAIL
}
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV4); // 8/4 = 2 MHz
return 1; // OK
}
/**
* @}
*/
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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/**
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/** @addtogroup CMSIS
* @{
*/
/** @addtogroup stm32f0xx_system
* @{
*/
/**
* @brief Define to prevent recursive inclusion
*/
#ifndef __SYSTEM_STM32F0XX_H
#define __SYSTEM_STM32F0XX_H
#ifdef __cplusplus
extern "C" {
#endif
/** @addtogroup STM32F0xx_System_Includes
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_types
* @{
*/
/* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate()
3) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) by calling HAL API function HAL_RCC_ClockConfig()
Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically.
*/
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_Constants
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_Macros
* @{
*/
/**
* @}
*/
/** @addtogroup STM32F0xx_System_Exported_Functions
* @{
*/
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
extern void SetSysClock(void);
/**
* @}
*/
#ifdef __cplusplus
}
#endif
#endif /*__SYSTEM_STM32F0XX_H */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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@ -1,31 +1,33 @@
/* [ROM = 128kb = 0x20000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_end__ = 0x0801FFFF;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
define symbol __region_RAM_start__ = 0x200000C0;
define symbol __region_RAM_end__ = 0x20003FFF;
/* Memory regions */
define memory mem with size = 4G;
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x1000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing = zeros { readwrite };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__intvec_start__ { readonly section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, block STACKHEAP };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.c
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -33,21 +33,21 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
// To keep track that the vectors remap is done
static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
if (NVIC_vtor_remap == 0) {
if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
NVIC_vtor_remap = 1; // The vectors remap is done
vtor_remap = 1; // The vectors remap is done
}
// Set the vector

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/cmsis_nvic.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

238
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f070xb.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f070xb.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F070xB devices Peripheral Access Layer Header File.
*
* This file contains:
@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@ -324,6 +323,7 @@ typedef struct
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@ -345,7 +345,6 @@ typedef struct
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@ -353,10 +352,10 @@ typedef struct
__IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
__IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
__IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
uint32_t RESERVED1; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
uint32_t RESERVED2; /*!< Reserved, Address offset: 0x20 */
__IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
__IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
__IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
@ -492,6 +491,7 @@ typedef struct
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@ -730,7 +730,6 @@ typedef struct
#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
/******************* Bit definition for ADC_CCR register ********************/
#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
#define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
@ -1050,8 +1049,8 @@ typedef struct
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@ -1086,12 +1085,13 @@ typedef struct
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@ -2053,11 +2053,16 @@ typedef struct
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
#define RTC_CR_ALRAE ((uint32_t)0x00000100)
#define RTC_CR_FMT ((uint32_t)0x00000040)
#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
#define RTC_CR_REFCKON ((uint32_t)0x00000010)
#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
/******************** Bits definition for RTC_ISR register *****************/
#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
@ -2065,18 +2070,23 @@ typedef struct
#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
#define RTC_ISR_TSF ((uint32_t)0x00000800)
#define RTC_ISR_WUTF ((uint32_t)0x00000400)
#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
#define RTC_ISR_INIT ((uint32_t)0x00000080)
#define RTC_ISR_INITF ((uint32_t)0x00000040)
#define RTC_ISR_RSF ((uint32_t)0x00000020)
#define RTC_ISR_INITS ((uint32_t)0x00000010)
#define RTC_ISR_SHPF ((uint32_t)0x00000008)
#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
/******************** Bits definition for RTC_PRER register ****************/
#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
/******************** Bits definition for RTC_WUTR register ****************/
#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
/******************** Bits definition for RTC_ALRMAR register **************/
#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
@ -2306,187 +2316,189 @@ typedef struct
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x04001F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /*!< USART3 DMA remap */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /*!< PF[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /*!< PF[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /*!< PF[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /*!< PF[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /*!< PF[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /*!< PF[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@ -3140,6 +3152,7 @@ typedef struct
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
((INSTANCE) == I2C2))
/****************************** IWDG Instances ********************************/
#define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
@ -3361,6 +3374,11 @@ typedef struct
#define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2))
/****************** UART Instances : Driver enable detection ********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
((INSTANCE) == USART2) || \
((INSTANCE) == USART3) || \
((INSTANCE) == USART4))
/****************************** USB Instances ********************************/
#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)

17
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/stm32f0xx.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,6 +64,13 @@
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F0)
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.0
* @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\

46
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.c
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@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -82,7 +82,6 @@
*/
#include "stm32f0xx.h"
#include "hal_tick.h"
/**
* @}
@ -108,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/**
* @}
*/
@ -161,8 +161,6 @@ uint8_t SetSysClock_PLL_HSI(void);
* @{
*/
extern int NVIC_vtor_remap;
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
@ -195,7 +193,7 @@ void SystemInit(void)
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
#if defined (STM32F072xB) || defined (STM32F078xB)
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@ -227,19 +225,6 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the Cube driver */
SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
HAL_Init();
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
/* Reset the timer to avoid issues after the RAM initialization */
TIM_MST_RESET_ON;
TIM_MST_RESET_OFF;
}
/**
@ -314,9 +299,9 @@ void SystemCoreClockUpdate (void)
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@ -379,17 +364,24 @@ void SetSysClock(void)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
//Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
// Select HSE oscillator as PLL source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
RCC_OscInitStruct.HSI48State = 0; // not used
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F070RB/system_stm32f0xx.h
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@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

48
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/TOOLCHAIN_IAR/stm32f072xb.icf
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@ -1,30 +1,34 @@
/* [ROM = 128kb = 0x20000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_end__ = 0x0801FFFF;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0;
define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x800;
define symbol __ICFEDIT_size_heap__ = 0x1000;
/**** End of ICF editor section. ###ICF###*/
/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
define symbol __region_RAM_start__ = 0x200000C0;
define symbol __region_RAM_end__ = 0x20003FFF;
/* Memory regions */
define memory mem with size = 4G;
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
/* Stack and Heap */
define symbol __size_cstack__ = 0x800;
define symbol __size_heap__ = 0x1000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing = zeros { readwrite };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__intvec_start__ { readonly section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, block STACKHEAP };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/cmsis_nvic.c
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@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -33,21 +33,21 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
// To keep track that the vectors remap is done
static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
if (NVIC_vtor_remap == 0) {
if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
NVIC_vtor_remap = 1; // The vectors remap is done
vtor_remap = 1; // The vectors remap is done
}
// Set the vector

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/hal_tick.h
View File

@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

419
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f072xb.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f072xb.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F072x8/STM32F072xB devices Peripheral Access Layer Header File.
*
* This file contains:
@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@ -449,6 +448,7 @@ typedef struct
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@ -470,7 +470,6 @@ typedef struct
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@ -644,6 +643,7 @@ typedef struct
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END ((uint32_t)0x0801FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@ -672,6 +672,7 @@ typedef struct
#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
@ -1145,9 +1146,10 @@ typedef struct
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@ -1162,9 +1164,23 @@ typedef struct
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@ -1179,40 +1195,82 @@ typedef struct
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@ -2224,7 +2282,6 @@ typedef struct
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
@ -2272,24 +2329,24 @@ typedef struct
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@ -2630,12 +2687,20 @@ typedef struct
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
/****************** Bit definition for EXTI_EMR register ********************/
#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
@ -2656,12 +2721,20 @@ typedef struct
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
/******************* Bit definition for EXTI_RTSR register ******************/
#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
@ -2683,6 +2756,9 @@ typedef struct
#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
/******************* Bit definition for EXTI_FTSR register *******************/
#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
@ -2704,6 +2780,9 @@ typedef struct
#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
/******************* Bit definition for EXTI_SWIER register *******************/
#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
@ -2725,6 +2804,9 @@ typedef struct
#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
/****************** Bit definition for EXTI_PR register *********************/
#define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
@ -2746,6 +2828,9 @@ typedef struct
#define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
#define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
#define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
#define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
#define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
#define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
/******************************************************************************/
/* */
@ -2766,8 +2851,8 @@ typedef struct
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@ -2802,12 +2887,13 @@ typedef struct
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
#define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@ -3834,6 +3920,7 @@ typedef struct
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_WUTIE ((uint32_t)0x00004000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
@ -4140,6 +4227,7 @@ typedef struct
#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
#define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x7F007F00) /*!< DMA remap mask */
#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
@ -4161,185 +4249,186 @@ typedef struct
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /*!< Enable I2C2 Fast mode plus */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */

17
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/stm32f0xx.h
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@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F0xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@ -18,7 +18,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -64,6 +64,13 @@
* @{
*/
/**
* @brief STM32 Family
*/
#if !defined (STM32F0)
#define STM32F0
#endif /* STM32F0 */
/* Uncomment the line below according to the target STM32 device used in your
application
*/
@ -105,11 +112,11 @@
#endif /* USE_HAL_DRIVER */
/**
* @brief CMSIS Device version number V2.2.0
* @brief CMSIS Device version number V2.2.2
*/
#define __STM32F0xx_CMSIS_DEVICE_VERSION_MAIN (0x02) /*!< [31:24] main version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
#define __STM32F0xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0xx_CMSIS_DEVICE_VERSION ((__CMSIS_DEVICE_VERSION_MAIN << 24)\
|(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\

60
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.c
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.c
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Source File.
*
* 1. This file provides two functions and one global variable to be called from
@ -42,7 +42,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -82,7 +82,6 @@
*/
#include "stm32f0xx.h"
#include "hal_tick.h"
/**
* @}
@ -108,6 +107,7 @@
#define HSI_VALUE ((uint32_t)8000000) /*!< Default value of the Internal oscillator in Hz.
This value can be provided and adapted by the user application. */
#endif /* HSI_VALUE */
/**
* @}
*/
@ -161,8 +161,6 @@ uint8_t SetSysClock_PLL_HSI(void);
* @{
*/
extern int NVIC_vtor_remap;
/**
* @brief Setup the microcontroller system.
* Initialize the default HSI clock source, vector table location and the PLL configuration is reset.
@ -195,7 +193,7 @@ void SystemInit(void)
/* Reset PREDIV[3:0] bits */
RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
#if defined (STM32F072xB) || defined (STM32F078xB)
#if defined (STM32F072xB) || defined (STM32F078xx)
/* Reset USART2SW[1:0], USART1SW[1:0], I2C1SW, CECSW, USBSW and ADCSW bits */
RCC->CFGR3 &= (uint32_t)0xFFFCFE2C;
#elif defined (STM32F071xB)
@ -227,19 +225,6 @@ void SystemInit(void)
/* Disable all interrupts */
RCC->CIR = 0x00000000;
/* Configure the Cube driver */
SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
NVIC_vtor_remap = 0; // Because it is not cleared the first time we enter in NVIC_SetVector()
HAL_Init();
/* Configure the System clock source, PLL Multiplier and Divider factors,
AHB/APBx prescalers and Flash settings */
SetSysClock();
/* Reset the timer to avoid issues after the RAM initialization */
TIM_MST_RESET_ON;
TIM_MST_RESET_OFF;
}
/**
@ -314,9 +299,9 @@ void SystemCoreClockUpdate (void)
#endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx */
else
{
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F070xB) || \
defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
#if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) \
|| defined(STM32F078xx) || defined(STM32F071xB) || defined(STM32F072xB) \
|| defined(STM32F070xB) || defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
/* HSI used as PLL clock source : SystemCoreClock = HSI/PREDIV * PLLMUL */
SystemCoreClock = (HSI_VALUE/predivfactor) * pllmull;
#else
@ -379,17 +364,24 @@ void SetSysClock(void)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
//Select HSI as system clock source to allow modification of the PLL configuration
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSI;
if(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0; // FAIL
}
// Select HSE oscillator as PLL source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
if (bypass == 0) {
RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
} else {
RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN only
}
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
@ -425,13 +417,13 @@ uint8_t SetSysClock_PLL_HSI(void)
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
// Select HSI48 oscillator as PLL source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
// Select PLLCLK = 48 MHz ((HSI 8 MHz / 2) * 12)
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI48;
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV2;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL2;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; // HSI div 2
RCC_OscInitStruct.PLL.PREDIV = RCC_PREDIV_DIV1;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL12;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
return 0; // FAIL
}
@ -446,7 +438,7 @@ uint8_t SetSysClock_PLL_HSI(void)
}
// Output clock on MCO1 pin(PA8) for debugging purpose
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI48, RCC_MCO_DIV1); // 48 MHz
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSI, RCC_MCO_DIV1); // 48 MHz
return 1; // OK
}

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F072RB/system_stm32f0xx.h
View File

@ -2,13 +2,13 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS Cortex-M0 Device System Source File for STM32F0xx devices.
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

48
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/TOOLCHAIN_IAR/stm32f091xc.icf
View File

@ -1,31 +1,33 @@
/* [ROM = 256kb = 0x40000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_end__ = 0x0803FFFF;
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
define symbol __ICFEDIT_region_ROM_end__ = 0x0803FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x200000C0;
define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x1000;
define symbol __ICFEDIT_size_heap__ = 0x2000;
/**** End of ICF editor section. ###ICF###*/
/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
define symbol __NVIC_start__ = 0x20000000;
define symbol __NVIC_end__ = 0x200000BF; /* Aligned on 8 bytes */
define symbol __region_RAM_start__ = 0x200000C0;
define symbol __region_RAM_end__ = 0x20007FFF;
/* Memory regions */
define memory mem with size = 4G;
define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x1000;
define symbol __size_heap__ = 0x2000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy with packing = zeros { readwrite };
initialize by copy { readwrite };
do not initialize { section .noinit };
place at address mem:__intvec_start__ { readonly section .intvec };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in RAM_region { readwrite, block STACKHEAP };
place in RAM_region { readwrite,
block CSTACK, block HEAP };
export symbol __ICFEDIT_region_RAM_start__;
export symbol __ICFEDIT_region_RAM_end__;

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

12
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.c
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -33,21 +33,21 @@
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
int NVIC_vtor_remap = 0; // To keep track that the vectors remap is done
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
int i;
// To keep track that the vectors remap is done
static volatile uint32_t vtor_remap = 0;
// Space for dynamic vectors, initialised to allocate in R/W
uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
// Copy and switch to dynamic vectors if first time called
if (NVIC_vtor_remap == 0) {
if (vtor_remap == 0) {
uint32_t *old_vectors = (uint32_t *)NVIC_FLASH_VECTOR_ADDRESS;
for (i = 0; i < NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SYSCFG->CFGR1 |= 0x03; // Embedded SRAM mapped at 0x00000000
NVIC_vtor_remap = 1; // The vectors remap is done
vtor_remap = 1; // The vectors remap is done
}
// Set the vector

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/cmsis_nvic.h
View File

@ -1,7 +1,7 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* Copyright (c) 2015, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/hal_tick.h
View File

@ -6,7 +6,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:

405
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F091RC/stm32f091xc.h
View File

@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f091xc.h
* @author MCD Application Team
* @version V2.2.0
* @date 05-December-2014
* @version V2.2.2
* @date 26-June-2015
* @brief CMSIS STM32F091xC devices Peripheral Access Layer Header File.
*
* This file contains:
@ -14,7 +14,7 @@
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
* <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@ -59,7 +59,6 @@
/** @addtogroup Configuration_section_for_CMSIS
* @{
*/
/**
* @brief Configuration of the Cortex-M0 Processor and Core Peripherals
*/
@ -453,6 +452,7 @@ typedef struct
/**
* @brief Reset and Clock Control
*/
typedef struct
{
__IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
@ -474,7 +474,6 @@ typedef struct
/**
* @brief Real-Time Clock
*/
typedef struct
{
__IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
@ -610,6 +609,7 @@ typedef struct
*/
#define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
#define FLASH_BANK1_END ((uint32_t)0x0803FFFF) /*!< FLASH END address of bank1 */
#define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
#define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
@ -637,6 +637,7 @@ typedef struct
#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
@ -754,7 +755,6 @@ typedef struct
#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
/**
* @}
*/
@ -1130,9 +1130,10 @@ typedef struct
/*!<CAN filter registers */
/******************* Bit definition for CAN_FMR register ********************/
#define CAN_FMR_FINIT ((uint32_t)0x00000001) /*!<Filter Init Mode */
#define CAN_FMR_CAN2SB ((uint32_t)0x00003F00) /*!<CAN2 start bank */
/******************* Bit definition for CAN_FM1R register *******************/
#define CAN_FM1R_FBM ((uint32_t)0x00003FFF) /*!<Filter Mode */
#define CAN_FM1R_FBM ((uint32_t)0x0FFFFFFF) /*!<Filter Mode */
#define CAN_FM1R_FBM0 ((uint32_t)0x00000001) /*!<Filter Init Mode bit 0 */
#define CAN_FM1R_FBM1 ((uint32_t)0x00000002) /*!<Filter Init Mode bit 1 */
#define CAN_FM1R_FBM2 ((uint32_t)0x00000004) /*!<Filter Init Mode bit 2 */
@ -1147,9 +1148,23 @@ typedef struct
#define CAN_FM1R_FBM11 ((uint32_t)0x00000800) /*!<Filter Init Mode bit 11 */
#define CAN_FM1R_FBM12 ((uint32_t)0x00001000) /*!<Filter Init Mode bit 12 */
#define CAN_FM1R_FBM13 ((uint32_t)0x00002000) /*!<Filter Init Mode bit 13 */
#define CAN_FM1R_FBM14 ((uint32_t)0x00004000) /*!<Filter Init Mode bit 14 */
#define CAN_FM1R_FBM15 ((uint32_t)0x00008000) /*!<Filter Init Mode bit 15 */
#define CAN_FM1R_FBM16 ((uint32_t)0x00010000) /*!<Filter Init Mode bit 16 */
#define CAN_FM1R_FBM17 ((uint32_t)0x00020000) /*!<Filter Init Mode bit 17 */
#define CAN_FM1R_FBM18 ((uint32_t)0x00040000) /*!<Filter Init Mode bit 18 */
#define CAN_FM1R_FBM19 ((uint32_t)0x00080000) /*!<Filter Init Mode bit 19 */
#define CAN_FM1R_FBM20 ((uint32_t)0x00100000) /*!<Filter Init Mode bit 20 */
#define CAN_FM1R_FBM21 ((uint32_t)0x00200000) /*!<Filter Init Mode bit 21 */
#define CAN_FM1R_FBM22 ((uint32_t)0x00400000) /*!<Filter Init Mode bit 22 */
#define CAN_FM1R_FBM23 ((uint32_t)0x00800000) /*!<Filter Init Mode bit 23 */
#define CAN_FM1R_FBM24 ((uint32_t)0x01000000) /*!<Filter Init Mode bit 24 */
#define CAN_FM1R_FBM25 ((uint32_t)0x02000000) /*!<Filter Init Mode bit 25 */
#define CAN_FM1R_FBM26 ((uint32_t)0x04000000) /*!<Filter Init Mode bit 26 */
#define CAN_FM1R_FBM27 ((uint32_t)0x08000000) /*!<Filter Init Mode bit 27 */
/******************* Bit definition for CAN_FS1R register *******************/
#define CAN_FS1R_FSC ((uint32_t)0x00003FFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC ((uint32_t)0x0FFFFFFF) /*!<Filter Scale Configuration */
#define CAN_FS1R_FSC0 ((uint32_t)0x00000001) /*!<Filter Scale Configuration bit 0 */
#define CAN_FS1R_FSC1 ((uint32_t)0x00000002) /*!<Filter Scale Configuration bit 1 */
#define CAN_FS1R_FSC2 ((uint32_t)0x00000004) /*!<Filter Scale Configuration bit 2 */
@ -1164,40 +1179,82 @@ typedef struct
#define CAN_FS1R_FSC11 ((uint32_t)0x00000800) /*!<Filter Scale Configuration bit 11 */
#define CAN_FS1R_FSC12 ((uint32_t)0x00001000) /*!<Filter Scale Configuration bit 12 */
#define CAN_FS1R_FSC13 ((uint32_t)0x00002000) /*!<Filter Scale Configuration bit 13 */
#define CAN_FS1R_FSC14 ((uint32_t)0x00004000) /*!<Filter Scale Configuration bit 14 */
#define CAN_FS1R_FSC15 ((uint32_t)0x00008000) /*!<Filter Scale Configuration bit 15 */
#define CAN_FS1R_FSC16 ((uint32_t)0x00010000) /*!<Filter Scale Configuration bit 16 */
#define CAN_FS1R_FSC17 ((uint32_t)0x00020000) /*!<Filter Scale Configuration bit 17 */
#define CAN_FS1R_FSC18 ((uint32_t)0x00040000) /*!<Filter Scale Configuration bit 18 */
#define CAN_FS1R_FSC19 ((uint32_t)0x00080000) /*!<Filter Scale Configuration bit 19 */
#define CAN_FS1R_FSC20 ((uint32_t)0x00100000) /*!<Filter Scale Configuration bit 20 */
#define CAN_FS1R_FSC21 ((uint32_t)0x00200000) /*!<Filter Scale Configuration bit 21 */
#define CAN_FS1R_FSC22 ((uint32_t)0x00400000) /*!<Filter Scale Configuration bit 22 */
#define CAN_FS1R_FSC23 ((uint32_t)0x00800000) /*!<Filter Scale Configuration bit 23 */
#define CAN_FS1R_FSC24 ((uint32_t)0x01000000) /*!<Filter Scale Configuration bit 24 */
#define CAN_FS1R_FSC25 ((uint32_t)0x02000000) /*!<Filter Scale Configuration bit 25 */
#define CAN_FS1R_FSC26 ((uint32_t)0x04000000) /*!<Filter Scale Configuration bit 26 */
#define CAN_FS1R_FSC27 ((uint32_t)0x08000000) /*!<Filter Scale Configuration bit 27 */
/****************** Bit definition for CAN_FFA1R register *******************/
#define CAN_FFA1R_FFA ((uint32_t)0x00003FFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment for Filter 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment for Filter 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment for Filter 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment for Filter 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment for Filter 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment for Filter 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment for Filter 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment for Filter 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment for Filter 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment for Filter 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment for Filter 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment for Filter 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment for Filter 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment for Filter 13 */
#define CAN_FFA1R_FFA ((uint32_t)0x0FFFFFFF) /*!<Filter FIFO Assignment */
#define CAN_FFA1R_FFA0 ((uint32_t)0x00000001) /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFA1R_FFA1 ((uint32_t)0x00000002) /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFA1R_FFA2 ((uint32_t)0x00000004) /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFA1R_FFA3 ((uint32_t)0x00000008) /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFA1R_FFA4 ((uint32_t)0x00000010) /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFA1R_FFA5 ((uint32_t)0x00000020) /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFA1R_FFA6 ((uint32_t)0x00000040) /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFA1R_FFA7 ((uint32_t)0x00000080) /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFA1R_FFA8 ((uint32_t)0x00000100) /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFA1R_FFA9 ((uint32_t)0x00000200) /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFA1R_FFA10 ((uint32_t)0x00000400) /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFA1R_FFA11 ((uint32_t)0x00000800) /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFA1R_FFA12 ((uint32_t)0x00001000) /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFA1R_FFA13 ((uint32_t)0x00002000) /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFA1R_FFA14 ((uint32_t)0x00004000) /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFA1R_FFA15 ((uint32_t)0x00008000) /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFA1R_FFA16 ((uint32_t)0x00010000) /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFA1R_FFA17 ((uint32_t)0x00020000) /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFA1R_FFA18 ((uint32_t)0x00040000) /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFA1R_FFA19 ((uint32_t)0x00080000) /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFA1R_FFA20 ((uint32_t)0x00100000) /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFA1R_FFA21 ((uint32_t)0x00200000) /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFA1R_FFA22 ((uint32_t)0x00400000) /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFA1R_FFA23 ((uint32_t)0x00800000) /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFA1R_FFA24 ((uint32_t)0x01000000) /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFA1R_FFA25 ((uint32_t)0x02000000) /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFA1R_FFA26 ((uint32_t)0x04000000) /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFA1R_FFA27 ((uint32_t)0x08000000) /*!<Filter FIFO Assignment bit 27 */
/******************* Bit definition for CAN_FA1R register *******************/
#define CAN_FA1R_FACT ((uint32_t)0x00003FFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter 0 Active */
#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter 1 Active */
#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter 2 Active */
#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter 3 Active */
#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter 4 Active */
#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter 5 Active */
#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter 6 Active */
#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter 7 Active */
#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter 8 Active */
#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter 9 Active */
#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter 10 Active */
#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter 11 Active */
#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter 12 Active */
#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter 13 Active */
#define CAN_FA1R_FACT ((uint32_t)0x0FFFFFFF) /*!<Filter Active */
#define CAN_FA1R_FACT0 ((uint32_t)0x00000001) /*!<Filter Active bit 0 */
#define CAN_FA1R_FACT1 ((uint32_t)0x00000002) /*!<Filter Active bit 1 */
#define CAN_FA1R_FACT2 ((uint32_t)0x00000004) /*!<Filter Active bit 2 */
#define CAN_FA1R_FACT3 ((uint32_t)0x00000008) /*!<Filter Active bit 3 */
#define CAN_FA1R_FACT4 ((uint32_t)0x00000010) /*!<Filter Active bit 4 */
#define CAN_FA1R_FACT5 ((uint32_t)0x00000020) /*!<Filter Active bit 5 */
#define CAN_FA1R_FACT6 ((uint32_t)0x00000040) /*!<Filter Active bit 6 */
#define CAN_FA1R_FACT7 ((uint32_t)0x00000080) /*!<Filter Active bit 7 */
#define CAN_FA1R_FACT8 ((uint32_t)0x00000100) /*!<Filter Active bit 8 */
#define CAN_FA1R_FACT9 ((uint32_t)0x00000200) /*!<Filter Active bit 9 */
#define CAN_FA1R_FACT10 ((uint32_t)0x00000400) /*!<Filter Active bit 10 */
#define CAN_FA1R_FACT11 ((uint32_t)0x00000800) /*!<Filter Active bit 11 */
#define CAN_FA1R_FACT12 ((uint32_t)0x00001000) /*!<Filter Active bit 12 */
#define CAN_FA1R_FACT13 ((uint32_t)0x00002000) /*!<Filter Active bit 13 */
#define CAN_FA1R_FACT14 ((uint32_t)0x00004000) /*!<Filter Active bit 14 */
#define CAN_FA1R_FACT15 ((uint32_t)0x00008000) /*!<Filter Active bit 15 */
#define CAN_FA1R_FACT16 ((uint32_t)0x00010000) /*!<Filter Active bit 16 */
#define CAN_FA1R_FACT17 ((uint32_t)0x00020000) /*!<Filter Active bit 17 */
#define CAN_FA1R_FACT18 ((uint32_t)0x00040000) /*!<Filter Active bit 18 */
#define CAN_FA1R_FACT19 ((uint32_t)0x00080000) /*!<Filter Active bit 19 */
#define CAN_FA1R_FACT20 ((uint32_t)0x00100000) /*!<Filter Active bit 20 */
#define CAN_FA1R_FACT21 ((uint32_t)0x00200000) /*!<Filter Active bit 21 */
#define CAN_FA1R_FACT22 ((uint32_t)0x00400000) /*!<Filter Active bit 22 */
#define CAN_FA1R_FACT23 ((uint32_t)0x00800000) /*!<Filter Active bit 23 */
#define CAN_FA1R_FACT24 ((uint32_t)0x01000000) /*!<Filter Active bit 24 */
#define CAN_FA1R_FACT25 ((uint32_t)0x02000000) /*!<Filter Active bit 25 */
#define CAN_FA1R_FACT26 ((uint32_t)0x04000000) /*!<Filter Active bit 26 */
#define CAN_FA1R_FACT27 ((uint32_t)0x08000000) /*!<Filter Active bit 27 */
/******************* Bit definition for CAN_F0R1 register *******************/
#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
@ -2209,7 +2266,6 @@ typedef struct
#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /*!< CEC Tx-Error IT Enable */
#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /*!< CEC Tx Missing Acknowledge IT Enable */
/******************************************************************************/
/* */
/* Analog Comparators (COMP) */
@ -2257,24 +2313,24 @@ typedef struct
#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
/* COMPx bits definition */
#define COMP_CSR_COMPxEN ((uint16_t)0x0001) /*!< COMPx enable */
#define COMP_CSR_COMPxMODE ((uint16_t)0x000C) /*!< COMPx power mode */
#define COMP_CSR_COMPxMODE_0 ((uint16_t)0x0004) /*!< COMPx power mode bit 0 */
#define COMP_CSR_COMPxMODE_1 ((uint16_t)0x0008) /*!< COMPx power mode bit 1 */
#define COMP_CSR_COMPxINSEL ((uint16_t)0x0070) /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 ((uint16_t)0x0010) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 ((uint16_t)0x0020) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 ((uint16_t)0x0040) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxOUTSEL ((uint16_t)0x0700) /*!< COMPx output select */
#define COMP_CSR_COMPxOUTSEL_0 ((uint16_t)0x0100) /*!< COMPx output select bit 0 */
#define COMP_CSR_COMPxOUTSEL_1 ((uint16_t)0x0200) /*!< COMPx output select bit 1 */
#define COMP_CSR_COMPxOUTSEL_2 ((uint16_t)0x0400) /*!< COMPx output select bit 2 */
#define COMP_CSR_COMPxPOL ((uint16_t)0x0800) /*!< COMPx output polarity */
#define COMP_CSR_COMPxHYST ((uint16_t)0x3000) /*!< COMPx hysteresis */
#define COMP_CSR_COMPxHYST_0 ((uint16_t)0x1000) /*!< COMPx hysteresis bit 0 */
#define COMP_CSR_COMPxHYST_1 ((uint16_t)0x2000) /*!< COMPx hysteresis bit 1 */
#define COMP_CSR_COMPxOUT ((uint16_t)0x4000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint16_t)0x8000) /*!< COMPx lock */
#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00000700) /*!< COMPx output select */
#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000100) /*!< COMPx output select bit 0 */
#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000200) /*!< COMPx output select bit 1 */
#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00000400) /*!< COMPx output select bit 2 */
#define COMP_CSR_COMPxPOL ((uint32_t)0x00000800) /*!< COMPx output polarity */
#define COMP_CSR_COMPxHYST ((uint32_t)0x00003000) /*!< COMPx hysteresis */
#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00001000) /*!< COMPx hysteresis bit 0 */
#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00002000) /*!< COMPx hysteresis bit 1 */
#define COMP_CSR_COMPxOUT ((uint32_t)0x00004000) /*!< COMPx output level */
#define COMP_CSR_COMPxLOCK ((uint32_t)0x00008000) /*!< COMPx lock */
/******************************************************************************/
/* */
@ -2770,15 +2826,19 @@ typedef struct
#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 - reserved */
#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 - reserved */
#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /*!< Interrupt Mask on line 29 - reserved */
#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /*!< Interrupt Mask on line 30 - reserved */
#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /*!< Interrupt Mask on line 31 */
/****************** Bit definition for EXTI_EMR register ********************/
@ -2800,15 +2860,19 @@ typedef struct
#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 - reserved */
#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 - reserved */
#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /*!< Event Mask on line 29 - reserved */
#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /*!< Event Mask on line 30 - reserved */
#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /*!< Event Mask on line 31 */
/******************* Bit definition for EXTI_RTSR register ******************/
@ -2926,8 +2990,8 @@ typedef struct
#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
/****************** FLASH Keys **********************************************/
#define FLASH_FKEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
#define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
to unlock the write access to the FPEC. */
#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
@ -2962,12 +3026,15 @@ typedef struct
#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
#define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
#define FLASH_OBR_USER ((uint32_t)0x0000FF00) /*!< User Option Bytes */
#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
#define FLASH_OBR_nBOOT0 ((uint32_t)0x00001000) /*!< nBOOT0 */
#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
#define FLASH_OBR_BOOT_SEL ((uint32_t)0x00008000) /*!< BOOT selection */
/* Old BOOT1 bit definition, maintained for legacy purpose */
#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
@ -4002,6 +4069,7 @@ typedef struct
#define RTC_CR_SUB1H ((uint32_t)0x00020000)
#define RTC_CR_ADD1H ((uint32_t)0x00010000)
#define RTC_CR_TSIE ((uint32_t)0x00008000)
#define RTC_CR_WUTIE ((uint32_t)0x00004000)
#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
#define RTC_CR_TSE ((uint32_t)0x00000800)
#define RTC_CR_WUTE ((uint32_t)0x00000400)
@ -4320,182 +4388,182 @@ typedef struct
#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
/***************** Bit definition for SYSCFG_EXTICR1 register **************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
#define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
#define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
#define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
#define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
/**
* @brief EXTI0 configuration
*/
#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!< PE[0] pin */
#define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
/**
* @brief EXTI1 configuration
*/
#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!< PE[1] pin */
#define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
/**
* @brief EXTI2 configuration
*/
#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!< PE[2] pin */
#define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
/**
* @brief EXTI3 configuration
*/
#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /*!< PF[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!< PE[3] pin */
#define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
/***************** Bit definition for SYSCFG_EXTICR2 register **************/
#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
#define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
#define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
#define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
#define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
/**
* @brief EXTI4 configuration
*/
#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!< PE[4] pin */
#define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
/**
* @brief EXTI5 configuration
*/
#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!< PE[5] pin */
#define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
/**
* @brief EXTI6 configuration
*/
#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!< PE[6] pin */
#define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
/**
* @brief EXTI7 configuration
*/
#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /*!< PF[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!< PE[7] pin */
#define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
/***************** Bit definition for SYSCFG_EXTICR3 register **************/
#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
#define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
#define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
#define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
#define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
/**
* @brief EXTI8 configuration
*/
#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
#define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!< PE[8] pin */
/**
* @brief EXTI9 configuration
*/
#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!< PE[9] pin */
#define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
/**
* @brief EXTI10 configuration
*/
#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PE[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!< PD[10] pin */
#define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
/**
* @brief EXTI11 configuration
*/
#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
#define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!< PE[11] pin */
/***************** Bit definition for SYSCFG_EXTICR4 register **************/
#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
#define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
#define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
#define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
#define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
/**
* @brief EXTI12 configuration
*/
#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
#define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!< PE[12] pin */
/**
* @brief EXTI13 configuration
*/
#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
#define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!< PE[13] pin */
/**
* @brief EXTI14 configuration
*/
#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
#define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!< PE[14] pin */
/**
* @brief EXTI15 configuration
*/
#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
#define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!< PE[15] pin */
/***************** Bit definition for SYSCFG_CFGR2 register ****************/
#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
@ -5661,6 +5729,7 @@ typedef struct
* @}
*/
/******************************************************************************/
/* For a painless codes migration between the STM32F3xx device product */
/* lines, the aliases defined below are put in place to overcome the */

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