ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge branch 'master' of https://github.com/mbedmicro/mbed into dev_nucleo_f303k8 

Conflicts:
	workspace_tools/host_tests/host_test.py
pull/1346/head
dbestm 2015-09-28 14:23:53 +02:00
parent 0fb5d52a8c cc65d391ef
commit d7ab336a2b
514 changed files with 62791 additions and 29835 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -68,6 +68,7 @@ STMicroelectronics:
* [Nucleo-F334R8](https://developer.mbed.org/platforms/ST-Nucleo-F334R8/) (Cortex-M4F)
* [Nucleo-F401RE](https://developer.mbed.org/platforms/ST-Nucleo-F401RE/) (Cortex-M4F)
* [Nucleo-F411RE](https://developer.mbed.org/platforms/ST-Nucleo-F411RE/) (Cortex-M4F)
* [Nucleo-L476RG](https://developer.mbed.org/platforms/ST-Nucleo-L476RG/) (Cortex-M4F)
* STM32F4XX (Cortex-M4F)
* STM32F3XX (Cortex-M4F)
* STM32F0-Discovery (Cortex-M0)
@ -76,6 +77,7 @@ STMicroelectronics:
* STM32F4-Discovery (Cortex-M4F)
* STM32F429-Discovery (Cortex-M4F)
* STM32L0-Discovery (Cortex-M0+)
* [STM32L4-Discovery](https://developer.mbed.org/platforms/ST-Discovery-L476VG/) (Cortex-M4F)
* [Arch Max](https://developer.mbed.org/platforms/Seeed-Arch-Max/) (Cortex-M4F)

769
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/CMSDK_BEID.h Normal file
View File

@ -0,0 +1,769 @@
/**************************************************************************//**
* @file CMSDK_BEID.h
* @brief CMSIS Core Peripheral Access Layer Header File for
* CMSDK_BEID Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef CMSDK_BEID_H
#define CMSDK_BEID_H
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/* ------------------- Cortex-M3 Processor Exceptions Numbers ------------------- */
NonMaskableInt_IRQn = -14, /* 2 Non Maskable Interrupt */
HardFault_IRQn = -13, /* 3 HardFault Interrupt */
MemoryManagement_IRQn = -12, /* 4 Memory Management Interrupt */
BusFault_IRQn = -11, /* 5 Bus Fault Interrupt */
UsageFault_IRQn = -10, /* 6 Usage Fault Interrupt */
SVCall_IRQn = -5, /* 11 SV Call Interrupt */
DebugMonitor_IRQn = -4, /* 12 Debug Monitor Interrupt */
PendSV_IRQn = -2, /* 14 Pend SV Interrupt */
SysTick_IRQn = -1, /* 15 System Tick Interrupt */
/* ---------------------- CMSDK_BEID Specific Interrupt Numbers ------------------ */
UARTRX0_IRQn = 0, /* UART 0 RX Interrupt */
UARTTX0_IRQn = 1, /* UART 0 TX Interrupt */
UARTRX1_IRQn = 2, /* UART 1 RX Interrupt */
UARTTX1_IRQn = 3, /* UART 1 TX Interrupt */
UARTRX2_IRQn = 4, /* UART 2 RX Interrupt */
UARTTX2_IRQn = 5, /* UART 2 TX Interrupt */
UARTRX3_IRQn = 6, /* Was PORT0_ALL_IRQn Port 1 combined Interrupt */
UARTTX3_IRQn = 7, /* Was PORT1_ALL_IRQn Port 1 combined Interrupt */
TIMER0_IRQn = 8, /* TIMER 0 Interrupt */
TIMER1_IRQn = 9, /* TIMER 1 Interrupt */
DUALTIMER_IRQn = 10, /* Dual Timer Interrupt */
SPI_IRQn = 11, /* SPI Interrupt */
UARTOVF_IRQn = 12, /* UART 0,1,2 Overflow Interrupt */
ETHERNET_IRQn = 13, /* Ethernet Interrupt */
I2S_IRQn = 14, /* I2S Interrupt */
TSC_IRQn = 15, /* Touch Screen Interrupt */
// DMA_IRQn = 15, /* PL230 DMA Done + Error Interrupt */
PORT0_0_IRQn = 16, /* All P0 I/O pins used as irq source */
PORT0_1_IRQn = 17, /* There are 16 pins in total */
PORT0_2_IRQn = 18,
PORT0_3_IRQn = 19,
PORT0_4_IRQn = 20,
PORT0_5_IRQn = 21,
PORT0_6_IRQn = 22,
PORT0_7_IRQn = 23,
PORT0_8_IRQn = 24,
PORT0_9_IRQn = 25,
PORT0_10_IRQn = 26,
PORT0_11_IRQn = 27,
PORT0_12_IRQn = 28,
PORT0_13_IRQn = 29,
PORT0_14_IRQn = 30,
PORT0_15_IRQn = 31,
} IRQn_Type;
/* ================================================================================ */
/* ================ Processor and Core Peripheral Section ================ */
/* ================================================================================ */
/* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */
#define __CM3_REV 0x0201 /* Core revision r2p1 */
#define __MPU_PRESENT 1 /* MPU present or not */
#define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */
#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */
#include <core_cm3.h> /* Processor and core peripherals */
#include "system_CMSDK_BEID.h" /* System Header */
/* ================================================================================ */
/* ================ Device Specific Peripheral Section ================ */
/* ================================================================================ */
/* ------------------- Start of section using anonymous unions ------------------ */
#if defined ( __CC_ARM )
#pragma push
#pragma anon_unions
#elif defined(__ICCARM__)
#pragma language=extended
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning 586
#else
#warning Not supported compiler type
#endif
/*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register */
__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register */
} CMSDK_UART_TypeDef;
/* CMSDK_UART DATA Register Definitions */
#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position */
#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask */
#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position */
#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask */
#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position */
#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask */
#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position */
#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask */
#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position */
#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask */
#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position */
#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask */
#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position */
#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask */
#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position */
#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask */
#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position */
#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask */
#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position */
#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask */
#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position */
#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask */
#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position */
#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask */
#define CMSDK_UART_INTSTATUS_RXORIRQ_Pos 3 /* CMSDK_UART CTRL: RXORIRQ Position */
#define CMSDK_UART_CTRL_RXORIRQ_Msk (0x01ul << CMSDK_UART_INTSTATUS_RXORIRQ_Pos) /* CMSDK_UART CTRL: RXORIRQ Mask */
#define CMSDK_UART_CTRL_TXORIRQ_Pos 2 /* CMSDK_UART CTRL: TXORIRQ Position */
#define CMSDK_UART_CTRL_TXORIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQ_Pos) /* CMSDK_UART CTRL: TXORIRQ Mask */
#define CMSDK_UART_CTRL_RXIRQ_Pos 1 /* CMSDK_UART CTRL: RXIRQ Position */
#define CMSDK_UART_CTRL_RXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQ_Pos) /* CMSDK_UART CTRL: RXIRQ Mask */
#define CMSDK_UART_CTRL_TXIRQ_Pos 0 /* CMSDK_UART CTRL: TXIRQ Position */
#define CMSDK_UART_CTRL_TXIRQ_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQ_Pos) /* CMSDK_UART CTRL: TXIRQ Mask */
#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position */
#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos) /* CMSDK_UART BAUDDIV: BAUDDIV Mask */
/*----------------------------- Timer (TIMER) -------------------------------*/
typedef struct
{
__IO uint32_t CTRL; /* Offset: 0x000 (R/W) Control Register */
__IO uint32_t VALUE; /* Offset: 0x004 (R/W) Current Value Register */
__IO uint32_t RELOAD; /* Offset: 0x008 (R/W) Reload Value Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register */
};
} CMSDK_TIMER_TypeDef;
/* CMSDK_TIMER CTRL Register Definitions */
#define CMSDK_TIMER_CTRL_IRQEN_Pos 3 /* CMSDK_TIMER CTRL: IRQEN Position */
#define CMSDK_TIMER_CTRL_IRQEN_Msk (0x01ul << CMSDK_TIMER_CTRL_IRQEN_Pos) /* CMSDK_TIMER CTRL: IRQEN Mask */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Pos 2 /* CMSDK_TIMER CTRL: SELEXTCLK Position */
#define CMSDK_TIMER_CTRL_SELEXTCLK_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTCLK_Pos) /* CMSDK_TIMER CTRL: SELEXTCLK Mask */
#define CMSDK_TIMER_CTRL_SELEXTEN_Pos 1 /* CMSDK_TIMER CTRL: SELEXTEN Position */
#define CMSDK_TIMER_CTRL_SELEXTEN_Msk (0x01ul << CMSDK_TIMER_CTRL_SELEXTEN_Pos) /* CMSDK_TIMER CTRL: SELEXTEN Mask */
#define CMSDK_TIMER_CTRL_EN_Pos 0 /* CMSDK_TIMER CTRL: EN Position */
#define CMSDK_TIMER_CTRL_EN_Msk (0x01ul << CMSDK_TIMER_CTRL_EN_Pos) /* CMSDK_TIMER CTRL: EN Mask */
#define CMSDK_TIMER_VAL_CURRENT_Pos 0 /* CMSDK_TIMER VALUE: CURRENT Position */
#define CMSDK_TIMER_VAL_CURRENT_Msk (0xFFFFFFFFul << CMSDK_TIMER_VAL_CURRENT_Pos) /* CMSDK_TIMER VALUE: CURRENT Mask */
#define CMSDK_TIMER_RELOAD_VAL_Pos 0 /* CMSDK_TIMER RELOAD: RELOAD Position */
#define CMSDK_TIMER_RELOAD_VAL_Msk (0xFFFFFFFFul << CMSDK_TIMER_RELOAD_VAL_Pos) /* CMSDK_TIMER RELOAD: RELOAD Mask */
#define CMSDK_TIMER_INTSTATUS_Pos 0 /* CMSDK_TIMER INTSTATUS: INTSTATUSPosition */
#define CMSDK_TIMER_INTSTATUS_Msk (0x01ul << CMSDK_TIMER_INTSTATUS_Pos) /* CMSDK_TIMER INTSTATUS: INTSTATUSMask */
#define CMSDK_TIMER_INTCLEAR_Pos 0 /* CMSDK_TIMER INTCLEAR: INTCLEAR Position */
#define CMSDK_TIMER_INTCLEAR_Msk (0x01ul << CMSDK_TIMER_INTCLEAR_Pos) /* CMSDK_TIMER INTCLEAR: INTCLEAR Mask */
/*------------- Timer (TIM) --------------------------------------------------*/
typedef struct
{
__IO uint32_t Timer1Load; /* Offset: 0x000 (R/W) Timer 1 Load */
__I uint32_t Timer1Value; /* Offset: 0x004 (R/ ) Timer 1 Counter Current Value */
__IO uint32_t Timer1Control; /* Offset: 0x008 (R/W) Timer 1 Control */
__O uint32_t Timer1IntClr; /* Offset: 0x00C ( /W) Timer 1 Interrupt Clear */
__I uint32_t Timer1RIS; /* Offset: 0x010 (R/ ) Timer 1 Raw Interrupt Status */
__I uint32_t Timer1MIS; /* Offset: 0x014 (R/ ) Timer 1 Masked Interrupt Status */
__IO uint32_t Timer1BGLoad; /* Offset: 0x018 (R/W) Background Load Register */
uint32_t RESERVED0;
__IO uint32_t Timer2Load; /* Offset: 0x020 (R/W) Timer 2 Load */
__I uint32_t Timer2Value; /* Offset: 0x024 (R/ ) Timer 2 Counter Current Value */
__IO uint32_t Timer2Control; /* Offset: 0x028 (R/W) Timer 2 Control */
__O uint32_t Timer2IntClr; /* Offset: 0x02C ( /W) Timer 2 Interrupt Clear */
__I uint32_t Timer2RIS; /* Offset: 0x030 (R/ ) Timer 2 Raw Interrupt Status */
__I uint32_t Timer2MIS; /* Offset: 0x034 (R/ ) Timer 2 Masked Interrupt Status */
__IO uint32_t Timer2BGLoad; /* Offset: 0x038 (R/W) Background Load Register */
uint32_t RESERVED1[945];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Integration Test Output Set Register */
} CMSDK_DUALTIMER_BOTH_TypeDef;
#define CMSDK_DUALTIMER1_LOAD_Pos 0 /* CMSDK_DUALTIMER1 LOAD: LOAD Position */
#define CMSDK_DUALTIMER1_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_LOAD_Pos) /* CMSDK_DUALTIMER1 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER1_VALUE_Pos 0 /* CMSDK_DUALTIMER1 VALUE: VALUE Position */
#define CMSDK_DUALTIMER1_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_VALUE_Pos) /* CMSDK_DUALTIMER1 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER1_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER1_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_EN_Pos) /* CMSDK_DUALTIMER1 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER1_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_MODE_Pos) /* CMSDK_DUALTIMER1 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER1_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER1 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER1_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER1_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER1 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER1_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER1 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER1_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER1_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER1 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER1_INTCLR_Pos 0 /* CMSDK_DUALTIMER1 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER1_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER1_INTCLR_Pos) /* CMSDK_DUALTIMER1 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER1_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER1 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER1_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER1_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER1 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER1_BGLOAD_Pos 0 /* CMSDK_DUALTIMER1 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER1_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER1_BGLOAD_Pos) /* CMSDK_DUALTIMER1 BGLOAD: Background Load Mask */
#define CMSDK_DUALTIMER2_LOAD_Pos 0 /* CMSDK_DUALTIMER2 LOAD: LOAD Position */
#define CMSDK_DUALTIMER2_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_LOAD_Pos) /* CMSDK_DUALTIMER2 LOAD: LOAD Mask */
#define CMSDK_DUALTIMER2_VALUE_Pos 0 /* CMSDK_DUALTIMER2 VALUE: VALUE Position */
#define CMSDK_DUALTIMER2_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_VALUE_Pos) /* CMSDK_DUALTIMER2 VALUE: VALUE Mask */
#define CMSDK_DUALTIMER2_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER2_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_EN_Pos) /* CMSDK_DUALTIMER2 CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER2_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_MODE_Pos) /* CMSDK_DUALTIMER2 CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER2_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER2 CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER2_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER2_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER2 CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER2_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER2 CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER2_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER2_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER2 CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER2_INTCLR_Pos 0 /* CMSDK_DUALTIMER2 INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER2_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER2_INTCLR_Pos) /* CMSDK_DUALTIMER2 INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER2_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER2 RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER2_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER2_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER2 MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER2_BGLOAD_Pos 0 /* CMSDK_DUALTIMER2 BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER2_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER2_BGLOAD_Pos) /* CMSDK_DUALTIMER2 BGLOAD: Background Load Mask */
typedef struct
{
__IO uint32_t TimerLoad; /* Offset: 0x000 (R/W) Timer Load */
__I uint32_t TimerValue; /* Offset: 0x000 (R/W) Timer Counter Current Value */
__IO uint32_t TimerControl; /* Offset: 0x000 (R/W) Timer Control */
__O uint32_t TimerIntClr; /* Offset: 0x000 (R/W) Timer Interrupt Clear */
__I uint32_t TimerRIS; /* Offset: 0x000 (R/W) Timer Raw Interrupt Status */
__I uint32_t TimerMIS; /* Offset: 0x000 (R/W) Timer Masked Interrupt Status */
__IO uint32_t TimerBGLoad; /* Offset: 0x000 (R/W) Background Load Register */
} CMSDK_DUALTIMER_SINGLE_TypeDef;
#define CMSDK_DUALTIMER_LOAD_Pos 0 /* CMSDK_DUALTIMER LOAD: LOAD Position */
#define CMSDK_DUALTIMER_LOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_LOAD_Pos) /* CMSDK_DUALTIMER LOAD: LOAD Mask */
#define CMSDK_DUALTIMER_VALUE_Pos 0 /* CMSDK_DUALTIMER VALUE: VALUE Position */
#define CMSDK_DUALTIMER_VALUE_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_VALUE_Pos) /* CMSDK_DUALTIMER VALUE: VALUE Mask */
#define CMSDK_DUALTIMER_CTRL_EN_Pos 7 /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Position */
#define CMSDK_DUALTIMER_CTRL_EN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_EN_Pos) /* CMSDK_DUALTIMER CTRL_EN: CTRL Enable Mask */
#define CMSDK_DUALTIMER_CTRL_MODE_Pos 6 /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Position */
#define CMSDK_DUALTIMER_CTRL_MODE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_MODE_Pos) /* CMSDK_DUALTIMER CTRL_MODE: CTRL MODE Mask */
#define CMSDK_DUALTIMER_CTRL_INTEN_Pos 5 /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Position */
#define CMSDK_DUALTIMER_CTRL_INTEN_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_INTEN_Pos) /* CMSDK_DUALTIMER CTRL_INTEN: CTRL Int Enable Mask */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Pos 2 /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Position */
#define CMSDK_DUALTIMER_CTRL_PRESCALE_Msk (0x3ul << CMSDK_DUALTIMER_CTRL_PRESCALE_Pos) /* CMSDK_DUALTIMER CTRL_PRESCALE: CTRL PRESCALE Mask */
#define CMSDK_DUALTIMER_CTRL_SIZE_Pos 1 /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Position */
#define CMSDK_DUALTIMER_CTRL_SIZE_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_SIZE_Pos) /* CMSDK_DUALTIMER CTRL_SIZE: CTRL SIZE Mask */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos 0 /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Position */
#define CMSDK_DUALTIMER_CTRL_ONESHOOT_Msk (0x1ul << CMSDK_DUALTIMER_CTRL_ONESHOOT_Pos) /* CMSDK_DUALTIMER CTRL_ONESHOOT: CTRL ONESHOOT Mask */
#define CMSDK_DUALTIMER_INTCLR_Pos 0 /* CMSDK_DUALTIMER INTCLR: INT Clear Position */
#define CMSDK_DUALTIMER_INTCLR_Msk (0x1ul << CMSDK_DUALTIMER_INTCLR_Pos) /* CMSDK_DUALTIMER INTCLR: INT Clear Mask */
#define CMSDK_DUALTIMER_RAWINTSTAT_Pos 0 /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Position */
#define CMSDK_DUALTIMER_RAWINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_RAWINTSTAT_Pos) /* CMSDK_DUALTIMER RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_DUALTIMER_MASKINTSTAT_Pos 0 /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Position */
#define CMSDK_DUALTIMER_MASKINTSTAT_Msk (0x1ul << CMSDK_DUALTIMER_MASKINTSTAT_Pos) /* CMSDK_DUALTIMER MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_DUALTIMER_BGLOAD_Pos 0 /* CMSDK_DUALTIMER BGLOAD: Background Load Position */
#define CMSDK_DUALTIMER_BGLOAD_Msk (0xFFFFFFFFul << CMSDK_DUALTIMER_BGLOAD_Pos) /* CMSDK_DUALTIMER BGLOAD: Background Load Mask */
/*-------------------- General Purpose Input Output (GPIO) -------------------*/
typedef struct
{
__IO uint32_t DATA; /* Offset: 0x000 (R/W) DATA Register */
__IO uint32_t DATAOUT; /* Offset: 0x004 (R/W) Data Output Latch Register */
uint32_t RESERVED0[2];
__IO uint32_t OUTENABLESET; /* Offset: 0x010 (R/W) Output Enable Set Register */
__IO uint32_t OUTENABLECLR; /* Offset: 0x014 (R/W) Output Enable Clear Register */
__IO uint32_t ALTFUNCSET; /* Offset: 0x018 (R/W) Alternate Function Set Register */
__IO uint32_t ALTFUNCCLR; /* Offset: 0x01C (R/W) Alternate Function Clear Register */
__IO uint32_t INTENSET; /* Offset: 0x020 (R/W) Interrupt Enable Set Register */
__IO uint32_t INTENCLR; /* Offset: 0x024 (R/W) Interrupt Enable Clear Register */
__IO uint32_t INTTYPESET; /* Offset: 0x028 (R/W) Interrupt Type Set Register */
__IO uint32_t INTTYPECLR; /* Offset: 0x02C (R/W) Interrupt Type Clear Register */
__IO uint32_t INTPOLSET; /* Offset: 0x030 (R/W) Interrupt Polarity Set Register */
__IO uint32_t INTPOLCLR; /* Offset: 0x034 (R/W) Interrupt Polarity Clear Register */
union {
__I uint32_t INTSTATUS; /* Offset: 0x038 (R/ ) Interrupt Status Register */
__O uint32_t INTCLEAR; /* Offset: 0x038 ( /W) Interrupt Clear Register */
};
uint32_t RESERVED1[241];
__IO uint32_t LB_MASKED[256]; /* Offset: 0x400 - 0x7FC Lower byte Masked Access Register (R/W) */
__IO uint32_t UB_MASKED[256]; /* Offset: 0x800 - 0xBFC Upper byte Masked Access Register (R/W) */
} CMSDK_GPIO_TypeDef;
#define CMSDK_GPIO_DATA_Pos 0 /* CMSDK_GPIO DATA: DATA Position */
#define CMSDK_GPIO_DATA_Msk (0xFFFFul << CMSDK_GPIO_DATA_Pos) /* CMSDK_GPIO DATA: DATA Mask */
#define CMSDK_GPIO_DATAOUT_Pos 0 /* CMSDK_GPIO DATAOUT: DATAOUT Position */
#define CMSDK_GPIO_DATAOUT_Msk (0xFFFFul << CMSDK_GPIO_DATAOUT_Pos) /* CMSDK_GPIO DATAOUT: DATAOUT Mask */
#define CMSDK_GPIO_OUTENSET_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENSET_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_OUTENCLR_Pos 0 /* CMSDK_GPIO OUTEN: OUTEN Position */
#define CMSDK_GPIO_OUTENCLR_Msk (0xFFFFul << CMSDK_GPIO_OUTEN_Pos) /* CMSDK_GPIO OUTEN: OUTEN Mask */
#define CMSDK_GPIO_ALTFUNCSET_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCSET_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_ALTFUNCCLR_Pos 0 /* CMSDK_GPIO ALTFUNC: ALTFUNC Position */
#define CMSDK_GPIO_ALTFUNCCLR_Msk (0xFFFFul << CMSDK_GPIO_ALTFUNC_Pos) /* CMSDK_GPIO ALTFUNC: ALTFUNC Mask */
#define CMSDK_GPIO_INTENSET_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENSET_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTENCLR_Pos 0 /* CMSDK_GPIO INTEN: INTEN Position */
#define CMSDK_GPIO_INTENCLR_Msk (0xFFFFul << CMSDK_GPIO_INTEN_Pos) /* CMSDK_GPIO INTEN: INTEN Mask */
#define CMSDK_GPIO_INTTYPESET_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPESET_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTTYPECLR_Pos 0 /* CMSDK_GPIO INTTYPE: INTTYPE Position */
#define CMSDK_GPIO_INTTYPECLR_Msk (0xFFFFul << CMSDK_GPIO_INTTYPE_Pos) /* CMSDK_GPIO INTTYPE: INTTYPE Mask */
#define CMSDK_GPIO_INTPOLSET_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLSET_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTPOLCLR_Pos 0 /* CMSDK_GPIO INTPOL: INTPOL Position */
#define CMSDK_GPIO_INTPOLCLR_Msk (0xFFFFul << CMSDK_GPIO_INTPOL_Pos) /* CMSDK_GPIO INTPOL: INTPOL Mask */
#define CMSDK_GPIO_INTSTATUS_Pos 0 /* CMSDK_GPIO INTSTATUS: INTSTATUS Position */
#define CMSDK_GPIO_INTSTATUS_Msk (0xFFul << CMSDK_GPIO_INTSTATUS_Pos) /* CMSDK_GPIO INTSTATUS: INTSTATUS Mask */
#define CMSDK_GPIO_INTCLEAR_Pos 0 /* CMSDK_GPIO INTCLEAR: INTCLEAR Position */
#define CMSDK_GPIO_INTCLEAR_Msk (0xFFul << CMSDK_GPIO_INTCLEAR_Pos) /* CMSDK_GPIO INTCLEAR: INTCLEAR Mask */
#define CMSDK_GPIO_MASKLOWBYTE_Pos 0 /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Position */
#define CMSDK_GPIO_MASKLOWBYTE_Msk (0x00FFul << CMSDK_GPIO_MASKLOWBYTE_Pos) /* CMSDK_GPIO MASKLOWBYTE: MASKLOWBYTE Mask */
#define CMSDK_GPIO_MASKHIGHBYTE_Pos 0 /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Position */
#define CMSDK_GPIO_MASKHIGHBYTE_Msk (0xFF00ul << CMSDK_GPIO_MASKHIGHBYTE_Pos) /* CMSDK_GPIO MASKHIGHBYTE: MASKHIGHBYTE Mask */
/*------------- System Control (SYSCON) --------------------------------------*/
typedef struct
{
__IO uint32_t REMAP; /* Offset: 0x000 (R/W) Remap Control Register */
__IO uint32_t PMUCTRL; /* Offset: 0x004 (R/W) PMU Control Register */
__IO uint32_t RESETOP; /* Offset: 0x008 (R/W) Reset Option Register */
__IO uint32_t EMICTRL; /* Offset: 0x00C (R/W) EMI Control Register */
__IO uint32_t RSTINFO; /* Offset: 0x010 (R/W) Reset Information Register */
uint32_t RESERVED0[3];
__IO uint32_t AHBPER0SET; /* Offset: 0x020 (R/W)AHB peripheral access control set */
__IO uint32_t AHBPER0CLR; /* Offset: 0x024 (R/W)AHB peripheral access control clear */
uint32_t RESERVED1[2];
__IO uint32_t APBPER0SET; /* Offset: 0x030 (R/W)APB peripheral access control set */
__IO uint32_t APBPER0CLR; /* Offset: 0x034 (R/W)APB peripheral access control clear */
uint32_t RESERVED2[2];
__IO uint32_t MAINCLK; /* Offset: 0x040 (R/W) Main Clock Control Register */
__IO uint32_t AUXCLK; /* Offset: 0x044 (R/W) Auxiliary / RTC Control Register */
__IO uint32_t PLLCTRL; /* Offset: 0x048 (R/W) PLL Control Register */
__IO uint32_t PLLSTATUS; /* Offset: 0x04C (R/W) PLL Status Register */
__IO uint32_t SLEEPCFG; /* Offset: 0x050 (R/W) Sleep Control Register */
__IO uint32_t FLASHAUXCFG; /* Offset: 0x054 (R/W) Flash auxiliary settings Control Register */
uint32_t RESERVED3[10];
__IO uint32_t AHBCLKCFG0SET; /* Offset: 0x080 (R/W) AHB Peripheral Clock set in Active state */
__IO uint32_t AHBCLKCFG0CLR; /* Offset: 0x084 (R/W) AHB Peripheral Clock clear in Active state */
__IO uint32_t AHBCLKCFG1SET; /* Offset: 0x088 (R/W) AHB Peripheral Clock set in Sleep state */
__IO uint32_t AHBCLKCFG1CLR; /* Offset: 0x08C (R/W) AHB Peripheral Clock clear in Sleep state */
__IO uint32_t AHBCLKCFG2SET; /* Offset: 0x090 (R/W) AHB Peripheral Clock set in Deep Sleep state */
__IO uint32_t AHBCLKCFG2CLR; /* Offset: 0x094 (R/W) AHB Peripheral Clock clear in Deep Sleep state */
uint32_t RESERVED4[2];
__IO uint32_t APBCLKCFG0SET; /* Offset: 0x0A0 (R/W) APB Peripheral Clock set in Active state */
__IO uint32_t APBCLKCFG0CLR; /* Offset: 0x0A4 (R/W) APB Peripheral Clock clear in Active state */
__IO uint32_t APBCLKCFG1SET; /* Offset: 0x0A8 (R/W) APB Peripheral Clock set in Sleep state */
__IO uint32_t APBCLKCFG1CLR; /* Offset: 0x0AC (R/W) APB Peripheral Clock clear in Sleep state */
__IO uint32_t APBCLKCFG2SET; /* Offset: 0x0B0 (R/W) APB Peripheral Clock set in Deep Sleep state */
__IO uint32_t APBCLKCFG2CLR; /* Offset: 0x0B4 (R/W) APB Peripheral Clock clear in Deep Sleep state */
uint32_t RESERVED5[2];
__IO uint32_t AHBPRST0SET; /* Offset: 0x0C0 (R/W) AHB Peripheral reset select set */
__IO uint32_t AHBPRST0CLR; /* Offset: 0x0C4 (R/W) AHB Peripheral reset select clear */
__IO uint32_t APBPRST0SET; /* Offset: 0x0C8 (R/W) APB Peripheral reset select set */
__IO uint32_t APBPRST0CLR; /* Offset: 0x0CC (R/W) APB Peripheral reset select clear */
__IO uint32_t PWRDNCFG0SET; /* Offset: 0x0D0 (R/W) AHB Power down sleep wakeup source set */
__IO uint32_t PWRDNCFG0CLR; /* Offset: 0x0D4 (R/W) AHB Power down sleep wakeup source clear */
__IO uint32_t PWRDNCFG1SET; /* Offset: 0x0D8 (R/W) APB Power down sleep wakeup source set */
__IO uint32_t PWRDNCFG1CLR; /* Offset: 0x0DC (R/W) APB Power down sleep wakeup source clear */
__O uint32_t RTCRESET; /* Offset: 0x0E0 ( /W) RTC reset */
__IO uint32_t EVENTCFG; /* Offset: 0x0E4 (R/W) Event interface Control Register */
uint32_t RESERVED6[2];
__IO uint32_t PWROVRIDE0; /* Offset: 0x0F0 (R/W) SRAM Power control overide */
__IO uint32_t PWROVRIDE1; /* Offset: 0x0F4 (R/W) Embedded Flash Power control overide */
__I uint32_t MEMORYSTATUS; /* Offset: 0x0F8 (R/ ) Memory Status Register */
uint32_t RESERVED7[1];
__IO uint32_t GPIOPADCFG0; /* Offset: 0x100 (R/W) IO pad settings */
__IO uint32_t GPIOPADCFG1; /* Offset: 0x104 (R/W) IO pad settings */
__IO uint32_t TESTMODECFG; /* Offset: 0x108 (R/W) Testmode boot bypass */
} CMSDK_SYSCON_TypeDef;
#define CMSDK_SYSCON_REMAP_Pos 0
#define CMSDK_SYSCON_REMAP_Msk (0x01ul << CMSDK_SYSCON_REMAP_Pos) /* CMSDK_SYSCON MEME_CTRL: REMAP Mask */
#define CMSDK_SYSCON_PMUCTRL_EN_Pos 0
#define CMSDK_SYSCON_PMUCTRL_EN_Msk (0x01ul << CMSDK_SYSCON_PMUCTRL_EN_Pos) /* CMSDK_SYSCON PMUCTRL: PMUCTRL ENABLE Mask */
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos 0
#define CMSDK_SYSCON_LOCKUPRST_RESETOP_Msk (0x01ul << CMSDK_SYSCON_LOCKUPRST_RESETOP_Pos) /* CMSDK_SYSCON SYS_CTRL: LOCKUP RESET ENABLE Mask */
#define CMSDK_SYSCON_EMICTRL_SIZE_Pos 24
#define CMSDK_SYSCON_EMICTRL_SIZE_Msk (0x00001ul << CMSDK_SYSCON_EMICTRL_SIZE_Pos) /* CMSDK_SYSCON EMICTRL: SIZE Mask */
#define CMSDK_SYSCON_EMICTRL_TACYC_Pos 16
#define CMSDK_SYSCON_EMICTRL_TACYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_TACYC_Pos) /* CMSDK_SYSCON EMICTRL: TURNAROUNDCYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_WCYC_Pos 8
#define CMSDK_SYSCON_EMICTRL_WCYC_Msk (0x00003ul << CMSDK_SYSCON_EMICTRL_WCYC_Pos) /* CMSDK_SYSCON EMICTRL: WRITECYCLE Mask */
#define CMSDK_SYSCON_EMICTRL_RCYC_Pos 0
#define CMSDK_SYSCON_EMICTRL_RCYC_Msk (0x00007ul << CMSDK_SYSCON_EMICTRL_RCYC_Pos) /* CMSDK_SYSCON EMICTRL: READCYCLE Mask */
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos 0
#define CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_SYSRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: SYSRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos 1
#define CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_WDOGRESETREQ_Pos) /* CMSDK_SYSCON RSTINFO: WDOGRESETREQ Mask */
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
/*------------- PL230 uDMA (PL230) --------------------------------------*/
typedef struct
{
__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
uint32_t RESERVED0[3];
__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
} CMSDK_PL230_TypeDef;
#define PL230_DMA_CHNL_BITS 0
#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
/*------------------- Watchdog ----------------------------------------------*/
typedef struct
{
__IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */
__I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */
__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */
__O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */
__I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */
__I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */
uint32_t RESERVED0[762];
__IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */
uint32_t RESERVED1[191];
__IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */
__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
}CMSDK_WATCHDOG_TypeDef;
#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
/* -------------------- End of section using anonymous unions ------------------- */
#if defined ( __CC_ARM )
#pragma pop
#elif defined(__ICCARM__)
/* leave anonymous unions enabled */
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__TMS470__)
/* anonymous unions are enabled by default */
#elif defined(__TASKING__)
#pragma warning restore
#else
#warning Not supported compiler type
#endif
/* ================================================================================ */
/* ================ Peripheral memory map ================ */
/* ================================================================================ */
/* Peripheral and SRAM base address */
#define CMSDK_FLASH_BASE (0x00000000UL)
#define CMSDK_SRAM_BASE (0x20000000UL)
#define CMSDK_PERIPH_BASE (0x40000000UL)
#define CMSDK_RAM_BASE (0x20000000UL)
#define CMSDK_APB_BASE (0x40000000UL)
#define CMSDK_AHB_BASE (0x40010000UL)
/* APB peripherals */
#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL)
#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL)
#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL)
#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE)
#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL)
#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x5000UL)
#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x4000UL)
#define CMSDK_UART2_BASE (CMSDK_APB_BASE + 0x6000UL)
#define CMSDK_UART3_BASE (CMSDK_APB_BASE + 0x7000UL)
#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL)
#define CMSDK_PL230_BASE (CMSDK_APB_BASE + 0xF000UL)
/* AHB peripherals */
#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL)
#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL)
#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL)
#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL)
#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL)
/* ================================================================================ */
/* ================ Peripheral declaration ================ */
/* ================================================================================ */
#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
#define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE )
#ifdef __cplusplus
}
#endif
#endif /* CMSDK_BEID_H */

616
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/SMM_MPS2.h Normal file
View File

@ -0,0 +1,616 @@
/*
* Copyright:
* ----------------------------------------------------------------
* This confidential and proprietary software may be used only as
* authorised by a licensing agreement from ARM Limited
* (C) COPYRIGHT 2014 ARM Limited
* ALL RIGHTS RESERVED
* The entire notice above must be reproduced on all authorised
* copies and copies may only be made to the extent permitted
* by a licensing agreement from ARM Limited.
* ----------------------------------------------------------------
* File: smm_mps2.h
* Release: Version 1.0
* ----------------------------------------------------------------
*/
#ifndef __SMM_MPS2_H
#define __SMM_MPS2_H
#include "peripherallink.h" /* device specific header file */
#if defined ( __CC_ARM )
#pragma anon_unions
#endif
/******************************************************************************/
/* FPGA System Register declaration */
/******************************************************************************/
typedef struct
{
__IO uint32_t LED; // Offset: 0x000 (R/W) LED connections
// [31:2] : Reserved
// [1:0] : LEDs
uint32_t RESERVED1[1];
__IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons
// [31:2] : Reserved
// [1:0] : Buttons
uint32_t RESERVED2[1];
__IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter
__IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter
__IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter
// Increments when 32-bit prescale counter reach zero
uint32_t RESERVED3[1];
__IO uint32_t PRESCALE; // Offset: 0x020 (R/W) Prescaler
// Bit[31:0] : reload value for prescale counter
__IO uint32_t PSCNTR; // Offset: 0x024 (R/W) 32-bit Prescale counter
// current value of the pre-scaler counter
// The Cycle Up Counter increment when the prescale down counter reach 0
// The pre-scaler counter is reloaded with PRESCALE after reaching 0.
uint32_t RESERVED4[9];
__IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */
// [31:10] : Reserved
// [9] : SHIELD_1_SPI_nCS
// [8] : SHIELD_0_SPI_nCS
// [7] : ADC_SPI_nCS
// [6] : CLCD_BL_CTRL
// [5] : CLCD_RD
// [4] : CLCD_RS
// [3] : CLCD_RESET
// [2] : RESERVED
// [1] : SPI_nSS
// [0] : CLCD_CS
} MPS2_FPGAIO_TypeDef;
// MISC register bit definitions
#define CLCD_CS_Pos 0
#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
#define SPI_nSS_Pos 1
#define SPI_nSS_Msk (1UL<<SPI_nSS_Pos)
#define CLCD_RESET_Pos 3
#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
#define CLCD_RS_Pos 4
#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
#define CLCD_RD_Pos 5
#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
#define CLCD_BL_Pos 6
#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
#define ADC_nCS_Pos 7
#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
#define SHIELD_0_nCS_Pos 8
#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
#define SHIELD_1_nCS_Pos 9
#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
/******************************************************************************/
/* SCC Register declaration */
/******************************************************************************/
typedef struct //
{
__IO uint32_t CFG_REG0; // Offset: 0x000 (R/W) Remaps block RAM to ZBT
// [31:1] : Reserved
// [0] 1 : REMAP BlockRam to ZBT
__IO uint32_t LEDS; // Offset: 0x004 (R/W) Controls the MCC user LEDs
// [31:8] : Reserved
// [7:0] : MCC LEDs
uint32_t RESERVED0[1];
__I uint32_t SWITCHES; // Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
// [31:8] : Reserved
// [7:0] : These bits indicate state of the MCC switches
__I uint32_t CFG_REG4; // Offset: 0x010 (R/ ) Denotes the board revision
// [31:4] : Reserved
// [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
uint32_t RESERVED1[35];
__IO uint32_t SYS_CFGDATA_RTN; // Offset: 0x0A0 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGDATA_OUT; // Offset: 0x0A4 (R/W) User data register
// [31:0] : Data
__IO uint32_t SYS_CFGCTRL; // Offset: 0x0A8 (R/W) Control register
// [31] : Start (generates interrupt on write to this bit)
// [30] : R/W access
// [29:26] : Reserved
// [25:20] : Function value
// [19:12] : Reserved
// [11:0] : Device (value of 0/1/2 for supported clocks)
__IO uint32_t SYS_CFGSTAT; // Offset: 0x0AC (R/W) Contains status information
// [31:2] : Reserved
// [1] : Error
// [0] : Complete
__IO uint32_t RESERVED2[20];
__IO uint32_t SCC_DLL; // Offset: 0x100 (R/W) DLL Lock Register
// [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
// [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
// [15:1] : Reserved
// [0] : This bit indicates if all enabled DLLs are locked
uint32_t RESERVED3[957];
__I uint32_t SCC_AID; // Offset: 0xFF8 (R/ ) SCC AID Register
// [31:24] : FPGA build number
// [23:20] : V2M-MPS2 target board revision (A = 0, B = 1)
// [19:11] : Reserved
// [10] : if “1” SCC_SW register has been implemented
// [9] : if “1” SCC_LED register has been implemented
// [8] : if “1” DLL lock register has been implemented
// [7:0] : number of SCC configuration register
__I uint32_t SCC_ID; // Offset: 0xFFC (R/ ) Contains information about the FPGA image
// [31:24] : Implementer ID: 0x41 = ARM
// [23:20] : Application note IP variant number
// [19:16] : IP Architecture: 0x4 =AHB
// [15:4] : Primary part number: 386 = AN386
// [3:0] : Application note IP revision number
} MPS2_SCC_TypeDef;
/******************************************************************************/
/* SSP Peripheral declaration */
/******************************************************************************/
typedef struct // Document DDI0194G_ssp_pl022_r1p3_trm.pdf
{
__IO uint32_t CR0; // Offset: 0x000 (R/W) Control register 0
// [31:16] : Reserved
// [15:8] : Serial clock rate
// [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
// [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
// [5:4] : Frame format
// [3:0] : Data Size Select
__IO uint32_t CR1; // Offset: 0x004 (R/W) Control register 1
// [31:4] : Reserved
// [3] : Slave-mode output disable
// [2] : Master or slave mode select
// [1] : Synchronous serial port enable
// [0] : Loop back mode
__IO uint32_t DR; // Offset: 0x008 (R/W) Data register
// [31:16] : Reserved
// [15:0] : Transmit/Receive FIFO
__I uint32_t SR; // Offset: 0x00C (R/ ) Status register
// [31:5] : Reserved
// [4] : PrimeCell SSP busy flag
// [3] : Receive FIFO full
// [2] : Receive FIFO not empty
// [1] : Transmit FIFO not full
// [0] : Transmit FIFO empty
__IO uint32_t CPSR; // Offset: 0x010 (R/W) Clock prescale register
// [31:8] : Reserved
// [8:0] : Clock prescale divisor
__IO uint32_t IMSC; // Offset: 0x014 (R/W) Interrupt mask set or clear register
// [31:4] : Reserved
// [3] : Transmit FIFO interrupt mask
// [2] : Receive FIFO interrupt mask
// [1] : Receive timeout interrupt mask
// [0] : Receive overrun interrupt mask
__I uint32_t RIS; // Offset: 0x018 (R/ ) Raw interrupt status register
// [31:4] : Reserved
// [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
// [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
// [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
// [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
__I uint32_t MIS; // Offset: 0x01C (R/ ) Masked interrupt status register
// [31:4] : Reserved
// [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
// [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
// [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
// [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
__O uint32_t ICR; // Offset: 0x020 ( /W) Interrupt clear register
// [31:2] : Reserved
// [1] : Clears the SSPRTINTR interrupt
// [0] : Clears the SSPRORINTR interrupt
__IO uint32_t DMACR; // Offset: 0x024 (R/W) DMA control register
// [31:2] : Reserved
// [1] : Transmit DMA Enable
// [0] : Receive DMA Enable
} MPS2_SSP_TypeDef;
// SSP_CR0 Control register 0
#define SSP_CR0_DSS_Pos 0 // Data Size Select
#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
#define SSP_CR0_FRF_Pos 4 // Frame Format Select
#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
#define SSP_CR0_SPO_Pos 6 // SSPCLKOUT polarity
#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
#define SSP_CR0_SPH_Pos 7 // SSPCLKOUT phase
#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
#define SSP_CR0_SCR_Pos 8 // Serial Clock Rate (divide)
#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
#define SSP_CR0_SCR_DFLT 0x0300 // Serial Clock Rate (divide), default set at 3
#define SSP_CR0_FRF_MOT 0x0000 // Frame format, Motorola
#define SSP_CR0_DSS_8 0x0007 // Data packet size, 8bits
#define SSP_CR0_DSS_16 0x000F // Data packet size, 16bits
// SSP_CR1 Control register 1
#define SSP_CR1_LBM_Pos 0 // Loop Back Mode
#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
#define SSP_CR1_SSE_Pos 1 // Serial port enable
#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
#define SSP_CR1_MS_Pos 2 // Master or Slave mode
#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
#define SSP_CR1_SOD_Pos 3 // Slave Output mode Disable
#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
// SSP_SR Status register
#define SSP_SR_TFE_Pos 0 // Transmit FIFO empty
#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
#define SSP_SR_TNF_Pos 1 // Transmit FIFO not full
#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
#define SSP_SR_RNE_Pos 2 // Receive FIFO not empty
#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
#define SSP_SR_RFF_Pos 3 // Receive FIFO full
#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
#define SSP_SR_BSY_Pos 4 // Busy
#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
// SSP_CPSR Clock prescale register
#define SSP_CPSR_CPD_Pos 0 // Clock prescale divisor
#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
#define SSP_CPSR_DFLT 0x0008 // Clock prescale (use with SCR), default set at 8
// SSPIMSC Interrupt mask set and clear register
#define SSP_IMSC_RORIM_Pos 0 // Receive overrun not Masked
#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
#define SSP_IMSC_RTIM_Pos 1 // Receive timeout not Masked
#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
#define SSP_IMSC_RXIM_Pos 2 // Receive FIFO not Masked
#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
#define SSP_IMSC_TXIM_Pos 3 // Transmit FIFO not Masked
#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
// SSPRIS Raw interrupt status register
#define SSP_RIS_RORRIS_Pos 0 // Raw Overrun interrupt flag
#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
#define SSP_RIS_RTRIS_Pos 1 // Raw Timemout interrupt flag
#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
#define SSP_RIS_RXRIS_Pos 2 // Raw Receive interrupt flag
#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
#define SSP_RIS_TXRIS_Pos 3 // Raw Transmit interrupt flag
#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
// SSPMIS Masked interrupt status register
#define SSP_MIS_RORMIS_Pos 0 // Masked Overrun interrupt flag
#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
#define SSP_MIS_RTMIS_Pos 1 // Masked Timemout interrupt flag
#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
#define SSP_MIS_RXMIS_Pos 2 // Masked Receive interrupt flag
#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
#define SSP_MIS_TXMIS_Pos 3 // Masked Transmit interrupt flag
#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
// SSPICR Interrupt clear register
#define SSP_ICR_RORIC_Pos 0 // Clears Overrun interrupt flag
#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
#define SSP_ICR_RTIC_Pos 1 // Clears Timemout interrupt flag
#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
// SSPDMACR DMA control register
#define SSP_DMACR_RXDMAE_Pos 0 // Enable Receive FIFO DMA
#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
#define SSP_DMACR_TXDMAE_Pos 1 // Enable Transmit FIFO DMA
#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
/******************************************************************************/
/* Audio and Touch Screen (I2C) Peripheral declaration */
/******************************************************************************/
typedef struct
{
union {
__O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W)
__I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ )
};
__O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W)
} MPS2_I2C_TypeDef;
#define SDA 1 << 1
#define SCL 1 << 0
/******************************************************************************/
/* Audio I2S Peripheral declaration */
/******************************************************************************/
typedef struct
{
/*!< Offset: 0x000 CONTROL Register (R/W) */
__IO uint32_t CONTROL; // <h> CONTROL </h>
// <o.0> TX Enable
// <0=> TX disabled
// <1=> TX enabled
// <o.1> TX IRQ Enable
// <0=> TX IRQ disabled
// <1=> TX IRQ enabled
// <o.2> RX Enable
// <0=> RX disabled
// <1=> RX enabled
// <o.3> RX IRQ Enable
// <0=> RX IRQ disabled
// <1=> RX IRQ enabled
// <o.10..8> TX Buffer Water Level
// <0=> / IRQ triggers when any space available
// <1=> / IRQ triggers when more than 1 space available
// <2=> / IRQ triggers when more than 2 space available
// <3=> / IRQ triggers when more than 3 space available
// <4=> Undefined!
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.14..12> RX Buffer Water Level
// <0=> Undefined!
// <1=> / IRQ triggers when less than 1 space available
// <2=> / IRQ triggers when less than 2 space available
// <3=> / IRQ triggers when less than 3 space available
// <4=> / IRQ triggers when less than 4 space available
// <5=> Undefined!
// <6=> Undefined!
// <7=> Undefined!
// <o.16> FIFO reset
// <0=> Normal operation
// <1=> FIFO reset
// <o.17> Audio Codec reset
// <0=> Normal operation
// <1=> Assert audio Codec reset
/*!< Offset: 0x004 STATUS Register (R/ ) */
__I uint32_t STATUS; // <h> STATUS </h>
// <o.0> TX Buffer alert
// <0=> TX buffer don't need service yet
// <1=> TX buffer need service
// <o.1> RX Buffer alert
// <0=> RX buffer don't need service yet
// <1=> RX buffer need service
// <o.2> TX Buffer Empty
// <0=> TX buffer have data
// <1=> TX buffer empty
// <o.3> TX Buffer Full
// <0=> TX buffer not full
// <1=> TX buffer full
// <o.4> RX Buffer Empty
// <0=> RX buffer have data
// <1=> RX buffer empty
// <o.5> RX Buffer Full
// <0=> RX buffer not full
// <1=> RX buffer full
union {
/*!< Offset: 0x008 Error Status Register (R/ ) */
__I uint32_t ERROR; // <h> ERROR </h>
// <o.0> TX error
// <0=> Okay
// <1=> TX overrun/underrun
// <o.1> RX error
// <0=> Okay
// <1=> RX overrun/underrun
/*!< Offset: 0x008 Error Clear Register ( /W) */
__O uint32_t ERRORCLR; // <h> ERRORCLR </h>
// <o.0> TX error
// <0=> Okay
// <1=> Clear TX error
// <o.1> RX error
// <0=> Okay
// <1=> Clear RX error
};
/*!< Offset: 0x00C Divide ratio Register (R/W) */
__IO uint32_t DIVIDE; // <h> Divide ratio for Left/Right clock </h>
// <o.9..0> TX error (default 0x80)
/*!< Offset: 0x010 Transmit Buffer ( /W) */
__O uint32_t TXBUF; // <h> Transmit buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
/*!< Offset: 0x014 Receive Buffer (R/ ) */
__I uint32_t RXBUF; // <h> Receive buffer </h>
// <o.15..0> Right channel
// <o.31..16> Left channel
uint32_t RESERVED1[186];
__IO uint32_t ITCR; // <h> Integration Test Control Register </h>
// <o.0> ITEN
// <0=> Normal operation
// <1=> Integration Test mode enable
__O uint32_t ITIP1; // <h> Integration Test Input Register 1</h>
// <o.0> SDIN
__O uint32_t ITOP1; // <h> Integration Test Output Register 1</h>
// <o.0> SDOUT
// <o.1> SCLK
// <o.2> LRCK
// <o.3> IRQOUT
} MPS2_I2S_TypeDef;
#define I2S_CONTROL_TXEN_Pos 0
#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
#define I2S_CONTROL_TXIRQEN_Pos 1
#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
#define I2S_CONTROL_RXEN_Pos 2
#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
#define I2S_CONTROL_RXIRQEN_Pos 3
#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
#define I2S_CONTROL_TXWLVL_Pos 8
#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
#define I2S_CONTROL_RXWLVL_Pos 12
#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
/* FIFO reset*/
#define I2S_CONTROL_FIFORST_Pos 16
#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
/* Codec reset*/
#define I2S_CONTROL_CODECRST_Pos 17
#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
#define I2S_STATUS_TXIRQ_Pos 0
#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
#define I2S_STATUS_RXIRQ_Pos 1
#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
#define I2S_STATUS_TXEmpty_Pos 2
#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
#define I2S_STATUS_TXFull_Pos 3
#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
#define I2S_STATUS_RXEmpty_Pos 4
#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
#define I2S_STATUS_RXFull_Pos 5
#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
#define I2S_ERROR_TXERR_Pos 0
#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
#define I2S_ERROR_RXERR_Pos 1
#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
/******************************************************************************/
/* SMSC9220 Register Definitions */
/******************************************************************************/
typedef struct // SMSC LAN9220
{
__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0)
uint32_t RESERVED1[0x7];
__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20)
uint32_t RESERVED2[0x7];
__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40)
__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44)
__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48)
__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C)
__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50)
__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54)
__IO uint32_t INT_STS; // Interrupt Status (offset 0x58)
__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C)
uint32_t RESERVED3; // Reserved for future use (offset 0x60)
__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64)
__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68)
__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C)
__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70)
__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74)
__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78)
__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C)
__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80)
__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84)
__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88)
__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C)
__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90)
uint32_t RESERVED4; // Reserved for future use (offset 0x94)
__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98)
__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C)
__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0)
__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4)
__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8)
__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC)
__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0)
__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
} SMSC9220_TypeDef;
// SMSC9220 MAC Registers Indices
#define SMSC9220_MAC_CR 0x1
#define SMSC9220_MAC_ADDRH 0x2
#define SMSC9220_MAC_ADDRL 0x3
#define SMSC9220_MAC_HASHH 0x4
#define SMSC9220_MAC_HASHL 0x5
#define SMSC9220_MAC_MII_ACC 0x6
#define SMSC9220_MAC_MII_DATA 0x7
#define SMSC9220_MAC_FLOW 0x8
#define SMSC9220_MAC_VLAN1 0x9
#define SMSC9220_MAC_VLAN2 0xA
#define SMSC9220_MAC_WUFF 0xB
#define SMSC9220_MAC_WUCSR 0xC
// SMSC9220 PHY Registers Indices
#define SMSC9220_PHY_BCONTROL 0x0
#define SMSC9220_PHY_BSTATUS 0x1
#define SMSC9220_PHY_ID1 0x2
#define SMSC9220_PHY_ID2 0x3
#define SMSC9220_PHY_ANEG_ADV 0x4
#define SMSC9220_PHY_ANEG_LPA 0x5
#define SMSC9220_PHY_ANEG_EXP 0x6
#define SMSC9220_PHY_MCONTROL 0x17
#define SMSC9220_PHY_MSTATUS 0x18
#define SMSC9220_PHY_CSINDICATE 0x27
#define SMSC9220_PHY_INTSRC 0x29
#define SMSC9220_PHY_INTMASK 0x30
#define SMSC9220_PHY_CS 0x31
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
#define MPS2_SSP0_BASE (0x40020000ul) /* User SSP Base Address */
#define MPS2_SSP1_BASE (0x40021000ul) /* CLCD SSP Base Address */
#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
#define MPS2_SSP3_BASE (0x40026000ul) /* shield 0 SSP Base Address */
#define MPS2_SSP4_BASE (0x40027000ul) /* shield 1 SSP Base Address */
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* Audio Interface I2C Base Address */
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* Audio Interface I2C Base Address */
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
#ifdef CORTEX_M7
#define SMSC9220_BASE (0xA0000000ul) /* Ethernet SMSC9220 Base Address */
#else
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
#endif
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
/******************************************************************************/
/* Peripheral declaration */
/******************************************************************************/
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
//******************************************************************************/
/* General MACRO Definitions */
/******************************************************************************/
//#define DEBUG
//#ifdef DEBUG
// #define debug(...) printf(__VA_ARGS__)
//#else
// #define debug(...)
//#endif // ifdef DEBUG
// Bit control macros
//#define HW_REG(base,offset) *((volatile unsigned int *)((base) + (offset)))
#define CREATE_MASK(msb, lsb) (((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
#define MASK_BITS(arg, msb, lsb) ((arg) & CREATE_MASK(msb, lsb))
#define EXTRACT_BITS(arg, msb, lsb) (MASK_BITS(arg, msb, lsb) >> (lsb))
#define INSERT_BITS(arg, msb, lsb, value) \
((arg) = ((arg) & ~CREATE_MASK(msb, lsb)) | (((value) << (lsb)) & CREATE_MASK(msb, lsb)))
#define MASK_FIELD(arg, field) MASK_BITS(arg, field##_MSB, field##_LSB)
#define EXTRACT_FIELD(arg, field) EXTRACT_BITS(arg, field##_MSB, field##_LSB)
#define INSERT_FIELD(arg, field, value) INSERT_BITS(arg, field##_MSB, field##_LSB, value)
#define SET_BIT(arg, bit) ((arg) |= (1 << (bit)))
#define CLEAR_BIT(arg, bit) ((arg) &= ~(1 << (bit)))
#define TEST_BIT(arg, bit) ((arg) & (1 << (bit)))
#ifndef NoOfElements
#define NoOfElements(array) (sizeof(array) / sizeof(array[0]))
#endif
#endif /* __SMM_MPS2_H */

15
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/MPS2.sct Normal file
View File

@ -0,0 +1,15 @@
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
LR_IROM1 0x00000000 0x00400000 { ; load region size_region
ER_IROM1 +0 { ; load address = execution address
*.o (RESET, +FIRST)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 +0 { ; RW data
.ANY (+RW +ZI)
}
}

291
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/TOOLCHAIN_ARM_STD/startup_MPS2.s Normal file
View File

@ -0,0 +1,291 @@
;/**************************************************************************//**
; * @file startup_CMSDK_CM3.s
; * @brief CMSIS Core Device Startup File for
; * CMSDK_CM3 Device
; * @version V3.02
; * @date 15. November 2013
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; ******************************************************************************/
;/* Copyright (c) 2011 - 2013 ARM LIMITED
;
; All rights reserved.
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; - Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; - Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; - Neither the name of ARM nor the names of its contributors may be used
; to endorse or promote products derived from this software without
; specific prior written permission.
; *
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
; POSSIBILITY OF SUCH DAMAGE.
; ---------------------------------------------------------------------------*/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00004000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00001000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD UARTRX0_Handler ; UART 0 RX Handler
DCD UARTTX0_Handler ; UART 0 TX Handler
DCD UARTRX1_Handler ; UART 1 RX Handler
DCD UARTTX1_Handler ; UART 1 TX Handler
DCD UARTRX2_Handler ; UART 2 RX Handler
DCD UARTTX2_Handler ; UART 2 TX Handler
DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler
DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler
DCD TIMER0_Handler ; TIMER 0 handler
DCD TIMER1_Handler ; TIMER 1 handler
DCD DUALTIMER_HANDLER ; Dual timer handler
DCD SPI_Handler ; SPI exceptions Handler
DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler
DCD ETHERNET_Handler ; Ethernet Overflow Handler
DCD I2S_Handler ; I2S Handler
DCD TSC_Handler ; Touch Screen handler
DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler
DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler
DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler
DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler
DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler
DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler
DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler
DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler
DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler
DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler
DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler
DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler
DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler
DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler
DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler
DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT UARTRX0_Handler [WEAK]
EXPORT UARTTX0_Handler [WEAK]
EXPORT UARTRX1_Handler [WEAK]
EXPORT UARTTX1_Handler [WEAK]
EXPORT UARTRX2_Handler [WEAK]
EXPORT UARTTX2_Handler [WEAK]
EXPORT PORT0_COMB_Handler [WEAK]
EXPORT PORT1_COMB_Handler [WEAK]
EXPORT TIMER0_Handler [WEAK]
EXPORT TIMER1_Handler [WEAK]
EXPORT DUALTIMER_HANDLER [WEAK]
EXPORT SPI_Handler [WEAK]
EXPORT UARTOVF_Handler [WEAK]
EXPORT ETHERNET_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
EXPORT TSC_Handler [WEAK]
EXPORT PORT0_0_Handler [WEAK]
EXPORT PORT0_1_Handler [WEAK]
EXPORT PORT0_2_Handler [WEAK]
EXPORT PORT0_3_Handler [WEAK]
EXPORT PORT0_4_Handler [WEAK]
EXPORT PORT0_5_Handler [WEAK]
EXPORT PORT0_6_Handler [WEAK]
EXPORT PORT0_7_Handler [WEAK]
EXPORT PORT0_8_Handler [WEAK]
EXPORT PORT0_9_Handler [WEAK]
EXPORT PORT0_10_Handler [WEAK]
EXPORT PORT0_11_Handler [WEAK]
EXPORT PORT0_12_Handler [WEAK]
EXPORT PORT0_13_Handler [WEAK]
EXPORT PORT0_14_Handler [WEAK]
EXPORT PORT0_15_Handler [WEAK]
UARTRX0_Handler
UARTTX0_Handler
UARTRX1_Handler
UARTTX1_Handler
UARTRX2_Handler
UARTTX2_Handler
PORT0_COMB_Handler
PORT1_COMB_Handler
TIMER0_Handler
TIMER1_Handler
DUALTIMER_HANDLER
SPI_Handler
UARTOVF_Handler
ETHERNET_Handler
I2S_Handler
TSC_Handler
PORT0_0_Handler
PORT0_1_Handler
PORT0_2_Handler
PORT0_3_Handler
PORT0_4_Handler
PORT0_5_Handler
PORT0_6_Handler
PORT0_7_Handler
PORT0_8_Handler
PORT0_9_Handler
PORT0_10_Handler
PORT0_11_Handler
PORT0_12_Handler
PORT0_13_Handler
PORT0_14_Handler
PORT0_15_Handler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
END

14
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis.h Normal file
View File

@ -0,0 +1,14 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC1768 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "CMSDK_BEID.h"
#include "SMM_MPS2.h"
#include "cmsis_nvic.h"
#endif

30
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.c Normal file
View File

@ -0,0 +1,30 @@
/* mbed Microcontroller Library - cmsis_nvic for LCP1768
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Location of vectors in RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
uint32_t i;
// Copy and switch to dynamic vectors if the first time called
if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
uint32_t *old_vectors = vectors;
vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
for (i=0; i<NVIC_NUM_VECTORS; i++) {
vectors[i] = old_vectors[i];
}
SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
}
vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)SCB->VTOR;
return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
}

26
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/cmsis_nvic.h Normal file
View File

@ -0,0 +1,26 @@
/* mbed Microcontroller Library - cmsis_nvic
* Copyright (c) 2009-2011 ARM Limited. All rights reserved.
*
* CMSIS-style functionality to support dynamic vectors
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#include "cmsis.h"
#define NVIC_NUM_VECTORS (16 + 32)
#define NVIC_USER_IRQ_OFFSET 16
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

34
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/peripherallink.h Normal file
View File

@ -0,0 +1,34 @@
/*-----------------------------------------------------------------------------
* Name: Device.h
* Purpose: Include the correct device header file
*-----------------------------------------------------------------------------
* This file is part of the uVision/ARM development tools.
* This software may only be used under the terms of a valid, current,
* end user licence from KEIL for a compatible version of KEIL software
* development tools. Nothing else gives you the right to use this software.
*
* This software is supplied "AS IS" without warranties of any kind.
*
* Copyright (c) 2013 KEIL - An ARM Company. All rights reserved.
*----------------------------------------------------------------------------*/
#ifndef __DEVICE_H
#define __DEVICE_H
#if defined CMSDK_CM0
#include "CMSDK_CM0.h" /* device specific header file */
#elif defined CMSDK_CM0plus
#include "CMSDK_CM0plus.h" /* device specific header file */
#elif defined CMSDK_CM3
#include "CMSDK_CM3.h" /* device specific header file */
#elif defined CMSDK_CM4
#include "CMSDK_CM4.h" /* device specific header file */
#elif defined CMSDK_CM7
#include "CMSDK_CM7.h" /* device specific header file */
#elif defined CMSDK_BEID
#include "CMSDK_BEID.h" /* device specific header file */
#else
#warning "no appropriate header file found!"
#endif
#endif /* __DEVICE_H */

95
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.c Normal file
View File

@ -0,0 +1,95 @@
/**************************************************************************//**
* @file system_CMSDK_BEID.c
* @brief CMSIS Device System Source File for
* CMSDK_M3 Device
* @version V3.02
* @date 15. November 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#include "CMSDK_BEID.h"
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define __XTAL (50000000UL) /* Oscillator frequency */
#define __SYSTEM_CLOCK (__XTAL / 2)
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate (void)
{
SystemCoreClock = __SYSTEM_CLOCK;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
#ifdef UNALIGNED_SUPPORT_DISABLE
SCB->CCR |= SCB_CCR_UNALIGN_TRP_Msk;
#endif
SystemCoreClock = __SYSTEM_CLOCK;
// Enable AHB and APB clock
CMSDK_SYSCON->AHBCLKCFG0SET = 0xF; // GPIO
CMSDK_SYSCON->APBCLKCFG0SET = 0x37; // UART0, UART1, TIMER0, TIMER1, DUAL TIMER
}

75
libraries/mbed/targets/cmsis/TARGET_ARM_SSG/TARGET_MPS2_BEID/system_CMSDK_BEID.h Normal file
View File

@ -0,0 +1,75 @@
/**************************************************************************//**
* @file system_CMSDK_BEID.h
* @brief CMSIS Device Peripheral Access Layer Header File for
* CMSDK_BEID Device
* @version V3.02
* @date 15. March 2013
*
* @note
*
******************************************************************************/
/* Copyright (c) 2011 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_CMSDK_BEID_H
#define SYSTEM_CMSDK_BEID_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_CMSDK_BEID_H */

53
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMD21/TARGET_SAMD21J18A/TOOLCHAIN_GCC_ARM/samd21j18a.ld
View File

@ -3,19 +3,17 @@ OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(4);
_sfixed = .;
@ -66,23 +64,24 @@ SECTIONS
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.dvectors (NOLOAD) :
{
_sdvectors = .;
. = . + 0xB0;
_edvectors = .;
} > ram
.relocate : AT (_etext)
.dvectors (NOLOAD) :
{
_sdvectors = .;
. = . + 0xB0;
_edvectors = .;
} > ram
.relocate :
AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
@ -105,12 +104,12 @@ SECTIONS
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(4);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(4);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
/* stack section */
.stack (NOLOAD):

53
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_GCC_ARM/samr21g18a.ld
View File

@ -3,19 +3,17 @@ OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(4);
_sfixed = .;
@ -66,23 +64,24 @@ SECTIONS
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.dvectors (NOLOAD) :
{
_sdvectors = .;
. = . + 0xB0;
_edvectors = .;
} > ram
.relocate : AT (_etext)
.dvectors (NOLOAD) :
{
_sdvectors = .;
. = . + 0xB0;
_edvectors = .;
} > ram
.relocate :
AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
@ -105,12 +104,12 @@ SECTIONS
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(4);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(4);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
} > ram
/* stack section */
.stack (NOLOAD):

145
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/TARGET_SAMR21/TARGET_SAMR21G18A/TOOLCHAIN_IAR/startup_samr21.c
View File

@ -42,7 +42,10 @@
#include "samr21.h"
typedef void (*intfunc) (void);
typedef union { intfunc __fun; void * __ptr; } intvec_elem;
typedef union {
intfunc __fun;
void * __ptr;
} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
@ -116,89 +119,89 @@ void Dummy_Handler(void);
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) USB_Handler, /* 7 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef ID_TC6
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC7
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_ADC
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) AC_Handler, /* 24 Analog Comparators */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved*/
(void*) (0UL), /* Reserved*/
#endif
(void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
(void*) (0UL), /* Reserved */
(void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
(void*) (0UL), /* Reserved */
};
/**------------------------------------------------------------------------------
@ -207,11 +210,11 @@ const DeviceVectors __vector_table[] = {
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
@ -220,20 +223,20 @@ int __low_level_init(void)
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
/* Change default QOS values to have the best performance and correct USB behaviour */
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
/* Change default QOS values to have the best performance and correct USB behaviour */
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
#if defined(ID_USB)
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
#endif
DMAC->QOSCTRL.bit.DQOS = 2;
DMAC->QOSCTRL.bit.FQOS = 2;
DMAC->QOSCTRL.bit.WRBQOS = 2;
DMAC->QOSCTRL.bit.DQOS = 2;
DMAC->QOSCTRL.bit.FQOS = 2;
DMAC->QOSCTRL.bit.WRBQOS = 2;
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
__iar_program_start();
__iar_program_start();
}
/**
@ -241,6 +244,6 @@ void Reset_Handler(void)
*/
void Dummy_Handler(void)
{
while (1) {
}
while (1) {
}
}

322
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_ac.h
View File

@ -59,14 +59,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -87,16 +87,16 @@ typedef union {
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -115,25 +115,25 @@ typedef union {
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -164,20 +164,20 @@ typedef union {
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -201,20 +201,20 @@ typedef union {
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -238,20 +238,20 @@ typedef union {
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -275,18 +275,18 @@ typedef union {
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -314,17 +314,17 @@ typedef union {
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -345,18 +345,18 @@ typedef union {
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -384,12 +384,12 @@ typedef union {
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -414,26 +414,26 @@ typedef union {
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,11 +519,11 @@ typedef union {
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -538,22 +538,22 @@ typedef union {
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

308
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_adc.h
View File

@ -59,13 +59,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -83,12 +83,12 @@ typedef union {
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -115,12 +115,12 @@ typedef union {
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -160,11 +160,11 @@ typedef union {
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -179,17 +179,17 @@ typedef union {
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -239,11 +239,11 @@ typedef union {
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -268,12 +268,12 @@ typedef union {
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -289,17 +289,17 @@ typedef union {
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -408,15 +408,15 @@ typedef union {
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -436,14 +436,14 @@ typedef union {
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -463,14 +463,14 @@ typedef union {
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -490,14 +490,14 @@ typedef union {
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -517,11 +517,11 @@ typedef union {
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -535,10 +535,10 @@ typedef union {
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -553,10 +553,10 @@ typedef union {
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -571,10 +571,10 @@ typedef union {
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -589,11 +589,11 @@ typedef union {
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -608,11 +608,11 @@ typedef union {
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -627,12 +627,12 @@ typedef union {
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -650,11 +650,11 @@ typedef union {
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -668,32 +668,32 @@ typedef union {
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

136
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dac.h
View File

@ -59,13 +59,13 @@
/* -------- DAC_CTRLA : (DAC Offset: 0x0) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -83,16 +83,16 @@ typedef union {
/* -------- DAC_CTRLB : (DAC Offset: 0x1) (R/W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
uint8_t :1; /*!< bit: 5 Reserved */
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EOEN:1; /*!< bit: 0 External Output Enable */
uint8_t IOEN:1; /*!< bit: 1 Internal Output Enable */
uint8_t LEFTADJ:1; /*!< bit: 2 Left Adjusted Data */
uint8_t VPD:1; /*!< bit: 3 Voltage Pump Disable */
uint8_t BDWP:1; /*!< bit: 4 Bypass DATABUF Write Protection */
uint8_t :1; /*!< bit: 5 Reserved */
uint8_t REFSEL:2; /*!< bit: 6.. 7 Reference Selection */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -123,12 +123,12 @@ typedef union {
/* -------- DAC_EVCTRL : (DAC Offset: 0x2) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event Input */
uint8_t EMPTYEO:1; /*!< bit: 1 Data Buffer Empty Event Output */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -144,13 +144,13 @@ typedef union {
/* -------- DAC_INTENCLR : (DAC Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -168,13 +168,13 @@ typedef union {
/* -------- DAC_INTENSET : (DAC Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun Interrupt Enable */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -192,13 +192,13 @@ typedef union {
/* -------- DAC_INTFLAG : (DAC Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t UNDERRUN:1; /*!< bit: 0 Underrun */
uint8_t EMPTY:1; /*!< bit: 1 Data Buffer Empty */
uint8_t SYNCRDY:1; /*!< bit: 2 Synchronization Ready */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -216,11 +216,11 @@ typedef union {
/* -------- DAC_STATUS : (DAC Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DAC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -234,10 +234,10 @@ typedef union {
/* -------- DAC_DATA : (DAC Offset: 0x8) (R/W 16) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DATA:16; /*!< bit: 0..15 Data value to be converted */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -252,10 +252,10 @@ typedef union {
/* -------- DAC_DATABUF : (DAC Offset: 0xC) (R/W 16) Data Buffer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DATABUF:16; /*!< bit: 0..15 Data Buffer */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DAC_DATABUF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -270,17 +270,17 @@ typedef union {
/** \brief DAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
RoReg8 Reserved2[0x2];
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
__IO DAC_CTRLA_Type CTRLA; /**< \brief Offset: 0x0 (R/W 8) Control A */
__IO DAC_CTRLB_Type CTRLB; /**< \brief Offset: 0x1 (R/W 8) Control B */
__IO DAC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x2 (R/W 8) Event Control */
RoReg8 Reserved1[0x1];
__IO DAC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO DAC_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO DAC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I DAC_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__IO DAC_DATA_Type DATA; /**< \brief Offset: 0x8 (R/W 16) Data */
RoReg8 Reserved2[0x2];
__IO DAC_DATABUF_Type DATABUF; /**< \brief Offset: 0xC (R/W 16) Data Buffer */
} Dac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

594
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dmac.h
View File

@ -59,23 +59,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :8; /*!< bit: 0.. 7 Reserved */
uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :8; /*!< bit: 0.. 7 Reserved */
uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -104,14 +104,14 @@ typedef union {
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -146,10 +146,10 @@ typedef union {
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -164,10 +164,10 @@ typedef union {
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -182,12 +182,12 @@ typedef union {
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -203,11 +203,11 @@ typedef union {
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -221,13 +221,13 @@ typedef union {
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -272,26 +272,26 @@ typedef union {
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -330,21 +330,21 @@ typedef union {
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
uint32_t :3; /*!< bit: 4.. 6 Reserved */
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
uint32_t :3; /*!< bit: 20..22 Reserved */
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
uint32_t :3; /*!< bit: 28..30 Reserved */
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
uint32_t :3; /*!< bit: 4.. 6 Reserved */
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
uint32_t :3; /*!< bit: 20..22 Reserved */
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
uint32_t :3; /*!< bit: 28..30 Reserved */
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -376,18 +376,18 @@ typedef union {
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
uint16_t :2; /*!< bit: 11..12 Reserved */
uint16_t FERR:1; /*!< bit: 13 Fetch Error */
uint16_t BUSY:1; /*!< bit: 14 Busy */
uint16_t PEND:1; /*!< bit: 15 Pending */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
uint16_t :2; /*!< bit: 11..12 Reserved */
uint16_t FERR:1; /*!< bit: 13 Fetch Error */
uint16_t BUSY:1; /*!< bit: 14 Busy */
uint16_t PEND:1; /*!< bit: 15 Pending */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -414,26 +414,26 @@ typedef union {
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -472,26 +472,26 @@ typedef union {
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -530,26 +530,26 @@ typedef union {
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -588,22 +588,22 @@ typedef union {
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
} bit; /*!< Structure used for bit access */
struct {
uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
} bit; /*!< Structure used for bit access */
struct {
uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -634,10 +634,10 @@ typedef union {
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -652,10 +652,10 @@ typedef union {
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -670,11 +670,11 @@ typedef union {
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -689,12 +689,12 @@ typedef union {
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -710,19 +710,19 @@ typedef union {
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
uint32_t :8; /*!< bit: 14..21 Reserved */
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TRIGSRC:6; /*!< bit: 8..13 Peripheral Trigger Source */
uint32_t :8; /*!< bit: 14..21 Reserved */
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -789,13 +789,13 @@ typedef union {
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -813,13 +813,13 @@ typedef union {
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -837,13 +837,13 @@ typedef union {
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Transfer Error */
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Transfer Error */
uint8_t TCMPL:1; /*!< bit: 1 Transfer Complete */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -861,13 +861,13 @@ typedef union {
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PEND:1; /*!< bit: 0 Channel Pending */
uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
uint8_t FERR:1; /*!< bit: 2 Fetch Error */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PEND:1; /*!< bit: 0 Channel Pending */
uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
uint8_t FERR:1; /*!< bit: 2 Fetch Error */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -885,18 +885,18 @@ typedef union {
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -967,10 +967,10 @@ typedef union {
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -984,10 +984,10 @@ typedef union {
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1001,10 +1001,10 @@ typedef union {
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1018,10 +1018,10 @@ typedef union {
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1035,49 +1035,49 @@ typedef union {
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
__IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
__IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
__IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
__IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
__IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
RoReg8 Reserved1[0x1];
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
__IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
RoReg8 Reserved2[0x8];
__IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
RoReg8 Reserved3[0x2];
__I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
__I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
__I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
__IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
__IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
RoReg8 Reserved4[0x3];
__IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
RoReg8 Reserved5[0x3];
__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
RoReg8 Reserved6[0x4];
__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
__IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
__I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
__IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
__IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
__IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
__IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
__IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
__IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
RoReg8 Reserved1[0x1];
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
__IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
RoReg8 Reserved2[0x8];
__IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
RoReg8 Reserved3[0x2];
__I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
__I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
__I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
__IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
__IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
RoReg8 Reserved4[0x3];
__IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
RoReg8 Reserved5[0x3];
__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
RoReg8 Reserved6[0x4];
__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
__IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
__I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Transfer Source Address */
__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Transfer Destination Address */
__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
__attribute__ ((aligned (8)))
__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

302
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_dsu.h
View File

@ -59,15 +59,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -87,15 +87,15 @@ typedef union {
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAIL:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAIL:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -117,20 +117,20 @@ typedef union {
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -155,11 +155,11 @@ typedef union {
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -174,11 +174,11 @@ typedef union {
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -193,10 +193,10 @@ typedef union {
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -211,10 +211,10 @@ typedef union {
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -229,16 +229,16 @@ typedef union {
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -267,13 +267,13 @@ typedef union {
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -292,10 +292,10 @@ typedef union {
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -310,11 +310,11 @@ typedef union {
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -328,12 +328,12 @@ typedef union {
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -351,11 +351,11 @@ typedef union {
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -370,12 +370,12 @@ typedef union {
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -393,13 +393,13 @@ typedef union {
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -419,12 +419,12 @@ typedef union {
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -442,11 +442,11 @@ typedef union {
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -461,12 +461,12 @@ typedef union {
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -484,11 +484,11 @@ typedef union {
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -503,11 +503,11 @@ typedef union {
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -522,30 +522,30 @@ typedef union {
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

342
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_eic.h
View File

@ -59,12 +59,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -80,11 +80,11 @@ typedef union {
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -98,12 +98,12 @@ typedef union {
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -132,11 +132,11 @@ typedef union {
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -150,30 +150,30 @@ typedef union {
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -220,30 +220,30 @@ typedef union {
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -290,30 +290,30 @@ typedef union {
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -360,30 +360,30 @@ typedef union {
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -430,30 +430,30 @@ typedef union {
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -500,25 +500,25 @@ typedef union {
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -666,16 +666,16 @@ typedef union {
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

366
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_evsys.h
View File

@ -59,13 +59,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -81,18 +81,18 @@ typedef union {
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -132,13 +132,13 @@ typedef union {
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -158,43 +158,43 @@ typedef union {
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -266,43 +266,43 @@ typedef union {
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -374,43 +374,43 @@ typedef union {
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -482,43 +482,43 @@ typedef union {
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -590,15 +590,15 @@ typedef union {
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

90
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_gclk.h
View File

@ -59,11 +59,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -77,11 +77,11 @@ typedef union {
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -95,15 +95,15 @@ typedef union {
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -215,20 +215,20 @@ typedef union {
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -276,13 +276,13 @@ typedef union {
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -300,11 +300,11 @@ typedef union {
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

24
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_hmatrixb.h
View File

@ -59,7 +59,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -71,7 +71,7 @@ typedef union {
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -83,10 +83,10 @@ typedef union {
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -101,18 +101,18 @@ typedef union {
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
RoReg8 Reserved2[0x10];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
RoReg8 Reserved2[0x10];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

362
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_i2s.h
View File

@ -59,22 +59,22 @@
/* -------- I2S_CTRLA : (I2S Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable */
uint8_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable */
uint8_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable */
uint8_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable */
uint8_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} I2S_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -104,26 +104,26 @@ typedef union {
/* -------- I2S_CLKCTRL : (I2S Offset: 0x04) (R/W 32) Clock Unit n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
uint32_t :2; /*!< bit: 9..10 Reserved */
uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
uint32_t :1; /*!< bit: 17 Reserved */
uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SLOTSIZE:2; /*!< bit: 0.. 1 Slot Size */
uint32_t NBSLOTS:3; /*!< bit: 2.. 4 Number of Slots in Frame */
uint32_t FSWIDTH:2; /*!< bit: 5.. 6 Frame Sync Width */
uint32_t BITDELAY:1; /*!< bit: 7 Data Delay from Frame Sync */
uint32_t FSSEL:1; /*!< bit: 8 Frame Sync Select */
uint32_t :2; /*!< bit: 9..10 Reserved */
uint32_t FSINV:1; /*!< bit: 11 Frame Sync Invert */
uint32_t SCKSEL:1; /*!< bit: 12 Serial Clock Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t MCKSEL:1; /*!< bit: 16 Master Clock Select */
uint32_t :1; /*!< bit: 17 Reserved */
uint32_t MCKEN:1; /*!< bit: 18 Master Clock Enable */
uint32_t MCKDIV:5; /*!< bit: 19..23 Master Clock Division Factor */
uint32_t MCKOUTDIV:5; /*!< bit: 24..28 Master Clock Output Division Factor */
uint32_t FSOUTINV:1; /*!< bit: 29 Frame Sync Output Invert */
uint32_t SCKOUTINV:1; /*!< bit: 30 Serial Clock Output Invert */
uint32_t MCKOUTINV:1; /*!< bit: 31 Master Clock Output Invert */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -200,31 +200,31 @@ typedef union {
/* -------- I2S_INTENCLR : (I2S Offset: 0x0C) (R/W 16) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -264,31 +264,31 @@ typedef union {
/* -------- I2S_INTENSET : (I2S Offset: 0x10) (R/W 16) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 Interrupt Enable */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 Interrupt Enable */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 Interrupt Enable */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 Interrupt Enable */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x Interrupt Enable */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x Interrupt Enable */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x Interrupt Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -328,31 +328,31 @@ typedef union {
/* -------- I2S_INTFLAG : (I2S Offset: 0x14) (R/W 16) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
uint16_t TXUR1:1; /*!< bit: 13 Transmit Underrun 1 */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t RXRDY:2; /*!< bit: 0.. 1 Receive Ready x */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t RXOR:2; /*!< bit: 4.. 5 Receive Overrun x */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t TXRDY:2; /*!< bit: 8.. 9 Transmit Ready x */
uint16_t :2; /*!< bit: 10..11 Reserved */
uint16_t TXUR:2; /*!< bit: 12..13 Transmit Underrun x */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -392,27 +392,27 @@ typedef union {
/* -------- I2S_SYNCBUSY : (I2S Offset: 0x18) (R/ 16) Synchronization Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset Synchronization Status */
uint16_t ENABLE:1; /*!< bit: 1 Enable Synchronization Status */
uint16_t CKEN0:1; /*!< bit: 2 Clock Unit 0 Enable Synchronization Status */
uint16_t CKEN1:1; /*!< bit: 3 Clock Unit 1 Enable Synchronization Status */
uint16_t SEREN0:1; /*!< bit: 4 Serializer 0 Enable Synchronization Status */
uint16_t SEREN1:1; /*!< bit: 5 Serializer 1 Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA0:1; /*!< bit: 8 Data 0 Synchronization Status */
uint16_t DATA1:1; /*!< bit: 9 Data 1 Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :2; /*!< bit: 0.. 1 Reserved */
uint16_t CKEN:2; /*!< bit: 2.. 3 Clock Unit x Enable Synchronization Status */
uint16_t SEREN:2; /*!< bit: 4.. 5 Serializer x Enable Synchronization Status */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t DATA:2; /*!< bit: 8.. 9 Data x Synchronization Status */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} I2S_SYNCBUSY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -449,37 +449,37 @@ typedef union {
/* -------- I2S_SERCTRL : (I2S Offset: 0x20) (R/W 32) Serializer n Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SERMODE:2; /*!< bit: 0.. 1 Serializer Mode */
uint32_t TXDEFAULT:2; /*!< bit: 2.. 3 Line Default Line when Slot Disabled */
uint32_t TXSAME:1; /*!< bit: 4 Transmit Data when Underrun */
uint32_t CLKSEL:1; /*!< bit: 5 Clock Unit Selection */
uint32_t :1; /*!< bit: 6 Reserved */
uint32_t SLOTADJ:1; /*!< bit: 7 Data Slot Formatting Adjust */
uint32_t DATASIZE:3; /*!< bit: 8..10 Data Word Size */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WORDADJ:1; /*!< bit: 12 Data Word Formatting Adjust */
uint32_t EXTEND:2; /*!< bit: 13..14 Data Formatting Bit Extension */
uint32_t BITREV:1; /*!< bit: 15 Data Formatting Bit Reverse */
uint32_t SLOTDIS0:1; /*!< bit: 16 Slot 0 Disabled for this Serializer */
uint32_t SLOTDIS1:1; /*!< bit: 17 Slot 1 Disabled for this Serializer */
uint32_t SLOTDIS2:1; /*!< bit: 18 Slot 2 Disabled for this Serializer */
uint32_t SLOTDIS3:1; /*!< bit: 19 Slot 3 Disabled for this Serializer */
uint32_t SLOTDIS4:1; /*!< bit: 20 Slot 4 Disabled for this Serializer */
uint32_t SLOTDIS5:1; /*!< bit: 21 Slot 5 Disabled for this Serializer */
uint32_t SLOTDIS6:1; /*!< bit: 22 Slot 6 Disabled for this Serializer */
uint32_t SLOTDIS7:1; /*!< bit: 23 Slot 7 Disabled for this Serializer */
uint32_t MONO:1; /*!< bit: 24 Mono Mode */
uint32_t DMA:1; /*!< bit: 25 Single or Multiple DMA Channels */
uint32_t RXLOOP:1; /*!< bit: 26 Loop-back Test Mode */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t :16; /*!< bit: 0..15 Reserved */
uint32_t SLOTDIS:8; /*!< bit: 16..23 Slot x Disabled for this Serializer */
uint32_t :8; /*!< bit: 24..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} I2S_SERCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -602,10 +602,10 @@ typedef union {
/* -------- I2S_DATA : (I2S Offset: 0x30) (R/W 32) Data n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Sample Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} I2S_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -620,20 +620,20 @@ typedef union {
/** \brief I2S hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
RoReg8 Reserved5[0x6];
__IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
RoReg8 Reserved6[0x8];
__IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
__IO I2S_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
RoReg8 Reserved1[0x3];
__IO I2S_CLKCTRL_Type CLKCTRL[2]; /**< \brief Offset: 0x04 (R/W 32) Clock Unit n Control */
__IO I2S_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 16) Interrupt Enable Clear */
RoReg8 Reserved2[0x2];
__IO I2S_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 16) Interrupt Enable Set */
RoReg8 Reserved3[0x2];
__IO I2S_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 16) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x2];
__I I2S_SYNCBUSY_Type SYNCBUSY; /**< \brief Offset: 0x18 (R/ 16) Synchronization Status */
RoReg8 Reserved5[0x6];
__IO I2S_SERCTRL_Type SERCTRL[2]; /**< \brief Offset: 0x20 (R/W 32) Serializer n Control */
RoReg8 Reserved6[0x8];
__IO I2S_DATA_Type DATA[2]; /**< \brief Offset: 0x30 (R/W 32) Data n */
} I2s;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

150
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_mtb.h
View File

@ -59,12 +59,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -80,17 +80,17 @@ typedef union {
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -117,13 +117,13 @@ typedef union {
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -142,7 +142,7 @@ typedef union {
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -152,7 +152,7 @@ typedef union {
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -162,7 +162,7 @@ typedef union {
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -172,7 +172,7 @@ typedef union {
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -182,7 +182,7 @@ typedef union {
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -192,7 +192,7 @@ typedef union {
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -202,7 +202,7 @@ typedef union {
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -212,7 +212,7 @@ typedef union {
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -222,7 +222,7 @@ typedef union {
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -232,7 +232,7 @@ typedef union {
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,7 +242,7 @@ typedef union {
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -252,7 +252,7 @@ typedef union {
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -262,7 +262,7 @@ typedef union {
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -272,7 +272,7 @@ typedef union {
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -282,7 +282,7 @@ typedef union {
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -292,7 +292,7 @@ typedef union {
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -302,7 +302,7 @@ typedef union {
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -312,7 +312,7 @@ typedef union {
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -322,7 +322,7 @@ typedef union {
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -332,7 +332,7 @@ typedef union {
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -342,7 +342,7 @@ typedef union {
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -352,7 +352,7 @@ typedef union {
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -362,35 +362,35 @@ typedef union {
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

154
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_nvmctrl.h
View File

@ -59,12 +59,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -114,18 +114,18 @@ typedef union {
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -168,13 +168,13 @@ typedef union {
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :1; /*!< bit: 19 Reserved */
uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :1; /*!< bit: 19 Reserved */
uint32_t RWWEEP:12; /*!< bit: 20..31 RWW EEPROM Pages */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -211,12 +211,12 @@ typedef union {
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -232,12 +232,12 @@ typedef union {
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -253,12 +253,12 @@ typedef union {
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready */
uint8_t ERROR:1; /*!< bit: 1 Error */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready */
uint8_t ERROR:1; /*!< bit: 1 Error */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -274,17 +274,17 @@ typedef union {
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -308,11 +308,11 @@ typedef union {
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -327,10 +327,10 @@ typedef union {
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -344,20 +344,20 @@ typedef union {
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL

24
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pac.h
View File

@ -59,11 +59,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -78,11 +78,11 @@ typedef union {
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -97,8 +97,8 @@ typedef union {
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

272
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_pm.h
View File

@ -59,7 +59,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint8_t reg; /*!< Type used for register access */
uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -71,11 +71,11 @@ typedef union {
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -96,11 +96,11 @@ typedef union {
/* -------- PM_EXTCTRL : (PM Offset: 0x02) (R/W 8) External Reset Controller -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SETDIS:1; /*!< bit: 0 External Reset Disable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_EXTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -114,11 +114,11 @@ typedef union {
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -149,11 +149,11 @@ typedef union {
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -184,11 +184,11 @@ typedef union {
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -219,11 +219,11 @@ typedef union {
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -254,17 +254,17 @@ typedef union {
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -290,17 +290,17 @@ typedef union {
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -326,17 +326,17 @@ typedef union {
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -362,33 +362,33 @@ typedef union {
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t TC6_:1; /*!< bit: 14 TC6 APB Clock Enable */
uint32_t TC7_:1; /*!< bit: 15 TC7 APB Clock Enable */
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t DAC_:1; /*!< bit: 18 DAC APB Clock Enable */
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t I2S_:1; /*!< bit: 20 I2S APB Clock Enable */
uint32_t AC1_:1; /*!< bit: 21 AC1 APB Clock Enable */
uint32_t LINCTRL_:1; /*!< bit: 22 LINCTRL APB Clock Enable */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -446,11 +446,11 @@ typedef union {
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -464,11 +464,11 @@ typedef union {
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -482,11 +482,11 @@ typedef union {
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -500,17 +500,17 @@ typedef union {
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -534,25 +534,25 @@ typedef union {
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
__IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
RoReg8 Reserved1[0x5];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
__IO PM_EXTCTRL_Type EXTCTRL; /**< \brief Offset: 0x02 (R/W 8) External Reset Controller */
RoReg8 Reserved1[0x5];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

170
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_port.h
View File

@ -59,10 +59,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -77,10 +77,10 @@ typedef union {
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -95,10 +95,10 @@ typedef union {
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -113,10 +113,10 @@ typedef union {
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -131,10 +131,10 @@ typedef union {
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -149,10 +149,10 @@ typedef union {
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -167,10 +167,10 @@ typedef union {
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -185,10 +185,10 @@ typedef union {
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -203,10 +203,10 @@ typedef union {
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -221,10 +221,10 @@ typedef union {
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -239,21 +239,21 @@ typedef union {
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -285,11 +285,11 @@ typedef union {
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -339,15 +339,15 @@ typedef union {
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -367,28 +367,28 @@ typedef union {
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
PortGroup Group[2]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS

610
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_rtc.h
View File

@ -59,16 +59,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :3; /*!< bit: 4.. 6 Reserved */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :3; /*!< bit: 4.. 6 Reserved */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -120,15 +120,15 @@ typedef union {
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -178,17 +178,17 @@ typedef union {
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :2; /*!< bit: 4.. 5 Reserved */
uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :2; /*!< bit: 4.. 5 Reserved */
uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,13 +242,13 @@ typedef union {
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
uint16_t :8; /*!< bit: 6..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
uint16_t :8; /*!< bit: 6..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -267,25 +267,25 @@ typedef union {
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -323,26 +323,26 @@ typedef union {
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
uint16_t :5; /*!< bit: 10..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
uint16_t :5; /*!< bit: 10..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -382,25 +382,25 @@ typedef union {
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -438,17 +438,17 @@ typedef union {
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -469,18 +469,18 @@ typedef union {
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -503,17 +503,17 @@ typedef union {
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -534,17 +534,17 @@ typedef union {
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -565,18 +565,18 @@ typedef union {
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -599,17 +599,17 @@ typedef union {
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -630,17 +630,17 @@ typedef union {
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -661,18 +661,18 @@ typedef union {
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -695,17 +695,17 @@ typedef union {
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -726,11 +726,11 @@ typedef union {
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -744,11 +744,11 @@ typedef union {
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -762,11 +762,11 @@ typedef union {
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -783,10 +783,10 @@ typedef union {
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -801,10 +801,10 @@ typedef union {
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -819,15 +819,15 @@ typedef union {
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -859,10 +859,10 @@ typedef union {
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PER:16; /*!< bit: 0..15 Counter Period */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PER:16; /*!< bit: 0..15 Counter Period */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -877,10 +877,10 @@ typedef union {
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -895,10 +895,10 @@ typedef union {
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -913,15 +913,15 @@ typedef union {
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -951,11 +951,11 @@ typedef union {
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -984,79 +984,79 @@ typedef union {
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
RoReg8 Reserved1[0x3];
__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
__IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
RoReg8 Reserved3[0x4];
__IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
__IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
RoReg8 Reserved3[0x4];
__IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
__IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
__IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
__IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
RoReg8 Reserved3[0x2];
__IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
RoReg8 Reserved4[0x2];
__IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
__IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
__IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
__IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
RoReg8 Reserved3[0x2];
__IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
RoReg8 Reserved4[0x2];
__IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
__IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
__IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
__IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
RoReg8 Reserved3[0x4];
RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
__IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
__IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
__IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
RoReg8 Reserved3[0x4];
RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

940
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sercom.h
View File

File diff suppressed because it is too large Load Diff

546
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_sysctrl.h
View File

@ -59,26 +59,26 @@
/* -------- SYSCTRL_INTENCLR : (SYSCTRL Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -120,26 +120,26 @@ typedef union {
/* -------- SYSCTRL_INTENSET : (SYSCTRL Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready Interrupt Enable */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready Interrupt Enable */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready Interrupt Enable */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready Interrupt Enable */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready Interrupt Enable */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds Interrupt Enable */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine Interrupt Enable */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse Interrupt Enable */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped Interrupt Enable */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready Interrupt Enable */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection Interrupt Enable */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready Interrupt Enable */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise Interrupt Enable */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall Interrupt Enable */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout Interrupt Enable */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -181,26 +181,26 @@ typedef union {
/* -------- SYSCTRL_INTFLAG : (SYSCTRL Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,26 +242,26 @@ typedef union {
/* -------- SYSCTRL_PCLKSR : (SYSCTRL Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t XOSCRDY:1; /*!< bit: 0 XOSC Ready */
uint32_t XOSC32KRDY:1; /*!< bit: 1 XOSC32K Ready */
uint32_t OSC32KRDY:1; /*!< bit: 2 OSC32K Ready */
uint32_t OSC8MRDY:1; /*!< bit: 3 OSC8M Ready */
uint32_t DFLLRDY:1; /*!< bit: 4 DFLL Ready */
uint32_t DFLLOOB:1; /*!< bit: 5 DFLL Out Of Bounds */
uint32_t DFLLLCKF:1; /*!< bit: 6 DFLL Lock Fine */
uint32_t DFLLLCKC:1; /*!< bit: 7 DFLL Lock Coarse */
uint32_t DFLLRCS:1; /*!< bit: 8 DFLL Reference Clock Stopped */
uint32_t BOD33RDY:1; /*!< bit: 9 BOD33 Ready */
uint32_t BOD33DET:1; /*!< bit: 10 BOD33 Detection */
uint32_t B33SRDY:1; /*!< bit: 11 BOD33 Synchronization Ready */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t DPLLLCKR:1; /*!< bit: 15 DPLL Lock Rise */
uint32_t DPLLLCKF:1; /*!< bit: 16 DPLL Lock Fall */
uint32_t DPLLLTO:1; /*!< bit: 17 DPLL Lock Timeout */
uint32_t :14; /*!< bit: 18..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_PCLKSR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -303,18 +303,18 @@ typedef union {
/* -------- SYSCTRL_XOSC : (SYSCTRL Offset: 0x10) (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t :3; /*!< bit: 3.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t :3; /*!< bit: 3.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t GAIN:3; /*!< bit: 8..10 Oscillator Gain */
uint16_t AMPGC:1; /*!< bit: 11 Automatic Amplitude Gain Control */
uint16_t STARTUP:4; /*!< bit: 12..15 Start-Up Time */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -352,21 +352,21 @@ typedef union {
/* -------- SYSCTRL_XOSC32K : (SYSCTRL Offset: 0x14) (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint16_t XTALEN:1; /*!< bit: 2 Crystal Oscillator Enable */
uint16_t EN32K:1; /*!< bit: 3 32kHz Output Enable */
uint16_t EN1K:1; /*!< bit: 4 1kHz Output Enable */
uint16_t AAMPEN:1; /*!< bit: 5 Automatic Amplitude Control Enable */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint16_t :1; /*!< bit: 11 Reserved */
uint16_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_XOSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -397,22 +397,22 @@ typedef union {
/* -------- SYSCTRL_OSC32K : (SYSCTRL Offset: 0x18) (R/W 32) 32kHz Internal Oscillator (OSC32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t EN32K:1; /*!< bit: 2 32kHz Output Enable */
uint32_t EN1K:1; /*!< bit: 3 1kHz Output Enable */
uint32_t :2; /*!< bit: 4.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t STARTUP:3; /*!< bit: 8..10 Oscillator Start-Up Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t WRTLOCK:1; /*!< bit: 12 Write Lock */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t CALIB:7; /*!< bit: 16..22 Oscillator Calibration */
uint32_t :9; /*!< bit: 23..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -442,12 +442,12 @@ typedef union {
/* -------- SYSCTRL_OSCULP32K : (SYSCTRL Offset: 0x1C) (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CALIB:5; /*!< bit: 0.. 4 Oscillator Calibration */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t WRTLOCK:1; /*!< bit: 7 Write Lock */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_OSCULP32K_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -464,19 +464,19 @@ typedef union {
/* -------- SYSCTRL_OSC8M : (SYSCTRL Offset: 0x20) (R/W 32) 8MHz Internal Oscillator (OSC8M) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t :4; /*!< bit: 2.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
uint32_t :2; /*!< bit: 28..29 Reserved */
uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Oscillator Enable */
uint32_t :4; /*!< bit: 2.. 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint32_t PRESC:2; /*!< bit: 8.. 9 Oscillator Prescaler */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t CALIB:12; /*!< bit: 16..27 Oscillator Calibration */
uint32_t :2; /*!< bit: 28..29 Reserved */
uint32_t FRANGE:2; /*!< bit: 30..31 Oscillator Frequency Range */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_OSC8M_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,22 +519,22 @@ typedef union {
/* -------- SYSCTRL_DFLLCTRL : (SYSCTRL Offset: 0x24) (R/W 16) DFLL48M Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :1; /*!< bit: 0 Reserved */
uint16_t ENABLE:1; /*!< bit: 1 DFLL Enable */
uint16_t MODE:1; /*!< bit: 2 Operating Mode Selection */
uint16_t STABLE:1; /*!< bit: 3 Stable DFLL Frequency */
uint16_t LLAW:1; /*!< bit: 4 Lose Lock After Wake */
uint16_t USBCRM:1; /*!< bit: 5 USB Clock Recovery Mode */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t ONDEMAND:1; /*!< bit: 7 On Demand Control */
uint16_t CCDIS:1; /*!< bit: 8 Chill Cycle Disable */
uint16_t QLDIS:1; /*!< bit: 9 Quick Lock Disable */
uint16_t BPLCKC:1; /*!< bit: 10 Bypass Coarse Lock */
uint16_t WAITLOCK:1; /*!< bit: 11 Wait Lock */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -568,12 +568,12 @@ typedef union {
/* -------- SYSCTRL_DFLLVAL : (SYSCTRL Offset: 0x28) (R/W 32) DFLL48M Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t FINE:10; /*!< bit: 0.. 9 Fine Value */
uint32_t COARSE:6; /*!< bit: 10..15 Coarse Value */
uint32_t DIFF:16; /*!< bit: 16..31 Multiplication Ratio Difference */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLVAL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -594,12 +594,12 @@ typedef union {
/* -------- SYSCTRL_DFLLMUL : (SYSCTRL Offset: 0x2C) (R/W 32) DFLL48M Multiplier -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MUL:16; /*!< bit: 0..15 DFLL Multiply Factor */
uint32_t FSTEP:10; /*!< bit: 16..25 Fine Maximum Step */
uint32_t CSTEP:6; /*!< bit: 26..31 Coarse Maximum Step */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLMUL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -620,11 +620,11 @@ typedef union {
/* -------- SYSCTRL_DFLLSYNC : (SYSCTRL Offset: 0x30) (R/W 8) DFLL48M Synchronization -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t READREQ:1; /*!< bit: 7 Read Request */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t READREQ:1; /*!< bit: 7 Read Request */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DFLLSYNC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -638,22 +638,22 @@ typedef union {
/* -------- SYSCTRL_BOD33 : (SYSCTRL Offset: 0x34) (R/W 32) 3.3V Brown-Out Detector (BOD33) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis */
uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MODE:1; /*!< bit: 8 Operation Mode */
uint32_t CEN:1; /*!< bit: 9 Clock Enable */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t ENABLE:1; /*!< bit: 1 Enable */
uint32_t HYST:1; /*!< bit: 2 Hysteresis */
uint32_t ACTION:2; /*!< bit: 3.. 4 BOD33 Action */
uint32_t :1; /*!< bit: 5 Reserved */
uint32_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MODE:1; /*!< bit: 8 Operation Mode */
uint32_t CEN:1; /*!< bit: 9 Clock Enable */
uint32_t :2; /*!< bit: 10..11 Reserved */
uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */
uint32_t LEVEL:6; /*!< bit: 16..21 BOD33 Threshold Level */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_BOD33_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -722,14 +722,14 @@ typedef union {
/* -------- SYSCTRL_VREG : (SYSCTRL Offset: 0x3C) (R/W 16) Voltage Regulator System (VREG) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t :6; /*!< bit: 0.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t :6; /*!< bit: 7..12 Reserved */
uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t :6; /*!< bit: 0.. 5 Reserved */
uint16_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint16_t :6; /*!< bit: 7..12 Reserved */
uint16_t FORCELDO:1; /*!< bit: 13 Force LDO Voltage Regulator */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} SYSCTRL_VREG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -745,15 +745,15 @@ typedef union {
/* -------- SYSCTRL_VREF : (SYSCTRL Offset: 0x40) (R/W 32) Voltage References System (VREF) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
uint32_t :13; /*!< bit: 3..15 Reserved */
uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Enable */
uint32_t BGOUTEN:1; /*!< bit: 2 Bandgap Output Enable */
uint32_t :13; /*!< bit: 3..15 Reserved */
uint32_t CALIB:11; /*!< bit: 16..26 Bandgap Voltage Generator Calibration */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_VREF_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -772,14 +772,14 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLA : (SYSCTRL Offset: 0x44) (R/W 8) DPLL Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 DPLL Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t RUNSTDBY:1; /*!< bit: 6 Run in Standby */
uint8_t ONDEMAND:1; /*!< bit: 7 On Demand Clock Activation */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -797,13 +797,13 @@ typedef union {
/* -------- SYSCTRL_DPLLRATIO : (SYSCTRL Offset: 0x48) (R/W 32) DPLL Ratio Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LDR:12; /*!< bit: 0..11 Loop Divider Ratio */
uint32_t :4; /*!< bit: 12..15 Reserved */
uint32_t LDRFRAC:4; /*!< bit: 16..19 Loop Divider Ratio Fractional Part */
uint32_t :12; /*!< bit: 20..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLRATIO_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -821,20 +821,20 @@ typedef union {
/* -------- SYSCTRL_DPLLCTRLB : (SYSCTRL Offset: 0x4C) (R/W 32) DPLL Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t FILTER:2; /*!< bit: 0.. 1 Proportional Integral Filter Selection */
uint32_t LPEN:1; /*!< bit: 2 Low-Power Enable */
uint32_t WUF:1; /*!< bit: 3 Wake Up Fast */
uint32_t REFCLK:2; /*!< bit: 4.. 5 Reference Clock Selection */
uint32_t :2; /*!< bit: 6.. 7 Reserved */
uint32_t LTIME:3; /*!< bit: 8..10 Lock Time */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t LBYPASS:1; /*!< bit: 12 Lock Bypass */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t DIV:11; /*!< bit: 16..26 Clock Divider */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -888,14 +888,14 @@ typedef union {
/* -------- SYSCTRL_DPLLSTATUS : (SYSCTRL Offset: 0x50) (R/ 8) DPLL Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
uint8_t DIV:1; /*!< bit: 3 Divider Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t LOCK:1; /*!< bit: 0 DPLL Lock Status */
uint8_t CLKRDY:1; /*!< bit: 1 Output Clock Ready */
uint8_t ENABLE:1; /*!< bit: 2 DPLL Enable */
uint8_t DIV:1; /*!< bit: 3 Divider Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} SYSCTRL_DPLLSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -915,34 +915,34 @@ typedef union {
/** \brief SYSCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
RoReg8 Reserved1[0x2];
__IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
RoReg8 Reserved2[0x2];
__IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
__IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
RoReg8 Reserved3[0x3];
__IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
__IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
RoReg8 Reserved4[0x2];
__IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
__IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
__IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
RoReg8 Reserved5[0x3];
__IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
RoReg8 Reserved6[0x4];
__IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
RoReg8 Reserved7[0x2];
__IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
__IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
RoReg8 Reserved8[0x3];
__IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
__IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
__I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
__IO SYSCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */
__IO SYSCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */
__IO SYSCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */
__I SYSCTRL_PCLKSR_Type PCLKSR; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */
__IO SYSCTRL_XOSC_Type XOSC; /**< \brief Offset: 0x10 (R/W 16) External Multipurpose Crystal Oscillator (XOSC) Control */
RoReg8 Reserved1[0x2];
__IO SYSCTRL_XOSC32K_Type XOSC32K; /**< \brief Offset: 0x14 (R/W 16) 32kHz External Crystal Oscillator (XOSC32K) Control */
RoReg8 Reserved2[0x2];
__IO SYSCTRL_OSC32K_Type OSC32K; /**< \brief Offset: 0x18 (R/W 32) 32kHz Internal Oscillator (OSC32K) Control */
__IO SYSCTRL_OSCULP32K_Type OSCULP32K; /**< \brief Offset: 0x1C (R/W 8) 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control */
RoReg8 Reserved3[0x3];
__IO SYSCTRL_OSC8M_Type OSC8M; /**< \brief Offset: 0x20 (R/W 32) 8MHz Internal Oscillator (OSC8M) Control */
__IO SYSCTRL_DFLLCTRL_Type DFLLCTRL; /**< \brief Offset: 0x24 (R/W 16) DFLL48M Control */
RoReg8 Reserved4[0x2];
__IO SYSCTRL_DFLLVAL_Type DFLLVAL; /**< \brief Offset: 0x28 (R/W 32) DFLL48M Value */
__IO SYSCTRL_DFLLMUL_Type DFLLMUL; /**< \brief Offset: 0x2C (R/W 32) DFLL48M Multiplier */
__IO SYSCTRL_DFLLSYNC_Type DFLLSYNC; /**< \brief Offset: 0x30 (R/W 8) DFLL48M Synchronization */
RoReg8 Reserved5[0x3];
__IO SYSCTRL_BOD33_Type BOD33; /**< \brief Offset: 0x34 (R/W 32) 3.3V Brown-Out Detector (BOD33) Control */
RoReg8 Reserved6[0x4];
__IO SYSCTRL_VREG_Type VREG; /**< \brief Offset: 0x3C (R/W 16) Voltage Regulator System (VREG) Control */
RoReg8 Reserved7[0x2];
__IO SYSCTRL_VREF_Type VREF; /**< \brief Offset: 0x40 (R/W 32) Voltage References System (VREF) Control */
__IO SYSCTRL_DPLLCTRLA_Type DPLLCTRLA; /**< \brief Offset: 0x44 (R/W 8) DPLL Control A */
RoReg8 Reserved8[0x3];
__IO SYSCTRL_DPLLRATIO_Type DPLLRATIO; /**< \brief Offset: 0x48 (R/W 32) DPLL Ratio Control */
__IO SYSCTRL_DPLLCTRLB_Type DPLLCTRLB; /**< \brief Offset: 0x4C (R/W 32) DPLL Control B */
__I SYSCTRL_DPLLSTATUS_Type DPLLSTATUS; /**< \brief Offset: 0x50 (R/ 8) DPLL Status */
} Sysctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

416
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tc.h
View File

@ -59,19 +59,19 @@
/* -------- TC_CTRLA : (TC Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
uint16_t :1; /*!< bit: 4 Reserved */
uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 TC Mode */
uint16_t :1; /*!< bit: 4 Reserved */
uint16_t WAVEGEN:2; /*!< bit: 5.. 6 Waveform Generation Operation */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler */
uint16_t RUNSTDBY:1; /*!< bit: 11 Run in Standby */
uint16_t PRESCSYNC:2; /*!< bit: 12..13 Prescaler and Counter Synchronization */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -137,13 +137,13 @@ typedef union {
/* -------- TC_READREQ : (TC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
uint16_t :9; /*!< bit: 5..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ADDR:5; /*!< bit: 0.. 4 Address */
uint16_t :9; /*!< bit: 5..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -162,14 +162,14 @@ typedef union {
/* -------- TC_CTRLBCLR : (TC Offset: 0x04) (R/W 8) Control B Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -194,14 +194,14 @@ typedef union {
/* -------- TC_CTRLBSET : (TC Offset: 0x05) (R/W 8) Control B Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DIR:1; /*!< bit: 0 Counter Direction */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t ONESHOT:1; /*!< bit: 2 One-Shot */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t CMD:2; /*!< bit: 6.. 7 Command */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLBSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -226,21 +226,21 @@ typedef union {
/* -------- TC_CTRLC : (TC Offset: 0x06) (R/W 8) Control C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t INVEN0:1; /*!< bit: 0 Output Waveform 0 Invert Enable */
uint8_t INVEN1:1; /*!< bit: 1 Output Waveform 1 Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN0:1; /*!< bit: 4 Capture Channel 0 Enable */
uint8_t CPTEN1:1; /*!< bit: 5 Capture Channel 1 Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t INVEN:2; /*!< bit: 0.. 1 Output Waveform x Invert Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t CPTEN:2; /*!< bit: 4.. 5 Capture Channel x Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_CTRLC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -266,11 +266,11 @@ typedef union {
/* -------- TC_DBGCTRL : (TC Offset: 0x08) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run Mode */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -284,24 +284,24 @@ typedef union {
/* -------- TC_EVCTRL : (TC Offset: 0x0A) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t EVACT:3; /*!< bit: 0.. 2 Event Action */
uint16_t :1; /*!< bit: 3 Reserved */
uint16_t TCINV:1; /*!< bit: 4 TC Inverted Event Input */
uint16_t TCEI:1; /*!< bit: 5 TC Event Input */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t OVFEO:1; /*!< bit: 8 Overflow/Underflow Event Output Enable */
uint16_t :3; /*!< bit: 9..11 Reserved */
uint16_t MCEO0:1; /*!< bit: 12 Match or Capture Channel 0 Event Output Enable */
uint16_t MCEO1:1; /*!< bit: 13 Match or Capture Channel 1 Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :12; /*!< bit: 0..11 Reserved */
uint16_t MCEO:2; /*!< bit: 12..13 Match or Capture Channel x Event Output Enable */
uint16_t :2; /*!< bit: 14..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} TC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -341,21 +341,21 @@ typedef union {
/* -------- TC_INTENCLR : (TC Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -380,21 +380,21 @@ typedef union {
/* -------- TC_INTENSET : (TC Offset: 0x0D) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow Interrupt Enable */
uint8_t ERR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 Interrupt Enable */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x Interrupt Enable */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -419,21 +419,21 @@ typedef union {
/* -------- TC_INTFLAG : (TC Offset: 0x0E) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow */
uint8_t ERR:1; /*!< bit: 1 Error */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t OVF:1; /*!< bit: 0 Overflow */
uint8_t ERR:1; /*!< bit: 1 Error */
uint8_t :1; /*!< bit: 2 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
uint8_t MC0:1; /*!< bit: 4 Match or Capture Channel 0 */
uint8_t MC1:1; /*!< bit: 5 Match or Capture Channel 1 */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :4; /*!< bit: 0.. 3 Reserved */
uint8_t MC:2; /*!< bit: 4.. 5 Match or Capture Channel x */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} TC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -458,14 +458,14 @@ typedef union {
/* -------- TC_STATUS : (TC Offset: 0x0F) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :3; /*!< bit: 0.. 2 Reserved */
uint8_t STOP:1; /*!< bit: 3 Stop */
uint8_t SLAVE:1; /*!< bit: 4 Slave */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :3; /*!< bit: 0.. 2 Reserved */
uint8_t STOP:1; /*!< bit: 3 Stop */
uint8_t SLAVE:1; /*!< bit: 4 Slave */
uint8_t :2; /*!< bit: 5.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -483,10 +483,10 @@ typedef union {
/* -------- TC_COUNT16_COUNT : (TC Offset: 0x10) (R/W 16) COUNT16 COUNT16 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Count Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -501,10 +501,10 @@ typedef union {
/* -------- TC_COUNT32_COUNT : (TC Offset: 0x10) (R/W 32) COUNT32 COUNT32 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Count Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,10 +519,10 @@ typedef union {
/* -------- TC_COUNT8_COUNT : (TC Offset: 0x10) (R/W 8) COUNT8 COUNT8 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COUNT:8; /*!< bit: 0.. 7 Counter Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -537,10 +537,10 @@ typedef union {
/* -------- TC_COUNT8_PER : (TC Offset: 0x14) (R/W 8) COUNT8 COUNT8 Period Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PER:8; /*!< bit: 0.. 7 Period Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -555,10 +555,10 @@ typedef union {
/* -------- TC_COUNT16_CC : (TC Offset: 0x18) (R/W 16) COUNT16 COUNT16 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CC:16; /*!< bit: 0..15 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} TC_COUNT16_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -573,10 +573,10 @@ typedef union {
/* -------- TC_COUNT32_CC : (TC Offset: 0x18) (R/W 32) COUNT32 COUNT32 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CC:32; /*!< bit: 0..31 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} TC_COUNT32_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -591,10 +591,10 @@ typedef union {
/* -------- TC_COUNT8_CC : (TC Offset: 0x18) (R/W 8) COUNT8 COUNT8 Compare/Capture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CC:8; /*!< bit: 0.. 7 Compare/Capture Value */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} TC_COUNT8_CC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -609,76 +609,76 @@ typedef union {
/** \brief TC_COUNT8 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 8-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
RoReg8 Reserved3[0x3];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
RoReg8 Reserved4[0x3];
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT8_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 8) COUNT8 Counter Value */
RoReg8 Reserved3[0x3];
__IO TC_COUNT8_PER_Type PER; /**< \brief Offset: 0x14 (R/W 8) COUNT8 Period Value */
RoReg8 Reserved4[0x3];
__IO TC_COUNT8_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 8) COUNT8 Compare/Capture */
} TcCount8;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT16 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
RoReg8 Reserved3[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT16_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) COUNT16 Counter Value */
RoReg8 Reserved3[0x6];
__IO TC_COUNT16_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 16) COUNT16 Compare/Capture */
} TcCount16;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief TC_COUNT32 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter Mode */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
RoReg8 Reserved3[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
__IO TC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
__IO TC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO TC_CTRLBCLR_Type CTRLBCLR; /**< \brief Offset: 0x04 (R/W 8) Control B Clear */
__IO TC_CTRLBSET_Type CTRLBSET; /**< \brief Offset: 0x05 (R/W 8) Control B Set */
__IO TC_CTRLC_Type CTRLC; /**< \brief Offset: 0x06 (R/W 8) Control C */
RoReg8 Reserved1[0x1];
__IO TC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x08 (R/W 8) Debug Control */
RoReg8 Reserved2[0x1];
__IO TC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x0A (R/W 16) Event Control */
__IO TC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
__IO TC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0D (R/W 8) Interrupt Enable Set */
__IO TC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x0E (R/W 8) Interrupt Flag Status and Clear */
__I TC_STATUS_Type STATUS; /**< \brief Offset: 0x0F (R/ 8) Status */
__IO TC_COUNT32_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) COUNT32 Counter Value */
RoReg8 Reserved3[0x4];
__IO TC_COUNT32_CC_Type CC[2]; /**< \brief Offset: 0x18 (R/W 32) COUNT32 Compare/Capture */
} TcCount32;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
TcCount8 COUNT8; /**< \brief Offset: 0x00 8-bit Counter Mode */
TcCount16 COUNT16; /**< \brief Offset: 0x00 16-bit Counter Mode */
TcCount32 COUNT32; /**< \brief Offset: 0x00 32-bit Counter Mode */
} Tc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

1076
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc.h
View File

File diff suppressed because it is too large Load Diff

1082
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_tcc_lighting.h
View File

File diff suppressed because it is too large Load Diff

1132
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_usb.h
View File

File diff suppressed because it is too large Load Diff

102
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/component/comp_wdt.h
View File

@ -59,14 +59,14 @@
/* -------- WDT_CTRL : (WDT Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :1; /*!< bit: 0 Reserved */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t WEN:1; /*!< bit: 2 Watchdog Timer Window Mode Enable */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t ALWAYSON:1; /*!< bit: 7 Always-On */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -84,11 +84,11 @@ typedef union {
/* -------- WDT_CONFIG : (WDT Offset: 0x1) (R/W 8) Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PER:4; /*!< bit: 0.. 3 Time-Out Period */
uint8_t WINDOW:4; /*!< bit: 4.. 7 Window Mode Time-Out Period */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -154,11 +154,11 @@ typedef union {
/* -------- WDT_EWCTRL : (WDT Offset: 0x2) (R/W 8) Early Warning Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EWOFFSET:4; /*!< bit: 0.. 3 Early Warning Interrupt Time Offset */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_EWCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -197,11 +197,11 @@ typedef union {
/* -------- WDT_INTENCLR : (WDT Offset: 0x4) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -215,11 +215,11 @@ typedef union {
/* -------- WDT_INTENSET : (WDT Offset: 0x5) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -233,11 +233,11 @@ typedef union {
/* -------- WDT_INTFLAG : (WDT Offset: 0x6) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t EW:1; /*!< bit: 0 Early Warning */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -251,11 +251,11 @@ typedef union {
/* -------- WDT_STATUS : (WDT Offset: 0x7) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -269,10 +269,10 @@ typedef union {
/* -------- WDT_CLEAR : (WDT Offset: 0x8) ( /W 8) Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CLEAR:8; /*!< bit: 0.. 7 Watchdog Clear */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} WDT_CLEAR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -289,15 +289,15 @@ typedef union {
/** \brief WDT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
__IO WDT_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__IO WDT_CONFIG_Type CONFIG; /**< \brief Offset: 0x1 (R/W 8) Configuration */
__IO WDT_EWCTRL_Type EWCTRL; /**< \brief Offset: 0x2 (R/W 8) Early Warning Interrupt Control */
RoReg8 Reserved1[0x1];
__IO WDT_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x4 (R/W 8) Interrupt Enable Clear */
__IO WDT_INTENSET_Type INTENSET; /**< \brief Offset: 0x5 (R/W 8) Interrupt Enable Set */
__IO WDT_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x6 (R/W 8) Interrupt Flag Status and Clear */
__I WDT_STATUS_Type STATUS; /**< \brief Offset: 0x7 (R/ 8) Status */
__O WDT_CLEAR_Type CLEAR; /**< \brief Offset: 0x8 ( /W 8) Clear */
} Wdt;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac.h
View File

@ -84,7 +84,7 @@
#define AC_CMP_NUM 2 // Number of comparators
#define AC_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC_GCLK_ID_DIG 31 // Index of Generic Clock for digital
#define AC_NUM_CMP 2
#define AC_NUM_CMP 2
#define AC_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMD21_AC_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_ac1.h
View File

@ -81,7 +81,7 @@
#define AC1_CMP_NUM 2 // Number of comparators
#define AC1_GCLK_ID_ANA 32 // Index of Generic Clock for analog
#define AC1_GCLK_ID_DIG 31 // Index of Generic Clock for digital
#define AC1_NUM_CMP 2
#define AC1_NUM_CMP 2
#define AC1_PAIRS 1 // Number of pairs of comparators
#endif /* _SAMD21_AC1_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_gclk.h
View File

@ -63,7 +63,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for GCLK peripheral ========== */
#define GCLK_GENDIV_BITS 16
#define GCLK_GENDIV_BITS 16
#define GCLK_GEN_NUM 9 // Number of Generic Clock Generators
#define GCLK_GEN_NUM_MSB 8 // Number of Generic Clock Generators - 1
#define GCLK_GEN_SOURCE_NUM_MSB 8 // Number of Generic Clock Sources - 1

18
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_nvmctrl.h
View File

@ -77,16 +77,16 @@
#define NVMCTRL_AUX3_ADDRESS 0x0080A000
#define NVMCTRL_CLK_AHB_ID 4 // Index of AHB Clock in PM.AHBMASK register
#define NVMCTRL_FACTORY_WORD_IMPLEMENTED_MASK 0xC0000007FFFFFFFF
#define NVMCTRL_FLASH_SIZE 65536
#define NVMCTRL_FLASH_SIZE 65536
#define NVMCTRL_LOCKBIT_ADDRESS 0x00802000
#define NVMCTRL_PAGES 1024
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_PAGES 1024
#define NVMCTRL_PAGE_HW 32
#define NVMCTRL_PAGE_SIZE 64
#define NVMCTRL_PAGE_W 16
#define NVMCTRL_PMSB 3
#define NVMCTRL_PSZ_BITS 6
#define NVMCTRL_ROW_PAGES 4
#define NVMCTRL_ROW_SIZE 256
#define NVMCTRL_USER_PAGE_ADDRESS 0x00800000
#define NVMCTRL_USER_PAGE_OFFSET 0x00800000
#define NVMCTRL_USER_WORD_IMPLEMENTED_MASK 0xC01FFFFFFFFFFFFF

10
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_pm.h
View File

@ -83,10 +83,10 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for PM peripheral ========== */
#define PM_CTRL_MCSEL_DFLL48M 3
#define PM_CTRL_MCSEL_GCLK 0
#define PM_CTRL_MCSEL_OSC8M 1
#define PM_CTRL_MCSEL_XOSC 2
#define PM_PM_CLK_APB_NUM 2
#define PM_CTRL_MCSEL_DFLL48M 3
#define PM_CTRL_MCSEL_GCLK 0
#define PM_CTRL_MCSEL_OSC8M 1
#define PM_CTRL_MCSEL_XOSC 2
#define PM_PM_CLK_APB_NUM 2
#endif /* _SAMD21_PM_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sbmatrix.h
View File

@ -149,7 +149,7 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SBMATRIX peripheral ========== */
#define SBMATRIX_DEFINED
#define SBMATRIX_DEFINED
/* ========== Instance parameters for SBMATRIX ========== */
#define SBMATRIX_SLAVE_FLASH 0
#define SBMATRIX_SLAVE_HPB0 1

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom0.h
View File

@ -141,6 +141,6 @@
#define SERCOM0_DMAC_ID_TX 2 // Index of DMA TX trigger
#define SERCOM0_GCLK_ID_CORE 20 // Index of Generic Clock for Core
#define SERCOM0_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM0_INT_MSB 6
#define SERCOM0_INT_MSB 6
#endif /* _SAMD21_SERCOM0_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom1.h
View File

@ -141,6 +141,6 @@
#define SERCOM1_DMAC_ID_TX 4 // Index of DMA TX trigger
#define SERCOM1_GCLK_ID_CORE 21 // Index of Generic Clock for Core
#define SERCOM1_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM1_INT_MSB 6
#define SERCOM1_INT_MSB 6
#endif /* _SAMD21_SERCOM1_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom2.h
View File

@ -141,6 +141,6 @@
#define SERCOM2_DMAC_ID_TX 6 // Index of DMA TX trigger
#define SERCOM2_GCLK_ID_CORE 22 // Index of Generic Clock for Core
#define SERCOM2_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM2_INT_MSB 6
#define SERCOM2_INT_MSB 6
#endif /* _SAMD21_SERCOM2_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom3.h
View File

@ -141,6 +141,6 @@
#define SERCOM3_DMAC_ID_TX 8 // Index of DMA TX trigger
#define SERCOM3_GCLK_ID_CORE 23 // Index of Generic Clock for Core
#define SERCOM3_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM3_INT_MSB 6
#define SERCOM3_INT_MSB 6
#endif /* _SAMD21_SERCOM3_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom4.h
View File

@ -141,6 +141,6 @@
#define SERCOM4_DMAC_ID_TX 10 // Index of DMA TX trigger
#define SERCOM4_GCLK_ID_CORE 24 // Index of Generic Clock for Core
#define SERCOM4_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM4_INT_MSB 6
#define SERCOM4_INT_MSB 6
#endif /* _SAMD21_SERCOM4_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sercom5.h
View File

@ -141,6 +141,6 @@
#define SERCOM5_DMAC_ID_TX 12 // Index of DMA TX trigger
#define SERCOM5_GCLK_ID_CORE 25 // Index of Generic Clock for Core
#define SERCOM5_GCLK_ID_SLOW 19 // Index of Generic Clock for SMbus timeout
#define SERCOM5_INT_MSB 6
#define SERCOM5_INT_MSB 6
#endif /* _SAMD21_SERCOM5_INSTANCE_ */

46
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_sysctrl.h
View File

@ -93,31 +93,31 @@
#endif /* (defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* ========== Instance parameters for SYSCTRL peripheral ========== */
#define SYSCTRL_BGAP_CALIB_MSB 11
#define SYSCTRL_BOD33_CALIB_MSB 5
#define SYSCTRL_DFLL48M_COARSE_MSB 5
#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_BGAP_CALIB_MSB 11
#define SYSCTRL_BOD33_CALIB_MSB 5
#define SYSCTRL_DFLL48M_COARSE_MSB 5
#define SYSCTRL_DFLL48M_FINE_MSB 9
#define SYSCTRL_GCLK_ID_DFLL48 0 // Index of Generic Clock for DFLL48
#define SYSCTRL_GCLK_ID_FDPLL 1 // Index of Generic Clock for DPLL
#define SYSCTRL_GCLK_ID_FDPLL32K 2 // Index of Generic Clock for DPLL 32K
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
#define SYSCTRL_POR33_ENTEST_MSB 1
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
#define SYSCTRL_VREF_CONTROL_MSB 48
#define SYSCTRL_VREF_STATUS_MSB 7
#define SYSCTRL_VREG_LEVEL_MSB 2
#define SYSCTRL_BOD12_VERSION 0x111
#define SYSCTRL_BOD33_VERSION 0x111
#define SYSCTRL_DFLL48M_VERSION 0x301
#define SYSCTRL_FDPLL_VERSION 0x111
#define SYSCTRL_OSCULP32K_VERSION 0x111
#define SYSCTRL_OSC8M_VERSION 0x120
#define SYSCTRL_OSC32K_VERSION 0x112
#define SYSCTRL_VREF_VERSION 0x201
#define SYSCTRL_VREG_VERSION 0x201
#define SYSCTRL_XOSC_VERSION 0x114
#define SYSCTRL_XOSC32K_VERSION 0x113
#define SYSCTRL_OSC32K_COARSE_CALIB_MSB 6
#define SYSCTRL_POR33_ENTEST_MSB 1
#define SYSCTRL_ULPVREF_DIVLEV_MSB 3
#define SYSCTRL_ULPVREG_FORCEGAIN_MSB 1
#define SYSCTRL_ULPVREG_RAMREFSEL_MSB 2
#define SYSCTRL_VREF_CONTROL_MSB 48
#define SYSCTRL_VREF_STATUS_MSB 7
#define SYSCTRL_VREG_LEVEL_MSB 2
#define SYSCTRL_BOD12_VERSION 0x111
#define SYSCTRL_BOD33_VERSION 0x111
#define SYSCTRL_DFLL48M_VERSION 0x301
#define SYSCTRL_FDPLL_VERSION 0x111
#define SYSCTRL_OSCULP32K_VERSION 0x111
#define SYSCTRL_OSC8M_VERSION 0x120
#define SYSCTRL_OSC32K_VERSION 0x112
#define SYSCTRL_VREF_VERSION 0x201
#define SYSCTRL_VREG_VERSION 0x201
#define SYSCTRL_XOSC_VERSION 0x114
#define SYSCTRL_XOSC32K_VERSION 0x113
#endif /* _SAMD21_SYSCTRL_INSTANCE_ */

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc3.h
View File

@ -106,7 +106,7 @@
#define TC3_DMAC_ID_MC_SIZE 2
#define TC3_DMAC_ID_OVF 24 // Indexes of DMA Overflow trigger
#define TC3_GCLK_ID 27 // Index of Generic Clock
#define TC3_MASTER 0
#define TC3_MASTER 0
#define TC3_OW_NUM 2 // Number of Output Waveforms
#define TC3_PERIOD_EXT 0 // Period feature implemented
#define TC3_SHADOW_EXT 0 // Shadow feature implemented

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc4.h
View File

@ -106,7 +106,7 @@
#define TC4_DMAC_ID_MC_SIZE 2
#define TC4_DMAC_ID_OVF 27 // Indexes of DMA Overflow trigger
#define TC4_GCLK_ID 28 // Index of Generic Clock
#define TC4_MASTER 1
#define TC4_MASTER 1
#define TC4_OW_NUM 2 // Number of Output Waveforms
#define TC4_PERIOD_EXT 0 // Period feature implemented
#define TC4_SHADOW_EXT 0 // Shadow feature implemented

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc5.h
View File

@ -106,7 +106,7 @@
#define TC5_DMAC_ID_MC_SIZE 2
#define TC5_DMAC_ID_OVF 30 // Indexes of DMA Overflow trigger
#define TC5_GCLK_ID 28 // Index of Generic Clock
#define TC5_MASTER 0
#define TC5_MASTER 0
#define TC5_OW_NUM 2 // Number of Output Waveforms
#define TC5_PERIOD_EXT 0 // Period feature implemented
#define TC5_SHADOW_EXT 0 // Shadow feature implemented

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc6.h
View File

@ -106,7 +106,7 @@
#define TC6_DMAC_ID_MC_SIZE 2
#define TC6_DMAC_ID_OVF 33 // Indexes of DMA Overflow trigger
#define TC6_GCLK_ID 29 // Index of Generic Clock
#define TC6_MASTER 1
#define TC6_MASTER 1
#define TC6_OW_NUM 2 // Number of Output Waveforms
#define TC6_PERIOD_EXT 0 // Period feature implemented
#define TC6_SHADOW_EXT 0 // Shadow feature implemented

2
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tc7.h
View File

@ -106,7 +106,7 @@
#define TC7_DMAC_ID_MC_SIZE 2
#define TC7_DMAC_ID_OVF 36 // Indexes of DMA Overflow trigger
#define TC7_GCLK_ID 29 // Index of Generic Clock
#define TC7_MASTER 0
#define TC7_MASTER 0
#define TC7_OW_NUM 2 // Number of Output Waveforms
#define TC7_PERIOD_EXT 0 // Period feature implemented
#define TC7_SHADOW_EXT 0 // Shadow feature implemented

4
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc0.h
View File

@ -124,11 +124,11 @@
#define TCC0_DTI 1 // Dead-Time-Insertion feature implemented
#define TCC0_EXT 31 // (@_DITHERING*16+@_PG*8+@_SWAP*4+@_DTI*2+@_OTMX*1)
#define TCC0_GCLK_ID 26 // Index of Generic Clock
#define TCC0_MASTER 0
#define TCC0_MASTER 0
#define TCC0_OTMX 1 // Output Matrix feature implemented
#define TCC0_OW_NUM 8 // Number of Output Waveforms
#define TCC0_PG 1 // Pattern Generation feature implemented
#define TCC0_SIZE 24
#define TCC0_SIZE 24
#define TCC0_SWAP 1 // DTI outputs swap feature implemented
#define TCC0_TYPE 1 // TCC type 0 : NA, 1 : Master, 2 : Slave

4
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc1.h
View File

@ -112,11 +112,11 @@
#define TCC1_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC1_EXT 24 // Coding of implemented extended features
#define TCC1_GCLK_ID 26 // Index of Generic Clock
#define TCC1_MASTER 1
#define TCC1_MASTER 1
#define TCC1_OTMX 0 // Output Matrix feature implemented
#define TCC1_OW_NUM 4 // Number of Output Waveforms
#define TCC1_PG 1 // Pattern Generation feature implemented
#define TCC1_SIZE 24
#define TCC1_SIZE 24
#define TCC1_SWAP 0 // DTI outputs swap feature implemented
#define TCC1_TYPE 2 // TCC type 0 : NA, 1 : Master, 2 : Slave

4
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/instance/ins_tcc2.h
View File

@ -108,11 +108,11 @@
#define TCC2_DTI 0 // Dead-Time-Insertion feature implemented
#define TCC2_EXT 0 // Coding of implemented extended features
#define TCC2_GCLK_ID 27 // Index of Generic Clock
#define TCC2_MASTER 0
#define TCC2_MASTER 0
#define TCC2_OTMX 0 // Output Matrix feature implemented
#define TCC2_OW_NUM 2 // Number of Output Waveforms
#define TCC2_PG 0 // Pattern Generation feature implemented
#define TCC2_SIZE 16
#define TCC2_SIZE 16
#define TCC2_SWAP 0 // DTI outputs swap feature implemented
#define TCC2_TYPE 0 // TCC type 0 : NA, 1 : Master, 2 : Slave

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g17au.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21G17AU_PIO_
#define _SAMD21G17AU_PIO_

6
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/pio/pio_samd21g18au.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21G18AU_PIO_
#define _SAMD21G18AU_PIO_

50
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21.h
View File

@ -53,55 +53,55 @@
*/
#if defined(__SAMD21E15A__) || defined(__ATSAMD21E15A__)
#include "samd21e15a.h"
#include "samd21e15a.h"
#elif defined(__SAMD21E16A__) || defined(__ATSAMD21E16A__)
#include "samd21e16a.h"
#include "samd21e16a.h"
#elif defined(__SAMD21E17A__) || defined(__ATSAMD21E17A__)
#include "samd21e17a.h"
#include "samd21e17a.h"
#elif defined(__SAMD21E18A__) || defined(__ATSAMD21E18A__)
#include "samd21e18a.h"
#include "samd21e18a.h"
#elif defined(__SAMD21G15A__) || defined(__ATSAMD21G15A__)
#include "samd21g15a.h"
#include "samd21g15a.h"
#elif defined(__SAMD21G16A__) || defined(__ATSAMD21G16A__)
#include "samd21g16a.h"
#include "samd21g16a.h"
#elif defined(__SAMD21G17A__) || defined(__ATSAMD21G17A__)
#include "samd21g17a.h"
#include "samd21g17a.h"
#elif defined(__SAMD21G17AU__) || defined(__ATSAMD21G17AU__)
#include "samd21g17au.h"
#include "samd21g17au.h"
#elif defined(__SAMD21G18A__) || defined(__ATSAMD21G18A__)
#include "samd21g18a.h"
#include "samd21g18a.h"
#elif defined (__SAMD21G18AU__) || defined(__ATSAMD21G18AU__)
#include "samd21g18au.h"
#include "samd21g18au.h"
#elif defined(__SAMD21J15A__) || defined(__ATSAMD21J15A__)
#include "samd21j15a.h"
#include "samd21j15a.h"
#elif defined(__SAMD21J16A__) || defined(__ATSAMD21J16A__)
#include "samd21j16a.h"
#include "samd21j16a.h"
#elif defined(__SAMD21J17A__) || defined(__ATSAMD21J17A__)
#include "samd21j17a.h"
#include "samd21j17a.h"
#elif defined(__SAMD21J18A__) || defined(__ATSAMD21J18A__)
#include "samd21j18a.h"
#include "samd21j18a.h"
#elif defined(__SAMD21E15B__) || defined(__ATSAMD21E15B__)
#include "samd21e15b.h"
#include "samd21e15b.h"
#elif defined(__SAMD21E15BU__) || defined(__ATSAMD21E15BU__)
#include "samd21e15bu.h"
#include "samd21e15bu.h"
#elif defined(__SAMD21E15L__) || defined(__ATSAMD21E15L__)
#include "samd21e15l.h"
#include "samd21e15l.h"
#elif defined(__SAMD21E16B__) || defined(__ATSAMD21E16B__)
#include "samd21e16b.h"
#include "samd21e16b.h"
#elif defined(__SAMD21E16BU__) || defined(__ATSAMD21E16BU__)
#include "samd21e16bu.h"
#include "samd21e16bu.h"
#elif defined(__SAMD21E16L__) || defined(__ATSAMD21E16L__)
#include "samd21e16l.h"
#include "samd21e16l.h"
#elif defined(__SAMD21G15B__) || defined(__ATSAMD21G15B__)
#include "samd21g15b.h"
#include "samd21g15b.h"
#elif defined(__SAMD21G16B__) || defined(__ATSAMD21G16B__)
#include "samd21g16b.h"
#include "samd21g16b.h"
#elif defined(__SAMD21J15B__) || defined(__ATSAMD21J15B__)
#include "samd21j15b.h"
#include "samd21j15b.h"
#elif defined(__SAMD21J16B__) || defined(__ATSAMD21J16B__)
#include "samd21j16b.h"
#include "samd21j16b.h"
#else
#error Library does not support the specified device.
#error Library does not support the specified device.
#endif
#endif /* _SAMD21_ */

168
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E15A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E15A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E15A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

170
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15b.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E15B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15B Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E15B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E15B Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

170
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15bu.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15BU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15BU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15BU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15BU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15BU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15BU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15BU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15BU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15BU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E15BU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15BU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15BU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15BU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15BU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15BU Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15BU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15BU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15BU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15BU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15BU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15BU Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15BU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15BU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15BU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E15BU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E15BU Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

166
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e15l.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,93 +90,91 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15L-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E15L-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E15L Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E15L System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E15L Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E15L Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E15L External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E15L Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E15L Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMD21E15L Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E15L Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E15L Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E15L Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E15L Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E15L Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E15L Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E15L Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E15L Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E15L Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E15L Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E15L Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E15L Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E15L Digital Analog Converter (DAC) */
AC1_IRQn = 28, /**< 28 SAMD21E15L Analog Comparators 1 (AC1) */
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnReserved7;
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnReserved26;
void* pfnReserved27;
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnReserved7;
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnReserved26;
void* pfnReserved27;
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -215,7 +213,7 @@ void AC1_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

168
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E16A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E16A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E16A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

170
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16b.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E16B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16B Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E16B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E16B Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

170
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16bu.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,95 +90,93 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16BU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16BU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16BU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16BU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16BU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16BU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16BU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16BU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16BU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E16BU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16BU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16BU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16BU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16BU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16BU Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16BU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16BU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16BU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16BU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16BU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16BU Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16BU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16BU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16BU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E16BU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E16BU Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -219,7 +217,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

166
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e16l.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,93 +90,91 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16L-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E16L-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E16L Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E16L System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E16L Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E16L Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E16L External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E16L Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E16L Direct Memory Access Controller (DMAC) */
EVSYS_IRQn = 8, /**< 8 SAMD21E16L Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E16L Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E16L Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E16L Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E16L Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E16L Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E16L Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E16L Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E16L Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E16L Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E16L Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E16L Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E16L Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E16L Digital Analog Converter (DAC) */
AC1_IRQn = 28, /**< 28 SAMD21E16L Analog Comparators 1 (AC1) */
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 29 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnReserved7;
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnReserved26;
void* pfnReserved27;
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnReserved7;
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnReserved26;
void* pfnReserved27;
void* pfnAC1_Handler; /* 28 Analog Comparators 1 */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -215,7 +213,7 @@ void AC1_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

168
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e17a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E17A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E17A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E17A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E17A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E17A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E17A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E17A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E17A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E17A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E17A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E17A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E17A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E17A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E17A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E17A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E17A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E17A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E17A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

168
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21e18a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,94 +93,92 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21E18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21E18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21E18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21E18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21E18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21E18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21E18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21E18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21E18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21E18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21E18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21E18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21E18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21E18A Serial Communication Interface 3 (SERCOM3) */
TCC0_IRQn = 15, /**< 15 SAMD21E18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21E18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21E18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21E18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21E18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21E18A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21E18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21E18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21E18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21E18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21E18A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnReserved13;
void* pfnReserved14;
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -221,7 +219,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

172
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G15A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G15A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G15A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G15A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G15A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G15A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G15A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G15A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G15A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G15A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G15A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G15A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G15A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G15A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G15A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G15A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G15A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G15A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G15A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G15A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

174
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g15b.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,97 +90,95 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G15B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G15B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G15B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G15B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G15B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G15B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G15B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G15B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G15B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G15B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G15B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G15B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G15B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G15B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G15B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G15B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G15B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G15B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G15B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G15B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G15B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G15B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G15B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G15B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G15B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G15B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G15B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G15B Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -223,7 +221,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

172
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G16A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G16A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G16A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G16A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G16A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G16A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G16A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G16A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G16A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G16A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G16A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G16A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G16A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G16A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G16A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G16A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G16A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G16A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G16A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G16A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

174
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g16b.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,97 +90,95 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G16B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G16B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G16B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G16B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G16B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G16B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G16B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G16B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G16B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G16B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G16B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G16B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G16B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G16B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G16B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G16B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G16B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G16B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G16B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G16B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G16B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G16B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G16B Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G16B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G16B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G16B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G16B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G16B Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -223,7 +221,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

172
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G17A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G17A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G17A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G17A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G17A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G17A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G17A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G17A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G17A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G17A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G17A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G17A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G17A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G17A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G17A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G17A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G17A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G17A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G17A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G17A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

184
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g17au.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21G17AU_
#define _SAMD21G17AU_
@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,99 +93,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G17AU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G17AU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G17AU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G17AU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G17AU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G17AU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G17AU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G17AU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G17AU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G17AU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G17AU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G17AU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G17AU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G17AU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G17AU Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G17AU Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G17AU Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G17AU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G17AU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G17AU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G17AU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G17AU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G17AU Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21G17AU Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21G17AU Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21G17AU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G17AU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G17AU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G17AU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G17AU Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -230,7 +228,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

172
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,96 +93,94 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G18A Basic Timer Counter 5 (TC5) */
ADC_IRQn = 23, /**< 23 SAMD21G18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G18A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnReserved21;
void* pfnReserved22;
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -225,7 +223,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

182
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21g18au.h
View File

@ -40,9 +40,9 @@
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef _SAMD21G18AU_
#define _SAMD21G18AU_
@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G18AU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21G18AU-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21G18AU Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21G18AU System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21G18AU Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21G18AU Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21G18AU External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21G18AU Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21G18AU Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21G18AU Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21G18AU Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21G18AU Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21G18AU Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21G18AU Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21G18AU Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21G18AU Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21G18AU Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21G18AU Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21G18AU Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21G18AU Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21G18AU Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21G18AU Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21G18AU Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21G18AU Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21G18AU Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21G18AU Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21G18AU Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21G18AU Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21G18AU Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21G18AU Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

176
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J15A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J15A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J15A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J15A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J15A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J15A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J15A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J15A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J15A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J15A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J15A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J15A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J15A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J15A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J15A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J15A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J15A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J15A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J15A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J15A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J15A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J15A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J15A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J15A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J15A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J15A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J15A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J15A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J15A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J15A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

178
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j15b.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J15B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J15B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J15B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J15B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J15B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J15B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J15B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J15B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J15B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J15B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J15B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J15B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J15B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J15B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J15B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J15B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J15B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J15B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J15B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J15B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J15B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J15B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J15B Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J15B Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J15B Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J15B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J15B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J15B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J15B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J15B Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

176
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J16A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J16A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J16A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J16A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J16A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J16A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J16A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J16A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J16A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J16A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J16A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J16A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J16A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J16A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J16A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J16A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J16A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J16A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J16A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J16A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J16A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J16A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J16A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J16A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J16A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J16A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J16A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J16A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J16A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J16A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

178
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j16b.h
View File

@ -56,7 +56,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -90,99 +90,97 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J16B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J16B-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J16B Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J16B System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J16B Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J16B Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J16B External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J16B Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J16B Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J16B Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J16B Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J16B Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J16B Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J16B Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J16B Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J16B Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J16B Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J16B Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J16B Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J16B Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J16B Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J16B Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J16B Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J16B Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J16B Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J16B Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J16B Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J16B Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J16B Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J16B Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
void* pfnReserved28;
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -227,7 +225,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

176
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j17a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J17A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J17A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J17A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J17A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J17A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J17A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J17A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J17A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J17A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J17A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J17A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J17A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J17A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J17A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J17A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J17A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J17A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J17A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J17A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J17A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J17A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J17A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J17A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J17A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J17A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J17A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J17A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J17A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J17A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J17A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

176
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMD21/include/samd21j18a.h
View File

@ -59,7 +59,7 @@
/*@{*/
#ifdef __cplusplus
extern "C" {
extern "C" {
#endif
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
@ -93,98 +93,96 @@ typedef volatile uint8_t RwReg8; /**< Read-Write 8-bit register (volati
/*@{*/
/** Interrupt Number Definition */
typedef enum IRQn
{
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
typedef enum IRQn {
/****** Cortex-M0+ Processor Exceptions Numbers ******************************/
NonMaskableInt_IRQn = -14,/**< 2 Non Maskable Interrupt */
HardFault_IRQn = -13,/**< 3 Cortex-M0+ Hard Fault Interrupt */
SVCall_IRQn = -5, /**< 11 Cortex-M0+ SV Call Interrupt */
PendSV_IRQn = -2, /**< 14 Cortex-M0+ Pend SV Interrupt */
SysTick_IRQn = -1, /**< 15 Cortex-M0+ System Tick Interrupt */
/****** SAMD21J18A-specific Interrupt Numbers ***********************/
PM_IRQn = 0, /**< 0 SAMD21J18A Power Manager (PM) */
SYSCTRL_IRQn = 1, /**< 1 SAMD21J18A System Control (SYSCTRL) */
WDT_IRQn = 2, /**< 2 SAMD21J18A Watchdog Timer (WDT) */
RTC_IRQn = 3, /**< 3 SAMD21J18A Real-Time Counter (RTC) */
EIC_IRQn = 4, /**< 4 SAMD21J18A External Interrupt Controller (EIC) */
NVMCTRL_IRQn = 5, /**< 5 SAMD21J18A Non-Volatile Memory Controller (NVMCTRL) */
DMAC_IRQn = 6, /**< 6 SAMD21J18A Direct Memory Access Controller (DMAC) */
USB_IRQn = 7, /**< 7 SAMD21J18A Universal Serial Bus (USB) */
EVSYS_IRQn = 8, /**< 8 SAMD21J18A Event System Interface (EVSYS) */
SERCOM0_IRQn = 9, /**< 9 SAMD21J18A Serial Communication Interface 0 (SERCOM0) */
SERCOM1_IRQn = 10, /**< 10 SAMD21J18A Serial Communication Interface 1 (SERCOM1) */
SERCOM2_IRQn = 11, /**< 11 SAMD21J18A Serial Communication Interface 2 (SERCOM2) */
SERCOM3_IRQn = 12, /**< 12 SAMD21J18A Serial Communication Interface 3 (SERCOM3) */
SERCOM4_IRQn = 13, /**< 13 SAMD21J18A Serial Communication Interface 4 (SERCOM4) */
SERCOM5_IRQn = 14, /**< 14 SAMD21J18A Serial Communication Interface 5 (SERCOM5) */
TCC0_IRQn = 15, /**< 15 SAMD21J18A Timer Counter Control 0 (TCC0) */
TCC1_IRQn = 16, /**< 16 SAMD21J18A Timer Counter Control 1 (TCC1) */
TCC2_IRQn = 17, /**< 17 SAMD21J18A Timer Counter Control 2 (TCC2) */
TC3_IRQn = 18, /**< 18 SAMD21J18A Basic Timer Counter 3 (TC3) */
TC4_IRQn = 19, /**< 19 SAMD21J18A Basic Timer Counter 4 (TC4) */
TC5_IRQn = 20, /**< 20 SAMD21J18A Basic Timer Counter 5 (TC5) */
TC6_IRQn = 21, /**< 21 SAMD21J18A Basic Timer Counter 6 (TC6) */
TC7_IRQn = 22, /**< 22 SAMD21J18A Basic Timer Counter 7 (TC7) */
ADC_IRQn = 23, /**< 23 SAMD21J18A Analog Digital Converter (ADC) */
AC_IRQn = 24, /**< 24 SAMD21J18A Analog Comparators (AC) */
DAC_IRQn = 25, /**< 25 SAMD21J18A Digital Analog Converter (DAC) */
PTC_IRQn = 26, /**< 26 SAMD21J18A Peripheral Touch Controller (PTC) */
I2S_IRQn = 27, /**< 27 SAMD21J18A Inter-IC Sound Interface (I2S) */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
PERIPH_COUNT_IRQn = 28 /**< Number of peripheral IDs */
} IRQn_Type;
typedef struct _DeviceVectors
{
/* Stack pointer */
void* pvStack;
typedef struct _DeviceVectors {
/* Stack pointer */
void* pvStack;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Cortex-M handlers */
void* pfnReset_Handler;
void* pfnNMI_Handler;
void* pfnHardFault_Handler;
void* pfnReservedM12;
void* pfnReservedM11;
void* pfnReservedM10;
void* pfnReservedM9;
void* pfnReservedM8;
void* pfnReservedM7;
void* pfnReservedM6;
void* pfnSVC_Handler;
void* pfnReservedM4;
void* pfnReservedM3;
void* pfnPendSV_Handler;
void* pfnSysTick_Handler;
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
/* Peripheral handlers */
void* pfnPM_Handler; /* 0 Power Manager */
void* pfnSYSCTRL_Handler; /* 1 System Control */
void* pfnWDT_Handler; /* 2 Watchdog Timer */
void* pfnRTC_Handler; /* 3 Real-Time Counter */
void* pfnEIC_Handler; /* 4 External Interrupt Controller */
void* pfnNVMCTRL_Handler; /* 5 Non-Volatile Memory Controller */
void* pfnDMAC_Handler; /* 6 Direct Memory Access Controller */
void* pfnUSB_Handler; /* 7 Universal Serial Bus */
void* pfnEVSYS_Handler; /* 8 Event System Interface */
void* pfnSERCOM0_Handler; /* 9 Serial Communication Interface 0 */
void* pfnSERCOM1_Handler; /* 10 Serial Communication Interface 1 */
void* pfnSERCOM2_Handler; /* 11 Serial Communication Interface 2 */
void* pfnSERCOM3_Handler; /* 12 Serial Communication Interface 3 */
void* pfnSERCOM4_Handler; /* 13 Serial Communication Interface 4 */
void* pfnSERCOM5_Handler; /* 14 Serial Communication Interface 5 */
void* pfnTCC0_Handler; /* 15 Timer Counter Control 0 */
void* pfnTCC1_Handler; /* 16 Timer Counter Control 1 */
void* pfnTCC2_Handler; /* 17 Timer Counter Control 2 */
void* pfnTC3_Handler; /* 18 Basic Timer Counter 3 */
void* pfnTC4_Handler; /* 19 Basic Timer Counter 4 */
void* pfnTC5_Handler; /* 20 Basic Timer Counter 5 */
void* pfnTC6_Handler; /* 21 Basic Timer Counter 6 */
void* pfnTC7_Handler; /* 22 Basic Timer Counter 7 */
void* pfnADC_Handler; /* 23 Analog Digital Converter */
void* pfnAC_Handler; /* 24 Analog Comparators */
void* pfnDAC_Handler; /* 25 Digital Analog Converter */
void* pfnPTC_Handler; /* 26 Peripheral Touch Controller */
void* pfnI2S_Handler; /* 27 Inter-IC Sound Interface */
} DeviceVectors;
/* Cortex-M0+ processor handlers */
@ -229,7 +227,7 @@ void I2S_Handler ( void );
* \brief Configuration of the Cortex-M0+ Processor and Core Peripherals
*/
#define LITTLE_ENDIAN 1
#define LITTLE_ENDIAN 1
#define __CM0PLUS_REV 1 /*!< Core revision r0p1 */
#define __MPU_PRESENT 0 /*!< MPU present or not */
#define __NVIC_PRIO_BITS 2 /*!< Number of bits used for Priority Levels */

322
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_ac.h
View File

@ -56,14 +56,14 @@
/* -------- AC_CTRLA : (AC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :4; /*!< bit: 3.. 6 Reserved */
uint8_t LPMUX:1; /*!< bit: 7 Low-Power Mux */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -84,16 +84,16 @@ typedef union {
/* -------- AC_CTRLB : (AC Offset: 0x01) ( /W 8) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t START0:1; /*!< bit: 0 Comparator 0 Start Comparison */
uint8_t START1:1; /*!< bit: 1 Comparator 1 Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t START:2; /*!< bit: 0.. 1 Comparator x Start Comparison */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -112,25 +112,25 @@ typedef union {
/* -------- AC_EVCTRL : (AC Offset: 0x02) (R/W 16) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COMPEO0:1; /*!< bit: 0 Comparator 0 Event Output Enable */
uint16_t COMPEO1:1; /*!< bit: 1 Comparator 1 Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO0:1; /*!< bit: 4 Window 0 Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI0:1; /*!< bit: 8 Comparator 0 Event Input */
uint16_t COMPEI1:1; /*!< bit: 9 Comparator 1 Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t COMPEO:2; /*!< bit: 0.. 1 Comparator x Event Output Enable */
uint16_t :2; /*!< bit: 2.. 3 Reserved */
uint16_t WINEO:1; /*!< bit: 4 Window x Event Output Enable */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t COMPEI:2; /*!< bit: 8.. 9 Comparator x Event Input */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} AC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -161,20 +161,20 @@ typedef union {
/* -------- AC_INTENCLR : (AC Offset: 0x04) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -198,20 +198,20 @@ typedef union {
/* -------- AC_INTENSET : (AC Offset: 0x05) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t COMP0:1; /*!< bit: 0 Comparator 0 Interrupt Enable */
uint8_t COMP1:1; /*!< bit: 1 Comparator 1 Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN0:1; /*!< bit: 4 Window 0 Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x Interrupt Enable */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WIN:1; /*!< bit: 4 Window x Interrupt Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -235,20 +235,20 @@ typedef union {
/* -------- AC_INTFLAG : (AC Offset: 0x06) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t WIN:1; /*!< bit: 4 Window x */
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
__I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
__I uint8_t :2; /*!< bit: 2.. 3 Reserved */
__I uint8_t WIN:1; /*!< bit: 4 Window x */
__I uint8_t :3; /*!< bit: 5.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -272,18 +272,18 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- AC_STATUSA : (AC Offset: 0x08) (R/ 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -311,17 +311,17 @@ typedef union {
/* -------- AC_STATUSB : (AC Offset: 0x09) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY0:1; /*!< bit: 0 Comparator 0 Ready */
uint8_t READY1:1; /*!< bit: 1 Comparator 1 Ready */
uint8_t :5; /*!< bit: 2.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
struct {
uint8_t READY:2; /*!< bit: 0.. 1 Comparator x Ready */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -342,18 +342,18 @@ typedef union {
/* -------- AC_STATUSC : (AC Offset: 0x0A) (R/ 8) Status C -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STATE0:1; /*!< bit: 0 Comparator 0 Current State */
uint8_t STATE1:1; /*!< bit: 1 Comparator 1 Current State */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t WSTATE0:2; /*!< bit: 4.. 5 Window 0 Current State */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t STATE:2; /*!< bit: 0.. 1 Comparator x Current State */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} AC_STATUSC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -381,12 +381,12 @@ typedef union {
/* -------- AC_WINCTRL : (AC Offset: 0x0C) (R/W 8) Window Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WEN0:1; /*!< bit: 0 Window 0 Mode Enable */
uint8_t WINTSEL0:2; /*!< bit: 1.. 2 Window 0 Interrupt Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -411,26 +411,26 @@ typedef union {
/* -------- AC_COMPCTRL : (AC Offset: 0x10) (R/W 32) Comparator Control n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ENABLE:1; /*!< bit: 0 Enable */
uint32_t SINGLE:1; /*!< bit: 1 Single-Shot Mode */
uint32_t SPEED:2; /*!< bit: 2.. 3 Speed Selection */
uint32_t :1; /*!< bit: 4 Reserved */
uint32_t INTSEL:2; /*!< bit: 5.. 6 Interrupt Selection */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t MUXNEG:3; /*!< bit: 8..10 Negative Input Mux Selection */
uint32_t :1; /*!< bit: 11 Reserved */
uint32_t MUXPOS:2; /*!< bit: 12..13 Positive Input Mux Selection */
uint32_t :1; /*!< bit: 14 Reserved */
uint32_t SWAP:1; /*!< bit: 15 Swap Inputs and Invert */
uint32_t OUT:2; /*!< bit: 16..17 Output */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t HYST:1; /*!< bit: 19 Hysteresis Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t FLEN:3; /*!< bit: 24..26 Filter Length */
uint32_t :5; /*!< bit: 27..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} AC_COMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -516,11 +516,11 @@ typedef union {
/* -------- AC_SCALER : (AC Offset: 0x20) (R/W 8) Scaler n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t VALUE:6; /*!< bit: 0.. 5 Scaler Value */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} AC_SCALER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -535,22 +535,22 @@ typedef union {
/** \brief AC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
__IO AC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__O AC_CTRLB_Type CTRLB; /**< \brief Offset: 0x01 ( /W 8) Control B */
__IO AC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x02 (R/W 16) Event Control */
__IO AC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x04 (R/W 8) Interrupt Enable Clear */
__IO AC_INTENSET_Type INTENSET; /**< \brief Offset: 0x05 (R/W 8) Interrupt Enable Set */
__IO AC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x06 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x08 (R/ 8) Status A */
__I AC_STATUSB_Type STATUSB; /**< \brief Offset: 0x09 (R/ 8) Status B */
__I AC_STATUSC_Type STATUSC; /**< \brief Offset: 0x0A (R/ 8) Status C */
RoReg8 Reserved2[0x1];
__IO AC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x0C (R/W 8) Window Control */
RoReg8 Reserved3[0x3];
__IO AC_COMPCTRL_Type COMPCTRL[2]; /**< \brief Offset: 0x10 (R/W 32) Comparator Control n */
RoReg8 Reserved4[0x8];
__IO AC_SCALER_Type SCALER[2]; /**< \brief Offset: 0x20 (R/W 8) Scaler n */
} Ac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

308
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_adc.h
View File

@ -56,13 +56,13 @@
/* -------- ADC_CTRLA : (ADC Offset: 0x00) (R/W 8) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t RUNSTDBY:1; /*!< bit: 2 Run in Standby */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -80,12 +80,12 @@ typedef union {
/* -------- ADC_REFCTRL : (ADC Offset: 0x01) (R/W 8) Reference Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t REFSEL:4; /*!< bit: 0.. 3 Reference Selection */
uint8_t :3; /*!< bit: 4.. 6 Reserved */
uint8_t REFCOMP:1; /*!< bit: 7 Reference Buffer Offset Compensation Enable */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_REFCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -112,12 +112,12 @@ typedef union {
/* -------- ADC_AVGCTRL : (ADC Offset: 0x02) (R/W 8) Average Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SAMPLENUM:4; /*!< bit: 0.. 3 Number of Samples to be Collected */
uint8_t ADJRES:3; /*!< bit: 4.. 6 Adjusting Result / Division Coefficient */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_AVGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -157,11 +157,11 @@ typedef union {
/* -------- ADC_SAMPCTRL : (ADC Offset: 0x03) (R/W 8) Sampling Time Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SAMPLEN:6; /*!< bit: 0.. 5 Sampling Time Length */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SAMPCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -176,17 +176,17 @@ typedef union {
/* -------- ADC_CTRLB : (ADC Offset: 0x04) (R/W 16) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t DIFFMODE:1; /*!< bit: 0 Differential Mode */
uint16_t LEFTADJ:1; /*!< bit: 1 Left-Adjusted Result */
uint16_t FREERUN:1; /*!< bit: 2 Free Running Mode */
uint16_t CORREN:1; /*!< bit: 3 Digital Correction Logic Enabled */
uint16_t RESSEL:2; /*!< bit: 4.. 5 Conversion Result Resolution */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t PRESCALER:3; /*!< bit: 8..10 Prescaler Configuration */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -236,11 +236,11 @@ typedef union {
/* -------- ADC_WINCTRL : (ADC Offset: 0x08) (R/W 8) Window Monitor Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WINMODE:3; /*!< bit: 0.. 2 Window Monitor Mode */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_WINCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -265,12 +265,12 @@ typedef union {
/* -------- ADC_SWTRIG : (ADC Offset: 0x0C) (R/W 8) Software Trigger -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t FLUSH:1; /*!< bit: 0 ADC Conversion Flush */
uint8_t START:1; /*!< bit: 1 ADC Start Conversion */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_SWTRIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -286,17 +286,17 @@ typedef union {
/* -------- ADC_INPUTCTRL : (ADC Offset: 0x10) (R/W 32) Input Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MUXPOS:5; /*!< bit: 0.. 4 Positive Mux Input Selection */
uint32_t :3; /*!< bit: 5.. 7 Reserved */
uint32_t MUXNEG:5; /*!< bit: 8..12 Negative Mux Input Selection */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t INPUTSCAN:4; /*!< bit: 16..19 Number of Input Channels Included in Scan */
uint32_t INPUTOFFSET:4; /*!< bit: 20..23 Positive Mux Setting Offset */
uint32_t GAIN:4; /*!< bit: 24..27 Gain Factor Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} ADC_INPUTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -405,15 +405,15 @@ typedef union {
/* -------- ADC_EVCTRL : (ADC Offset: 0x14) (R/W 8) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t STARTEI:1; /*!< bit: 0 Start Conversion Event In */
uint8_t SYNCEI:1; /*!< bit: 1 Synchronization Event In */
uint8_t :2; /*!< bit: 2.. 3 Reserved */
uint8_t RESRDYEO:1; /*!< bit: 4 Result Ready Event Out */
uint8_t WINMONEO:1; /*!< bit: 5 Window Monitor Event Out */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -433,14 +433,14 @@ typedef union {
/* -------- ADC_INTENCLR : (ADC Offset: 0x16) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -460,14 +460,14 @@ typedef union {
/* -------- ADC_INTENSET : (ADC Offset: 0x17) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t RESRDY:1; /*!< bit: 0 Result Ready Interrupt Enable */
uint8_t OVERRUN:1; /*!< bit: 1 Overrun Interrupt Enable */
uint8_t WINMON:1; /*!< bit: 2 Window Monitor Interrupt Enable */
uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready Interrupt Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -487,14 +487,14 @@ typedef union {
/* -------- ADC_INTFLAG : (ADC Offset: 0x18) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t RESRDY:1; /*!< bit: 0 Result Ready */
__I uint8_t OVERRUN:1; /*!< bit: 1 Overrun */
__I uint8_t WINMON:1; /*!< bit: 2 Window Monitor */
__I uint8_t SYNCRDY:1; /*!< bit: 3 Synchronization Ready */
__I uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -514,11 +514,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- ADC_STATUS : (ADC Offset: 0x19) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -532,10 +532,10 @@ typedef union {
/* -------- ADC_RESULT : (ADC Offset: 0x1A) (R/ 16) Result -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t RESULT:16; /*!< bit: 0..15 Result Conversion Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_RESULT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -550,10 +550,10 @@ typedef union {
/* -------- ADC_WINLT : (ADC Offset: 0x1C) (R/W 16) Window Monitor Lower Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t WINLT:16; /*!< bit: 0..15 Window Lower Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINLT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -568,10 +568,10 @@ typedef union {
/* -------- ADC_WINUT : (ADC Offset: 0x20) (R/W 16) Window Monitor Upper Threshold -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t WINUT:16; /*!< bit: 0..15 Window Upper Threshold */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_WINUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -586,11 +586,11 @@ typedef union {
/* -------- ADC_GAINCORR : (ADC Offset: 0x24) (R/W 16) Gain Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t GAINCORR:12; /*!< bit: 0..11 Gain Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_GAINCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -605,11 +605,11 @@ typedef union {
/* -------- ADC_OFFSETCORR : (ADC Offset: 0x26) (R/W 16) Offset Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t OFFSETCORR:12; /*!< bit: 0..11 Offset Correction Value */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_OFFSETCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -624,12 +624,12 @@ typedef union {
/* -------- ADC_CALIB : (ADC Offset: 0x28) (R/W 16) Calibration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t LINEARITY_CAL:8; /*!< bit: 0.. 7 Linearity Calibration Value */
uint16_t BIAS_CAL:3; /*!< bit: 8..10 Bias Calibration Value */
uint16_t :5; /*!< bit: 11..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} ADC_CALIB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -647,11 +647,11 @@ typedef union {
/* -------- ADC_DBGCTRL : (ADC Offset: 0x2A) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} ADC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -665,32 +665,32 @@ typedef union {
/** \brief ADC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
__IO ADC_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 8) Control A */
__IO ADC_REFCTRL_Type REFCTRL; /**< \brief Offset: 0x01 (R/W 8) Reference Control */
__IO ADC_AVGCTRL_Type AVGCTRL; /**< \brief Offset: 0x02 (R/W 8) Average Control */
__IO ADC_SAMPCTRL_Type SAMPCTRL; /**< \brief Offset: 0x03 (R/W 8) Sampling Time Control */
__IO ADC_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 16) Control B */
RoReg8 Reserved1[0x2];
__IO ADC_WINCTRL_Type WINCTRL; /**< \brief Offset: 0x08 (R/W 8) Window Monitor Control */
RoReg8 Reserved2[0x3];
__IO ADC_SWTRIG_Type SWTRIG; /**< \brief Offset: 0x0C (R/W 8) Software Trigger */
RoReg8 Reserved3[0x3];
__IO ADC_INPUTCTRL_Type INPUTCTRL; /**< \brief Offset: 0x10 (R/W 32) Input Control */
__IO ADC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x14 (R/W 8) Event Control */
RoReg8 Reserved4[0x1];
__IO ADC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x16 (R/W 8) Interrupt Enable Clear */
__IO ADC_INTENSET_Type INTENSET; /**< \brief Offset: 0x17 (R/W 8) Interrupt Enable Set */
__IO ADC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 8) Interrupt Flag Status and Clear */
__I ADC_STATUS_Type STATUS; /**< \brief Offset: 0x19 (R/ 8) Status */
__I ADC_RESULT_Type RESULT; /**< \brief Offset: 0x1A (R/ 16) Result */
__IO ADC_WINLT_Type WINLT; /**< \brief Offset: 0x1C (R/W 16) Window Monitor Lower Threshold */
RoReg8 Reserved5[0x2];
__IO ADC_WINUT_Type WINUT; /**< \brief Offset: 0x20 (R/W 16) Window Monitor Upper Threshold */
RoReg8 Reserved6[0x2];
__IO ADC_GAINCORR_Type GAINCORR; /**< \brief Offset: 0x24 (R/W 16) Gain Correction */
__IO ADC_OFFSETCORR_Type OFFSETCORR; /**< \brief Offset: 0x26 (R/W 16) Offset Correction */
__IO ADC_CALIB_Type CALIB; /**< \brief Offset: 0x28 (R/W 16) Calibration */
__IO ADC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x2A (R/W 8) Debug Control */
} Adc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

594
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dmac.h
View File

@ -56,23 +56,23 @@
/* -------- DMAC_CTRL : (DMAC Offset: 0x00) (R/W 16) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :8; /*!< bit: 0.. 7 Reserved */
uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t DMAENABLE:1; /*!< bit: 1 DMA Enable */
uint16_t CRCENABLE:1; /*!< bit: 2 CRC Enable */
uint16_t :5; /*!< bit: 3.. 7 Reserved */
uint16_t LVLEN0:1; /*!< bit: 8 Priority Level 0 Enable */
uint16_t LVLEN1:1; /*!< bit: 9 Priority Level 1 Enable */
uint16_t LVLEN2:1; /*!< bit: 10 Priority Level 2 Enable */
uint16_t LVLEN3:1; /*!< bit: 11 Priority Level 3 Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint16_t :8; /*!< bit: 0.. 7 Reserved */
uint16_t LVLEN:4; /*!< bit: 8..11 Priority Level x Enable */
uint16_t :4; /*!< bit: 12..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} DMAC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -101,14 +101,14 @@ typedef union {
/* -------- DMAC_CRCCTRL : (DMAC Offset: 0x02) (R/W 16) CRC Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CRCBEATSIZE:2; /*!< bit: 0.. 1 CRC Beat Size */
uint16_t CRCPOLY:2; /*!< bit: 2.. 3 CRC Polynomial Type */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t CRCSRC:6; /*!< bit: 8..13 CRC Input Source */
uint16_t :2; /*!< bit: 14..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_CRCCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -143,10 +143,10 @@ typedef union {
/* -------- DMAC_CRCDATAIN : (DMAC Offset: 0x04) (R/W 32) CRC Data Input -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CRCDATAIN:32; /*!< bit: 0..31 CRC Data Input */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CRCDATAIN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -161,10 +161,10 @@ typedef union {
/* -------- DMAC_CRCCHKSUM : (DMAC Offset: 0x08) (R/W 32) CRC Checksum -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CRCCHKSUM:32; /*!< bit: 0..31 CRC Checksum */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CRCCHKSUM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -179,12 +179,12 @@ typedef union {
/* -------- DMAC_CRCSTATUS : (DMAC Offset: 0x0C) (R/W 8) CRC Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CRCBUSY:1; /*!< bit: 0 CRC Module Busy */
uint8_t CRCZERO:1; /*!< bit: 1 CRC Zero */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CRCSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -200,11 +200,11 @@ typedef union {
/* -------- DMAC_DBGCTRL : (DMAC Offset: 0x0D) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Debug Run */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -218,13 +218,13 @@ typedef union {
/* -------- DMAC_QOSCTRL : (DMAC Offset: 0x0E) (R/W 8) QOS Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t WRBQOS:2; /*!< bit: 0.. 1 Write-Back Quality of Service */
uint8_t FQOS:2; /*!< bit: 2.. 3 Fetch Quality of Service */
uint8_t DQOS:2; /*!< bit: 4.. 5 Data Transfer Quality of Service */
uint8_t :2; /*!< bit: 6.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_QOSCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -269,26 +269,26 @@ typedef union {
/* -------- DMAC_SWTRIGCTRL : (DMAC Offset: 0x10) (R/W 32) Software Trigger Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SWTRIG0:1; /*!< bit: 0 Channel 0 Software Trigger */
uint32_t SWTRIG1:1; /*!< bit: 1 Channel 1 Software Trigger */
uint32_t SWTRIG2:1; /*!< bit: 2 Channel 2 Software Trigger */
uint32_t SWTRIG3:1; /*!< bit: 3 Channel 3 Software Trigger */
uint32_t SWTRIG4:1; /*!< bit: 4 Channel 4 Software Trigger */
uint32_t SWTRIG5:1; /*!< bit: 5 Channel 5 Software Trigger */
uint32_t SWTRIG6:1; /*!< bit: 6 Channel 6 Software Trigger */
uint32_t SWTRIG7:1; /*!< bit: 7 Channel 7 Software Trigger */
uint32_t SWTRIG8:1; /*!< bit: 8 Channel 8 Software Trigger */
uint32_t SWTRIG9:1; /*!< bit: 9 Channel 9 Software Trigger */
uint32_t SWTRIG10:1; /*!< bit: 10 Channel 10 Software Trigger */
uint32_t SWTRIG11:1; /*!< bit: 11 Channel 11 Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t SWTRIG:12; /*!< bit: 0..11 Channel x Software Trigger */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_SWTRIGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -327,21 +327,21 @@ typedef union {
/* -------- DMAC_PRICTRL0 : (DMAC Offset: 0x14) (R/W 32) Priority Control 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
uint32_t :3; /*!< bit: 4.. 6 Reserved */
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
uint32_t :3; /*!< bit: 20..22 Reserved */
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
uint32_t :3; /*!< bit: 28..30 Reserved */
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LVLPRI0:4; /*!< bit: 0.. 3 Level 0 Channel Priority Number */
uint32_t :3; /*!< bit: 4.. 6 Reserved */
uint32_t RRLVLEN0:1; /*!< bit: 7 Level 0 Round-Robin Scheduling Enable */
uint32_t LVLPRI1:4; /*!< bit: 8..11 Level 1 Channel Priority Number */
uint32_t :3; /*!< bit: 12..14 Reserved */
uint32_t RRLVLEN1:1; /*!< bit: 15 Level 1 Round-Robin Scheduling Enable */
uint32_t LVLPRI2:4; /*!< bit: 16..19 Level 2 Channel Priority Number */
uint32_t :3; /*!< bit: 20..22 Reserved */
uint32_t RRLVLEN2:1; /*!< bit: 23 Level 2 Round-Robin Scheduling Enable */
uint32_t LVLPRI3:4; /*!< bit: 24..27 Level 3 Channel Priority Number */
uint32_t :3; /*!< bit: 28..30 Reserved */
uint32_t RRLVLEN3:1; /*!< bit: 31 Level 3 Round-Robin Scheduling Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_PRICTRL0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -373,18 +373,18 @@ typedef union {
/* -------- DMAC_INTPEND : (DMAC Offset: 0x20) (R/W 16) Interrupt Pending -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
uint16_t :2; /*!< bit: 11..12 Reserved */
uint16_t FERR:1; /*!< bit: 13 Fetch Error */
uint16_t BUSY:1; /*!< bit: 14 Busy */
uint16_t PEND:1; /*!< bit: 15 Pending */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t TERR:1; /*!< bit: 8 Transfer Error */
uint16_t TCMPL:1; /*!< bit: 9 Transfer Complete */
uint16_t SUSP:1; /*!< bit: 10 Channel Suspend */
uint16_t :2; /*!< bit: 11..12 Reserved */
uint16_t FERR:1; /*!< bit: 13 Fetch Error */
uint16_t BUSY:1; /*!< bit: 14 Busy */
uint16_t PEND:1; /*!< bit: 15 Pending */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_INTPEND_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -411,26 +411,26 @@ typedef union {
/* -------- DMAC_INTSTATUS : (DMAC Offset: 0x24) (R/ 32) Interrupt Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CHINT0:1; /*!< bit: 0 Channel 0 Pending Interrupt */
uint32_t CHINT1:1; /*!< bit: 1 Channel 1 Pending Interrupt */
uint32_t CHINT2:1; /*!< bit: 2 Channel 2 Pending Interrupt */
uint32_t CHINT3:1; /*!< bit: 3 Channel 3 Pending Interrupt */
uint32_t CHINT4:1; /*!< bit: 4 Channel 4 Pending Interrupt */
uint32_t CHINT5:1; /*!< bit: 5 Channel 5 Pending Interrupt */
uint32_t CHINT6:1; /*!< bit: 6 Channel 6 Pending Interrupt */
uint32_t CHINT7:1; /*!< bit: 7 Channel 7 Pending Interrupt */
uint32_t CHINT8:1; /*!< bit: 8 Channel 8 Pending Interrupt */
uint32_t CHINT9:1; /*!< bit: 9 Channel 9 Pending Interrupt */
uint32_t CHINT10:1; /*!< bit: 10 Channel 10 Pending Interrupt */
uint32_t CHINT11:1; /*!< bit: 11 Channel 11 Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t CHINT:12; /*!< bit: 0..11 Channel x Pending Interrupt */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_INTSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -469,26 +469,26 @@ typedef union {
/* -------- DMAC_BUSYCH : (DMAC Offset: 0x28) (R/ 32) Busy Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t BUSYCH0:1; /*!< bit: 0 Busy Channel 0 */
uint32_t BUSYCH1:1; /*!< bit: 1 Busy Channel 1 */
uint32_t BUSYCH2:1; /*!< bit: 2 Busy Channel 2 */
uint32_t BUSYCH3:1; /*!< bit: 3 Busy Channel 3 */
uint32_t BUSYCH4:1; /*!< bit: 4 Busy Channel 4 */
uint32_t BUSYCH5:1; /*!< bit: 5 Busy Channel 5 */
uint32_t BUSYCH6:1; /*!< bit: 6 Busy Channel 6 */
uint32_t BUSYCH7:1; /*!< bit: 7 Busy Channel 7 */
uint32_t BUSYCH8:1; /*!< bit: 8 Busy Channel 8 */
uint32_t BUSYCH9:1; /*!< bit: 9 Busy Channel 9 */
uint32_t BUSYCH10:1; /*!< bit: 10 Busy Channel 10 */
uint32_t BUSYCH11:1; /*!< bit: 11 Busy Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t BUSYCH:12; /*!< bit: 0..11 Busy Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_BUSYCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -527,26 +527,26 @@ typedef union {
/* -------- DMAC_PENDCH : (DMAC Offset: 0x2C) (R/ 32) Pending Channels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PENDCH0:1; /*!< bit: 0 Pending Channel 0 */
uint32_t PENDCH1:1; /*!< bit: 1 Pending Channel 1 */
uint32_t PENDCH2:1; /*!< bit: 2 Pending Channel 2 */
uint32_t PENDCH3:1; /*!< bit: 3 Pending Channel 3 */
uint32_t PENDCH4:1; /*!< bit: 4 Pending Channel 4 */
uint32_t PENDCH5:1; /*!< bit: 5 Pending Channel 5 */
uint32_t PENDCH6:1; /*!< bit: 6 Pending Channel 6 */
uint32_t PENDCH7:1; /*!< bit: 7 Pending Channel 7 */
uint32_t PENDCH8:1; /*!< bit: 8 Pending Channel 8 */
uint32_t PENDCH9:1; /*!< bit: 9 Pending Channel 9 */
uint32_t PENDCH10:1; /*!< bit: 10 Pending Channel 10 */
uint32_t PENDCH11:1; /*!< bit: 11 Pending Channel 11 */
uint32_t :20; /*!< bit: 12..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t PENDCH:12; /*!< bit: 0..11 Pending Channel x */
uint32_t :20; /*!< bit: 12..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_PENDCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -585,22 +585,22 @@ typedef union {
/* -------- DMAC_ACTIVE : (DMAC Offset: 0x30) (R/ 32) Active Channel and Levels -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
} bit; /*!< Structure used for bit access */
struct {
uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t LVLEX0:1; /*!< bit: 0 Level 0 Channel Trigger Request Executing */
uint32_t LVLEX1:1; /*!< bit: 1 Level 1 Channel Trigger Request Executing */
uint32_t LVLEX2:1; /*!< bit: 2 Level 2 Channel Trigger Request Executing */
uint32_t LVLEX3:1; /*!< bit: 3 Level 3 Channel Trigger Request Executing */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t ID:5; /*!< bit: 8..12 Active Channel ID */
uint32_t :2; /*!< bit: 13..14 Reserved */
uint32_t ABUSY:1; /*!< bit: 15 Active Channel Busy */
uint32_t BTCNT:16; /*!< bit: 16..31 Active Channel Block Transfer Count */
} bit; /*!< Structure used for bit access */
struct {
uint32_t LVLEX:4; /*!< bit: 0.. 3 Level x Channel Trigger Request Executing */
uint32_t :28; /*!< bit: 4..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} DMAC_ACTIVE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -631,10 +631,10 @@ typedef union {
/* -------- DMAC_BASEADDR : (DMAC Offset: 0x34) (R/W 32) Descriptor Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t BASEADDR:32; /*!< bit: 0..31 Descriptor Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_BASEADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -649,10 +649,10 @@ typedef union {
/* -------- DMAC_WRBADDR : (DMAC Offset: 0x38) (R/W 32) Write-Back Memory Section Base Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t WRBADDR:32; /*!< bit: 0..31 Write-Back Memory Base Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_WRBADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -667,11 +667,11 @@ typedef union {
/* -------- DMAC_CHID : (DMAC Offset: 0x3F) (R/W 8) Channel ID -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ID:4; /*!< bit: 0.. 3 Channel ID */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -686,12 +686,12 @@ typedef union {
/* -------- DMAC_CHCTRLA : (DMAC Offset: 0x40) (R/W 8) Channel Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Channel Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Channel Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHCTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -707,19 +707,19 @@ typedef union {
/* -------- DMAC_CHCTRLB : (DMAC Offset: 0x44) (R/W 32) Channel Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
uint32_t :8; /*!< bit: 14..21 Reserved */
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EVACT:3; /*!< bit: 0.. 2 Event Input Action */
uint32_t EVIE:1; /*!< bit: 3 Channel Event Input Enable */
uint32_t EVOE:1; /*!< bit: 4 Channel Event Output Enable */
uint32_t LVL:2; /*!< bit: 5.. 6 Channel Arbitration Level */
uint32_t :1; /*!< bit: 7 Reserved */
uint32_t TRIGSRC:6; /*!< bit: 8..13 Trigger Source */
uint32_t :8; /*!< bit: 14..21 Reserved */
uint32_t TRIGACT:2; /*!< bit: 22..23 Trigger Action */
uint32_t CMD:2; /*!< bit: 24..25 Software Command */
uint32_t :6; /*!< bit: 26..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_CHCTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -786,13 +786,13 @@ typedef union {
/* -------- DMAC_CHINTENCLR : (DMAC Offset: 0x4C) (R/W 8) Channel Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -810,13 +810,13 @@ typedef union {
/* -------- DMAC_CHINTENSET : (DMAC Offset: 0x4D) (R/W 8) Channel Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error Interrupt Enable */
uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete Interrupt Enable */
uint8_t SUSP:1; /*!< bit: 2 Channel Suspend Interrupt Enable */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -834,13 +834,13 @@ typedef union {
/* -------- DMAC_CHINTFLAG : (DMAC Offset: 0x4E) (R/W 8) Channel Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
__I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
__I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t TERR:1; /*!< bit: 0 Channel Transfer Error */
__I uint8_t TCMPL:1; /*!< bit: 1 Channel Transfer Complete */
__I uint8_t SUSP:1; /*!< bit: 2 Channel Suspend */
__I uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHINTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -858,13 +858,13 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- DMAC_CHSTATUS : (DMAC Offset: 0x4F) (R/ 8) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PEND:1; /*!< bit: 0 Channel Pending */
uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PEND:1; /*!< bit: 0 Channel Pending */
uint8_t BUSY:1; /*!< bit: 1 Channel Busy */
uint8_t FERR:1; /*!< bit: 2 Channel Fetch Error */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DMAC_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -882,18 +882,18 @@ typedef union {
/* -------- DMAC_BTCTRL : (DMAC Offset: 0x00) (R/W 16) Block Transfer Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t VALID:1; /*!< bit: 0 Descriptor Valid */
uint16_t EVOSEL:2; /*!< bit: 1.. 2 Event Output Selection */
uint16_t BLOCKACT:2; /*!< bit: 3.. 4 Block Action */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t BEATSIZE:2; /*!< bit: 8.. 9 Beat Size */
uint16_t SRCINC:1; /*!< bit: 10 Source Address Increment Enable */
uint16_t DSTINC:1; /*!< bit: 11 Destination Address Increment Enable */
uint16_t STEPSEL:1; /*!< bit: 12 Step Selection */
uint16_t STEPSIZE:3; /*!< bit: 13..15 Address Increment Step Size */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_BTCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -965,10 +965,10 @@ typedef union {
/* -------- DMAC_BTCNT : (DMAC Offset: 0x02) (R/W 16) Block Transfer Count -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t BTCNT:16; /*!< bit: 0..15 Block Transfer Count */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} DMAC_BTCNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -982,10 +982,10 @@ typedef union {
/* -------- DMAC_SRCADDR : (DMAC Offset: 0x04) (R/W 32) Block Transfer Source Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SRCADDR:32; /*!< bit: 0..31 Transfer Source Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_SRCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -999,10 +999,10 @@ typedef union {
/* -------- DMAC_DSTADDR : (DMAC Offset: 0x08) (R/W 32) Block Transfer Destination Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DSTADDR:32; /*!< bit: 0..31 Transfer Destination Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_DSTADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1016,10 +1016,10 @@ typedef union {
/* -------- DMAC_DESCADDR : (DMAC Offset: 0x0C) (R/W 32) Next Descriptor Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DESCADDR:32; /*!< bit: 0..31 Next Descriptor Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DMAC_DESCADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -1033,49 +1033,49 @@ typedef union {
/** \brief DMAC APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
__IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
__IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
__IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
__IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
__IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
RoReg8 Reserved1[0x1];
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
__IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
RoReg8 Reserved2[0x8];
__IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
RoReg8 Reserved3[0x2];
__I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
__I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
__I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
__IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
__IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
RoReg8 Reserved4[0x3];
__IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
RoReg8 Reserved5[0x3];
__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
RoReg8 Reserved6[0x4];
__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
__IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
__I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
__IO DMAC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) Control */
__IO DMAC_CRCCTRL_Type CRCCTRL; /**< \brief Offset: 0x02 (R/W 16) CRC Control */
__IO DMAC_CRCDATAIN_Type CRCDATAIN; /**< \brief Offset: 0x04 (R/W 32) CRC Data Input */
__IO DMAC_CRCCHKSUM_Type CRCCHKSUM; /**< \brief Offset: 0x08 (R/W 32) CRC Checksum */
__IO DMAC_CRCSTATUS_Type CRCSTATUS; /**< \brief Offset: 0x0C (R/W 8) CRC Status */
__IO DMAC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0D (R/W 8) Debug Control */
__IO DMAC_QOSCTRL_Type QOSCTRL; /**< \brief Offset: 0x0E (R/W 8) QOS Control */
RoReg8 Reserved1[0x1];
__IO DMAC_SWTRIGCTRL_Type SWTRIGCTRL; /**< \brief Offset: 0x10 (R/W 32) Software Trigger Control */
__IO DMAC_PRICTRL0_Type PRICTRL0; /**< \brief Offset: 0x14 (R/W 32) Priority Control 0 */
RoReg8 Reserved2[0x8];
__IO DMAC_INTPEND_Type INTPEND; /**< \brief Offset: 0x20 (R/W 16) Interrupt Pending */
RoReg8 Reserved3[0x2];
__I DMAC_INTSTATUS_Type INTSTATUS; /**< \brief Offset: 0x24 (R/ 32) Interrupt Status */
__I DMAC_BUSYCH_Type BUSYCH; /**< \brief Offset: 0x28 (R/ 32) Busy Channels */
__I DMAC_PENDCH_Type PENDCH; /**< \brief Offset: 0x2C (R/ 32) Pending Channels */
__I DMAC_ACTIVE_Type ACTIVE; /**< \brief Offset: 0x30 (R/ 32) Active Channel and Levels */
__IO DMAC_BASEADDR_Type BASEADDR; /**< \brief Offset: 0x34 (R/W 32) Descriptor Memory Section Base Address */
__IO DMAC_WRBADDR_Type WRBADDR; /**< \brief Offset: 0x38 (R/W 32) Write-Back Memory Section Base Address */
RoReg8 Reserved4[0x3];
__IO DMAC_CHID_Type CHID; /**< \brief Offset: 0x3F (R/W 8) Channel ID */
__IO DMAC_CHCTRLA_Type CHCTRLA; /**< \brief Offset: 0x40 (R/W 8) Channel Control A */
RoReg8 Reserved5[0x3];
__IO DMAC_CHCTRLB_Type CHCTRLB; /**< \brief Offset: 0x44 (R/W 32) Channel Control B */
RoReg8 Reserved6[0x4];
__IO DMAC_CHINTENCLR_Type CHINTENCLR; /**< \brief Offset: 0x4C (R/W 8) Channel Interrupt Enable Clear */
__IO DMAC_CHINTENSET_Type CHINTENSET; /**< \brief Offset: 0x4D (R/W 8) Channel Interrupt Enable Set */
__IO DMAC_CHINTFLAG_Type CHINTFLAG; /**< \brief Offset: 0x4E (R/W 8) Channel Interrupt Flag Status and Clear */
__I DMAC_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x4F (R/ 8) Channel Status */
} Dmac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief DMAC Descriptor SRAM registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
__IO DMAC_BTCTRL_Type BTCTRL; /**< \brief Offset: 0x00 (R/W 16) Block Transfer Control */
__IO DMAC_BTCNT_Type BTCNT; /**< \brief Offset: 0x02 (R/W 16) Block Transfer Count */
__IO DMAC_SRCADDR_Type SRCADDR; /**< \brief Offset: 0x04 (R/W 32) Block Transfer Source Address */
__IO DMAC_DSTADDR_Type DSTADDR; /**< \brief Offset: 0x08 (R/W 32) Block Transfer Destination Address */
__IO DMAC_DESCADDR_Type DESCADDR; /**< \brief Offset: 0x0C (R/W 32) Next Descriptor Address */
} DmacDescriptor
#ifdef __GNUC__
__attribute__ ((aligned (8)))
__attribute__ ((aligned (8)))
#endif
;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

302
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_dsu.h
View File

@ -56,15 +56,15 @@
/* -------- DSU_CTRL : (DSU Offset: 0x0000) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :1; /*!< bit: 1 Reserved */
uint8_t CRC:1; /*!< bit: 2 32-bit Cyclic Redundancy Check */
uint8_t MBIST:1; /*!< bit: 3 Memory Built-In Self-Test */
uint8_t CE:1; /*!< bit: 4 Chip Erase */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -84,15 +84,15 @@ typedef union {
/* -------- DSU_STATUSA : (DSU Offset: 0x0001) (R/W 8) Status A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAIL:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DONE:1; /*!< bit: 0 Done */
uint8_t CRSTEXT:1; /*!< bit: 1 CPU Reset Phase Extension */
uint8_t BERR:1; /*!< bit: 2 Bus Error */
uint8_t FAIL:1; /*!< bit: 3 Failure */
uint8_t PERR:1; /*!< bit: 4 Protection Error */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -114,20 +114,20 @@ typedef union {
/* -------- DSU_STATUSB : (DSU Offset: 0x0002) (R/ 8) Status B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PROT:1; /*!< bit: 0 Protected */
uint8_t DBGPRES:1; /*!< bit: 1 Debugger Present */
uint8_t DCCD0:1; /*!< bit: 2 Debug Communication Channel 0 Dirty */
uint8_t DCCD1:1; /*!< bit: 3 Debug Communication Channel 1 Dirty */
uint8_t HPE:1; /*!< bit: 4 Hot-Plugging Enable */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint8_t :2; /*!< bit: 0.. 1 Reserved */
uint8_t DCCD:2; /*!< bit: 2.. 3 Debug Communication Channel x Dirty */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} DSU_STATUSB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -152,11 +152,11 @@ typedef union {
/* -------- DSU_ADDR : (DSU Offset: 0x0004) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t ADDR:30; /*!< bit: 2..31 Address */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -171,11 +171,11 @@ typedef union {
/* -------- DSU_LENGTH : (DSU Offset: 0x0008) (R/W 32) Length -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t LENGTH:30; /*!< bit: 2..31 Length */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_LENGTH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -190,10 +190,10 @@ typedef union {
/* -------- DSU_DATA : (DSU Offset: 0x000C) (R/W 32) Data -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DATA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -208,10 +208,10 @@ typedef union {
/* -------- DSU_DCC : (DSU Offset: 0x0010) (R/W 32) Debug Communication Channel n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DATA:32; /*!< bit: 0..31 Data */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DCC_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -226,16 +226,16 @@ typedef union {
/* -------- DSU_DID : (DSU Offset: 0x0018) (R/ 32) Device Identification -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DEVSEL:8; /*!< bit: 0.. 7 Device Select */
uint32_t REVISION:4; /*!< bit: 8..11 Revision */
uint32_t DIE:4; /*!< bit: 12..15 Die Identification */
uint32_t SERIES:6; /*!< bit: 16..21 Product Series */
uint32_t :1; /*!< bit: 22 Reserved */
uint32_t FAMILY:5; /*!< bit: 23..27 Product Family */
uint32_t PROCESSOR:4; /*!< bit: 28..31 Processor */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_DID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -264,13 +264,13 @@ typedef union {
/* -------- DSU_ENTRY : (DSU Offset: 0x1000) (R/ 32) Coresight ROM Table Entry n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EPRES:1; /*!< bit: 0 Entry Present */
uint32_t FMT:1; /*!< bit: 1 Format */
uint32_t :10; /*!< bit: 2..11 Reserved */
uint32_t ADDOFF:20; /*!< bit: 12..31 Address Offset */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_ENTRY_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -289,10 +289,10 @@ typedef union {
/* -------- DSU_END : (DSU Offset: 0x1008) (R/ 32) Coresight ROM Table End -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t END:32; /*!< bit: 0..31 End Marker */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_END_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -307,11 +307,11 @@ typedef union {
/* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) (R/ 32) Coresight ROM Table Memory Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SMEMP:1; /*!< bit: 0 System Memory Present */
uint32_t :31; /*!< bit: 1..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_MEMTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -325,12 +325,12 @@ typedef union {
/* -------- DSU_PID4 : (DSU Offset: 0x1FD0) (R/ 32) Peripheral Identification 4 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t JEPCC:4; /*!< bit: 0.. 3 JEP-106 Continuation Code */
uint32_t FKBC:4; /*!< bit: 4.. 7 4KB Count */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -348,11 +348,11 @@ typedef union {
/* -------- DSU_PID0 : (DSU Offset: 0x1FE0) (R/ 32) Peripheral Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PARTNBL:8; /*!< bit: 0.. 7 Part Number Low */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -367,12 +367,12 @@ typedef union {
/* -------- DSU_PID1 : (DSU Offset: 0x1FE4) (R/ 32) Peripheral Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PARTNBH:4; /*!< bit: 0.. 3 Part Number High */
uint32_t JEPIDCL:4; /*!< bit: 4.. 7 Low part of the JEP-106 Identity Code */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -390,13 +390,13 @@ typedef union {
/* -------- DSU_PID2 : (DSU Offset: 0x1FE8) (R/ 32) Peripheral Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t JEPIDCH:3; /*!< bit: 0.. 2 JEP-106 Identity Code High */
uint32_t JEPU:1; /*!< bit: 3 JEP-106 Identity Code is used */
uint32_t REVISION:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -416,12 +416,12 @@ typedef union {
/* -------- DSU_PID3 : (DSU Offset: 0x1FEC) (R/ 32) Peripheral Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CUSMOD:4; /*!< bit: 0.. 3 ARM CUSMOD */
uint32_t REVAND:4; /*!< bit: 4.. 7 Revision Number */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -439,11 +439,11 @@ typedef union {
/* -------- DSU_CID0 : (DSU Offset: 0x1FF0) (R/ 32) Component Identification 0 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB0:8; /*!< bit: 0.. 7 Preamble Byte 0 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -458,12 +458,12 @@ typedef union {
/* -------- DSU_CID1 : (DSU Offset: 0x1FF4) (R/ 32) Component Identification 1 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLE:4; /*!< bit: 0.. 3 Preamble */
uint32_t CCLASS:4; /*!< bit: 4.. 7 Component Class */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -481,11 +481,11 @@ typedef union {
/* -------- DSU_CID2 : (DSU Offset: 0x1FF8) (R/ 32) Component Identification 2 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB2:8; /*!< bit: 0.. 7 Preamble Byte 2 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -500,11 +500,11 @@ typedef union {
/* -------- DSU_CID3 : (DSU Offset: 0x1FFC) (R/ 32) Component Identification 3 -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PREAMBLEB3:8; /*!< bit: 0.. 7 Preamble Byte 3 */
uint32_t :24; /*!< bit: 8..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} DSU_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -519,30 +519,30 @@ typedef union {
/** \brief DSU hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
__O DSU_CTRL_Type CTRL; /**< \brief Offset: 0x0000 ( /W 8) Control */
__IO DSU_STATUSA_Type STATUSA; /**< \brief Offset: 0x0001 (R/W 8) Status A */
__I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
RoReg8 Reserved1[0x1];
__IO DSU_ADDR_Type ADDR; /**< \brief Offset: 0x0004 (R/W 32) Address */
__IO DSU_LENGTH_Type LENGTH; /**< \brief Offset: 0x0008 (R/W 32) Length */
__IO DSU_DATA_Type DATA; /**< \brief Offset: 0x000C (R/W 32) Data */
__IO DSU_DCC_Type DCC[2]; /**< \brief Offset: 0x0010 (R/W 32) Debug Communication Channel n */
__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identification */
RoReg8 Reserved2[0xFE4];
__I DSU_ENTRY_Type ENTRY[2]; /**< \brief Offset: 0x1000 (R/ 32) Coresight ROM Table Entry n */
__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) Coresight ROM Table End */
RoReg8 Reserved3[0xFC0];
__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) Coresight ROM Table Memory Type */
__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */
RoReg8 Reserved4[0xC];
__I DSU_PID0_Type PID0; /**< \brief Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */
__I DSU_PID1_Type PID1; /**< \brief Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */
__I DSU_PID2_Type PID2; /**< \brief Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */
__I DSU_PID3_Type PID3; /**< \brief Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */
__I DSU_CID0_Type CID0; /**< \brief Offset: 0x1FF0 (R/ 32) Component Identification 0 */
__I DSU_CID1_Type CID1; /**< \brief Offset: 0x1FF4 (R/ 32) Component Identification 1 */
__I DSU_CID2_Type CID2; /**< \brief Offset: 0x1FF8 (R/ 32) Component Identification 2 */
__I DSU_CID3_Type CID3; /**< \brief Offset: 0x1FFC (R/ 32) Component Identification 3 */
} Dsu;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

342
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_eic.h
View File

@ -56,12 +56,12 @@
/* -------- EIC_CTRL : (EIC Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t ENABLE:1; /*!< bit: 1 Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -77,11 +77,11 @@ typedef union {
/* -------- EIC_STATUS : (EIC Offset: 0x01) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -95,12 +95,12 @@ typedef union {
/* -------- EIC_NMICTRL : (EIC Offset: 0x02) (R/W 8) Non-Maskable Interrupt Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t NMISENSE:3; /*!< bit: 0.. 2 Non-Maskable Interrupt Sense */
uint8_t NMIFILTEN:1; /*!< bit: 3 Non-Maskable Interrupt Filter Enable */
uint8_t :4; /*!< bit: 4.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMICTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -129,11 +129,11 @@ typedef union {
/* -------- EIC_NMIFLAG : (EIC Offset: 0x03) (R/W 8) Non-Maskable Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t NMI:1; /*!< bit: 0 Non-Maskable Interrupt */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EIC_NMIFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -147,30 +147,30 @@ typedef union {
/* -------- EIC_EVCTRL : (EIC Offset: 0x04) (R/W 32) Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINTEO0:1; /*!< bit: 0 External Interrupt 0 Event Output Enable */
uint32_t EXTINTEO1:1; /*!< bit: 1 External Interrupt 1 Event Output Enable */
uint32_t EXTINTEO2:1; /*!< bit: 2 External Interrupt 2 Event Output Enable */
uint32_t EXTINTEO3:1; /*!< bit: 3 External Interrupt 3 Event Output Enable */
uint32_t EXTINTEO4:1; /*!< bit: 4 External Interrupt 4 Event Output Enable */
uint32_t EXTINTEO5:1; /*!< bit: 5 External Interrupt 5 Event Output Enable */
uint32_t EXTINTEO6:1; /*!< bit: 6 External Interrupt 6 Event Output Enable */
uint32_t EXTINTEO7:1; /*!< bit: 7 External Interrupt 7 Event Output Enable */
uint32_t EXTINTEO8:1; /*!< bit: 8 External Interrupt 8 Event Output Enable */
uint32_t EXTINTEO9:1; /*!< bit: 9 External Interrupt 9 Event Output Enable */
uint32_t EXTINTEO10:1; /*!< bit: 10 External Interrupt 10 Event Output Enable */
uint32_t EXTINTEO11:1; /*!< bit: 11 External Interrupt 11 Event Output Enable */
uint32_t EXTINTEO12:1; /*!< bit: 12 External Interrupt 12 Event Output Enable */
uint32_t EXTINTEO13:1; /*!< bit: 13 External Interrupt 13 Event Output Enable */
uint32_t EXTINTEO14:1; /*!< bit: 14 External Interrupt 14 Event Output Enable */
uint32_t EXTINTEO15:1; /*!< bit: 15 External Interrupt 15 Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINTEO:16; /*!< bit: 0..15 External Interrupt x Event Output Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -217,30 +217,30 @@ typedef union {
/* -------- EIC_INTENCLR : (EIC Offset: 0x08) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -287,30 +287,30 @@ typedef union {
/* -------- EIC_INTENSET : (EIC Offset: 0x0C) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 Enable */
uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 Enable */
uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 Enable */
uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 Enable */
uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 Enable */
uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 Enable */
uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 Enable */
uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 Enable */
uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 Enable */
uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 Enable */
uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 Enable */
uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 Enable */
uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 Enable */
uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 Enable */
uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 Enable */
uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -357,30 +357,30 @@ typedef union {
/* -------- EIC_INTFLAG : (EIC Offset: 0x10) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
__I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
__I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
__I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
__I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
__I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
__I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
__I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
__I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
__I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
__I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
__I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
__I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
__I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
__I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
__I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
__I uint32_t EXTINT0:1; /*!< bit: 0 External Interrupt 0 */
__I uint32_t EXTINT1:1; /*!< bit: 1 External Interrupt 1 */
__I uint32_t EXTINT2:1; /*!< bit: 2 External Interrupt 2 */
__I uint32_t EXTINT3:1; /*!< bit: 3 External Interrupt 3 */
__I uint32_t EXTINT4:1; /*!< bit: 4 External Interrupt 4 */
__I uint32_t EXTINT5:1; /*!< bit: 5 External Interrupt 5 */
__I uint32_t EXTINT6:1; /*!< bit: 6 External Interrupt 6 */
__I uint32_t EXTINT7:1; /*!< bit: 7 External Interrupt 7 */
__I uint32_t EXTINT8:1; /*!< bit: 8 External Interrupt 8 */
__I uint32_t EXTINT9:1; /*!< bit: 9 External Interrupt 9 */
__I uint32_t EXTINT10:1; /*!< bit: 10 External Interrupt 10 */
__I uint32_t EXTINT11:1; /*!< bit: 11 External Interrupt 11 */
__I uint32_t EXTINT12:1; /*!< bit: 12 External Interrupt 12 */
__I uint32_t EXTINT13:1; /*!< bit: 13 External Interrupt 13 */
__I uint32_t EXTINT14:1; /*!< bit: 14 External Interrupt 14 */
__I uint32_t EXTINT15:1; /*!< bit: 15 External Interrupt 15 */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint32_t EXTINT:16; /*!< bit: 0..15 External Interrupt x */
__I uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -427,30 +427,30 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- EIC_WAKEUP : (EIC Offset: 0x14) (R/W 32) Wake-Up Enable -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t WAKEUPEN0:1; /*!< bit: 0 External Interrupt 0 Wake-up Enable */
uint32_t WAKEUPEN1:1; /*!< bit: 1 External Interrupt 1 Wake-up Enable */
uint32_t WAKEUPEN2:1; /*!< bit: 2 External Interrupt 2 Wake-up Enable */
uint32_t WAKEUPEN3:1; /*!< bit: 3 External Interrupt 3 Wake-up Enable */
uint32_t WAKEUPEN4:1; /*!< bit: 4 External Interrupt 4 Wake-up Enable */
uint32_t WAKEUPEN5:1; /*!< bit: 5 External Interrupt 5 Wake-up Enable */
uint32_t WAKEUPEN6:1; /*!< bit: 6 External Interrupt 6 Wake-up Enable */
uint32_t WAKEUPEN7:1; /*!< bit: 7 External Interrupt 7 Wake-up Enable */
uint32_t WAKEUPEN8:1; /*!< bit: 8 External Interrupt 8 Wake-up Enable */
uint32_t WAKEUPEN9:1; /*!< bit: 9 External Interrupt 9 Wake-up Enable */
uint32_t WAKEUPEN10:1; /*!< bit: 10 External Interrupt 10 Wake-up Enable */
uint32_t WAKEUPEN11:1; /*!< bit: 11 External Interrupt 11 Wake-up Enable */
uint32_t WAKEUPEN12:1; /*!< bit: 12 External Interrupt 12 Wake-up Enable */
uint32_t WAKEUPEN13:1; /*!< bit: 13 External Interrupt 13 Wake-up Enable */
uint32_t WAKEUPEN14:1; /*!< bit: 14 External Interrupt 14 Wake-up Enable */
uint32_t WAKEUPEN15:1; /*!< bit: 15 External Interrupt 15 Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t WAKEUPEN:16; /*!< bit: 0..15 External Interrupt x Wake-up Enable */
uint32_t :16; /*!< bit: 16..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EIC_WAKEUP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -497,25 +497,25 @@ typedef union {
/* -------- EIC_CONFIG : (EIC Offset: 0x18) (R/W 32) Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SENSE0:3; /*!< bit: 0.. 2 Input Sense 0 Configuration */
uint32_t FILTEN0:1; /*!< bit: 3 Filter 0 Enable */
uint32_t SENSE1:3; /*!< bit: 4.. 6 Input Sense 1 Configuration */
uint32_t FILTEN1:1; /*!< bit: 7 Filter 1 Enable */
uint32_t SENSE2:3; /*!< bit: 8..10 Input Sense 2 Configuration */
uint32_t FILTEN2:1; /*!< bit: 11 Filter 2 Enable */
uint32_t SENSE3:3; /*!< bit: 12..14 Input Sense 3 Configuration */
uint32_t FILTEN3:1; /*!< bit: 15 Filter 3 Enable */
uint32_t SENSE4:3; /*!< bit: 16..18 Input Sense 4 Configuration */
uint32_t FILTEN4:1; /*!< bit: 19 Filter 4 Enable */
uint32_t SENSE5:3; /*!< bit: 20..22 Input Sense 5 Configuration */
uint32_t FILTEN5:1; /*!< bit: 23 Filter 5 Enable */
uint32_t SENSE6:3; /*!< bit: 24..26 Input Sense 6 Configuration */
uint32_t FILTEN6:1; /*!< bit: 27 Filter 6 Enable */
uint32_t SENSE7:3; /*!< bit: 28..30 Input Sense 7 Configuration */
uint32_t FILTEN7:1; /*!< bit: 31 Filter 7 Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EIC_CONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -663,16 +663,16 @@ typedef union {
/** \brief EIC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
__IO EIC_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__I EIC_STATUS_Type STATUS; /**< \brief Offset: 0x01 (R/ 8) Status */
__IO EIC_NMICTRL_Type NMICTRL; /**< \brief Offset: 0x02 (R/W 8) Non-Maskable Interrupt Control */
__IO EIC_NMIFLAG_Type NMIFLAG; /**< \brief Offset: 0x03 (R/W 8) Non-Maskable Interrupt Flag Status and Clear */
__IO EIC_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 32) Event Control */
__IO EIC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x08 (R/W 32) Interrupt Enable Clear */
__IO EIC_INTENSET_Type INTENSET; /**< \brief Offset: 0x0C (R/W 32) Interrupt Enable Set */
__IO EIC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x10 (R/W 32) Interrupt Flag Status and Clear */
__IO EIC_WAKEUP_Type WAKEUP; /**< \brief Offset: 0x14 (R/W 32) Wake-Up Enable */
__IO EIC_CONFIG_Type CONFIG[2]; /**< \brief Offset: 0x18 (R/W 32) Configuration n */
} Eic;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

366
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_evsys.h
View File

@ -56,13 +56,13 @@
/* -------- EVSYS_CTRL : (EVSYS Offset: 0x00) ( /W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :3; /*!< bit: 1.. 3 Reserved */
uint8_t GCLKREQ:1; /*!< bit: 4 Generic Clock Requests */
uint8_t :3; /*!< bit: 5.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} EVSYS_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -78,18 +78,18 @@ typedef union {
/* -------- EVSYS_CHANNEL : (EVSYS Offset: 0x04) (R/W 32) Channel -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t CHANNEL:4; /*!< bit: 0.. 3 Channel Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SWEVT:1; /*!< bit: 8 Software Event */
uint32_t :7; /*!< bit: 9..15 Reserved */
uint32_t EVGEN:7; /*!< bit: 16..22 Event Generator Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PATH:2; /*!< bit: 24..25 Path Selection */
uint32_t EDGSEL:2; /*!< bit: 26..27 Edge Detection Selection */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHANNEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -129,13 +129,13 @@ typedef union {
/* -------- EVSYS_USER : (EVSYS Offset: 0x08) (R/W 16) User Multiplexer -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t USER:5; /*!< bit: 0.. 4 User Multiplexer Selection */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t CHANNEL:5; /*!< bit: 8..12 Channel Event Selection */
uint16_t :3; /*!< bit: 13..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} EVSYS_USER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -155,43 +155,43 @@ typedef union {
/* -------- EVSYS_CHSTATUS : (EVSYS Offset: 0x0C) (R/ 32) Channel Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t USRRDY0:1; /*!< bit: 0 Channel 0 User Ready */
uint32_t USRRDY1:1; /*!< bit: 1 Channel 1 User Ready */
uint32_t USRRDY2:1; /*!< bit: 2 Channel 2 User Ready */
uint32_t USRRDY3:1; /*!< bit: 3 Channel 3 User Ready */
uint32_t USRRDY4:1; /*!< bit: 4 Channel 4 User Ready */
uint32_t USRRDY5:1; /*!< bit: 5 Channel 5 User Ready */
uint32_t USRRDY6:1; /*!< bit: 6 Channel 6 User Ready */
uint32_t USRRDY7:1; /*!< bit: 7 Channel 7 User Ready */
uint32_t CHBUSY0:1; /*!< bit: 8 Channel 0 Busy */
uint32_t CHBUSY1:1; /*!< bit: 9 Channel 1 Busy */
uint32_t CHBUSY2:1; /*!< bit: 10 Channel 2 Busy */
uint32_t CHBUSY3:1; /*!< bit: 11 Channel 3 Busy */
uint32_t CHBUSY4:1; /*!< bit: 12 Channel 4 Busy */
uint32_t CHBUSY5:1; /*!< bit: 13 Channel 5 Busy */
uint32_t CHBUSY6:1; /*!< bit: 14 Channel 6 Busy */
uint32_t CHBUSY7:1; /*!< bit: 15 Channel 7 Busy */
uint32_t USRRDY8:1; /*!< bit: 16 Channel 8 User Ready */
uint32_t USRRDY9:1; /*!< bit: 17 Channel 9 User Ready */
uint32_t USRRDY10:1; /*!< bit: 18 Channel 10 User Ready */
uint32_t USRRDY11:1; /*!< bit: 19 Channel 11 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSY8:1; /*!< bit: 24 Channel 8 Busy */
uint32_t CHBUSY9:1; /*!< bit: 25 Channel 9 Busy */
uint32_t CHBUSY10:1; /*!< bit: 26 Channel 10 Busy */
uint32_t CHBUSY11:1; /*!< bit: 27 Channel 11 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t USRRDY:8; /*!< bit: 0.. 7 Channel x User Ready */
uint32_t CHBUSY:8; /*!< bit: 8..15 Channel x Busy */
uint32_t USRRDYp8:4; /*!< bit: 16..19 Channel x+8 User Ready */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t CHBUSYp8:4; /*!< bit: 24..27 Channel x+8 Busy */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_CHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -263,43 +263,43 @@ typedef union {
/* -------- EVSYS_INTENCLR : (EVSYS Offset: 0x10) (R/W 32) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -371,43 +371,43 @@ typedef union {
/* -------- EVSYS_INTENSET : (EVSYS Offset: 0x14) (R/W 32) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun Interrupt Enable */
uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun Interrupt Enable */
uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun Interrupt Enable */
uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun Interrupt Enable */
uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun Interrupt Enable */
uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun Interrupt Enable */
uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun Interrupt Enable */
uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun Interrupt Enable */
uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection Interrupt Enable */
uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection Interrupt Enable */
uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection Interrupt Enable */
uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection Interrupt Enable */
uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection Interrupt Enable */
uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection Interrupt Enable */
uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection Interrupt Enable */
uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection Interrupt Enable */
uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun Interrupt Enable */
uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun Interrupt Enable */
uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun Interrupt Enable */
uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection Interrupt Enable */
uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection Interrupt Enable */
uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection Interrupt Enable */
uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun Interrupt Enable */
uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection Interrupt Enable */
uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun Interrupt Enable */
uint32_t :4; /*!< bit: 20..23 Reserved */
uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection Interrupt Enable */
uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -479,43 +479,43 @@ typedef union {
/* -------- EVSYS_INTFLAG : (EVSYS Offset: 0x18) (R/W 32) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
__I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
__I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
__I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
__I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
__I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
__I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
__I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
__I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
__I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
__I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
__I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
__I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
__I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
__I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
__I uint32_t :4; /*!< bit: 20..23 Reserved */
__I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
__I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
__I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
__I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
__I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
__I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
__I uint32_t :4; /*!< bit: 20..23 Reserved */
__I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
struct {
__I uint32_t OVR0:1; /*!< bit: 0 Channel 0 Overrun */
__I uint32_t OVR1:1; /*!< bit: 1 Channel 1 Overrun */
__I uint32_t OVR2:1; /*!< bit: 2 Channel 2 Overrun */
__I uint32_t OVR3:1; /*!< bit: 3 Channel 3 Overrun */
__I uint32_t OVR4:1; /*!< bit: 4 Channel 4 Overrun */
__I uint32_t OVR5:1; /*!< bit: 5 Channel 5 Overrun */
__I uint32_t OVR6:1; /*!< bit: 6 Channel 6 Overrun */
__I uint32_t OVR7:1; /*!< bit: 7 Channel 7 Overrun */
__I uint32_t EVD0:1; /*!< bit: 8 Channel 0 Event Detection */
__I uint32_t EVD1:1; /*!< bit: 9 Channel 1 Event Detection */
__I uint32_t EVD2:1; /*!< bit: 10 Channel 2 Event Detection */
__I uint32_t EVD3:1; /*!< bit: 11 Channel 3 Event Detection */
__I uint32_t EVD4:1; /*!< bit: 12 Channel 4 Event Detection */
__I uint32_t EVD5:1; /*!< bit: 13 Channel 5 Event Detection */
__I uint32_t EVD6:1; /*!< bit: 14 Channel 6 Event Detection */
__I uint32_t EVD7:1; /*!< bit: 15 Channel 7 Event Detection */
__I uint32_t OVR8:1; /*!< bit: 16 Channel 8 Overrun */
__I uint32_t OVR9:1; /*!< bit: 17 Channel 9 Overrun */
__I uint32_t OVR10:1; /*!< bit: 18 Channel 10 Overrun */
__I uint32_t OVR11:1; /*!< bit: 19 Channel 11 Overrun */
__I uint32_t :4; /*!< bit: 20..23 Reserved */
__I uint32_t EVD8:1; /*!< bit: 24 Channel 8 Event Detection */
__I uint32_t EVD9:1; /*!< bit: 25 Channel 9 Event Detection */
__I uint32_t EVD10:1; /*!< bit: 26 Channel 10 Event Detection */
__I uint32_t EVD11:1; /*!< bit: 27 Channel 11 Event Detection */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} bit; /*!< Structure used for bit access */
struct {
__I uint32_t OVR:8; /*!< bit: 0.. 7 Channel x Overrun */
__I uint32_t EVD:8; /*!< bit: 8..15 Channel x Event Detection */
__I uint32_t OVRp8:4; /*!< bit: 16..19 Channel x+8 Overrun */
__I uint32_t :4; /*!< bit: 20..23 Reserved */
__I uint32_t EVDp8:4; /*!< bit: 24..27 Channel x+8 Event Detection */
__I uint32_t :4; /*!< bit: 28..31 Reserved */
} vec; /*!< Structure used for vec access */
uint32_t reg; /*!< Type used for register access */
} EVSYS_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -587,15 +587,15 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/** \brief EVSYS hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
__O EVSYS_CTRL_Type CTRL; /**< \brief Offset: 0x00 ( /W 8) Control */
RoReg8 Reserved1[0x3];
__IO EVSYS_CHANNEL_Type CHANNEL; /**< \brief Offset: 0x04 (R/W 32) Channel */
__IO EVSYS_USER_Type USER; /**< \brief Offset: 0x08 (R/W 16) User Multiplexer */
RoReg8 Reserved2[0x2];
__I EVSYS_CHSTATUS_Type CHSTATUS; /**< \brief Offset: 0x0C (R/ 32) Channel Status */
__IO EVSYS_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x10 (R/W 32) Interrupt Enable Clear */
__IO EVSYS_INTENSET_Type INTENSET; /**< \brief Offset: 0x14 (R/W 32) Interrupt Enable Set */
__IO EVSYS_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x18 (R/W 32) Interrupt Flag Status and Clear */
} Evsys;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

90
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_gclk.h
View File

@ -56,11 +56,11 @@
/* -------- GCLK_CTRL : (GCLK Offset: 0x0) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SWRST:1; /*!< bit: 0 Software Reset */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -74,11 +74,11 @@ typedef union {
/* -------- GCLK_STATUS : (GCLK Offset: 0x1) (R/ 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy Status */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} GCLK_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -92,15 +92,15 @@ typedef union {
/* -------- GCLK_CLKCTRL : (GCLK Offset: 0x2) (R/W 16) Generic Clock Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ID:6; /*!< bit: 0.. 5 Generic Clock Selection ID */
uint16_t :2; /*!< bit: 6.. 7 Reserved */
uint16_t GEN:4; /*!< bit: 8..11 Generic Clock Generator */
uint16_t :2; /*!< bit: 12..13 Reserved */
uint16_t CLKEN:1; /*!< bit: 14 Clock Enable */
uint16_t WRTLOCK:1; /*!< bit: 15 Write Lock */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} GCLK_CLKCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -212,20 +212,20 @@ typedef union {
/* -------- GCLK_GENCTRL : (GCLK Offset: 0x4) (R/W 32) Generic Clock Generator Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t SRC:5; /*!< bit: 8..12 Source Select */
uint32_t :3; /*!< bit: 13..15 Reserved */
uint32_t GENEN:1; /*!< bit: 16 Generic Clock Generator Enable */
uint32_t IDC:1; /*!< bit: 17 Improve Duty Cycle */
uint32_t OOV:1; /*!< bit: 18 Output Off Value */
uint32_t OE:1; /*!< bit: 19 Output Enable */
uint32_t DIVSEL:1; /*!< bit: 20 Divide Selection */
uint32_t RUNSTDBY:1; /*!< bit: 21 Run in Standby */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -273,13 +273,13 @@ typedef union {
/* -------- GCLK_GENDIV : (GCLK Offset: 0x8) (R/W 32) Generic Clock Generator Division -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ID:4; /*!< bit: 0.. 3 Generic Clock Generator Selection */
uint32_t :4; /*!< bit: 4.. 7 Reserved */
uint32_t DIV:16; /*!< bit: 8..23 Division Factor */
uint32_t :8; /*!< bit: 24..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} GCLK_GENDIV_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -297,11 +297,11 @@ typedef union {
/** \brief GCLK hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
__IO GCLK_CTRL_Type CTRL; /**< \brief Offset: 0x0 (R/W 8) Control */
__I GCLK_STATUS_Type STATUS; /**< \brief Offset: 0x1 (R/ 8) Status */
__IO GCLK_CLKCTRL_Type CLKCTRL; /**< \brief Offset: 0x2 (R/W 16) Generic Clock Control */
__IO GCLK_GENCTRL_Type GENCTRL; /**< \brief Offset: 0x4 (R/W 32) Generic Clock Generator Control */
__IO GCLK_GENDIV_Type GENDIV; /**< \brief Offset: 0x8 (R/W 32) Generic Clock Generator Division */
} Gclk;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

24
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_hmatrixb.h
View File

@ -56,7 +56,7 @@
/* -------- HMATRIXB_PRAS : (HMATRIXB Offset: 0x080) (R/W 32) PRS Priority A for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRAS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -68,7 +68,7 @@ typedef union {
/* -------- HMATRIXB_PRBS : (HMATRIXB Offset: 0x084) (R/W 32) PRS Priority B for Slave -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_PRBS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -80,10 +80,10 @@ typedef union {
/* -------- HMATRIXB_SFR : (HMATRIXB Offset: 0x110) (R/W 32) Special Function -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SFR:32; /*!< bit: 0..31 Special Function Register */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} HMATRIXB_SFR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -98,18 +98,18 @@ typedef union {
/** \brief HmatrixbPrs hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
__IO HMATRIXB_PRAS_Type PRAS; /**< \brief Offset: 0x000 (R/W 32) Priority A for Slave */
__IO HMATRIXB_PRBS_Type PRBS; /**< \brief Offset: 0x004 (R/W 32) Priority B for Slave */
} HmatrixbPrs;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief HMATRIXB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
RoReg8 Reserved2[0x10];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
RoReg8 Reserved1[0x80];
HmatrixbPrs Prs[16]; /**< \brief Offset: 0x080 HmatrixbPrs groups */
RoReg8 Reserved2[0x10];
__IO HMATRIXB_SFR_Type SFR[16]; /**< \brief Offset: 0x110 (R/W 32) Special Function */
} Hmatrixb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

150
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_mtb.h
View File

@ -56,12 +56,12 @@
/* -------- MTB_POSITION : (MTB Offset: 0x000) (R/W 32) MTB Position -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :2; /*!< bit: 0.. 1 Reserved */
uint32_t WRAP:1; /*!< bit: 2 Pointer Value Wraps */
uint32_t POINTER:29; /*!< bit: 3..31 Trace Packet Location Pointer */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_POSITION_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -77,17 +77,17 @@ typedef union {
/* -------- MTB_MASTER : (MTB Offset: 0x004) (R/W 32) MTB Master -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t MASK:5; /*!< bit: 0.. 4 Maximum Value of the Trace Buffer in SRAM */
uint32_t TSTARTEN:1; /*!< bit: 5 Trace Start Input Enable */
uint32_t TSTOPEN:1; /*!< bit: 6 Trace Stop Input Enable */
uint32_t SFRWPRIV:1; /*!< bit: 7 Special Function Register Write Privilege */
uint32_t RAMPRIV:1; /*!< bit: 8 SRAM Privilege */
uint32_t HALTREQ:1; /*!< bit: 9 Halt Request */
uint32_t :21; /*!< bit: 10..30 Reserved */
uint32_t EN:1; /*!< bit: 31 Main Trace Enable */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_MASTER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -114,13 +114,13 @@ typedef union {
/* -------- MTB_FLOW : (MTB Offset: 0x008) (R/W 32) MTB Flow -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t AUTOSTOP:1; /*!< bit: 0 Auto Stop Tracing */
uint32_t AUTOHALT:1; /*!< bit: 1 Auto Halt Request */
uint32_t :1; /*!< bit: 2 Reserved */
uint32_t WATERMARK:29; /*!< bit: 3..31 Watermark value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} MTB_FLOW_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -139,7 +139,7 @@ typedef union {
/* -------- MTB_BASE : (MTB Offset: 0x00C) (R/ 32) MTB Base -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_BASE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -149,7 +149,7 @@ typedef union {
/* -------- MTB_ITCTRL : (MTB Offset: 0xF00) (R/W 32) MTB Integration Mode Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_ITCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -159,7 +159,7 @@ typedef union {
/* -------- MTB_CLAIMSET : (MTB Offset: 0xFA0) (R/W 32) MTB Claim Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -169,7 +169,7 @@ typedef union {
/* -------- MTB_CLAIMCLR : (MTB Offset: 0xFA4) (R/W 32) MTB Claim Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CLAIMCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -179,7 +179,7 @@ typedef union {
/* -------- MTB_LOCKACCESS : (MTB Offset: 0xFB0) (R/W 32) MTB Lock Access -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKACCESS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -189,7 +189,7 @@ typedef union {
/* -------- MTB_LOCKSTATUS : (MTB Offset: 0xFB4) (R/ 32) MTB Lock Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_LOCKSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -199,7 +199,7 @@ typedef union {
/* -------- MTB_AUTHSTATUS : (MTB Offset: 0xFB8) (R/ 32) MTB Authentication Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_AUTHSTATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -209,7 +209,7 @@ typedef union {
/* -------- MTB_DEVARCH : (MTB Offset: 0xFBC) (R/ 32) MTB Device Architecture -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVARCH_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -219,7 +219,7 @@ typedef union {
/* -------- MTB_DEVID : (MTB Offset: 0xFC8) (R/ 32) MTB Device Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVID_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -229,7 +229,7 @@ typedef union {
/* -------- MTB_DEVTYPE : (MTB Offset: 0xFCC) (R/ 32) MTB Device Type -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_DEVTYPE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -239,7 +239,7 @@ typedef union {
/* -------- MTB_PID4 : (MTB Offset: 0xFD0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID4_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -249,7 +249,7 @@ typedef union {
/* -------- MTB_PID5 : (MTB Offset: 0xFD4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID5_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -259,7 +259,7 @@ typedef union {
/* -------- MTB_PID6 : (MTB Offset: 0xFD8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID6_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -269,7 +269,7 @@ typedef union {
/* -------- MTB_PID7 : (MTB Offset: 0xFDC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID7_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -279,7 +279,7 @@ typedef union {
/* -------- MTB_PID0 : (MTB Offset: 0xFE0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -289,7 +289,7 @@ typedef union {
/* -------- MTB_PID1 : (MTB Offset: 0xFE4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -299,7 +299,7 @@ typedef union {
/* -------- MTB_PID2 : (MTB Offset: 0xFE8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -309,7 +309,7 @@ typedef union {
/* -------- MTB_PID3 : (MTB Offset: 0xFEC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_PID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -319,7 +319,7 @@ typedef union {
/* -------- MTB_CID0 : (MTB Offset: 0xFF0) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID0_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -329,7 +329,7 @@ typedef union {
/* -------- MTB_CID1 : (MTB Offset: 0xFF4) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID1_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -339,7 +339,7 @@ typedef union {
/* -------- MTB_CID2 : (MTB Offset: 0xFF8) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID2_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -349,7 +349,7 @@ typedef union {
/* -------- MTB_CID3 : (MTB Offset: 0xFFC) (R/ 32) CoreSight -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint32_t reg; /*!< Type used for register access */
uint32_t reg; /*!< Type used for register access */
} MTB_CID3_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -359,35 +359,35 @@ typedef union {
/** \brief MTB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
__IO MTB_POSITION_Type POSITION; /**< \brief Offset: 0x000 (R/W 32) MTB Position */
__IO MTB_MASTER_Type MASTER; /**< \brief Offset: 0x004 (R/W 32) MTB Master */
__IO MTB_FLOW_Type FLOW; /**< \brief Offset: 0x008 (R/W 32) MTB Flow */
__I MTB_BASE_Type BASE; /**< \brief Offset: 0x00C (R/ 32) MTB Base */
RoReg8 Reserved1[0xEF0];
__IO MTB_ITCTRL_Type ITCTRL; /**< \brief Offset: 0xF00 (R/W 32) MTB Integration Mode Control */
RoReg8 Reserved2[0x9C];
__IO MTB_CLAIMSET_Type CLAIMSET; /**< \brief Offset: 0xFA0 (R/W 32) MTB Claim Set */
__IO MTB_CLAIMCLR_Type CLAIMCLR; /**< \brief Offset: 0xFA4 (R/W 32) MTB Claim Clear */
RoReg8 Reserved3[0x8];
__IO MTB_LOCKACCESS_Type LOCKACCESS; /**< \brief Offset: 0xFB0 (R/W 32) MTB Lock Access */
__I MTB_LOCKSTATUS_Type LOCKSTATUS; /**< \brief Offset: 0xFB4 (R/ 32) MTB Lock Status */
__I MTB_AUTHSTATUS_Type AUTHSTATUS; /**< \brief Offset: 0xFB8 (R/ 32) MTB Authentication Status */
__I MTB_DEVARCH_Type DEVARCH; /**< \brief Offset: 0xFBC (R/ 32) MTB Device Architecture */
RoReg8 Reserved4[0x8];
__I MTB_DEVID_Type DEVID; /**< \brief Offset: 0xFC8 (R/ 32) MTB Device Configuration */
__I MTB_DEVTYPE_Type DEVTYPE; /**< \brief Offset: 0xFCC (R/ 32) MTB Device Type */
__I MTB_PID4_Type PID4; /**< \brief Offset: 0xFD0 (R/ 32) CoreSight */
__I MTB_PID5_Type PID5; /**< \brief Offset: 0xFD4 (R/ 32) CoreSight */
__I MTB_PID6_Type PID6; /**< \brief Offset: 0xFD8 (R/ 32) CoreSight */
__I MTB_PID7_Type PID7; /**< \brief Offset: 0xFDC (R/ 32) CoreSight */
__I MTB_PID0_Type PID0; /**< \brief Offset: 0xFE0 (R/ 32) CoreSight */
__I MTB_PID1_Type PID1; /**< \brief Offset: 0xFE4 (R/ 32) CoreSight */
__I MTB_PID2_Type PID2; /**< \brief Offset: 0xFE8 (R/ 32) CoreSight */
__I MTB_PID3_Type PID3; /**< \brief Offset: 0xFEC (R/ 32) CoreSight */
__I MTB_CID0_Type CID0; /**< \brief Offset: 0xFF0 (R/ 32) CoreSight */
__I MTB_CID1_Type CID1; /**< \brief Offset: 0xFF4 (R/ 32) CoreSight */
__I MTB_CID2_Type CID2; /**< \brief Offset: 0xFF8 (R/ 32) CoreSight */
__I MTB_CID3_Type CID3; /**< \brief Offset: 0xFFC (R/ 32) CoreSight */
} Mtb;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

152
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_nvmctrl.h
View File

@ -56,12 +56,12 @@
/* -------- NVMCTRL_CTRLA : (NVMCTRL Offset: 0x00) (R/W 16) Control A -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t CMD:7; /*!< bit: 0.. 6 Command */
uint16_t :1; /*!< bit: 7 Reserved */
uint16_t CMDEX:8; /*!< bit: 8..15 Command Execution */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLA_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -107,18 +107,18 @@ typedef union {
/* -------- NVMCTRL_CTRLB : (NVMCTRL Offset: 0x04) (R/W 32) Control B -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t RWS:4; /*!< bit: 1.. 4 NVM Read Wait States */
uint32_t :2; /*!< bit: 5.. 6 Reserved */
uint32_t MANW:1; /*!< bit: 7 Manual Write */
uint32_t SLEEPPRM:2; /*!< bit: 8.. 9 Power Reduction Mode during Sleep */
uint32_t :6; /*!< bit: 10..15 Reserved */
uint32_t READMODE:2; /*!< bit: 16..17 NVMCTRL Read Mode */
uint32_t CACHEDIS:1; /*!< bit: 18 Cache Disable */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_CTRLB_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -161,12 +161,12 @@ typedef union {
/* -------- NVMCTRL_PARAM : (NVMCTRL Offset: 0x08) (R/W 32) NVM Parameter -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t NVMP:16; /*!< bit: 0..15 NVM Pages */
uint32_t PSZ:3; /*!< bit: 16..18 Page Size */
uint32_t :13; /*!< bit: 19..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_PARAM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -200,12 +200,12 @@ typedef union {
/* -------- NVMCTRL_INTENCLR : (NVMCTRL Offset: 0x0C) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -221,12 +221,12 @@ typedef union {
/* -------- NVMCTRL_INTENSET : (NVMCTRL Offset: 0x10) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t READY:1; /*!< bit: 0 NVM Ready Interrupt Enable */
uint8_t ERROR:1; /*!< bit: 1 Error Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -242,12 +242,12 @@ typedef union {
/* -------- NVMCTRL_INTFLAG : (NVMCTRL Offset: 0x14) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t READY:1; /*!< bit: 0 NVM Ready */
__I uint8_t ERROR:1; /*!< bit: 1 Error */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t READY:1; /*!< bit: 0 NVM Ready */
__I uint8_t ERROR:1; /*!< bit: 1 Error */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} NVMCTRL_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -263,17 +263,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- NVMCTRL_STATUS : (NVMCTRL Offset: 0x18) (R/W 16) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PRM:1; /*!< bit: 0 Power Reduction Mode */
uint16_t LOAD:1; /*!< bit: 1 NVM Page Buffer Active Loading */
uint16_t PROGE:1; /*!< bit: 2 Programming Error Status */
uint16_t LOCKE:1; /*!< bit: 3 Lock Error Status */
uint16_t NVME:1; /*!< bit: 4 NVM Error */
uint16_t :3; /*!< bit: 5.. 7 Reserved */
uint16_t SB:1; /*!< bit: 8 Security Bit Status */
uint16_t :7; /*!< bit: 9..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -297,11 +297,11 @@ typedef union {
/* -------- NVMCTRL_ADDR : (NVMCTRL Offset: 0x1C) (R/W 32) Address -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t ADDR:22; /*!< bit: 0..21 NVM Address */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} NVMCTRL_ADDR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -316,10 +316,10 @@ typedef union {
/* -------- NVMCTRL_LOCK : (NVMCTRL Offset: 0x20) (R/W 16) Lock Section -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t LOCK:16; /*!< bit: 0..15 Region Lock Bits */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} NVMCTRL_LOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -333,20 +333,20 @@ typedef union {
/** \brief NVMCTRL APB hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
__IO NVMCTRL_CTRLA_Type CTRLA; /**< \brief Offset: 0x00 (R/W 16) Control A */
RoReg8 Reserved1[0x2];
__IO NVMCTRL_CTRLB_Type CTRLB; /**< \brief Offset: 0x04 (R/W 32) Control B */
__IO NVMCTRL_PARAM_Type PARAM; /**< \brief Offset: 0x08 (R/W 32) NVM Parameter */
__IO NVMCTRL_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x0C (R/W 8) Interrupt Enable Clear */
RoReg8 Reserved2[0x3];
__IO NVMCTRL_INTENSET_Type INTENSET; /**< \brief Offset: 0x10 (R/W 8) Interrupt Enable Set */
RoReg8 Reserved3[0x3];
__IO NVMCTRL_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x14 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x3];
__IO NVMCTRL_STATUS_Type STATUS; /**< \brief Offset: 0x18 (R/W 16) Status */
RoReg8 Reserved5[0x2];
__IO NVMCTRL_ADDR_Type ADDR; /**< \brief Offset: 0x1C (R/W 32) Address */
__IO NVMCTRL_LOCK_Type LOCK; /**< \brief Offset: 0x20 (R/W 16) Lock Section */
} Nvmctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_NVMCTRL_CAL

24
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pac.h
View File

@ -56,11 +56,11 @@
/* -------- PAC_WPCLR : (PAC Offset: 0x0) (R/W 32) Write Protection Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -75,11 +75,11 @@ typedef union {
/* -------- PAC_WPSET : (PAC Offset: 0x4) (R/W 32) Write Protection Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t :1; /*!< bit: 0 Reserved */
uint32_t WP:31; /*!< bit: 1..31 Write Protection Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PAC_WPSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -94,8 +94,8 @@ typedef union {
/** \brief PAC hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
__IO PAC_WPCLR_Type WPCLR; /**< \brief Offset: 0x0 (R/W 32) Write Protection Clear */
__IO PAC_WPSET_Type WPSET; /**< \brief Offset: 0x4 (R/W 32) Write Protection Set */
} Pac;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

256
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_pm.h
View File

@ -56,7 +56,7 @@
/* -------- PM_CTRL : (PM Offset: 0x00) (R/W 8) Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
uint8_t reg; /*!< Type used for register access */
uint8_t reg; /*!< Type used for register access */
} PM_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -68,11 +68,11 @@ typedef union {
/* -------- PM_SLEEP : (PM Offset: 0x01) (R/W 8) Sleep Mode -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t IDLE:2; /*!< bit: 0.. 1 Idle Mode Configuration */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_SLEEP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -93,11 +93,11 @@ typedef union {
/* -------- PM_CPUSEL : (PM Offset: 0x08) (R/W 8) CPU Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CPUDIV:3; /*!< bit: 0.. 2 CPU Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_CPUSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -128,11 +128,11 @@ typedef union {
/* -------- PM_APBASEL : (PM Offset: 0x09) (R/W 8) APBA Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBADIV:3; /*!< bit: 0.. 2 APBA Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBASEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -163,11 +163,11 @@ typedef union {
/* -------- PM_APBBSEL : (PM Offset: 0x0A) (R/W 8) APBB Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBBDIV:3; /*!< bit: 0.. 2 APBB Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBBSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -198,11 +198,11 @@ typedef union {
/* -------- PM_APBCSEL : (PM Offset: 0x0B) (R/W 8) APBC Clock Select -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t APBCDIV:3; /*!< bit: 0.. 2 APBC Prescaler Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_APBCSEL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -233,17 +233,17 @@ typedef union {
/* -------- PM_AHBMASK : (PM Offset: 0x14) (R/W 32) AHB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t HPB0_:1; /*!< bit: 0 HPB0 AHB Clock Mask */
uint32_t HPB1_:1; /*!< bit: 1 HPB1 AHB Clock Mask */
uint32_t HPB2_:1; /*!< bit: 2 HPB2 AHB Clock Mask */
uint32_t DSU_:1; /*!< bit: 3 DSU AHB Clock Mask */
uint32_t NVMCTRL_:1; /*!< bit: 4 NVMCTRL AHB Clock Mask */
uint32_t DMAC_:1; /*!< bit: 5 DMAC AHB Clock Mask */
uint32_t USB_:1; /*!< bit: 6 USB AHB Clock Mask */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_AHBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -269,17 +269,17 @@ typedef union {
/* -------- PM_APBAMASK : (PM Offset: 0x18) (R/W 32) APBA Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC0_:1; /*!< bit: 0 PAC0 APB Clock Enable */
uint32_t PM_:1; /*!< bit: 1 PM APB Clock Enable */
uint32_t SYSCTRL_:1; /*!< bit: 2 SYSCTRL APB Clock Enable */
uint32_t GCLK_:1; /*!< bit: 3 GCLK APB Clock Enable */
uint32_t WDT_:1; /*!< bit: 4 WDT APB Clock Enable */
uint32_t RTC_:1; /*!< bit: 5 RTC APB Clock Enable */
uint32_t EIC_:1; /*!< bit: 6 EIC APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBAMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -305,17 +305,17 @@ typedef union {
/* -------- PM_APBBMASK : (PM Offset: 0x1C) (R/W 32) APBB Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC1_:1; /*!< bit: 0 PAC1 APB Clock Enable */
uint32_t DSU_:1; /*!< bit: 1 DSU APB Clock Enable */
uint32_t NVMCTRL_:1; /*!< bit: 2 NVMCTRL APB Clock Enable */
uint32_t PORT_:1; /*!< bit: 3 PORT APB Clock Enable */
uint32_t DMAC_:1; /*!< bit: 4 DMAC APB Clock Enable */
uint32_t USB_:1; /*!< bit: 5 USB APB Clock Enable */
uint32_t HMATRIX_:1; /*!< bit: 6 HMATRIX APB Clock Enable */
uint32_t :25; /*!< bit: 7..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBBMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -341,31 +341,31 @@ typedef union {
/* -------- PM_APBCMASK : (PM Offset: 0x20) (R/W 32) APBC Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t :2; /*!< bit: 14..15 Reserved */
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t :1; /*!< bit: 20 Reserved */
uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PAC2_:1; /*!< bit: 0 PAC2 APB Clock Enable */
uint32_t EVSYS_:1; /*!< bit: 1 EVSYS APB Clock Enable */
uint32_t SERCOM0_:1; /*!< bit: 2 SERCOM0 APB Clock Enable */
uint32_t SERCOM1_:1; /*!< bit: 3 SERCOM1 APB Clock Enable */
uint32_t SERCOM2_:1; /*!< bit: 4 SERCOM2 APB Clock Enable */
uint32_t SERCOM3_:1; /*!< bit: 5 SERCOM3 APB Clock Enable */
uint32_t SERCOM4_:1; /*!< bit: 6 SERCOM4 APB Clock Enable */
uint32_t SERCOM5_:1; /*!< bit: 7 SERCOM5 APB Clock Enable */
uint32_t TCC0_:1; /*!< bit: 8 TCC0 APB Clock Enable */
uint32_t TCC1_:1; /*!< bit: 9 TCC1 APB Clock Enable */
uint32_t TCC2_:1; /*!< bit: 10 TCC2 APB Clock Enable */
uint32_t TC3_:1; /*!< bit: 11 TC3 APB Clock Enable */
uint32_t TC4_:1; /*!< bit: 12 TC4 APB Clock Enable */
uint32_t TC5_:1; /*!< bit: 13 TC5 APB Clock Enable */
uint32_t :2; /*!< bit: 14..15 Reserved */
uint32_t ADC_:1; /*!< bit: 16 ADC APB Clock Enable */
uint32_t AC_:1; /*!< bit: 17 AC APB Clock Enable */
uint32_t :1; /*!< bit: 18 Reserved */
uint32_t PTC_:1; /*!< bit: 19 PTC APB Clock Enable */
uint32_t :1; /*!< bit: 20 Reserved */
uint32_t RFCTRL_:1; /*!< bit: 21 RFCTRL APB Clock Enable */
uint32_t :10; /*!< bit: 22..31 Reserved */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PM_APBCMASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -413,11 +413,11 @@ typedef union {
/* -------- PM_INTENCLR : (PM Offset: 0x34) (R/W 8) Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -431,11 +431,11 @@ typedef union {
/* -------- PM_INTENSET : (PM Offset: 0x35) (R/W 8) Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CKRDY:1; /*!< bit: 0 Clock Ready Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -449,11 +449,11 @@ typedef union {
/* -------- PM_INTFLAG : (PM Offset: 0x36) (R/W 8) Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t CKRDY:1; /*!< bit: 0 Clock Ready */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -467,17 +467,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- PM_RCAUSE : (PM Offset: 0x38) (R/ 8) Reset Cause -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t POR:1; /*!< bit: 0 Power On Reset */
uint8_t BOD12:1; /*!< bit: 1 Brown Out 12 Detector Reset */
uint8_t BOD33:1; /*!< bit: 2 Brown Out 33 Detector Reset */
uint8_t :1; /*!< bit: 3 Reserved */
uint8_t EXT:1; /*!< bit: 4 External Reset */
uint8_t WDT:1; /*!< bit: 5 Watchdog Reset */
uint8_t SYST:1; /*!< bit: 6 System Reset Request */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PM_RCAUSE_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -501,24 +501,24 @@ typedef union {
/** \brief PM hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
RoReg8 Reserved1[0x6];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
__IO PM_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 8) Control */
__IO PM_SLEEP_Type SLEEP; /**< \brief Offset: 0x01 (R/W 8) Sleep Mode */
RoReg8 Reserved1[0x6];
__IO PM_CPUSEL_Type CPUSEL; /**< \brief Offset: 0x08 (R/W 8) CPU Clock Select */
__IO PM_APBASEL_Type APBASEL; /**< \brief Offset: 0x09 (R/W 8) APBA Clock Select */
__IO PM_APBBSEL_Type APBBSEL; /**< \brief Offset: 0x0A (R/W 8) APBB Clock Select */
__IO PM_APBCSEL_Type APBCSEL; /**< \brief Offset: 0x0B (R/W 8) APBC Clock Select */
RoReg8 Reserved2[0x8];
__IO PM_AHBMASK_Type AHBMASK; /**< \brief Offset: 0x14 (R/W 32) AHB Mask */
__IO PM_APBAMASK_Type APBAMASK; /**< \brief Offset: 0x18 (R/W 32) APBA Mask */
__IO PM_APBBMASK_Type APBBMASK; /**< \brief Offset: 0x1C (R/W 32) APBB Mask */
__IO PM_APBCMASK_Type APBCMASK; /**< \brief Offset: 0x20 (R/W 32) APBC Mask */
RoReg8 Reserved3[0x10];
__IO PM_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x34 (R/W 8) Interrupt Enable Clear */
__IO PM_INTENSET_Type INTENSET; /**< \brief Offset: 0x35 (R/W 8) Interrupt Enable Set */
__IO PM_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x36 (R/W 8) Interrupt Flag Status and Clear */
RoReg8 Reserved4[0x1];
__I PM_RCAUSE_Type RCAUSE; /**< \brief Offset: 0x38 (R/ 8) Reset Cause */
} Pm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

170
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_port.h
View File

@ -56,10 +56,10 @@
/* -------- PORT_DIR : (PORT Offset: 0x00) (R/W 32) GROUP Data Direction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIR:32; /*!< bit: 0..31 Port Data Direction */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -74,10 +74,10 @@ typedef union {
/* -------- PORT_DIRCLR : (PORT Offset: 0x04) (R/W 32) GROUP Data Direction Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRCLR:32; /*!< bit: 0..31 Port Data Direction Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -92,10 +92,10 @@ typedef union {
/* -------- PORT_DIRSET : (PORT Offset: 0x08) (R/W 32) GROUP Data Direction Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRSET:32; /*!< bit: 0..31 Port Data Direction Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -110,10 +110,10 @@ typedef union {
/* -------- PORT_DIRTGL : (PORT Offset: 0x0C) (R/W 32) GROUP Data Direction Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t DIRTGL:32; /*!< bit: 0..31 Port Data Direction Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_DIRTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -128,10 +128,10 @@ typedef union {
/* -------- PORT_OUT : (PORT Offset: 0x10) (R/W 32) GROUP Data Output Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUT:32; /*!< bit: 0..31 Port Data Output Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -146,10 +146,10 @@ typedef union {
/* -------- PORT_OUTCLR : (PORT Offset: 0x14) (R/W 32) GROUP Data Output Value Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTCLR:32; /*!< bit: 0..31 Port Data Output Value Clear */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -164,10 +164,10 @@ typedef union {
/* -------- PORT_OUTSET : (PORT Offset: 0x18) (R/W 32) GROUP Data Output Value Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTSET:32; /*!< bit: 0..31 Port Data Output Value Set */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -182,10 +182,10 @@ typedef union {
/* -------- PORT_OUTTGL : (PORT Offset: 0x1C) (R/W 32) GROUP Data Output Value Toggle -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t OUTTGL:32; /*!< bit: 0..31 Port Data Output Value Toggle */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_OUTTGL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -200,10 +200,10 @@ typedef union {
/* -------- PORT_IN : (PORT Offset: 0x20) (R/ 32) GROUP Data Input Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t IN:32; /*!< bit: 0..31 Port Data Input Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_IN_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -218,10 +218,10 @@ typedef union {
/* -------- PORT_CTRL : (PORT Offset: 0x24) (R/W 32) GROUP Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SAMPLING:32; /*!< bit: 0..31 Input Sampling Mode */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -236,21 +236,21 @@ typedef union {
/* -------- PORT_WRCONFIG : (PORT Offset: 0x28) ( /W 32) GROUP Write Configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t PINMASK:16; /*!< bit: 0..15 Pin Mask for Multiple Pin Configuration */
uint32_t PMUXEN:1; /*!< bit: 16 Peripheral Multiplexer Enable */
uint32_t INEN:1; /*!< bit: 17 Input Enable */
uint32_t PULLEN:1; /*!< bit: 18 Pull Enable */
uint32_t :3; /*!< bit: 19..21 Reserved */
uint32_t DRVSTR:1; /*!< bit: 22 Output Driver Strength Selection */
uint32_t :1; /*!< bit: 23 Reserved */
uint32_t PMUX:4; /*!< bit: 24..27 Peripheral Multiplexing */
uint32_t WRPMUX:1; /*!< bit: 28 Write PMUX */
uint32_t :1; /*!< bit: 29 Reserved */
uint32_t WRPINCFG:1; /*!< bit: 30 Write PINCFG */
uint32_t HWSEL:1; /*!< bit: 31 Half-Word Select */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} PORT_WRCONFIG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -282,11 +282,11 @@ typedef union {
/* -------- PORT_PMUX : (PORT Offset: 0x30) (R/W 8) GROUP Peripheral Multiplexing n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PMUXE:4; /*!< bit: 0.. 3 Peripheral Multiplexing Even */
uint8_t PMUXO:4; /*!< bit: 4.. 7 Peripheral Multiplexing Odd */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PMUX_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -336,15 +336,15 @@ typedef union {
/* -------- PORT_PINCFG : (PORT Offset: 0x40) (R/W 8) GROUP Pin Configuration n -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t PMUXEN:1; /*!< bit: 0 Peripheral Multiplexer Enable */
uint8_t INEN:1; /*!< bit: 1 Input Enable */
uint8_t PULLEN:1; /*!< bit: 2 Pull Enable */
uint8_t :3; /*!< bit: 3.. 5 Reserved */
uint8_t DRVSTR:1; /*!< bit: 6 Output Driver Strength Selection */
uint8_t :1; /*!< bit: 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} PORT_PINCFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -364,28 +364,28 @@ typedef union {
/** \brief PortGroup hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
__IO PORT_DIR_Type DIR; /**< \brief Offset: 0x00 (R/W 32) Data Direction */
__IO PORT_DIRCLR_Type DIRCLR; /**< \brief Offset: 0x04 (R/W 32) Data Direction Clear */
__IO PORT_DIRSET_Type DIRSET; /**< \brief Offset: 0x08 (R/W 32) Data Direction Set */
__IO PORT_DIRTGL_Type DIRTGL; /**< \brief Offset: 0x0C (R/W 32) Data Direction Toggle */
__IO PORT_OUT_Type OUT; /**< \brief Offset: 0x10 (R/W 32) Data Output Value */
__IO PORT_OUTCLR_Type OUTCLR; /**< \brief Offset: 0x14 (R/W 32) Data Output Value Clear */
__IO PORT_OUTSET_Type OUTSET; /**< \brief Offset: 0x18 (R/W 32) Data Output Value Set */
__IO PORT_OUTTGL_Type OUTTGL; /**< \brief Offset: 0x1C (R/W 32) Data Output Value Toggle */
__I PORT_IN_Type IN; /**< \brief Offset: 0x20 (R/ 32) Data Input Value */
__IO PORT_CTRL_Type CTRL; /**< \brief Offset: 0x24 (R/W 32) Control */
__O PORT_WRCONFIG_Type WRCONFIG; /**< \brief Offset: 0x28 ( /W 32) Write Configuration */
RoReg8 Reserved1[0x4];
__IO PORT_PMUX_Type PMUX[16]; /**< \brief Offset: 0x30 (R/W 8) Peripheral Multiplexing n */
__IO PORT_PINCFG_Type PINCFG[32]; /**< \brief Offset: 0x40 (R/W 8) Pin Configuration n */
RoReg8 Reserved2[0x20];
} PortGroup;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief PORT hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
PortGroup Group[3]; /**< \brief Offset: 0x00 PortGroup groups [GROUPS] */
} Port;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#define SECTION_PORT_IOBUS

22
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rfctrl.h
View File

@ -56,16 +56,16 @@
/* -------- RFCTRL_FECFG : (RFCTRL Offset: 0x0) (R/W 16) Front-end control bus configuration -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t F0CFG:2; /*!< bit: 0.. 1 Front-end control signal 0 configuration */
uint16_t F1CFG:2; /*!< bit: 2.. 3 Front-end control signal 1 configuration */
uint16_t F2CFG:2; /*!< bit: 4.. 5 Front-end control signal 2 configuration */
uint16_t F3CFG:2; /*!< bit: 6.. 7 Front-end control signal 3 configuration */
uint16_t F4CFG:2; /*!< bit: 8.. 9 Front-end control signal 4 configuration */
uint16_t F5CFG:2; /*!< bit: 10..11 Front-end control signal 5 configuration */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RFCTRL_FECFG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -95,7 +95,7 @@ typedef union {
/** \brief RFCTRL hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
__IO RFCTRL_FECFG_Type FECFG; /**< \brief Offset: 0x0 (R/W 16) Front-end control bus configuration */
} Rfctrl;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

610
libraries/mbed/targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0+/utils/cmsis/TARGET_SAMR21/include/component/comp_rtc.h
View File

@ -56,16 +56,16 @@
/* -------- RTC_MODE0_CTRL : (RTC Offset: 0x00) (R/W 16) MODE0 MODE0 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :3; /*!< bit: 4.. 6 Reserved */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :3; /*!< bit: 4.. 6 Reserved */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -117,15 +117,15 @@ typedef union {
/* -------- RTC_MODE1_CTRL : (RTC Offset: 0x00) (R/W 16) MODE1 MODE1 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :4; /*!< bit: 4.. 7 Reserved */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -175,17 +175,17 @@ typedef union {
/* -------- RTC_MODE2_CTRL : (RTC Offset: 0x00) (R/W 16) MODE2 MODE2 Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :2; /*!< bit: 4.. 5 Reserved */
uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t SWRST:1; /*!< bit: 0 Software Reset */
uint16_t ENABLE:1; /*!< bit: 1 Enable */
uint16_t MODE:2; /*!< bit: 2.. 3 Operating Mode */
uint16_t :2; /*!< bit: 4.. 5 Reserved */
uint16_t CLKREP:1; /*!< bit: 6 Clock Representation */
uint16_t MATCHCLR:1; /*!< bit: 7 Clear on Match */
uint16_t PRESCALER:4; /*!< bit: 8..11 Prescaler */
uint16_t :4; /*!< bit: 12..15 Reserved */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_CTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -239,13 +239,13 @@ typedef union {
/* -------- RTC_READREQ : (RTC Offset: 0x02) (R/W 16) Read Request -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
uint16_t :8; /*!< bit: 6..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t ADDR:6; /*!< bit: 0.. 5 Address */
uint16_t :8; /*!< bit: 6..13 Reserved */
uint16_t RCONT:1; /*!< bit: 14 Read Continuously */
uint16_t RREQ:1; /*!< bit: 15 Read Request */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_READREQ_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -264,25 +264,25 @@ typedef union {
/* -------- RTC_MODE0_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE0 MODE0 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:1; /*!< bit: 8 Compare x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE0_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -320,26 +320,26 @@ typedef union {
/* -------- RTC_MODE1_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE1 MODE1 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
uint16_t :5; /*!< bit: 10..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t CMPEO0:1; /*!< bit: 8 Compare 0 Event Output Enable */
uint16_t CMPEO1:1; /*!< bit: 9 Compare 1 Event Output Enable */
uint16_t :5; /*!< bit: 10..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t CMPEO:2; /*!< bit: 8.. 9 Compare x Event Output Enable */
uint16_t :6; /*!< bit: 10..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -379,25 +379,25 @@ typedef union {
/* -------- RTC_MODE2_EVCTRL : (RTC Offset: 0x04) (R/W 16) MODE2 MODE2 Event Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PEREO0:1; /*!< bit: 0 Periodic Interval 0 Event Output Enable */
uint16_t PEREO1:1; /*!< bit: 1 Periodic Interval 1 Event Output Enable */
uint16_t PEREO2:1; /*!< bit: 2 Periodic Interval 2 Event Output Enable */
uint16_t PEREO3:1; /*!< bit: 3 Periodic Interval 3 Event Output Enable */
uint16_t PEREO4:1; /*!< bit: 4 Periodic Interval 4 Event Output Enable */
uint16_t PEREO5:1; /*!< bit: 5 Periodic Interval 5 Event Output Enable */
uint16_t PEREO6:1; /*!< bit: 6 Periodic Interval 6 Event Output Enable */
uint16_t PEREO7:1; /*!< bit: 7 Periodic Interval 7 Event Output Enable */
uint16_t ALARMEO0:1; /*!< bit: 8 Alarm 0 Event Output Enable */
uint16_t :6; /*!< bit: 9..14 Reserved */
uint16_t OVFEO:1; /*!< bit: 15 Overflow Event Output Enable */
} bit; /*!< Structure used for bit access */
struct {
uint16_t PEREO:8; /*!< bit: 0.. 7 Periodic Interval x Event Output Enable */
uint16_t ALARMEO:1; /*!< bit: 8 Alarm x Event Output Enable */
uint16_t :7; /*!< bit: 9..15 Reserved */
} vec; /*!< Structure used for vec access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE2_EVCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -435,17 +435,17 @@ typedef union {
/* -------- RTC_MODE0_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE0 MODE0 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -466,18 +466,18 @@ typedef union {
/* -------- RTC_MODE1_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE1 MODE1 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -500,17 +500,17 @@ typedef union {
/* -------- RTC_MODE2_INTENCLR : (RTC Offset: 0x06) (R/W 8) MODE2 MODE2 Interrupt Enable Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENCLR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -531,17 +531,17 @@ typedef union {
/* -------- RTC_MODE0_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE0 MODE0 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:1; /*!< bit: 0 Compare x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -562,18 +562,18 @@ typedef union {
/* -------- RTC_MODE1_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE1 MODE1 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t CMP0:1; /*!< bit: 0 Compare 0 Interrupt Enable */
uint8_t CMP1:1; /*!< bit: 1 Compare 1 Interrupt Enable */
uint8_t :4; /*!< bit: 2.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t CMP:2; /*!< bit: 0.. 1 Compare x Interrupt Enable */
uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -596,17 +596,17 @@ typedef union {
/* -------- RTC_MODE2_INTENSET : (RTC Offset: 0x07) (R/W 8) MODE2 MODE2 Interrupt Enable Set -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 Interrupt Enable */
uint8_t :5; /*!< bit: 1.. 5 Reserved */
uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready Interrupt Enable */
uint8_t OVF:1; /*!< bit: 7 Overflow Interrupt Enable */
} bit; /*!< Structure used for bit access */
struct {
uint8_t ALARM:1; /*!< bit: 0 Alarm x Interrupt Enable */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTENSET_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -627,17 +627,17 @@ typedef union {
/* -------- RTC_MODE0_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE0 MODE0 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t CMP:1; /*!< bit: 0 Compare x */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t CMP:1; /*!< bit: 0 Compare x */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE0_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -658,18 +658,18 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- RTC_MODE1_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE1 MODE1 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
__I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
__I uint8_t :4; /*!< bit: 2.. 5 Reserved */
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t CMP0:1; /*!< bit: 0 Compare 0 */
__I uint8_t CMP1:1; /*!< bit: 1 Compare 1 */
__I uint8_t :4; /*!< bit: 2.. 5 Reserved */
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t CMP:2; /*!< bit: 0.. 1 Compare x */
__I uint8_t :6; /*!< bit: 2.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE1_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -692,17 +692,17 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- RTC_MODE2_INTFLAG : (RTC Offset: 0x08) (R/W 8) MODE2 MODE2 Interrupt Flag Status and Clear -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union { // __I to avoid read-modify-write on write-to-clear register
struct {
__I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
struct {
__I uint8_t ALARM0:1; /*!< bit: 0 Alarm 0 */
__I uint8_t :5; /*!< bit: 1.. 5 Reserved */
__I uint8_t SYNCRDY:1; /*!< bit: 6 Synchronization Ready */
__I uint8_t OVF:1; /*!< bit: 7 Overflow */
} bit; /*!< Structure used for bit access */
struct {
__I uint8_t ALARM:1; /*!< bit: 0 Alarm x */
__I uint8_t :7; /*!< bit: 1.. 7 Reserved */
} vec; /*!< Structure used for vec access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_INTFLAG_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -723,11 +723,11 @@ typedef union { // __I to avoid read-modify-write on write-to-clear register
/* -------- RTC_STATUS : (RTC Offset: 0x0A) (R/W 8) Status -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t :7; /*!< bit: 0.. 6 Reserved */
uint8_t SYNCBUSY:1; /*!< bit: 7 Synchronization Busy */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_STATUS_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -741,11 +741,11 @@ typedef union {
/* -------- RTC_DBGCTRL : (RTC Offset: 0x0B) (R/W 8) Debug Control -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t DBGRUN:1; /*!< bit: 0 Run During Debug */
uint8_t :7; /*!< bit: 1.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_DBGCTRL_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -759,11 +759,11 @@ typedef union {
/* -------- RTC_FREQCORR : (RTC Offset: 0x0C) (R/W 8) Frequency Correction -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t VALUE:7; /*!< bit: 0.. 6 Correction Value */
uint8_t SIGN:1; /*!< bit: 7 Correction Sign */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_FREQCORR_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -780,10 +780,10 @@ typedef union {
/* -------- RTC_MODE0_COUNT : (RTC Offset: 0x10) (R/W 32) MODE0 MODE0 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COUNT:32; /*!< bit: 0..31 Counter Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -798,10 +798,10 @@ typedef union {
/* -------- RTC_MODE1_COUNT : (RTC Offset: 0x10) (R/W 16) MODE1 MODE1 Counter Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COUNT:16; /*!< bit: 0..15 Counter Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COUNT_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -816,15 +816,15 @@ typedef union {
/* -------- RTC_MODE2_CLOCK : (RTC Offset: 0x10) (R/W 32) MODE2 MODE2 Clock Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_CLOCK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -856,10 +856,10 @@ typedef union {
/* -------- RTC_MODE1_PER : (RTC Offset: 0x14) (R/W 16) MODE1 MODE1 Counter Period -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t PER:16; /*!< bit: 0..15 Counter Period */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t PER:16; /*!< bit: 0..15 Counter Period */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_PER_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -874,10 +874,10 @@ typedef union {
/* -------- RTC_MODE0_COMP : (RTC Offset: 0x18) (R/W 32) MODE0 MODE0 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t COMP:32; /*!< bit: 0..31 Compare Value */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE0_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -892,10 +892,10 @@ typedef union {
/* -------- RTC_MODE1_COMP : (RTC Offset: 0x18) (R/W 16) MODE1 MODE1 Compare n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
struct {
uint16_t COMP:16; /*!< bit: 0..15 Compare Value */
} bit; /*!< Structure used for bit access */
uint16_t reg; /*!< Type used for register access */
} RTC_MODE1_COMP_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -910,15 +910,15 @@ typedef union {
/* -------- RTC_MODE2_ALARM : (RTC Offset: 0x18) (R/W 32) MODE2 MODE2_ALARM Alarm n Value -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
struct {
uint32_t SECOND:6; /*!< bit: 0.. 5 Second */
uint32_t MINUTE:6; /*!< bit: 6..11 Minute */
uint32_t HOUR:5; /*!< bit: 12..16 Hour */
uint32_t DAY:5; /*!< bit: 17..21 Day */
uint32_t MONTH:4; /*!< bit: 22..25 Month */
uint32_t YEAR:6; /*!< bit: 26..31 Year */
} bit; /*!< Structure used for bit access */
uint32_t reg; /*!< Type used for register access */
} RTC_MODE2_ALARM_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -948,11 +948,11 @@ typedef union {
/* -------- RTC_MODE2_MASK : (RTC Offset: 0x1C) (R/W 8) MODE2 MODE2_ALARM Alarm n Mask -------- */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
struct {
uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
struct {
uint8_t SEL:3; /*!< bit: 0.. 2 Alarm Mask Selection */
uint8_t :5; /*!< bit: 3.. 7 Reserved */
} bit; /*!< Structure used for bit access */
uint8_t reg; /*!< Type used for register access */
} RTC_MODE2_MASK_Type;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
@ -981,79 +981,79 @@ typedef union {
/** \brief RtcMode2Alarm hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct {
__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
RoReg8 Reserved1[0x3];
__IO RTC_MODE2_ALARM_Type ALARM; /**< \brief Offset: 0x00 (R/W 32) MODE2_ALARM Alarm n Value */
__IO RTC_MODE2_MASK_Type MASK; /**< \brief Offset: 0x04 (R/W 8) MODE2_ALARM Alarm n Mask */
RoReg8 Reserved1[0x3];
} RtcMode2Alarm;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE0 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 32-bit Counter with Single 32-bit Compare */
__IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
RoReg8 Reserved3[0x4];
__IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
__IO RTC_MODE0_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE0 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE0_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE0 Event Control */
__IO RTC_MODE0_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE0 Interrupt Enable Clear */
__IO RTC_MODE0_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE0 Interrupt Enable Set */
__IO RTC_MODE0_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE0 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE0_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 32) MODE0 Counter Value */
RoReg8 Reserved3[0x4];
__IO RTC_MODE0_COMP_Type COMP[1]; /**< \brief Offset: 0x18 (R/W 32) MODE0 Compare n Value */
} RtcMode0;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE1 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* 16-bit Counter with Two 16-bit Compares */
__IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
__IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
__IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
RoReg8 Reserved3[0x2];
__IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
RoReg8 Reserved4[0x2];
__IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
__IO RTC_MODE1_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE1 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE1_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE1 Event Control */
__IO RTC_MODE1_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE1 Interrupt Enable Clear */
__IO RTC_MODE1_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE1 Interrupt Enable Set */
__IO RTC_MODE1_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE1 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE1_COUNT_Type COUNT; /**< \brief Offset: 0x10 (R/W 16) MODE1 Counter Value */
RoReg8 Reserved3[0x2];
__IO RTC_MODE1_PER_Type PER; /**< \brief Offset: 0x14 (R/W 16) MODE1 Counter Period */
RoReg8 Reserved4[0x2];
__IO RTC_MODE1_COMP_Type COMP[2]; /**< \brief Offset: 0x18 (R/W 16) MODE1 Compare n Value */
} RtcMode1;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/** \brief RTC_MODE2 hardware registers */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef struct { /* Clock/Calendar with Alarm */
__IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
__IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
__IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
RoReg8 Reserved3[0x4];
RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
__IO RTC_MODE2_CTRL_Type CTRL; /**< \brief Offset: 0x00 (R/W 16) MODE2 Control */
__IO RTC_READREQ_Type READREQ; /**< \brief Offset: 0x02 (R/W 16) Read Request */
__IO RTC_MODE2_EVCTRL_Type EVCTRL; /**< \brief Offset: 0x04 (R/W 16) MODE2 Event Control */
__IO RTC_MODE2_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x06 (R/W 8) MODE2 Interrupt Enable Clear */
__IO RTC_MODE2_INTENSET_Type INTENSET; /**< \brief Offset: 0x07 (R/W 8) MODE2 Interrupt Enable Set */
__IO RTC_MODE2_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 8) MODE2 Interrupt Flag Status and Clear */
RoReg8 Reserved1[0x1];
__IO RTC_STATUS_Type STATUS; /**< \brief Offset: 0x0A (R/W 8) Status */
__IO RTC_DBGCTRL_Type DBGCTRL; /**< \brief Offset: 0x0B (R/W 8) Debug Control */
__IO RTC_FREQCORR_Type FREQCORR; /**< \brief Offset: 0x0C (R/W 8) Frequency Correction */
RoReg8 Reserved2[0x3];
__IO RTC_MODE2_CLOCK_Type CLOCK; /**< \brief Offset: 0x10 (R/W 32) MODE2 Clock Value */
RoReg8 Reserved3[0x4];
RtcMode2Alarm Mode2Alarm[1]; /**< \brief Offset: 0x18 RtcMode2Alarm groups [ALARM_NUM] */
} RtcMode2;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
typedef union {
RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
RtcMode0 MODE0; /**< \brief Offset: 0x00 32-bit Counter with Single 32-bit Compare */
RtcMode1 MODE1; /**< \brief Offset: 0x00 16-bit Counter with Two 16-bit Compares */
RtcMode2 MODE2; /**< \brief Offset: 0x00 Clock/Calendar with Alarm */
} Rtc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */

Some files were not shown because too many files have changed in this diff Show More