mirror of https://github.com/ARMmbed/mbed-os.git
STM32Cube_FW_WB_V1.4.0 - CMSIS part
jeromecoutant
parent
b74756dceb
commit
d6e4b15c1a
File diff suppressed because it is too large
Load Diff
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@ -302,7 +302,7 @@ typedef struct
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typedef struct
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{
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__IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */
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__IO uint32_t PDKEYR; /*!< FLASH Power-down in run mode flash key Address offset: 0x04 */
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__IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */
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__IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
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__IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
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__IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
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@ -441,7 +441,6 @@ typedef struct
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__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
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} QUADSPI_TypeDef;
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/**
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* @brief Reset and Clock Control
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*/
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@ -710,7 +709,6 @@ typedef struct
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__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
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} RNG_TypeDef;
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/**
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* @brief Touch Sensing Controller (TSC)
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*/
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@ -732,7 +730,6 @@ typedef struct
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__IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
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} TSC_TypeDef;
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/**
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* @brief LCD
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*/
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@ -794,7 +791,6 @@ typedef struct
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__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
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} CRS_TypeDef;
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/**
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* @brief Inter-Processor Communication
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*/
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@ -936,7 +932,8 @@ typedef struct
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#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
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#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */
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/* Size SRAMx */
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/* Memory Size */
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#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
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#define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */
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#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */
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#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
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@ -3029,6 +3026,9 @@ typedef struct
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#define EXTI_RTSR1_RT16_Pos (16U)
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#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
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#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
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#define EXTI_RTSR1_RT17_Pos (17U)
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#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
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#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
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#define EXTI_RTSR1_RT18_Pos (18U)
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#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
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#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
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@ -3298,7 +3298,7 @@ typedef struct
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/****************** Bit definition for EXTI_SWIER2 register *****************/
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#define EXTI_SWIER2_SWI_Pos (0U)
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#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */
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#define EXTI_SWIER2_SWI EXTI_SWIER2_SWIER_Msk /*!< Falling trigger event configuration bit */
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#define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */
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#define EXTI_SWIER2_SWI33_Pos (1U)
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#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
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#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
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@ -3405,12 +3405,6 @@ typedef struct
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#define EXTI_IMR1_IM25_Pos (25U)
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#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
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#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */
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#define EXTI_IMR1_IM26_Pos (26U)
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#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
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#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU1 Interrupt Mask on line 26 */
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#define EXTI_IMR1_IM27_Pos (27U)
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#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
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#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU1 Interrupt Mask on line 27 */
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#define EXTI_IMR1_IM28_Pos (28U)
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#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
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#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */
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@ -3496,18 +3490,9 @@ typedef struct
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#define EXTI_IMR2_Pos (0U)
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#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */
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#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */
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#define EXTI_IMR2_IM32_Pos (0U)
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#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
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#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU1 Interrupt Mask on line 32 */
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#define EXTI_IMR2_IM33_Pos (1U)
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#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
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#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */
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#define EXTI_IMR2_IM34_Pos (2U)
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#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
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#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU1 Interrupt Mask on line 34 */
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#define EXTI_IMR2_IM35_Pos (3U)
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#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
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#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU1 Interrupt Mask on line 35 */
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#define EXTI_IMR2_IM36_Pos (4U)
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#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
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#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */
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@ -3541,9 +3526,6 @@ typedef struct
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#define EXTI_IMR2_IM46_Pos (14U)
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#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
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#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */
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#define EXTI_IMR2_IM47_Pos (15U)
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#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
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#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< CPU1 Interrupt Mask on line 47 */
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#define EXTI_IMR2_IM48_Pos (16U)
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#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
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#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */
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@ -3641,12 +3623,6 @@ typedef struct
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#define EXTI_C2IMR1_IM25_Pos (25U)
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#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */
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#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */
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#define EXTI_C2IMR1_IM26_Pos (26U)
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#define EXTI_C2IMR1_IM26_Msk (0x1UL << EXTI_C2IMR1_IM26_Pos) /*!< 0x04000000 */
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#define EXTI_C2IMR1_IM26 EXTI_C2IMR1_IM26_Msk /*!< CPU2 Interrupt Mask on line 26 */
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#define EXTI_C2IMR1_IM27_Pos (27U)
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#define EXTI_C2IMR1_IM27_Msk (0x1UL << EXTI_C2IMR1_IM27_Pos) /*!< 0x08000000 */
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#define EXTI_C2IMR1_IM27 EXTI_C2IMR1_IM27_Msk /*!< CPU2 Interrupt Mask on line 27 */
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#define EXTI_C2IMR1_IM28_Pos (28U)
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#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */
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#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */
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@ -3732,18 +3708,9 @@ typedef struct
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#define EXTI_C2IMR2_Pos (0U)
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#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */
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#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */
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#define EXTI_C2IMR2_IM32_Pos (0U)
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#define EXTI_C2IMR2_IM32_Msk (0x1UL << EXTI_C2IMR2_IM32_Pos) /*!< 0x00000001 */
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#define EXTI_C2IMR2_IM32 EXTI_C2IMR2_IM32_Msk /*!< CPU2 Interrupt Mask on line 32 */
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#define EXTI_C2IMR2_IM33_Pos (1U)
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#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */
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#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */
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#define EXTI_C2IMR2_IM34_Pos (2U)
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#define EXTI_C2IMR2_IM34_Msk (0x1UL << EXTI_C2IMR2_IM34_Pos) /*!< 0x00000004 */
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#define EXTI_C2IMR2_IM34 EXTI_C2IMR2_IM34_Msk /*!< CPU2 Interrupt Mask on line 34 */
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#define EXTI_C2IMR2_IM35_Pos (3U)
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#define EXTI_C2IMR2_IM35_Msk (0x1UL << EXTI_C2IMR2_IM35_Pos) /*!< 0x00000008 */
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#define EXTI_C2IMR2_IM35 EXTI_C2IMR2_IM35_Msk /*!< CPU2 Interrupt Mask on line 35 */
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#define EXTI_C2IMR2_IM36_Pos (4U)
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#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */
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#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */
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@ -3777,9 +3744,6 @@ typedef struct
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#define EXTI_C2IMR2_IM46_Pos (14U)
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#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */
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#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */
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#define EXTI_C2IMR2_IM47_Pos (15U)
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#define EXTI_C2IMR2_IM47_Msk (0x1UL << EXTI_C2IMR2_IM47_Pos) /*!< 0x00008000 */
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#define EXTI_C2IMR2_IM47 EXTI_C2IMR2_IM47_Msk /*!< CPU2 Interrupt Mask on line 47 */
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#define EXTI_C2IMR2_IM48_Pos (16U)
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#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */
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#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */
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@ -3790,10 +3754,10 @@ typedef struct
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#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */
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#define EXTI_C2EMR2_EM40_Pos (8U)
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#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */
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#define EXTI_C2EMR2_EM40 EXTI_C2EMR1_EM40_Msk /*!< CPU2 Event Mask on line 40 */
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#define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */
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#define EXTI_C2EMR2_EM41_Pos (9U)
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#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR1_EM41_Pos) /*!< 0x00000200 */
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#define EXTI_C2EMR2_EM41 EXTI_C2EMR1_EM41_Msk /*!< CPU2 Event Mask on line 41 */
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#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */
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#define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */
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/******************************************************************************/
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/* */
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@ -4054,9 +4018,9 @@ typedef struct
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#define FLASH_ACR_LATENCY_Pos (0U)
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#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
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#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
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#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
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#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
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#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
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#define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
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#define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
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#define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
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#define FLASH_ACR_PRFTEN_Pos (8U)
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#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
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#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */
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@ -4164,7 +4128,7 @@ typedef struct
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#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */
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#define FLASH_CR_OBL_LAUNCH_Pos (27U)
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#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
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#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option bute loading */
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#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
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#define FLASH_CR_OPTLOCK_Pos (30U)
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#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
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#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */
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@ -6491,7 +6455,7 @@ typedef struct
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#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
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#define PWR_SR2_PVMO_Pos (12U)
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#define PWR_SR2_PVMO_Msk (0x5UL << PWR_SR2_PVMO_Pos) /*!< 0x0000F000 */
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#define PWR_SR2_PVMO_Msk (0x5UL << PWR_SR2_PVMO_Pos) /*!< 0x00005000 */
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#define PWR_SR2_PVMO PWR_SR2_PVMO_Msk /*!< Peripheral voltage monitor output for all power domains */
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#define PWR_SR2_PVMO1_Pos (12U)
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#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
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@ -6502,7 +6466,7 @@ typedef struct
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/******************** Bit definition for PWR_SCR register ********************/
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#define PWR_SCR_CWUF_Pos (0U)
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#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x000000FF */
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#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
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#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */
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#define PWR_SCR_CWUF1_Pos (0U)
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#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
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@ -6573,7 +6537,6 @@ typedef struct
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#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
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#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */
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/******************** Bit definition for PWR_PUCRA register *****************/
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#define PWR_PUCRA_PA0_Pos (0U)
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#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
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@ -7071,7 +7034,6 @@ typedef struct
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#define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */
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#define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */
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/******************** Bit definition for PWR_EXTSCR register ********************/
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#define PWR_EXTSCR_C1CSSF_Pos (0U)
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#define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */
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@ -7296,12 +7258,17 @@ typedef struct
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#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
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#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
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/******************************************************************************/
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/* */
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/* Reset and Clock Control */
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/* */
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/******************************************************************************/
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/*
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* @brief Specific device feature definitions
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*/
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#define RCC_SMPS_SUPPORT
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#define RCC_MCO3_SUPPORT
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#define RCC_LSCO3_SUPPORT
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/******************** Bit definition for RCC_CR register *****************/
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#define RCC_CR_MSION_Pos (0U)
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@ -7369,6 +7336,7 @@ typedef struct
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#define RCC_CR_PLLRDY_Pos (25U)
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#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
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#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
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#define RCC_CR_PLLSAI1ON_Pos (26U)
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#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
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#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
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@ -7979,7 +7947,6 @@ typedef struct
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#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
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#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
|
||||
|
||||
|
||||
/******************** Bit definition for RCC_AHB1SMENR register ****************/
|
||||
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
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||||
#define RCC_AHB1SMENR_DMA1SMEN_Msk (0x1UL << RCC_AHB1SMENR_DMA1SMEN_Pos) /*!< 0x00000001 */
|
||||
|
|
@ -9375,9 +9342,9 @@ typedef struct
|
|||
#define SPI_CR1_BR_Pos (3U)
|
||||
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
|
||||
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
|
||||
#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */
|
||||
#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */
|
||||
#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */
|
||||
#define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
|
||||
#define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
|
||||
#define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
|
||||
|
||||
#define SPI_CR1_SPE_Pos (6U)
|
||||
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
|
||||
|
|
@ -9438,10 +9405,10 @@ typedef struct
|
|||
#define SPI_CR2_DS_Pos (8U)
|
||||
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
|
||||
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
|
||||
#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */
|
||||
#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */
|
||||
#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */
|
||||
#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */
|
||||
#define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
|
||||
#define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
|
||||
#define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
|
||||
#define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
|
||||
#define SPI_CR2_FRXTH_Pos (12U)
|
||||
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
|
||||
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
|
||||
|
|
@ -9477,13 +9444,13 @@ typedef struct
|
|||
#define SPI_SR_FRLVL_Pos (9U)
|
||||
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
|
||||
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
|
||||
#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
|
||||
#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
|
||||
#define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
|
||||
#define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
|
||||
#define SPI_SR_FTLVL_Pos (11U)
|
||||
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
|
||||
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
|
||||
#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
|
||||
#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
|
||||
#define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
|
||||
#define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
|
||||
|
||||
/******************** Bit definition for SPI_DR register ********************/
|
||||
#define SPI_DR_DR_Pos (0U)
|
||||
|
|
@ -9992,7 +9959,6 @@ typedef struct
|
|||
#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
|
||||
#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!< CNT[13:0] bits (Counter value) */
|
||||
|
||||
|
||||
/******************************************************************************/
|
||||
/* */
|
||||
/* LCD Controller (LCD) */
|
||||
|
|
@ -13352,7 +13318,6 @@ typedef struct
|
|||
/*********************** UART Instances : Smard card mode *********************/
|
||||
#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
|
||||
|
||||
|
||||
/*********************** UART Instances : Driver Enable ***********************/
|
||||
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \
|
||||
((INSTANCE) == LPUART1))
|
||||
|
|
@ -13363,7 +13328,6 @@ typedef struct
|
|||
/******************** LPUART Instance *****************************************/
|
||||
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
|
||||
|
||||
|
||||
/******************************* ADC Instances ********************************/
|
||||
#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
|
||||
|
||||
|
|
@ -13372,7 +13336,6 @@ typedef struct
|
|||
/******************************* AES Instances ********************************/
|
||||
#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES1) || ((INSTANCE) == AES2))
|
||||
|
||||
|
||||
/******************************** COMP Instances ******************************/
|
||||
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
|
||||
((INSTANCE) == COMP2))
|
||||
|
|
@ -13673,9 +13636,6 @@ typedef struct
|
|||
((INSTANCE) == TIM16) || \
|
||||
((INSTANCE) == TIM17))
|
||||
|
||||
/****************** TIM Instances : supporting synchronization ****************/
|
||||
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
|
||||
|
||||
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
|
||||
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)
|
||||
|
||||
|
|
|
|||
|
|
@ -69,7 +69,7 @@
|
|||
* @brief CMSIS Device version number
|
||||
*/
|
||||
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
|
||||
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
|
||||
|
|
@ -87,10 +87,11 @@
|
|||
|
||||
#if defined(STM32WB55xx)
|
||||
#include "stm32wb55xx.h"
|
||||
#elif defined(STM32WB50xx)
|
||||
#include "stm32wb50xx.h"
|
||||
#else
|
||||
#error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
|
|
@ -64,7 +64,9 @@ extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
|
|||
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
|
||||
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
|
||||
|
||||
#if defined(STM32WB55xx)
|
||||
extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue