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STM32Cube_FW_WB_V1.4.0 - CMSIS part

pull/12283/head
jeromecoutant 2020-01-17 17:08:38 +01:00
parent b74756dceb
commit d6e4b15c1a
4 changed files with 11260 additions and 92 deletions
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11205
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h Normal file
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140
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h
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@ -302,7 +302,7 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH Power-down in run mode flash key Address offset: 0x04 */ __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
@ -401,15 +401,15 @@ typedef struct
__IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */
__IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */
uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */
@ -441,7 +441,6 @@ typedef struct
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef; } QUADSPI_TypeDef;
/** /**
* @brief Reset and Clock Control * @brief Reset and Clock Control
*/ */
@ -456,7 +455,7 @@ uint32_t RESERVED0; /*!< Reserved,
__IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
__IO uint32_t SMPSCR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x24 */ __IO uint32_t SMPSCR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
@ -710,7 +709,6 @@ typedef struct
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef; } RNG_TypeDef;
/** /**
* @brief Touch Sensing Controller (TSC) * @brief Touch Sensing Controller (TSC)
*/ */
@ -732,7 +730,6 @@ typedef struct
__IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
} TSC_TypeDef; } TSC_TypeDef;
/** /**
* @brief LCD * @brief LCD
*/ */
@ -794,7 +791,6 @@ typedef struct
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef; } CRS_TypeDef;
/** /**
* @brief Inter-Processor Communication * @brief Inter-Processor Communication
*/ */
@ -936,7 +932,8 @@ typedef struct
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */ #define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */
/* Size SRAMx */ /* Memory Size */
#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
#define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */ #define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */
#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ #define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
@ -3029,6 +3026,9 @@ typedef struct
#define EXTI_RTSR1_RT16_Pos (16U) #define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT18_Pos (18U) #define EXTI_RTSR1_RT18_Pos (18U)
#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
@ -3297,8 +3297,8 @@ typedef struct
/****************** Bit definition for EXTI_SWIER2 register *****************/ /****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI_Pos (0U) #define EXTI_SWIER2_SWI_Pos (0U)
#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ #define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */
#define EXTI_SWIER2_SWI EXTI_SWIER2_SWIER_Msk /*!< Falling trigger event configuration bit */ #define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */
#define EXTI_SWIER2_SWI33_Pos (1U) #define EXTI_SWIER2_SWI33_Pos (1U)
#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ #define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
@ -3405,12 +3405,6 @@ typedef struct
#define EXTI_IMR1_IM25_Pos (25U) #define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU1 Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU1 Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U) #define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */
@ -3496,18 +3490,9 @@ typedef struct
#define EXTI_IMR2_Pos (0U) #define EXTI_IMR2_Pos (0U)
#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ #define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */
#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ #define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */
#define EXTI_IMR2_IM32_Pos (0U) #define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU1 Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU1 Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU1 Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U) #define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */
@ -3541,9 +3526,6 @@ typedef struct
#define EXTI_IMR2_IM46_Pos (14U) #define EXTI_IMR2_IM46_Pos (14U)
#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */
#define EXTI_IMR2_IM47_Pos (15U)
#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< CPU1 Interrupt Mask on line 47 */
#define EXTI_IMR2_IM48_Pos (16U) #define EXTI_IMR2_IM48_Pos (16U)
#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */
@ -3641,12 +3623,6 @@ typedef struct
#define EXTI_C2IMR1_IM25_Pos (25U) #define EXTI_C2IMR1_IM25_Pos (25U)
#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ #define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ #define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */
#define EXTI_C2IMR1_IM26_Pos (26U)
#define EXTI_C2IMR1_IM26_Msk (0x1UL << EXTI_C2IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_C2IMR1_IM26 EXTI_C2IMR1_IM26_Msk /*!< CPU2 Interrupt Mask on line 26 */
#define EXTI_C2IMR1_IM27_Pos (27U)
#define EXTI_C2IMR1_IM27_Msk (0x1UL << EXTI_C2IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_C2IMR1_IM27 EXTI_C2IMR1_IM27_Msk /*!< CPU2 Interrupt Mask on line 27 */
#define EXTI_C2IMR1_IM28_Pos (28U) #define EXTI_C2IMR1_IM28_Pos (28U)
#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ #define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ #define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */
@ -3732,18 +3708,9 @@ typedef struct
#define EXTI_C2IMR2_Pos (0U) #define EXTI_C2IMR2_Pos (0U)
#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ #define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */
#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ #define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */
#define EXTI_C2IMR2_IM32_Pos (0U)
#define EXTI_C2IMR2_IM32_Msk (0x1UL << EXTI_C2IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_C2IMR2_IM32 EXTI_C2IMR2_IM32_Msk /*!< CPU2 Interrupt Mask on line 32 */
#define EXTI_C2IMR2_IM33_Pos (1U) #define EXTI_C2IMR2_IM33_Pos (1U)
#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ #define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ #define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */
#define EXTI_C2IMR2_IM34_Pos (2U)
#define EXTI_C2IMR2_IM34_Msk (0x1UL << EXTI_C2IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_C2IMR2_IM34 EXTI_C2IMR2_IM34_Msk /*!< CPU2 Interrupt Mask on line 34 */
#define EXTI_C2IMR2_IM35_Pos (3U)
#define EXTI_C2IMR2_IM35_Msk (0x1UL << EXTI_C2IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_C2IMR2_IM35 EXTI_C2IMR2_IM35_Msk /*!< CPU2 Interrupt Mask on line 35 */
#define EXTI_C2IMR2_IM36_Pos (4U) #define EXTI_C2IMR2_IM36_Pos (4U)
#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ #define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ #define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */
@ -3777,9 +3744,6 @@ typedef struct
#define EXTI_C2IMR2_IM46_Pos (14U) #define EXTI_C2IMR2_IM46_Pos (14U)
#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ #define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */
#define EXTI_C2IMR2_IM47_Pos (15U)
#define EXTI_C2IMR2_IM47_Msk (0x1UL << EXTI_C2IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_C2IMR2_IM47 EXTI_C2IMR2_IM47_Msk /*!< CPU2 Interrupt Mask on line 47 */
#define EXTI_C2IMR2_IM48_Pos (16U) #define EXTI_C2IMR2_IM48_Pos (16U)
#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ #define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ #define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */
@ -3790,10 +3754,10 @@ typedef struct
#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ #define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */
#define EXTI_C2EMR2_EM40_Pos (8U) #define EXTI_C2EMR2_EM40_Pos (8U)
#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ #define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_C2EMR2_EM40 EXTI_C2EMR1_EM40_Msk /*!< CPU2 Event Mask on line 40 */ #define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */
#define EXTI_C2EMR2_EM41_Pos (9U) #define EXTI_C2EMR2_EM41_Pos (9U)
#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR1_EM41_Pos) /*!< 0x00000200 */ #define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_C2EMR2_EM41 EXTI_C2EMR1_EM41_Msk /*!< CPU2 Event Mask on line 41 */ #define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4054,9 +4018,9 @@ typedef struct
#define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
#define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */
@ -4164,7 +4128,7 @@ typedef struct
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */
#define FLASH_CR_OBL_LAUNCH_Pos (27U) #define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option bute loading */ #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
#define FLASH_CR_OPTLOCK_Pos (30U) #define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */
@ -6491,7 +6455,7 @@ typedef struct
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
#define PWR_SR2_PVMO_Pos (12U) #define PWR_SR2_PVMO_Pos (12U)
#define PWR_SR2_PVMO_Msk (0x5UL << PWR_SR2_PVMO_Pos) /*!< 0x0000F000 */ #define PWR_SR2_PVMO_Msk (0x5UL << PWR_SR2_PVMO_Pos) /*!< 0x00005000 */
#define PWR_SR2_PVMO PWR_SR2_PVMO_Msk /*!< Peripheral voltage monitor output for all power domains */ #define PWR_SR2_PVMO PWR_SR2_PVMO_Msk /*!< Peripheral voltage monitor output for all power domains */
#define PWR_SR2_PVMO1_Pos (12U) #define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */ #define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
@ -6502,7 +6466,7 @@ typedef struct
/******************** Bit definition for PWR_SCR register ********************/ /******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U) #define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x000000FF */ #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */
#define PWR_SCR_CWUF1_Pos (0U) #define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
@ -6573,7 +6537,6 @@ typedef struct
#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ #define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */
/******************** Bit definition for PWR_PUCRA register *****************/ /******************** Bit definition for PWR_PUCRA register *****************/
#define PWR_PUCRA_PA0_Pos (0U) #define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
@ -7071,7 +7034,6 @@ typedef struct
#define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */ #define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */
#define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */ #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */
/******************** Bit definition for PWR_EXTSCR register ********************/ /******************** Bit definition for PWR_EXTSCR register ********************/
#define PWR_EXTSCR_C1CSSF_Pos (0U) #define PWR_EXTSCR_C1CSSF_Pos (0U)
#define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ #define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */
@ -7296,12 +7258,17 @@ typedef struct
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */ #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* Reset and Clock Control */ /* Reset and Clock Control */
/* */ /* */
/******************************************************************************/ /******************************************************************************/
/*
* @brief Specific device feature definitions
*/
#define RCC_SMPS_SUPPORT
#define RCC_MCO3_SUPPORT
#define RCC_LSCO3_SUPPORT
/******************** Bit definition for RCC_CR register *****************/ /******************** Bit definition for RCC_CR register *****************/
#define RCC_CR_MSION_Pos (0U) #define RCC_CR_MSION_Pos (0U)
@ -7369,6 +7336,7 @@ typedef struct
#define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
#define RCC_CR_PLLSAI1ON_Pos (26U) #define RCC_CR_PLLSAI1ON_Pos (26U)
#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */ #define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */ #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
@ -7844,9 +7812,9 @@ typedef struct
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U) #define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_APB3RSTR register **************/ /******************** Bit definition for RCC_APB3RSTR register **************/
#define RCC_APB3RSTR_RFRST_Pos (0U) #define RCC_APB3RSTR_RFRST_Pos (0U)
@ -7975,10 +7943,9 @@ typedef struct
#define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U) #define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ****************/ /******************** Bit definition for RCC_AHB1SMENR register ****************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
@ -8022,9 +7989,9 @@ typedef struct
#define RCC_AHB2SMENR_ADCSMEN_Pos (13U) #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */ #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
#define RCC_AHB2SMENR_AES1SMEN_Pos (16U) #define RCC_AHB2SMENR_AES1SMEN_Pos (16U)
#define RCC_AHB2SMENR_AES1SMEN_Msk (0x1UL << RCC_AHB2SMENR_AES1SMEN_Pos) /*!< 0x00010000 */ #define RCC_AHB2SMENR_AES1SMEN_Msk (0x1UL << RCC_AHB2SMENR_AES1SMEN_Pos) /*!< 0x00010000 */
#define RCC_AHB2SMENR_AES1SMEN RCC_AHB2SMENR_AES1SMEN_Msk #define RCC_AHB2SMENR_AES1SMEN RCC_AHB2SMENR_AES1SMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register ***************/ /******************** Bit definition for RCC_AHB3SMENR register ***************/
#define RCC_AHB3SMENR_QUADSPISMEN_Pos (8U) #define RCC_AHB3SMENR_QUADSPISMEN_Pos (8U)
@ -8548,7 +8515,7 @@ typedef struct
#define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk #define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk
#define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U) #define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U)
#define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */ #define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */
#define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk #define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk
/******************** Bit definition for RCC_C2APB1SMENR1 register **************/ /******************** Bit definition for RCC_C2APB1SMENR1 register **************/
#define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U) #define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U)
@ -9375,9 +9342,9 @@ typedef struct
#define SPI_CR1_BR_Pos (3U) #define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U) #define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
@ -9438,10 +9405,10 @@ typedef struct
#define SPI_CR2_DS_Pos (8U) #define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */ #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */ #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */ #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */ #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U) #define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
@ -9477,13 +9444,13 @@ typedef struct
#define SPI_SR_FRLVL_Pos (9U) #define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U) #define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/ /******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U) #define SPI_DR_DR_Pos (0U)
@ -9992,7 +9959,6 @@ typedef struct
#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!< CNT[13:0] bits (Counter value) */ #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!< CNT[13:0] bits (Counter value) */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* LCD Controller (LCD) */ /* LCD Controller (LCD) */
@ -13352,7 +13318,6 @@ typedef struct
/*********************** UART Instances : Smard card mode *********************/ /*********************** UART Instances : Smard card mode *********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
/*********************** UART Instances : Driver Enable ***********************/ /*********************** UART Instances : Driver Enable ***********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \ #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \
((INSTANCE) == LPUART1)) ((INSTANCE) == LPUART1))
@ -13363,7 +13328,6 @@ typedef struct
/******************** LPUART Instance *****************************************/ /******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/******************************* ADC Instances ********************************/ /******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
@ -13372,7 +13336,6 @@ typedef struct
/******************************* AES Instances ********************************/ /******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES1) || ((INSTANCE) == AES2)) #define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES1) || ((INSTANCE) == AES2))
/******************************** COMP Instances ******************************/ /******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2)) ((INSTANCE) == COMP2))
@ -13673,9 +13636,6 @@ typedef struct
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

5
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h
View File

@ -69,7 +69,7 @@
* @brief CMSIS Device version number * @brief CMSIS Device version number
*/ */
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ #define __STM32WBxx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\ #define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
@ -87,10 +87,11 @@
#if defined(STM32WB55xx) #if defined(STM32WB55xx)
#include "stm32wb55xx.h" #include "stm32wb55xx.h"
#elif defined(STM32WB50xx)
#include "stm32wb50xx.h"
#else #else
#error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)" #error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
#endif #endif
/** /**
* @} * @}
*/ */

2
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/system_stm32wbxx.h
View File

@ -64,7 +64,9 @@ extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
#if defined(STM32WB55xx)
extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */ extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
#endif
/** /**
* @} * @}
*/ */