mirror of https://github.com/ARMmbed/mbed-os.git
M263: Fix compile error on analogin/out & crypto-misc
parent
b9a2e06a1a
commit
d52fced891
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@ -57,23 +57,14 @@ void analogin_init(analogin_t *obj, PinName pin)
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// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
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if (! eadc_modinit_mask) {
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/* Reset module
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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SYS_ResetModule_S(modinit->rsetidx);
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// Reset module
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SYS_ResetModule(modinit->rsetidx);
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/* Select IP clock source
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Select IP clock source
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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/* Enable IP clock
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_EnableModuleClock_S(modinit->clkidx);
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// Enable IP clock
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CLK_EnableModuleClock(modinit->clkidx);
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// Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
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EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);
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@ -66,23 +66,14 @@ void analogout_init(dac_t *obj, PinName pin)
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* channels are deactivated.
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*/
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if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) {
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/* Reset IP
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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SYS_ResetModule_S(modinit->rsetidx);
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// Reset IP
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SYS_ResetModule(modinit->rsetidx);
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/* Select IP clock source and clock divider
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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// Select IP clock source and clock divider
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CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
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/* Enable IP clock
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_EnableModuleClock_S(modinit->clkidx);
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// Enable IP clock
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CLK_EnableModuleClock(modinit->clkidx);
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/* The conversion settling time is 8us when 12-bit input code transition from
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* lowest code (0x000) to highest code (0xFFF). */
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@ -134,11 +125,8 @@ void analogout_free(dac_t *obj)
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/* See analogout_init() for reason */
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if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) {
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/* Disable IP clock
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*
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* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
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*/
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CLK_DisableModuleClock_S(modinit->clkidx);
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// Disable IP clock
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CLK_DisableModuleClock(modinit->clkidx);
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}
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}
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@ -90,7 +90,7 @@ void crypto_init(void)
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}
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core_util_atomic_incr_u16(&crypto_init_counter, 1);
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if (crypto_init_counter == 1) {
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/* Enable IP clock
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// Enable IP clock
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SYS_UnlockReg(); // Unlock protected register
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CLK_EnableModuleClock(CRPT_MODULE);
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SYS_LockReg(); // Lock protected register
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