M263: Fix compile error on analogin/out & crypto-misc

pull/11122/head
cyliangtw 2019-06-13 15:35:02 +08:00
parent b9a2e06a1a
commit d52fced891
3 changed files with 15 additions and 36 deletions

View File

@ -57,23 +57,14 @@ void analogin_init(analogin_t *obj, PinName pin)
// NOTE: All channels (identified by ADCName) share a ADC module. This reset will also affect other channels of the same ADC module.
if (! eadc_modinit_mask) {
/* Reset module
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
// Reset module
SYS_ResetModule(modinit->rsetidx);
/* Select IP clock source
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Select IP clock source
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
// Enable IP clock
CLK_EnableModuleClock(modinit->clkidx);
// Set the ADC internal sampling time, input mode as single-end and enable the A/D converter
EADC_Open(eadc_base, EADC_CTL_DIFFEN_SINGLE_END);

View File

@ -66,23 +66,14 @@ void analogout_init(dac_t *obj, PinName pin)
* channels are deactivated.
*/
if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) {
/* Reset IP
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
SYS_ResetModule_S(modinit->rsetidx);
// Reset IP
SYS_ResetModule(modinit->rsetidx);
/* Select IP clock source and clock divider
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_SetModuleClock_S(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
// Select IP clock source and clock divider
CLK_SetModuleClock(modinit->clkidx, modinit->clksrc, modinit->clkdiv);
/* Enable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_EnableModuleClock_S(modinit->clkidx);
// Enable IP clock
CLK_EnableModuleClock(modinit->clkidx);
/* The conversion settling time is 8us when 12-bit input code transition from
* lowest code (0x000) to highest code (0xFFF). */
@ -134,11 +125,8 @@ void analogout_free(dac_t *obj)
/* See analogout_init() for reason */
if ((! dac_modinit_mask[0]) && (! dac_modinit_mask[1])) {
/* Disable IP clock
*
* NOTE: We must call secure version (from non-secure domain) because SYS/CLK regions are secure.
*/
CLK_DisableModuleClock_S(modinit->clkidx);
// Disable IP clock
CLK_DisableModuleClock(modinit->clkidx);
}
}

View File

@ -90,7 +90,7 @@ void crypto_init(void)
}
core_util_atomic_incr_u16(&crypto_init_counter, 1);
if (crypto_init_counter == 1) {
/* Enable IP clock
// Enable IP clock
SYS_UnlockReg(); // Unlock protected register
CLK_EnableModuleClock(CRPT_MODULE);
SYS_LockReg(); // Lock protected register