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Merge branch 'master' of https://github.com/mbedmicro/mbed

pull/123/head
bcostm 2013-12-10 10:35:26 +01:00
parent 0aa8b93e26 28b16e995d
commit d44996c26c
367 changed files with 31324 additions and 12511 deletions
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5
.travis.yml Normal file
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@ -0,0 +1,5 @@
---
install: "sudo $TRAVIS_BUILD_DIR/travis/install_dependencies.sh > /dev/null"
python:
- "2.7"
script: "python workspace_tools/build_travis.py"

2
README.md
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@ -1,6 +1,8 @@
mbed SDK mbed SDK
======== ========
[![Build Status](https://travis-ci.org/mbedmicro/mbed.png)](https://travis-ci.org/mbedmicro/mbed/builds)
The mbed Software Development Kit (SDK) is a C/C++ microcontroller software platform relied upon by tens of thousands of The mbed Software Development Kit (SDK) is a C/C++ microcontroller software platform relied upon by tens of thousands of
developers to build projects fast. developers to build projects fast.

2
libraries/USBDevice/USBDevice/USBEndpoints.h
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@ -43,6 +43,8 @@ typedef enum {
#include "USBEndpoints_LPC11U.h" #include "USBEndpoints_LPC11U.h"
#elif defined(TARGET_KL25Z) #elif defined(TARGET_KL25Z)
#include "USBEndpoints_KL25Z.h" #include "USBEndpoints_KL25Z.h"
#elif defined (TARGET_STM32F4XX)
#include "USBEndpoints_STM32F4.h"
#else #else
#error "Unknown target type" #error "Unknown target type"
#endif #endif

61
libraries/USBDevice/USBDevice/USBEndpoints_STM32F4.h Normal file
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@ -0,0 +1,61 @@
/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define NUMBER_OF_LOGICAL_ENDPOINTS (4)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
/* Define physical endpoint numbers */
/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
/* ---------------- ------------ ---------- --- */
#define EP0OUT (0) /* Control 64 No */
#define EP0IN (1) /* Control 64 No */
#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
/* Maximum Packet sizes */
#define MAX_PACKET_SIZE_EP0 (64)
#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP3 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
/* Generic endpoints - intended to be portable accross devices */
/* and be suitable for simple USB devices. */
/* Bulk endpoint */
#define EPBULK_OUT (EP2OUT)
#define EPBULK_IN (EP2IN)
/* Interrupt endpoint */
#define EPINT_OUT (EP1OUT)
#define EPINT_IN (EP1IN)
/* Isochronous endpoint */
#define EPISO_OUT (EP3OUT)
#define EPISO_IN (EP3IN)
#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)

5
libraries/USBDevice/USBDevice/USBHAL.h
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@ -74,9 +74,9 @@ protected:
virtual bool EP2_IN_callback(){return false;}; virtual bool EP2_IN_callback(){return false;};
virtual bool EP3_OUT_callback(){return false;}; virtual bool EP3_OUT_callback(){return false;};
virtual bool EP3_IN_callback(){return false;}; virtual bool EP3_IN_callback(){return false;};
#if !defined(TARGET_STM32F4)
virtual bool EP4_OUT_callback(){return false;}; virtual bool EP4_OUT_callback(){return false;};
virtual bool EP4_IN_callback(){return false;}; virtual bool EP4_IN_callback(){return false;};
#if !defined(TARGET_LPC11U24) #if !defined(TARGET_LPC11U24)
virtual bool EP5_OUT_callback(){return false;}; virtual bool EP5_OUT_callback(){return false;};
virtual bool EP5_IN_callback(){return false;}; virtual bool EP5_IN_callback(){return false;};
@ -101,6 +101,7 @@ protected:
virtual bool EP15_OUT_callback(){return false;}; virtual bool EP15_OUT_callback(){return false;};
virtual bool EP15_IN_callback(){return false;}; virtual bool EP15_IN_callback(){return false;};
#endif #endif
#endif
private: private:
void usbisr(void); void usbisr(void);
@ -109,6 +110,8 @@ private:
#if defined(TARGET_LPC11U24) #if defined(TARGET_LPC11U24)
bool (USBHAL::*epCallback[10 - 2])(void); bool (USBHAL::*epCallback[10 - 2])(void);
#elif defined(TARGET_STM32F4XX)
bool (USBHAL::*epCallback[8 - 2])(void);
#else #else
bool (USBHAL::*epCallback[32 - 2])(void); bool (USBHAL::*epCallback[32 - 2])(void);
#endif #endif

402
libraries/USBDevice/USBDevice/USBHAL_STM32F4.cpp Normal file
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@ -0,0 +1,402 @@
/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_STM32F4XX)
#include "USBHAL.h"
#include "USBRegs_STM32.h"
#include "pinmap.h"
USBHAL * USBHAL::instance;
static volatile int epComplete = 0;
static uint32_t bufferEnd = 0;
static const uint32_t rxFifoSize = 512;
static uint32_t rxFifoCount = 0;
static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
return 0;
}
USBHAL::USBHAL(void) {
NVIC_DisableIRQ(OTG_FS_IRQn);
epCallback[0] = &USBHAL::EP1_OUT_callback;
epCallback[1] = &USBHAL::EP1_IN_callback;
epCallback[2] = &USBHAL::EP2_OUT_callback;
epCallback[3] = &USBHAL::EP2_IN_callback;
epCallback[4] = &USBHAL::EP3_OUT_callback;
epCallback[5] = &USBHAL::EP3_IN_callback;
// Enable power and clocking
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
pin_function(PA_8, STM_PIN_DATA(2, 10));
pin_function(PA_9, STM_PIN_DATA(0, 0));
pin_function(PA_10, STM_PIN_DATA(2, 10));
pin_function(PA_11, STM_PIN_DATA(2, 10));
pin_function(PA_12, STM_PIN_DATA(2, 10));
// Set ID pin to open drain with pull-up resistor
pin_mode(PA_10, OpenDrain);
GPIOA->PUPDR &= ~(0x3 << 20);
GPIOA->PUPDR |= 1 << 20;
// Set VBUS pin to open drain
pin_mode(PA_9, OpenDrain);
RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
// Enable interrupts
OTG_FS->GREGS.GAHBCFG |= (1 << 0);
// Turnaround time to maximum value - too small causes packet loss
OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
// Unmask global interrupts
OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
(1 << 4) | // RX FIFO not empty
(1 << 12); // USB reset
OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
(1 << 2); // Non-zero-length status OUT handshake
OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
(1 << 16); // Power Up
instance = this;
NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
NVIC_SetPriority(OTG_FS_IRQn, 1);
}
USBHAL::~USBHAL(void) {
}
void USBHAL::connect(void) {
NVIC_EnableIRQ(OTG_FS_IRQn);
}
void USBHAL::disconnect(void) {
NVIC_DisableIRQ(OTG_FS_IRQn);
}
void USBHAL::configureDevice(void) {
// Not needed
}
void USBHAL::unconfigureDevice(void) {
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
OTG_FS->DREGS.DCFG |= (address << 4);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
uint32_t flags) {
uint32_t epIndex = endpoint >> 1;
uint32_t type;
switch (endpoint) {
case EP0IN:
case EP0OUT:
type = 0;
break;
case EPISO_IN:
case EPISO_OUT:
type = 1;
case EPBULK_IN:
case EPBULK_OUT:
type = 2;
break;
case EPINT_IN:
case EPINT_OUT:
type = 3;
break;
}
// Generic in or out EP controls
uint32_t control = (maxPacket << 0) | // Packet size
(1 << 15) | // Active endpoint
(type << 18); // Endpoint type
if (endpoint & 0x1) { // In Endpoint
// Set up the Tx FIFO
if (endpoint == EP0IN) {
OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
else {
OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
(bufferEnd << 0);
}
bufferEnd += maxPacket >> 2;
// Set the In EP specific control settings
if (endpoint != EP0IN) {
control |= (1 << 28); // SD0PID
}
control |= (epIndex << 22) | // TxFIFO index
(1 << 27); // SNAK
OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
}
else { // Out endpoint
// Set the out EP specific control settings
control |= (1 << 26); // CNAK
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
// Unmask the interrupt
OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
}
return true;
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
}
void USBHAL::EP0readStage(void) {
}
void USBHAL::EP0read(void) {
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
uint32_t* buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
buffer32[i >> 2] = OTG_FS->FIFO[0][0];
}
rxFifoCount = 0;
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
endpointWrite(0, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
}
void USBHAL::EP0stall(void) {
// If we stall the out endpoint here then we have problems transferring
// and setup requests after the (stalled) get device qualifier requests.
// TODO: Find out if this is correct behavior, or whether we are doing
// something else wrong
stallEndpoint(EP0IN);
// stallEndpoint(EP0OUT);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
uint32_t epIndex = endpoint >> 1;
uint32_t size = (1 << 19) | // 1 packet
(maximumSize << 0); // Packet size
// if (endpoint == EP0OUT) {
size |= (1 << 29); // 1 setup packet
// }
OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
(1 << 26); // Clear NAK
epComplete &= ~(1 << endpoint);
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
if (!(epComplete & (1 << endpoint))) {
return EP_PENDING;
}
uint32_t* buffer32 = (uint32_t *) buffer;
uint32_t length = rxFifoCount;
for (uint32_t i = 0; i < length; i += 4) {
buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
}
rxFifoCount = 0;
*bytesRead = length;
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
uint32_t epIndex = endpoint >> 1;
OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
(size << 0); // Size of packet
OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
(1 << 26); // CNAK
OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
}
epComplete &= ~(1 << endpoint);
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
if (epComplete & (1 << endpoint)) {
epComplete &= ~(1 << endpoint);
return EP_COMPLETED;
}
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
if (endpoint & 0x1) { // In EP
OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
else { // Out EP
OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
(1 << 21); // Stall
}
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
return false;
}
void USBHAL::remoteWakeup(void) {
}
void USBHAL::_usbisr(void) {
instance->usbisr();
}
void USBHAL::usbisr(void) {
if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
// Set SNAK bits
OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
OTG_FS->DREGS.DIEPMSK = (1 << 0);
bufferEnd = 0;
// Set the receive FIFO size
OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
bufferEnd += rxFifoSize >> 2;
// Create the endpoints, and wait for setup packets on out EP0
realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
OTG_FS->GREGS.GINTSTS = (1 << 12);
}
if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
uint32_t status = OTG_FS->GREGS.GRXSTSP;
uint32_t endpoint = (status & 0xF) << 1;
uint32_t length = (status >> 4) & 0x7FF;
uint32_t type = (status >> 17) & 0xF;
rxFifoCount = length;
if (type == 0x6) {
// Setup packet
for (uint32_t i=0; i<length; i+=4) {
setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
}
rxFifoCount = 0;
}
if (type == 0x4) {
// Setup complete
EP0setupCallback();
endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
}
if (type == 0x2) {
// Out packet
if (endpoint == EP0OUT) {
EP0out();
}
else {
epComplete |= (1 << endpoint);
if ((instance->*(epCallback[endpoint - 2]))()) {
epComplete &= (1 << endpoint);
}
}
}
for (uint32_t i=0; i<rxFifoCount; i+=4) {
(void) OTG_FS->FIFO[0][0];
}
OTG_FS->GREGS.GINTSTS = (1 << 4);
}
if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
// Loop through the in endpoints
for (uint32_t i=0; i<4; i++) {
if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
// If the Tx FIFO is empty on EP0 we need to send a further
// packet, so call EP0in()
if (i == 0) {
EP0in();
}
// Clear the interrupt
OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
// Stop firing Tx empty interrupts
// Will get turned on again if another write is called
OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
}
// If the transfer is complete
if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
epComplete |= (1 << (1 + (i << 1)));
OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
}
}
}
OTG_FS->GREGS.GINTSTS = (1 << 18);
}
if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
OTG_FS->GREGS.GINTSTS = (1 << 3);
}
}
#endif

149
libraries/USBDevice/USBDevice/USBRegs_STM32.h Normal file
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@ -0,0 +1,149 @@
/**
******************************************************************************
* @file usb_regs.h
* @author MCD Application Team
* @version V2.1.0
* @date 19-March-2012
* @brief hardware registers
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
*
* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
* You may not use this file except in compliance with the License.
* You may obtain a copy of the License at:
*
* http://www.st.com/software_license_agreement_liberty_v2
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
******************************************************************************
*/
#ifndef __USB_OTG_REGS_H__
#define __USB_OTG_REGS_H__
typedef struct //000h
{
__IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
__IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
__IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
__IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
__IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
__IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
__IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
__IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
__IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
__IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
__IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
__IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
uint32_t Reserved30[2]; /* Reserved 030h*/
__IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
__IO uint32_t CID; /* User ID Register 03Ch*/
uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
__IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
__IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
}
USB_OTG_GREGS;
typedef struct // 800h
{
__IO uint32_t DCFG; /* dev Configuration Register 800h*/
__IO uint32_t DCTL; /* dev Control Register 804h*/
__IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
uint32_t Reserved0C; /* Reserved 80Ch*/
__IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
__IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
__IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
__IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
uint32_t Reserved20; /* Reserved 820h*/
uint32_t Reserved9; /* Reserved 824h*/
__IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
__IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
__IO uint32_t DTHRCTL; /* dev thr 830h*/
__IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
}
USB_OTG_DREGS;
typedef struct
{
__IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
__IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
uint32_t Reserved14;
__IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
}
USB_OTG_INEPREGS;
typedef struct
{
__IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
__IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
__IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
uint32_t Reserved14[3];
}
USB_OTG_OUTEPREGS;
typedef struct
{
__IO uint32_t HCFG; /* Host Configuration Register 400h*/
__IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
__IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
uint32_t Reserved40C; /* Reserved 40Ch*/
__IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
__IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
__IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
}
USB_OTG_HREGS;
typedef struct
{
__IO uint32_t HCCHAR;
__IO uint32_t HCSPLT;
__IO uint32_t HCINT;
__IO uint32_t HCINTMSK;
__IO uint32_t HCTSIZ;
uint32_t Reserved[3];
}
USB_OTG_HC_REGS;
typedef struct
{
USB_OTG_GREGS GREGS;
uint32_t RESERVED0[188];
USB_OTG_HREGS HREGS;
uint32_t RESERVED1[9];
__IO uint32_t HPRT;
uint32_t RESERVED2[47];
USB_OTG_HC_REGS HC_REGS[8];
uint32_t RESERVED3[128];
USB_OTG_DREGS DREGS;
uint32_t RESERVED4[50];
USB_OTG_INEPREGS INEP_REGS[4];
uint32_t RESERVED5[96];
USB_OTG_OUTEPREGS OUTEP_REGS[4];
uint32_t RESERVED6[160];
__IO uint32_t PCGCCTL;
uint32_t RESERVED7[127];
__IO uint32_t FIFO[4][1024];
}
USB_OTG_CORE_REGS;
#define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
#define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
#endif //__USB_OTG_REGS_H__
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

26
libraries/USBDevice/USBSerial/USBCDC.cpp
View File

@ -52,6 +52,7 @@ bool USBCDC::USBCallback_request(void) {
break; break;
case CDC_SET_LINE_CODING: case CDC_SET_LINE_CODING:
transfer->remaining = 7; transfer->remaining = 7;
transfer->notify = true;
success = true; success = true;
terminal_connected = true; terminal_connected = true;
break; break;
@ -67,6 +68,31 @@ bool USBCDC::USBCallback_request(void) {
return success; return success;
} }
void USBCDC::USBCallback_requestCompleted(uint8_t *buf, uint32_t length) {
// Request of setting line coding has 7 bytes
if (length != 7) {
return;
}
CONTROL_TRANSFER * transfer = getTransferPtr();
/* Process class-specific requests */
if (transfer->setup.bmRequestType.Type == CLASS_TYPE) {
if (transfer->setup.bRequest == CDC_SET_LINE_CODING) {
if (memcmp(cdc_line_coding, buf, 7)) {
memcpy(cdc_line_coding, buf, 7);
int baud = buf[0] + (buf[1] << 8)
+ (buf[2] << 16) + (buf[3] << 24);
int stop = buf[4];
int bits = buf[6];
int parity = buf[5];
lineCodingChanged(baud, bits, parity, stop);
}
}
}
}
// Called in ISR context // Called in ISR context
// Set configuration. Return false if the // Set configuration. Return false if the

12
libraries/USBDevice/USBSerial/USBCDC.h
View File

@ -99,9 +99,21 @@ protected:
* @returns true if successful * @returns true if successful
*/ */
bool readEP_NB(uint8_t * buffer, uint32_t * size); bool readEP_NB(uint8_t * buffer, uint32_t * size);
/*
* Called by USBCallback_requestCompleted when CDC line coding is changed
* Warning: Called in ISR
*
* @param baud The baud rate
* @param bits The number of bits in a word (5-8)
* @param parity The parity
* @param stop The number of stop bits (1 or 2)
*/
virtual void lineCodingChanged(int baud, int bits, int parity, int stop) {};
protected: protected:
virtual bool USBCallback_request(); virtual bool USBCallback_request();
virtual void USBCallback_requestCompleted(uint8_t *buf, uint32_t length);
virtual bool USBCallback_setConfiguration(uint8_t configuration); virtual bool USBCallback_setConfiguration(uint8_t configuration);
volatile bool terminal_connected; volatile bool terminal_connected;

40
libraries/USBDevice/USBSerial/USBSerial.h
View File

@ -55,7 +55,9 @@ public:
* @param product_release Your preoduct_release (default: 0x0001) * @param product_release Your preoduct_release (default: 0x0001)
* *
*/ */
USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001): USBCDC(vendor_id, product_id, product_release), buf(128){ }; USBSerial(uint16_t vendor_id = 0x1f00, uint16_t product_id = 0x2012, uint16_t product_release = 0x0001): USBCDC(vendor_id, product_id, product_release), buf(128){
settingsChangedCallback = 0;
};
/** /**
@ -79,6 +81,22 @@ public:
* @returns the number of bytes available * @returns the number of bytes available
*/ */
uint8_t available(); uint8_t available();
/** Determine if there is a character available to read
*
* @returns
* 1 if there is a character available to read,
* 0 otherwise
*/
int readable() { return available() ? 1 : 0; }
/** Determine if there is space available to write a character
*
* @returns
* 1 if there is space to write a character,
* 0 otherwise
*/
int writeable() { return 1; } // always return 1, for write operation is blocking
/** /**
* Write a block of data. * Write a block of data.
@ -110,19 +128,33 @@ public:
* *
* @param fptr function pointer * @param fptr function pointer
*/ */
void attach(void (*fn)(void)) { void attach(void (*fptr)(void)) {
if(fn != NULL) { if(fptr != NULL) {
rx.attach(fn); rx.attach(fptr);
} }
} }
/**
* Attach a callback to call when serial's settings are changed.
*
* @param fptr function pointer
*/
void attach(void (*fptr)(int baud, int bits, int parity, int stop)) {
settingsChangedCallback = fptr;
}
protected: protected:
virtual bool EP2_OUT_callback(); virtual bool EP2_OUT_callback();
virtual void lineCodingChanged(int baud, int bits, int parity, int stop){
if (settingsChangedCallback) {
settingsChangedCallback(baud, bits, parity, stop);
}
}
private: private:
FunctionPointer rx; FunctionPointer rx;
CircBuffer<uint8_t> buf; CircBuffer<uint8_t> buf;
void (*settingsChangedCallback)(int baud, int bits, int parity, int stop);
}; };
#endif #endif

62
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_abs_f32.c * Title: arm_abs_f32.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -46,11 +51,12 @@
* Computes the absolute value of a vector on an element-by-element basis. * Computes the absolute value of a vector on an element-by-element basis.
* *
* <pre> * <pre>
* pDst[n] = abs(pSrcA[n]), 0 <= n < blockSize. * pDst[n] = abs(pSrc[n]), 0 <= n < blockSize.
* </pre> * </pre>
* *
* The operation can be done in-place by setting the input and output pointers to the same buffer. * The functions support in-place computation allowing the source and
* There are separate functions for floating-point, Q7, Q15, and Q31 data types. * destination pointers to reference the same memory buffer.
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
*/ */
/** /**
@ -73,7 +79,7 @@ void arm_abs_f32(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t in1, in2, in3, in4; /* temporary variables */ float32_t in1, in2, in3, in4; /* temporary variables */
@ -141,7 +147,7 @@ void arm_abs_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

88
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_abs_q15.c * Title: arm_abs_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -64,7 +69,8 @@ void arm_abs_q15(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
__SIMD32_TYPE *simd;
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -77,6 +83,7 @@ void arm_abs_q15(
/* First part of the processing with loop unrolling. Compute 4 outputs at a time. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
** a second loop below computes the remaining 1 to 3 samples. */ ** a second loop below computes the remaining 1 to 3 samples. */
simd = __SIMD32_CONST(pDst);
while(blkCnt > 0u) while(blkCnt > 0u)
{ {
/* C = |A| */ /* C = |A| */
@ -86,19 +93,17 @@ void arm_abs_q15(
/* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */
#ifndef ARM_MATH_BIG_ENDIAN #ifndef ARM_MATH_BIG_ENDIAN
*simd++ =
*__SIMD32(pDst)++ = __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
__PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)), ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
((in2 > 0) ? in2 : __QSUB16(0, in2)), 16);
#else #else
*__SIMD32(pDst)++ = *simd++ =
__PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)), __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
((in1 > 0) ? in1 : __QSUB16(0, in1)), 16); ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
@ -108,23 +113,24 @@ void arm_abs_q15(
#ifndef ARM_MATH_BIG_ENDIAN #ifndef ARM_MATH_BIG_ENDIAN
*__SIMD32(pDst)++ = *simd++ =
__PKHBT(((in1 > 0) ? in1 : __QSUB16(0, in1)), __PKHBT(((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)),
((in2 > 0) ? in2 : __QSUB16(0, in2)), 16); ((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)), 16);
#else #else
*__SIMD32(pDst)++ = *simd++ =
__PKHBT(((in2 > 0) ? in2 : __QSUB16(0, in2)), __PKHBT(((in2 > 0) ? in2 : (q15_t)__QSUB16(0, in2)),
((in1 > 0) ? in1 : __QSUB16(0, in1)), 16); ((in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1)), 16);
#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ #endif /* #ifndef ARM_MATH_BIG_ENDIAN */
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;
} }
pDst = (q15_t *)simd;
/* If the blockSize is not a multiple of 4, compute any remaining output samples here. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
** No loop unrolling is used. */ ** No loop unrolling is used. */
blkCnt = blockSize % 0x4u; blkCnt = blockSize % 0x4u;
@ -136,7 +142,7 @@ void arm_abs_q15(
in1 = *pSrc++; in1 = *pSrc++;
/* Calculate absolute value of input and then store the result in the destination buffer. */ /* Calculate absolute value of input and then store the result in the destination buffer. */
*pDst++ = (in1 > 0) ? in1 : __QSUB16(0, in1); *pDst++ = (in1 > 0) ? in1 : (q15_t)__QSUB16(0, in1);
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;
@ -164,7 +170,7 @@ void arm_abs_q15(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

65
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_abs_q31.c * Title: arm_abs_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_abs_q31(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
q31_t in; /* Input value */ q31_t in; /* Input value */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t in1, in2, in3, in4; q31_t in1, in2, in3, in4;
@ -85,10 +90,10 @@ void arm_abs_q31(
in3 = *pSrc++; in3 = *pSrc++;
in4 = *pSrc++; in4 = *pSrc++;
*pDst++ = (in1 > 0) ? in1 : __QSUB(0, in1); *pDst++ = (in1 > 0) ? in1 : (q31_t)__QSUB(0, in1);
*pDst++ = (in2 > 0) ? in2 : __QSUB(0, in2); *pDst++ = (in2 > 0) ? in2 : (q31_t)__QSUB(0, in2);
*pDst++ = (in3 > 0) ? in3 : __QSUB(0, in3); *pDst++ = (in3 > 0) ? in3 : (q31_t)__QSUB(0, in3);
*pDst++ = (in4 > 0) ? in4 : __QSUB(0, in4); *pDst++ = (in4 > 0) ? in4 : (q31_t)__QSUB(0, in4);
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;
@ -105,14 +110,14 @@ void arm_abs_q31(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {
/* C = |A| */ /* C = |A| */
/* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */
in = *pSrc++; in = *pSrc++;
*pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); *pDst++ = (in > 0) ? in : ((in == INT32_MIN) ? INT32_MAX : -in);
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;

63
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_abs_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_abs_q7.c * Title: arm_abs_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -69,7 +74,7 @@ void arm_abs_q7(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
q7_t in; /* Input value1 */ q7_t in; /* Input value1 */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t in1, in2, in3, in4; /* temporary input variables */ q31_t in1, in2, in3, in4; /* temporary input variables */
@ -89,22 +94,22 @@ void arm_abs_q7(
in3 = (q31_t) * (pSrc + 2); in3 = (q31_t) * (pSrc + 2);
/* find absolute value */ /* find absolute value */
out1 = (in1 > 0) ? in1 : __QSUB8(0, in1); out1 = (in1 > 0) ? in1 : (q31_t)__QSUB8(0, in1);
/* read input */ /* read input */
in4 = (q31_t) * (pSrc + 3); in4 = (q31_t) * (pSrc + 3);
/* find absolute value */ /* find absolute value */
out2 = (in2 > 0) ? in2 : __QSUB8(0, in2); out2 = (in2 > 0) ? in2 : (q31_t)__QSUB8(0, in2);
/* store result to destination */ /* store result to destination */
*pDst = (q7_t) out1; *pDst = (q7_t) out1;
/* find absolute value */ /* find absolute value */
out3 = (in3 > 0) ? in3 : __QSUB8(0, in3); out3 = (in3 > 0) ? in3 : (q31_t)__QSUB8(0, in3);
/* find absolute value */ /* find absolute value */
out4 = (in4 > 0) ? in4 : __QSUB8(0, in4); out4 = (in4 > 0) ? in4 : (q31_t)__QSUB8(0, in4);
/* store result to destination */ /* store result to destination */
*(pDst + 1) = (q7_t) out2; *(pDst + 1) = (q7_t) out2;
@ -131,7 +136,7 @@ void arm_abs_q7(
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
blkCnt = blockSize; blkCnt = blockSize;
#endif // #define ARM_MATH_CM0 #endif // #define ARM_MATH_CM0_FAMILY
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_add_f32.c * Title: arm_add_f32.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -73,7 +78,7 @@ void arm_add_f32(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */ float32_t inA1, inA2, inA3, inA4; /* temporary input variabels */
@ -127,7 +132,7 @@ void arm_add_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_add_q15.c * Title: arm_add_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_add_q15(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2, inB1, inB2; q31_t inA1, inA2, inB1, inB2;
@ -125,7 +130,7 @@ void arm_add_q15(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_add_q31.c * Title: arm_add_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -67,7 +72,7 @@ void arm_add_q31(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2, inA3, inA4; q31_t inA1, inA2, inA3, inA4;
@ -134,7 +139,7 @@ void arm_add_q31(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_add_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_add_q7.c * Title: arm_add_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_add_q7(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -119,7 +124,7 @@ void arm_add_q7(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

72
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_dot_prod_f32.c * Title: arm_dot_prod_f32.c
@ -11,39 +11,49 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
/** /**
* @ingroup groupMath * @ingroup groupMath
*/ */
/** /**
* @defgroup dot_prod Vector Dot Product * @defgroup dot_prod Vector Dot Product
* *
* Computes the dot product of two vectors. * Computes the dot product of two vectors.
* The vectors are multiplied element-by-element and then summed. * The vectors are multiplied element-by-element and then summed.
*
* <pre>
* sum = pSrcA[0]*pSrcB[0] + pSrcA[1]*pSrcB[1] + ... + pSrcA[blockSize-1]*pSrcB[blockSize-1]
* </pre>
*
* There are separate functions for floating-point, Q7, Q15, and Q31 data types. * There are separate functions for floating-point, Q7, Q15, and Q31 data types.
*/ */
@ -72,7 +82,7 @@ void arm_dot_prod_f32(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
/*loop Unrolling */ /*loop Unrolling */
@ -104,7 +114,7 @@ void arm_dot_prod_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_dot_prod_q15.c * Title: arm_dot_prod_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -70,7 +75,7 @@ void arm_dot_prod_q15(
q63_t sum = 0; /* Temporary result storage */ q63_t sum = 0; /* Temporary result storage */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -123,7 +128,7 @@ void arm_dot_prod_q15(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
/* Store the result in the destination buffer in 34.30 format */ /* Store the result in the destination buffer in 34.30 format */
*result = sum; *result = sum;

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_dot_prod_q31.c * Title: arm_dot_prod_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -72,7 +77,7 @@ void arm_dot_prod_q31(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2, inA3, inA4; q31_t inA1, inA2, inA3, inA4;
@ -116,7 +121,7 @@ void arm_dot_prod_q31(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_dot_prod_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_dot_prod_q7.c * Title: arm_dot_prod_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -71,7 +76,7 @@ void arm_dot_prod_q7(
q31_t sum = 0; /* Temporary variables to store output */ q31_t sum = 0; /* Temporary variables to store output */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -142,7 +147,7 @@ void arm_dot_prod_q7(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
/* Store the result in the destination buffer in 18.14 format */ /* Store the result in the destination buffer in 18.14 format */

58
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_mult_f32.c * Title: arm_mult_f32.c
@ -11,29 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -75,7 +77,7 @@ void arm_mult_f32(
uint32_t blockSize) uint32_t blockSize)
{ {
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t inA1, inA2, inA3, inA4; /* temporary input variables */ float32_t inA1, inA2, inA3, inA4; /* temporary input variables */
@ -154,7 +156,7 @@ void arm_mult_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

58
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_mult_q15.c * Title: arm_mult_q15.c
@ -11,29 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -70,7 +72,7 @@ void arm_mult_q15(
{ {
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2, inB1, inB2; /* temporary input variables */ q31_t inA1, inA2, inB1, inB2; /* temporary input variables */
@ -133,7 +135,7 @@ void arm_mult_q15(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)

58
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_mult_q31.c * Title: arm_mult_q31.c
@ -11,29 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -69,7 +71,7 @@ void arm_mult_q31(
{ {
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2, inA3, inA4; /* temporary input variables */ q31_t inA1, inA2, inA3, inA4; /* temporary input variables */
@ -124,7 +126,7 @@ void arm_mult_q31(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

61
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_mult_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_mult_q7.c * Title: arm_mult_q7.c
@ -11,32 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.5 2010/04/26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* incorporated review comments and updated with latest CMSIS layer * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* Version 0.0.3 2010/03/10 DP * POSSIBILITY OF SUCH DAMAGE.
* Initial version
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -72,7 +71,7 @@ void arm_mult_q7(
{ {
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ q7_t out1, out2, out3, out4; /* Temporary variables to store the product */
@ -109,7 +108,7 @@ void arm_mult_q7(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)

59
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_negate_f32.c * Title: arm_negate_f32.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -47,6 +52,10 @@
* <pre> * <pre>
* pDst[n] = -pSrc[n], 0 <= n < blockSize. * pDst[n] = -pSrc[n], 0 <= n < blockSize.
* </pre> * </pre>
*
* The functions support in-place computation allowing the source and
* destination pointers to reference the same memory buffer.
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
*/ */
/** /**
@ -70,7 +79,7 @@ void arm_negate_f32(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t in1, in2, in3, in4; /* temporary variables */ float32_t in1, in2, in3, in4; /* temporary variables */
@ -119,7 +128,7 @@ void arm_negate_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_negate_q15.c * Title: arm_negate_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -68,7 +73,7 @@ void arm_negate_q15(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
q15_t in; q15_t in;
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -118,7 +123,7 @@ void arm_negate_q15(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

57
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_negate_q31.c * Title: arm_negate_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -65,7 +70,7 @@ void arm_negate_q31(
q31_t in; /* Temporary variable */ q31_t in; /* Temporary variable */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t in1, in2, in3, in4; q31_t in1, in2, in3, in4;
@ -104,7 +109,7 @@ void arm_negate_q31(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
@ -112,7 +117,7 @@ void arm_negate_q31(
/* C = -A */ /* C = -A */
/* Negate and then store the result in the destination buffer. */ /* Negate and then store the result in the destination buffer. */
in = *pSrc++; in = *pSrc++;
*pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_negate_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_negate_q7.c * Title: arm_negate_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -65,7 +70,7 @@ void arm_negate_q7(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
q7_t in; q7_t in;
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t input; /* Input values1-4 */ q31_t input; /* Input values1-4 */
@ -101,7 +106,7 @@ void arm_negate_q7(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

59
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_offset_f32.c * Title: arm_offset_f32.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -47,7 +52,9 @@
* pDst[n] = pSrc[n] + offset, 0 <= n < blockSize. * pDst[n] = pSrc[n] + offset, 0 <= n < blockSize.
* </pre> * </pre>
* *
* There are separate functions for floating-point, Q7, Q15, and Q31 data types. * The functions support in-place computation allowing the source and
* destination pointers to reference the same memory buffer.
* There are separate functions for floating-point, Q7, Q15, and Q31 data types.
*/ */
/** /**
@ -73,7 +80,7 @@ void arm_offset_f32(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t in1, in2, in3, in4; float32_t in1, in2, in3, in4;
@ -140,7 +147,7 @@ void arm_offset_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_offset_q15.c * Title: arm_offset_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_offset_q15(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t offset_packed; /* Offset packed to 32 bit */ q31_t offset_packed; /* Offset packed to 32 bit */
@ -122,7 +127,7 @@ void arm_offset_q15(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_offset_q31.c * Title: arm_offset_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_offset_q31(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t in1, in2, in3, in4; q31_t in1, in2, in3, in4;
@ -126,7 +131,7 @@ void arm_offset_q31(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_offset_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_offset_q7.c * Title: arm_offset_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_offset_q7(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t offset_packed; /* Offset packed to 32 bit */ q31_t offset_packed; /* Offset packed to 32 bit */
@ -121,7 +126,7 @@ void arm_offset_q7(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

58
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_scale_f32.c * Title: arm_scale_f32.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -61,6 +66,9 @@
* <pre> * <pre>
* scale = scaleFract * 2^shift. * scale = scaleFract * 2^shift.
* </pre> * </pre>
*
* The functions support in-place computation allowing the source and destination
* pointers to reference the same memory buffer.
*/ */
/** /**
@ -85,7 +93,7 @@ void arm_scale_f32(
uint32_t blockSize) uint32_t blockSize)
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t in1, in2, in3, in4; /* temporary variabels */ float32_t in1, in2, in3, in4; /* temporary variabels */
@ -143,7 +151,7 @@ void arm_scale_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_scale_q15.c * Title: arm_scale_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -70,7 +75,7 @@ void arm_scale_q15(
int8_t kShift = 15 - shift; /* shift to apply after scaling */ int8_t kShift = 15 - shift; /* shift to apply after scaling */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q15_t in1, in2, in3, in4; q15_t in1, in2, in3, in4;
@ -148,7 +153,7 @@ void arm_scale_q15(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

180
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q31.c
View File

@ -1,62 +1,67 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. May 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_scale_q31.c * Title: arm_scale_q31.c
* *
* Description: Multiplies a Q31 vector by a scalar. * Description: Multiplies a Q31 vector by a scalar.
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
* *
* Version 1.1.0 2012/02/15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* Updated with more optimizations, bug fixes and minor API changes. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Version 1.0.10 2011/7/15 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* Big Endian support added and Merged M0 and M3/M4 Source code. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Version 1.0.3 2010/11/29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* Re-organized the CMSIS folders and updated documentation. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Version 1.0.2 2010/11/11 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* Documentation updated. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* * POSSIBILITY OF SUCH DAMAGE.
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated
*
* Version 0.0.7 2010/06/10
* Misra-C changes done
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
/** /**
* @ingroup groupMath * @ingroup groupMath
*/ */
/** /**
* @addtogroup scale * @addtogroup scale
* @{ * @{
*/ */
/** /**
* @brief Multiplies a Q31 vector by a scalar. * @brief Multiplies a Q31 vector by a scalar.
* @param[in] *pSrc points to the input vector * @param[in] *pSrc points to the input vector
* @param[in] scaleFract fractional portion of the scale value * @param[in] scaleFract fractional portion of the scale value
* @param[in] shift number of bits to shift the result by * @param[in] shift number of bits to shift the result by
* @param[out] *pDst points to the output vector * @param[out] *pDst points to the output vector
* @param[in] blockSize number of samples in the vector * @param[in] blockSize number of samples in the vector
* @return none. * @return none.
* *
* <b>Scaling and Overflow Behavior:</b> * <b>Scaling and Overflow Behavior:</b>
* \par * \par
* The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format. * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.31 format.
* These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.
*/ */
void arm_scale_q31( void arm_scale_q31(
@ -71,7 +76,7 @@ void arm_scale_q31(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
q31_t in, out; q31_t in, out;
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -84,7 +89,7 @@ void arm_scale_q31(
if(sign == 0u) if(sign == 0u)
{ {
/* First part of the processing with loop unrolling. Compute 4 outputs at a time. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
** a second loop below computes the remaining 1 to 3 samples. */ ** a second loop below computes the remaining 1 to 3 samples. */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {
@ -138,9 +143,7 @@ void arm_scale_q31(
} }
else else
{ {
kShift = -kShift; /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
/* First part of the processing with loop unrolling. Compute 4 outputs at a time.
** a second loop below computes the remaining 1 to 3 samples. */ ** a second loop below computes the remaining 1 to 3 samples. */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {
@ -157,11 +160,11 @@ void arm_scale_q31(
in4 = ((q63_t) in4 * scaleFract) >> 32; in4 = ((q63_t) in4 * scaleFract) >> 32;
/* apply shifting */ /* apply shifting */
out1 = in1 >> kShift; out1 = in1 >> -kShift;
out2 = in2 >> kShift; out2 = in2 >> -kShift;
out3 = in3 >> kShift; out3 = in3 >> -kShift;
out4 = in4 >> kShift; out4 = in4 >> -kShift;
/* Store result destination */ /* Store result destination */
*pDst = out1; *pDst = out1;
@ -178,46 +181,59 @@ void arm_scale_q31(
blkCnt--; blkCnt--;
} }
} }
/* If the blockSize is not a multiple of 4, compute any remaining output samples here. /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
** No loop unrolling is used. */ ** No loop unrolling is used. */
blkCnt = blockSize % 0x4u; blkCnt = blockSize % 0x4u;
#else #else
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
if(sign != 0u)
kShift = -kShift;
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) if(sign == 0)
{ {
/* C = A * scale */ while(blkCnt > 0u)
/* Scale the input and then store the result in the destination buffer. */ {
in = *pSrc++; /* C = A * scale */
in = ((q63_t) in * scaleFract) >> 32; /* Scale the input and then store the result in the destination buffer. */
in = *pSrc++;
in = ((q63_t) in * scaleFract) >> 32;
if(sign == 0) out = in << kShift;
{
out = in << kShift; if(in != (out >> kShift))
if(in != (out >> kShift)) out = 0x7FFFFFFF ^ (in >> 31);
out = 0x7FFFFFFF ^ (in >> 31);
}
else
{
out = in >> kShift;
}
*pDst++ = out; *pDst++ = out;
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;
}
}
else
{
while(blkCnt > 0u)
{
/* C = A * scale */
/* Scale the input and then store the result in the destination buffer. */
in = *pSrc++;
in = ((q63_t) in * scaleFract) >> 32;
out = in >> -kShift;
*pDst++ = out;
/* Decrement the loop counter */
blkCnt--;
}
} }
} }
/** /**
* @} end of scale group * @} end of scale group
*/ */

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_scale_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_scale_q7.c * Title: arm_scale_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -69,7 +74,7 @@ void arm_scale_q7(
int8_t kShift = 7 - shift; /* shift to apply after scaling */ int8_t kShift = 7 - shift; /* shift to apply after scaling */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */
@ -135,7 +140,7 @@ void arm_scale_q7(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_shift_q15.c * Title: arm_shift_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -67,7 +72,7 @@ void arm_shift_q15(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
uint8_t sign; /* Sign of shiftBits */ uint8_t sign; /* Sign of shiftBits */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -234,7 +239,7 @@ void arm_shift_q15(
} }
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

58
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_shift_q31.c * Title: arm_shift_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -51,6 +56,9 @@
* *
* If <code>shift</code> is positive then the elements of the vector are shifted to the left. * If <code>shift</code> is positive then the elements of the vector are shifted to the left.
* If <code>shift</code> is negative then the elements of the vector are shifted to the right. * If <code>shift</code> is negative then the elements of the vector are shifted to the right.
*
* The functions support in-place computation allowing the source and destination
* pointers to reference the same memory buffer.
*/ */
/** /**
@ -82,7 +90,7 @@ void arm_shift_q31(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */ uint8_t sign = (shiftBits & 0x80); /* Sign of shiftBits */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
q31_t in1, in2, in3, in4; /* Temporary input variables */ q31_t in1, in2, in3, in4; /* Temporary input variables */
q31_t out1, out2, out3, out4; /* Temporary output variables */ q31_t out1, out2, out3, out4; /* Temporary output variables */
@ -173,7 +181,7 @@ void arm_shift_q31(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_shift_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_shift_q7.c * Title: arm_shift_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -72,7 +77,7 @@ void arm_shift_q7(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
uint8_t sign; /* Sign of shiftBits */ uint8_t sign; /* Sign of shiftBits */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q7_t in1; /* Input value1 */ q7_t in1; /* Input value1 */
@ -207,7 +212,7 @@ void arm_shift_q7(
} }
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }
/** /**

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sub_f32.c * Title: arm_sub_f32.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -74,7 +79,7 @@ void arm_sub_f32(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t inA1, inA2, inA3, inA4; /* temporary variables */ float32_t inA1, inA2, inA3, inA4; /* temporary variables */
@ -127,7 +132,7 @@ void arm_sub_f32(
/* Initialize blkCnt with number of samples */ /* Initialize blkCnt with number of samples */
blkCnt = blockSize; blkCnt = blockSize;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sub_q15.c * Title: arm_sub_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -67,7 +72,7 @@ void arm_sub_q15(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2; q31_t inA1, inA2;
@ -125,7 +130,7 @@ void arm_sub_q15(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sub_q31.c * Title: arm_sub_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -67,7 +72,7 @@ void arm_sub_q31(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inA1, inA2, inA3, inA4; q31_t inA1, inA2, inA3, inA4;
@ -132,7 +137,7 @@ void arm_sub_q31(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

55
libraries/dsp/cmsis_dsp/BasicMathFunctions/arm_sub_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sub_q7.c * Title: arm_sub_q7.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -66,7 +71,7 @@ void arm_sub_q7(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -116,7 +121,7 @@ void arm_sub_q7(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

15580
libraries/dsp/cmsis_dsp/CommonTables/arm_common_tables.c
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File diff suppressed because it is too large Load Diff

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_conj_f32.c * Title: arm_cmplx_conj_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -78,7 +86,7 @@ void arm_cmplx_conj_f32(
{ {
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t inR1, inR2, inR3, inR4; float32_t inR1, inR2, inR3, inR4;
@ -155,7 +163,7 @@ void arm_cmplx_conj_f32(
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
blkCnt = numSamples; blkCnt = numSamples;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_conj_q15.c * Title: arm_cmplx_conj_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -60,7 +68,7 @@ void arm_cmplx_conj_q15(
uint32_t numSamples) uint32_t numSamples)
{ {
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -144,7 +152,7 @@ void arm_cmplx_conj_q15(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

54
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_conj_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_conj_q31.c * Title: arm_cmplx_conj_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -61,7 +69,7 @@ void arm_cmplx_conj_q31(
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
q31_t in; /* Input value */ q31_t in; /* Input value */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */ q31_t inR1, inR2, inR3, inR4; /* Temporary real variables */
@ -151,7 +159,7 @@ void arm_cmplx_conj_q31(
blkCnt = numSamples; blkCnt = numSamples;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {
@ -160,7 +168,7 @@ void arm_cmplx_conj_q31(
/* Saturated to 0x7fffffff if the input is -1(0x80000000) */ /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
*pDst++ = *pSrc++; *pDst++ = *pSrc++;
in = *pSrc++; in = *pSrc++;
*pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; *pDst++ = (in == INT32_MIN) ? INT32_MAX : -in;
/* Decrement the loop counter */ /* Decrement the loop counter */
blkCnt--; blkCnt--;

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_dot_prod_f32.c * Title: arm_cmplx_dot_prod_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -86,7 +94,7 @@ void arm_cmplx_dot_prod_f32(
{ {
float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */ float32_t real_sum = 0.0f, imag_sum = 0.0f; /* Temporary result storage */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -148,7 +156,7 @@ void arm_cmplx_dot_prod_f32(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
/* Store the real and imaginary results in the destination buffers */ /* Store the real and imaginary results in the destination buffers */
*realResult = real_sum; *realResult = real_sum;

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_dot_prod_q15.c * Title: arm_cmplx_dot_prod_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -68,7 +76,7 @@ void arm_cmplx_dot_prod_q15(
{ {
q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -130,7 +138,7 @@ void arm_cmplx_dot_prod_q15(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
/* Store the real and imaginary results in 8.24 format */ /* Store the real and imaginary results in 8.24 format */
/* Convert real data in 34.30 to 8.24 by 6 right shifts */ /* Convert real data in 34.30 to 8.24 by 6 right shifts */

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_dot_prod_q31.c * Title: arm_cmplx_dot_prod_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -69,7 +77,7 @@ void arm_cmplx_dot_prod_q31(
{ {
q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */ q63_t real_sum = 0, imag_sum = 0; /* Temporary result storage */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -133,7 +141,7 @@ void arm_cmplx_dot_prod_q31(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
/* Store the real and imaginary results in 16.48 format */ /* Store the real and imaginary results in 16.48 format */
*realResult = real_sum; *realResult = real_sum;

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mag_f32.c * Title: arm_cmplx_mag_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -80,7 +88,7 @@ void arm_cmplx_mag_f32(
{ {
float32_t realIn, imagIn; /* Temporary variables to hold input values */ float32_t realIn, imagIn; /* Temporary variables to hold input values */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -148,7 +156,7 @@ void arm_cmplx_mag_f32(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mag_q15.c * Title: arm_cmplx_mag_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -61,7 +69,7 @@ void arm_cmplx_mag_q15(
{ {
q31_t acc0, acc1; /* Accumulators */ q31_t acc0, acc1; /* Accumulators */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -136,7 +144,7 @@ void arm_cmplx_mag_q15(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mag_q31.c * Title: arm_cmplx_mag_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -63,7 +71,7 @@ void arm_cmplx_mag_q31(
q31_t acc0, acc1; /* Accumulators */ q31_t acc0, acc1; /* Accumulators */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */ q31_t real1, real2, imag1, imag2; /* Temporary variables to hold input values */
@ -155,7 +163,7 @@ void arm_cmplx_mag_q31(
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
blkCnt = numSamples; blkCnt = numSamples;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mag_squared_f32.c * Title: arm_cmplx_mag_squared_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -81,7 +89,7 @@ void arm_cmplx_mag_squared_f32(
float32_t real, imag; /* Temporary variables to store real and imaginary values */ float32_t real, imag; /* Temporary variables to store real and imaginary values */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */ float32_t real1, real2, real3, real4; /* Temporary variables to hold real values */
float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */ float32_t imag1, imag2, imag3, imag4; /* Temporary variables to hold imaginary values */
float32_t mul1, mul2, mul3, mul4; /* Temporary variables */ float32_t mul1, mul2, mul3, mul4; /* Temporary variables */
@ -185,7 +193,7 @@ void arm_cmplx_mag_squared_f32(
blkCnt = numSamples; blkCnt = numSamples;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mag_squared_q15.c * Title: arm_cmplx_mag_squared_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -60,7 +68,7 @@ void arm_cmplx_mag_squared_q15(
{ {
q31_t acc0, acc1; /* Accumulators */ q31_t acc0, acc1; /* Accumulators */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -131,7 +139,7 @@ void arm_cmplx_mag_squared_q15(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mag_squared_q31.c * Title: arm_cmplx_mag_squared_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------- */ * ---------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -63,7 +71,7 @@ void arm_cmplx_mag_squared_q31(
q31_t real, imag; /* Temporary variables to store real and imaginary values */ q31_t real, imag; /* Temporary variables to store real and imaginary values */
q31_t acc0, acc1; /* Accumulators */ q31_t acc0, acc1; /* Accumulators */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counter */ uint32_t blkCnt; /* loop counter */
@ -144,7 +152,7 @@ void arm_cmplx_mag_squared_q31(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mult_cmplx_f32.c * Title: arm_cmplx_mult_cmplx_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -81,7 +89,7 @@ void arm_cmplx_mult_cmplx_f32(
float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */ float32_t a1, b1, c1, d1; /* Temporary variables to store real and imaginary values */
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */ float32_t a2, b2, c2, d2; /* Temporary variables to store real and imaginary values */
@ -174,7 +182,7 @@ void arm_cmplx_mult_cmplx_f32(
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
blkCnt = numSamples; blkCnt = numSamples;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mult_cmplx_q15.c * Title: arm_cmplx_mult_cmplx_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -62,7 +70,7 @@ void arm_cmplx_mult_cmplx_q15(
{ {
q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */ q15_t a, b, c, d; /* Temporary variables to store real and imaginary values */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
@ -176,7 +184,7 @@ void arm_cmplx_mult_cmplx_q15(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mult_cmplx_q31.c * Title: arm_cmplx_mult_cmplx_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -67,7 +75,7 @@ void arm_cmplx_mult_cmplx_q31(
q31_t mul1, mul2, mul3, mul4; q31_t mul1, mul2, mul3, mul4;
q31_t out1, out2; q31_t out1, out2;
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -309,7 +317,7 @@ void arm_cmplx_mult_cmplx_q31(
blkCnt--; blkCnt--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mult_real_f32.c * Title: arm_cmplx_mult_real_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -83,7 +91,7 @@ void arm_cmplx_mult_real_f32(
float32_t in; /* Temporary variable to store input value */ float32_t in; /* Temporary variable to store input value */
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */ float32_t inA1, inA2, inA3, inA4; /* Temporary variables to hold input data */
@ -196,7 +204,7 @@ void arm_cmplx_mult_real_f32(
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
blkCnt = numSamples; blkCnt = numSamples;
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
while(blkCnt > 0u) while(blkCnt > 0u)
{ {

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mult_real_q15.c * Title: arm_cmplx_mult_real_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -64,7 +72,7 @@ void arm_cmplx_mult_real_q15(
{ {
q15_t in; /* Temporary variable to store input value */ q15_t in; /* Temporary variable to store input value */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
@ -186,7 +194,7 @@ void arm_cmplx_mult_real_q15(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cmplx_mult_real_q31.c * Title: arm_cmplx_mult_real_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -64,7 +72,7 @@ void arm_cmplx_mult_real_q31(
{ {
q31_t inA1; /* Temporary variable to store input value */ q31_t inA1; /* Temporary variable to store input value */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
uint32_t blkCnt; /* loop counters */ uint32_t blkCnt; /* loop counters */
@ -206,7 +214,7 @@ void arm_cmplx_mult_real_q31(
numSamples--; numSamples--;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

48
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_pid_init_f32.c * Title: arm_pid_init_f32.c
@ -12,23 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ------------------------------------------------------------------- */ * ------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

52
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_pid_init_q15.c * Title: arm_pid_init_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -55,7 +63,7 @@ void arm_pid_init_q15(
int32_t resetStateFlag) int32_t resetStateFlag)
{ {
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -105,7 +113,7 @@ void arm_pid_init_q15(
memset(S->state, 0, 3u * sizeof(q15_t)); memset(S->state, 0, 3u * sizeof(q15_t));
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

52
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_init_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_pid_init_q31.c * Title: arm_pid_init_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ------------------------------------------------------------------- */ * ------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -55,7 +63,7 @@ void arm_pid_init_q31(
int32_t resetStateFlag) int32_t resetStateFlag)
{ {
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -80,7 +88,7 @@ void arm_pid_init_q31(
temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd); temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp); S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
/* Derived coefficient A2 */ /* Derived coefficient A2 */
S->A2 = S->Kd; S->A2 = S->Kd;

48
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_pid_reset_f32.c * Title: arm_pid_reset_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ------------------------------------------------------------------- */ * ------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

48
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_pid_reset_q15.c * Title: arm_pid_reset_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

48
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_pid_reset_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_pid_reset_q31.c * Title: arm_pid_reset_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ------------------------------------------------------------------- */ * ------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

48
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sin_cos_f32.c * Title: arm_sin_cos_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

56
libraries/dsp/cmsis_dsp/ControllerFunctions/arm_sin_cos_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sin_cos_q31.c * Title: arm_sin_cos_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -272,7 +280,7 @@ void arm_sin_cos_q31(
q31_t x0; /* Nearest input value */ q31_t x0; /* Nearest input value */
q31_t y0, y1; /* Nearest output values */ q31_t y0, y1; /* Nearest output values */
q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */ q31_t xSpacing = INPUT_SPACING; /* Spaing between inputs */
int32_t i; /* Index */ uint32_t i; /* Index */
q31_t oneByXSpacing; /* 1/ xSpacing value */ q31_t oneByXSpacing; /* 1/ xSpacing value */
q31_t out; /* temporary variable */ q31_t out; /* temporary variable */
uint32_t sign_bits; /* No.of sign bits */ uint32_t sign_bits; /* No.of sign bits */
@ -282,11 +290,7 @@ void arm_sin_cos_q31(
i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing; i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
/* Checking min and max index of table */ /* Checking min and max index of table */
if(i < 0) if(i >= 359)
{
i = 0;
}
else if(i >= 359)
{ {
i = 358; i = 358;
} }

56
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cos_f32.c * Title: arm_cos_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -43,7 +51,8 @@
* Q15, Q31, and floating-point data types. * Q15, Q31, and floating-point data types.
* The input to the floating-point version is in radians while the * The input to the floating-point version is in radians while the
* fixed-point Q15 and Q31 have a scaled input with the range * fixed-point Q15 and Q31 have a scaled input with the range
* [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi. * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
* value of 2*pi wraps around to 0.
* *
* The implementation is based on table lookup using 256 values together with cubic interpolation. * The implementation is based on table lookup using 256 values together with cubic interpolation.
* The steps used are: * The steps used are:
@ -77,9 +86,10 @@
/** /**
* \par * \par
* <b>Example code for Generation of Cos Table:</b> * <b>Example code for Generation of Cos Table:</b>
* <pre>
* tableSize = 256; * tableSize = 256;
* <pre>for(n = -1; n < (tableSize + 2); n++) * for(n = -1; n < (tableSize + 2); n++)
* { * {
* cosTable[n+1]= cos(2*pi*n/tableSize); * cosTable[n+1]= cos(2*pi*n/tableSize);
* } </pre> * } </pre>

81
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cos_q15.c * Title: arm_cos_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -43,21 +51,21 @@
/** /**
* \par * \par
* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps * Table values are in Q15 (1.15 fixed-point format) and generation is done in
* \par * three steps. First, generate cos values in floating point:
* First Generate cos values in floating point: * <pre>
* tableSize = 256; * tableSize = 256;
* <pre>for(n = -1; n < (tableSize + 1); n++) * for(n = -1; n < (tableSize + 1); n++)
* { * {
* cosTable[n+1]= cos(2*pi*n/tableSize); * cosTable[n+1]= cos(2*pi*n/tableSize);
* }</pre> * } </pre>
* where pi value is 3.14159265358979 * where pi value is 3.14159265358979
* \par * \par
* Secondly Convert Floating point to Q15(Fixed point): * Second, convert floating-point to Q15 (fixed-point):
* (cosTable[i] * pow(2, 15)) * (cosTable[i] * pow(2, 15))
* \par * \par
* Finally Rounding to nearest integer is done * Finally, round to the nearest integer value:
* cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); * cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
*/ */
static const q15_t cosTableQ15[259] = { static const q15_t cosTableQ15[259] = {
@ -102,7 +110,8 @@ static const q15_t cosTableQ15[259] = {
* @param[in] x Scaled input value in radians. * @param[in] x Scaled input value in radians.
* @return cos(x). * @return cos(x).
* *
* The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian
* value in the range [0 2*pi).
*/ */
q15_t arm_cos_q15( q15_t arm_cos_q15(

62
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_cos_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_cos_q31.c * Title: arm_cos_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -43,19 +51,20 @@
/** /**
* \par * \par
* Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps * Table values are in Q31 (1.31 fixed-point format) and generation is done in
* First Generate cos values in floating point: * three steps. First, generate cos values in floating point:
* <pre>
* tableSize = 256; * tableSize = 256;
* <pre>for(n = -1; n < (tableSize + 1); n++) * for(n = -1; n < (tableSize + 1); n++)
* { * {
* cosTable[n+1]= cos(2*pi*n/tableSize); * cosTable[n+1]= cos(2*pi*n/tableSize);
* } </pre> * } </pre>
* where pi value is 3.14159265358979 * where pi value is 3.14159265358979
* \par * \par
* Secondly Convert Floating point to Q31(Fixed point): * Second, convert floating-point to Q31 (Fixed point):
* (cosTable[i] * pow(2, 31)) * (cosTable[i] * pow(2, 31))
* \par * \par
* Finally Rounding to nearest integer is done * Finally, round to the nearest integer value:
* cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5); * cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);
*/ */
@ -133,7 +142,8 @@ static const q31_t cosTableQ31[259] = {
* @param[in] x Scaled input value in radians. * @param[in] x Scaled input value in radians.
* @return cos(x). * @return cos(x).
* *
* The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian
* value in the range [0 2*pi).
*/ */
q31_t arm_cos_q31( q31_t arm_cos_q31(

56
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sin_f32.c * Title: arm_sin_f32.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -44,7 +52,8 @@
* Q15, Q31, and floating-point data types. * Q15, Q31, and floating-point data types.
* The input to the floating-point version is in radians while the * The input to the floating-point version is in radians while the
* fixed-point Q15 and Q31 have a scaled input with the range * fixed-point Q15 and Q31 have a scaled input with the range
* [0 +0.9999] mapping to [0 2*pi), Where range excludes 2*pi. * [0 +0.9999] mapping to [0 2*pi). The fixed-point range is chosen so that a
* value of 2*pi wraps around to 0.
* *
* The implementation is based on table lookup using 256 values together with cubic interpolation. * The implementation is based on table lookup using 256 values together with cubic interpolation.
* The steps used are: * The steps used are:
@ -78,9 +87,10 @@
/** /**
* \par * \par
* Example code for Generation of Floating-point Sin Table: * Example code for the generation of the floating-point sine table:
* <pre>
* tableSize = 256; * tableSize = 256;
* <pre>for(n = -1; n < (tableSize + 1); n++) * for(n = -1; n < (tableSize + 1); n++)
* { * {
* sinTable[n+1]=sin(2*pi*n/tableSize); * sinTable[n+1]=sin(2*pi*n/tableSize);
* }</pre> * }</pre>

72
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sin_q15.c * Title: arm_sin_q15.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -42,24 +50,24 @@
*/ */
/** /**
* \par * \par
* Example code for Generation of Q15 Sin Table: * Table values are in Q15 (1.15 fixed-point format) and generation is done in
* \par * three steps. First, generate sin values in floating point:
* <pre>tableSize = 256; * <pre>
* tableSize = 256;
* for(n = -1; n < (tableSize + 1); n++) * for(n = -1; n < (tableSize + 1); n++)
* { * {
* sinTable[n+1]=sin(2*pi*n/tableSize); * sinTable[n+1]= sin(2*pi*n/tableSize);
* } </pre> * } </pre>
* where pi value is 3.14159265358979 * where pi value is 3.14159265358979
* \par * \par
* Convert Floating point to Q15(Fixed point): * Second, convert floating-point to Q15 (fixed-point):
* (sinTable[i] * pow(2, 15)) * (sinTable[i] * pow(2, 15))
* \par * \par
* rounding to nearest integer is done * Finally, round to the nearest integer value:
* sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
*/ */
static const q15_t sinTableQ15[259] = { static const q15_t sinTableQ15[259] = {
0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8, 0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
@ -103,7 +111,7 @@ static const q15_t sinTableQ15[259] = {
* @param[in] x Scaled input value in radians. * @param[in] x Scaled input value in radians.
* @return sin(x). * @return sin(x).
* *
* The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. * The Q15 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi).
*/ */
q15_t arm_sin_q15( q15_t arm_sin_q15(

70
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sin_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sin_q31.c * Title: arm_sin_q31.c
@ -11,23 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -43,19 +51,20 @@
/** /**
* \par * \par
* Tables generated are in Q31(1.31 Fixed point format) * Table values are in Q31 (1.31 fixed-point format) and generation is done in
* Generation of sin values in floating point: * three steps. First, generate sin values in floating point:
* <pre>tableSize = 256; * <pre>
* tableSize = 256;
* for(n = -1; n < (tableSize + 1); n++) * for(n = -1; n < (tableSize + 1); n++)
* { * {
* sinTable[n+1]= sin(2*pi*n/tableSize); * sinTable[n+1]= sin(2*pi*n/tableSize);
* } </pre> * } </pre>
* where pi value is 3.14159265358979 * where pi value is 3.14159265358979
* \par * \par
* Convert Floating point to Q31(Fixed point): * Second, convert floating-point to Q31 (Fixed point):
* (sinTable[i] * pow(2, 31)) * (sinTable[i] * pow(2, 31))
* \par * \par
* rounding to nearest integer is done * Finally, round to the nearest integer value:
* sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5); * sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);
*/ */
@ -129,12 +138,11 @@ static const q31_t sinTableQ31[259] = {
/** /**
* @brief Fast approximation to the trigonometric sine function for Q31 data. * @brief Fast approximation to the trigonometric sine function for Q31 data.
* @param[in] x Scaled input value in radians. * @param[in] x Scaled input value in radians.
* @return sin(x). * @return sin(x).
* *
* The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi), Here range excludes 2*pi. * The Q31 input value is in the range [0 +0.9999] and is mapped to a radian value in the range [0 2*pi). */
*/
q31_t arm_sin_q31( q31_t arm_sin_q31(
q31_t x) q31_t x)

56
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2011 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sqrt_q15.c * Title: arm_sqrt_q15.c
@ -11,15 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.0 2011/03/08 * - Redistributions of source code must retain the above copyright
* Alpha release. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.1 2011/09/30 * notice, this list of conditions and the following disclaimer in
* Beta release. * the documentation and/or other materials provided with the
* * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
#include "arm_common_tables.h" #include "arm_common_tables.h"
@ -38,8 +54,9 @@
* @brief Q15 square root function. * @brief Q15 square root function.
* @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF. * @param[in] in input value. The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
* @param[out] *pOut square root of input value. * @param[out] *pOut square root of input value.
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * @return The function returns ARM_MATH_SUCCESS if the input value is positive
* <code>in</code> is negative value and returns zero output for negative values. * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
* negative inputs, the function returns *pOut = 0.
*/ */
arm_status arm_sqrt_q15( arm_status arm_sqrt_q15(
@ -49,6 +66,11 @@ arm_status arm_sqrt_q15(
q15_t number, temp1, var1, signBits1, half; q15_t number, temp1, var1, signBits1, half;
q31_t bits_val1; q31_t bits_val1;
float32_t temp_float1; float32_t temp_float1;
union
{
q31_t fracval;
float32_t floatval;
} tempconv;
number = in; number = in;
@ -75,11 +97,13 @@ arm_status arm_sqrt_q15(
/*Convert to float */ /*Convert to float */
temp_float1 = number * 3.051757812500000e-005f; temp_float1 = number * 3.051757812500000e-005f;
/*Store as integer */ /*Store as integer */
bits_val1 = *(int *) &temp_float1; tempconv.floatval = temp_float1;
bits_val1 = tempconv.fracval;
/* Subtract the shifted value from the magic number to give intial guess */ /* Subtract the shifted value from the magic number to give intial guess */
bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
/* Store as float */ /* Store as float */
temp_float1 = *(float *) &bits_val1; tempconv.fracval = bits_val1;
temp_float1 = tempconv.floatval;
/* Convert to integer format */ /* Convert to integer format */
var1 = (q31_t) (temp_float1 * 16384); var1 = (q31_t) (temp_float1 * 16384);

56
libraries/dsp/cmsis_dsp/FastMathFunctions/arm_sqrt_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2011 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_sqrt_q31.c * Title: arm_sqrt_q31.c
@ -11,15 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.0 2011/03/08 * - Redistributions of source code must retain the above copyright
* Alpha release. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.1 2011/09/30 * notice, this list of conditions and the following disclaimer in
* Beta release. * the documentation and/or other materials provided with the
* * distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
#include "arm_common_tables.h" #include "arm_common_tables.h"
@ -37,8 +53,9 @@
* @brief Q31 square root function. * @brief Q31 square root function.
* @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. * @param[in] in input value. The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
* @param[out] *pOut square root of input value. * @param[out] *pOut square root of input value.
* @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if * @return The function returns ARM_MATH_SUCCESS if the input value is positive
* <code>in</code> is negative value and returns zero output for negative values. * and ARM_MATH_ARGUMENT_ERROR if the input is negative. For
* negative inputs, the function returns *pOut = 0.
*/ */
arm_status arm_sqrt_q31( arm_status arm_sqrt_q31(
@ -47,6 +64,11 @@ arm_status arm_sqrt_q31(
{ {
q31_t number, temp1, bits_val1, var1, signBits1, half; q31_t number, temp1, bits_val1, var1, signBits1, half;
float32_t temp_float1; float32_t temp_float1;
union
{
q31_t fracval;
float32_t floatval;
} tempconv;
number = in; number = in;
@ -73,11 +95,13 @@ arm_status arm_sqrt_q31(
/*Convert to float */ /*Convert to float */
temp_float1 = number * 4.6566128731e-010f; temp_float1 = number * 4.6566128731e-010f;
/*Store as integer */ /*Store as integer */
bits_val1 = *(int *) &temp_float1; tempconv.floatval = temp_float1;
bits_val1 = tempconv.fracval;
/* Subtract the shifted value from the magic number to give intial guess */ /* Subtract the shifted value from the magic number to give intial guess */
bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess bits_val1 = 0x5f3759df - (bits_val1 >> 1); // gives initial guess
/* Store as float */ /* Store as float */
temp_float1 = *(float *) &bits_val1; tempconv.fracval = bits_val1;
temp_float1 = tempconv.floatval;
/* Convert to integer format */ /* Convert to integer format */
var1 = (q31_t) (temp_float1 * 1073741824); var1 = (q31_t) (temp_float1 * 1073741824);

51
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_32x64_init_q31.c * Title: arm_biquad_cascade_df1_32x64_init_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

58
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
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@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_32x64_q31.c * Title: arm_biquad_cascade_df1_32x64_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -100,6 +105,9 @@
* There is also an associated initialization function which performs the following operations: * There is also an associated initialization function which performs the following operations:
* - Sets the values of the internal structure fields. * - Sets the values of the internal structure fields.
* - Zeros out the values in the state buffer. * - Zeros out the values in the state buffer.
* To do this manually without calling the init function, assign the follow subfields of the instance structure:
* numStages, pCoeffs, postShift, pState. Also set all of the values in pState to zero.
*
* \par * \par
* Use of the initialization function is optional. * Use of the initialization function is optional.
* However, if the initialization function is used, then the instance structure cannot be placed into a const data section. * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
@ -198,7 +206,7 @@ void arm_biquad_cas_df1_32x64_q31(
uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */ uint32_t lShift = 32u - uShift; /* Shift to be applied to the output */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -545,7 +553,7 @@ void arm_biquad_cas_df1_32x64_q31(
} while(--stage); } while(--stage);
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }
/** /**

60
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_f32.c
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@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_f32.c * Title: arm_biquad_cascade_df1_f32.c
@ -12,29 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -104,6 +106,8 @@
* The initialization function performs following operations: * The initialization function performs following operations:
* - Sets the values of the internal structure fields. * - Sets the values of the internal structure fields.
* - Zeros out the values in the state buffer. * - Zeros out the values in the state buffer.
* To do this manually without calling the init function, assign the follow subfields of the instance structure:
* numStages, pCoeffs, pState. Also set all of the values in pState to zero.
* *
* \par * \par
* Use of the initialization function is optional. * Use of the initialization function is optional.
@ -188,7 +192,7 @@ void arm_biquad_cascade_df1_f32(
uint32_t sample, stage = S->numStages; /* loop counters */ uint32_t sample, stage = S->numStages; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -411,7 +415,7 @@ void arm_biquad_cascade_df1_f32(
} while(stage > 0u); } while(stage > 0u);
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

53
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_fast_q15.c * Title: arm_biquad_cascade_df1_fast_q15.c
@ -12,28 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.9 2010/08/16 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Initial version * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

136
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_fast_q31.c * Title: arm_biquad_cascade_df1_fast_q31.c
@ -12,27 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.9 2010/08/27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Initial version * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -76,7 +80,7 @@ void arm_biquad_cascade_df1_fast_q31(
q31_t * pDst, q31_t * pDst,
uint32_t blockSize) uint32_t blockSize)
{ {
q31_t acc; /* accumulator */ q31_t acc = 0; /* accumulator */
q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */ q31_t Xn1, Xn2, Yn1, Yn2; /* Filter state variables */
q31_t b0, b1, b2, a1, a2; /* Filter coefficients */ q31_t b0, b1, b2, a1, a2; /* Filter coefficients */
q31_t *pIn = pSrc; /* input pointer initialization */ q31_t *pIn = pSrc; /* input pointer initialization */
@ -120,15 +124,20 @@ void arm_biquad_cascade_df1_fast_q31(
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
/* acc = b0 * x[n] */ /* acc = b0 * x[n] */
acc = (q31_t) (((q63_t) b1 * Xn1) >> 32); //acc = (q31_t) (((q63_t) b1 * Xn1) >> 32);
mult_32x32_keep32_R(acc, b1, Xn1);
/* acc += b1 * x[n-1] */ /* acc += b1 * x[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b0 * (Xn))) >> 32);
multAcc_32x32_keep32_R(acc, b0, Xn);
/* acc += b[2] * x[n-2] */ /* acc += b[2] * x[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
multAcc_32x32_keep32_R(acc, b2, Xn2);
/* acc += a1 * y[n-1] */ /* acc += a1 * y[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
multAcc_32x32_keep32_R(acc, a1, Yn1);
/* acc += a2 * y[n-2] */ /* acc += a2 * y[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
multAcc_32x32_keep32_R(acc, a2, Yn2);
/* The result is converted to 1.31 , Yn2 variable is reused */ /* The result is converted to 1.31 , Yn2 variable is reused */
Yn2 = acc << shift; Yn2 = acc << shift;
@ -141,15 +150,20 @@ void arm_biquad_cascade_df1_fast_q31(
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
/* acc = b0 * x[n] */ /* acc = b0 * x[n] */
acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32); //acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
mult_32x32_keep32_R(acc, b0, Xn2);
/* acc += b1 * x[n-1] */ /* acc += b1 * x[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
multAcc_32x32_keep32_R(acc, b1, Xn);
/* acc += b[2] * x[n-2] */ /* acc += b[2] * x[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
multAcc_32x32_keep32_R(acc, b2, Xn1);
/* acc += a1 * y[n-1] */ /* acc += a1 * y[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
multAcc_32x32_keep32_R(acc, a1, Yn2);
/* acc += a2 * y[n-2] */ /* acc += a2 * y[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
multAcc_32x32_keep32_R(acc, a2, Yn1);
/* The result is converted to 1.31, Yn1 variable is reused */ /* The result is converted to 1.31, Yn1 variable is reused */
Yn1 = acc << shift; Yn1 = acc << shift;
@ -162,15 +176,20 @@ void arm_biquad_cascade_df1_fast_q31(
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
/* acc = b0 * x[n] */ /* acc = b0 * x[n] */
acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32); //acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
mult_32x32_keep32_R(acc, b0, Xn1);
/* acc += b1 * x[n-1] */ /* acc += b1 * x[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
multAcc_32x32_keep32_R(acc, b1, Xn2);
/* acc += b[2] * x[n-2] */ /* acc += b[2] * x[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
multAcc_32x32_keep32_R(acc, b2, Xn);
/* acc += a1 * y[n-1] */ /* acc += a1 * y[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
multAcc_32x32_keep32_R(acc, a1, Yn1);
/* acc += a2 * y[n-2] */ /* acc += a2 * y[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
multAcc_32x32_keep32_R(acc, a2, Yn2);
/* The result is converted to 1.31, Yn2 variable is reused */ /* The result is converted to 1.31, Yn2 variable is reused */
Yn2 = acc << shift; Yn2 = acc << shift;
@ -184,15 +203,20 @@ void arm_biquad_cascade_df1_fast_q31(
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
/* acc = b0 * x[n] */ /* acc = b0 * x[n] */
acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32); //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
mult_32x32_keep32_R(acc, b0, Xn);
/* acc += b1 * x[n-1] */ /* acc += b1 * x[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
multAcc_32x32_keep32_R(acc, b1, Xn1);
/* acc += b[2] * x[n-2] */ /* acc += b[2] * x[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
multAcc_32x32_keep32_R(acc, b2, Xn2);
/* acc += a1 * y[n-1] */ /* acc += a1 * y[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
multAcc_32x32_keep32_R(acc, a1, Yn2);
/* acc += a2 * y[n-2] */ /* acc += a2 * y[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
multAcc_32x32_keep32_R(acc, a2, Yn1);
/* Every time after the output is computed state should be updated. */ /* Every time after the output is computed state should be updated. */
/* The states should be updated as: */ /* The states should be updated as: */
@ -217,22 +241,28 @@ void arm_biquad_cascade_df1_fast_q31(
** No loop unrolling is used. */ ** No loop unrolling is used. */
sample = (blockSize & 0x3u); sample = (blockSize & 0x3u);
while(sample > 0u) while(sample > 0u)
{ {
/* Read the input */ /* Read the input */
Xn = *pIn++; Xn = *pIn++;
/* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */ /* acc = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
/* acc = b0 * x[n] */ /* acc = b0 * x[n] */
acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32); //acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
mult_32x32_keep32_R(acc, b0, Xn);
/* acc += b1 * x[n-1] */ /* acc += b1 * x[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
multAcc_32x32_keep32_R(acc, b1, Xn1);
/* acc += b[2] * x[n-2] */ /* acc += b[2] * x[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
multAcc_32x32_keep32_R(acc, b2, Xn2);
/* acc += a1 * y[n-1] */ /* acc += a1 * y[n-1] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
multAcc_32x32_keep32_R(acc, a1, Yn1);
/* acc += a2 * y[n-2] */ /* acc += a2 * y[n-2] */
acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32); //acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
multAcc_32x32_keep32_R(acc, a2, Yn2);
/* The result is converted to 1.31 */ /* The result is converted to 1.31 */
acc = acc << shift; acc = acc << shift;
@ -252,7 +282,7 @@ void arm_biquad_cascade_df1_fast_q31(
/* decrement the loop counter */ /* decrement the loop counter */
sample--; sample--;
} }
/* The first stage goes from the input buffer to the output buffer. */ /* The first stage goes from the input buffer to the output buffer. */
/* Subsequent stages occur in-place in the output buffer */ /* Subsequent stages occur in-place in the output buffer */

54
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
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@ -1,8 +1,8 @@
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_init_f32.c * Title: arm_biquad_cascade_df1_init_f32.c
@ -11,29 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------*/ * ---------------------------------------------------------------------------*/
#include "arm_math.h" #include "arm_math.h"

54
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
View File

@ -1,8 +1,8 @@
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_init_q15.c * Title: arm_biquad_cascade_df1_init_q15.c
@ -11,29 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------*/ * ---------------------------------------------------------------------------*/
#include "arm_math.h" #include "arm_math.h"

54
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
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@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_init_q31.c * Title: arm_biquad_cascade_df1_init_q31.c
@ -12,29 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

59
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q15.c
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@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_q15.c * Title: arm_biquad_cascade_df1_q15.c
@ -12,29 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -78,7 +80,7 @@ void arm_biquad_cascade_df1_q15(
{ {
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -327,6 +329,7 @@ void arm_biquad_cascade_df1_q15(
{ {
/* Reading the coefficients */ /* Reading the coefficients */
b0 = *pCoeffs++; b0 = *pCoeffs++;
pCoeffs++; // skip the 0 coefficient
b1 = *pCoeffs++; b1 = *pCoeffs++;
b2 = *pCoeffs++; b2 = *pCoeffs++;
a1 = *pCoeffs++; a1 = *pCoeffs++;
@ -398,7 +401,7 @@ void arm_biquad_cascade_df1_q15(
} while(--stage); } while(--stage);
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

58
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df1_q31.c
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@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df1_q31.c * Title: arm_biquad_cascade_df1_q31.c
@ -12,29 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.5 2010/04/26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* incorporated review comments and updated with latest CMSIS layer * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.3 2010/03/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Initial version * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -88,7 +90,7 @@ void arm_biquad_cascade_df1_q31(
uint32_t sample, stage = S->numStages; /* loop counters */ uint32_t sample, stage = S->numStages; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
q31_t acc_l, acc_h; /* temporary output variables */ q31_t acc_l, acc_h; /* temporary output variables */
@ -392,7 +394,7 @@ void arm_biquad_cascade_df1_q31(
} while(--stage); } while(--stage);
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }
/** /**

596
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
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@ -1,8 +1,7 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df2T_f32.c * Title: arm_biquad_cascade_df2T_f32.c
@ -12,366 +11,349 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
/** /**
* @ingroup groupFilters * @ingroup groupFilters
*/ */
/** /**
* @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure * @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure
* *
* This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure. * This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.
* The filters are implemented as a cascade of second order Biquad sections. * The filters are implemented as a cascade of second order Biquad sections.
* These functions provide a slight memory savings as compared to the direct form I Biquad filter functions. * These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.
* Only floating-point data is supported. * Only floating-point data is supported.
* *
* This function operate on blocks of input and output data and each call to the function * This function operate on blocks of input and output data and each call to the function
* processes <code>blockSize</code> samples through the filter. * processes <code>blockSize</code> samples through the filter.
* <code>pSrc</code> points to the array of input data and * <code>pSrc</code> points to the array of input data and
* <code>pDst</code> points to the array of output data. * <code>pDst</code> points to the array of output data.
* Both arrays contain <code>blockSize</code> values. * Both arrays contain <code>blockSize</code> values.
* *
* \par Algorithm * \par Algorithm
* Each Biquad stage implements a second order filter using the difference equation: * Each Biquad stage implements a second order filter using the difference equation:
* <pre> * <pre>
* y[n] = b0 * x[n] + d1 * y[n] = b0 * x[n] + d1
* d1 = b1 * x[n] + a1 * y[n] + d2 * d1 = b1 * x[n] + a1 * y[n] + d2
* d2 = b2 * x[n] + a2 * y[n] * d2 = b2 * x[n] + a2 * y[n]
* </pre> * </pre>
* where d1 and d2 represent the two state values. * where d1 and d2 represent the two state values.
* *
* \par * \par
* A Biquad filter using a transposed Direct Form II structure is shown below. * A Biquad filter using a transposed Direct Form II structure is shown below.
* \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad" * \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"
* Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients. * Coefficients <code>b0, b1, and b2 </code> multiply the input signal <code>x[n]</code> and are referred to as the feedforward coefficients.
* Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients. * Coefficients <code>a1</code> and <code>a2</code> multiply the output signal <code>y[n]</code> and are referred to as the feedback coefficients.
* Pay careful attention to the sign of the feedback coefficients. * Pay careful attention to the sign of the feedback coefficients.
* Some design tools flip the sign of the feedback coefficients: * Some design tools flip the sign of the feedback coefficients:
* <pre> * <pre>
* y[n] = b0 * x[n] + d1; * y[n] = b0 * x[n] + d1;
* d1 = b1 * x[n] - a1 * y[n] + d2; * d1 = b1 * x[n] - a1 * y[n] + d2;
* d2 = b2 * x[n] - a2 * y[n]; * d2 = b2 * x[n] - a2 * y[n];
* </pre> * </pre>
* In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library. * In this case the feedback coefficients <code>a1</code> and <code>a2</code> must be negated when used with the CMSIS DSP Library.
* *
* \par * \par
* Higher order filters are realized as a cascade of second order sections. * Higher order filters are realized as a cascade of second order sections.
* <code>numStages</code> refers to the number of second order stages used. * <code>numStages</code> refers to the number of second order stages used.
* For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages. * For example, an 8th order filter would be realized with <code>numStages=4</code> second order stages.
* A 9th order filter would be realized with <code>numStages=5</code> second order stages with the * A 9th order filter would be realized with <code>numStages=5</code> second order stages with the
* coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>). * coefficients for one of the stages configured as a first order filter (<code>b2=0</code> and <code>a2=0</code>).
* *
* \par * \par
* <code>pState</code> points to the state variable array. * <code>pState</code> points to the state variable array.
* Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>. * Each Biquad stage has 2 state variables <code>d1</code> and <code>d2</code>.
* The state variables are arranged in the <code>pState</code> array as: * The state variables are arranged in the <code>pState</code> array as:
* <pre> * <pre>
* {d11, d12, d21, d22, ...} * {d11, d12, d21, d22, ...}
* </pre> * </pre>
* where <code>d1x</code> refers to the state variables for the first Biquad and * where <code>d1x</code> refers to the state variables for the first Biquad and
* <code>d2x</code> refers to the state variables for the second Biquad. * <code>d2x</code> refers to the state variables for the second Biquad.
* The state array has a total length of <code>2*numStages</code> values. * The state array has a total length of <code>2*numStages</code> values.
* The state variables are updated after each block of data is processed; the coefficients are untouched. * The state variables are updated after each block of data is processed; the coefficients are untouched.
* *
* \par * \par
* The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II. * The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.
* The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types. * The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.
* That is why the Direct Form I structure supports Q15 and Q31 data types. * That is why the Direct Form I structure supports Q15 and Q31 data types.
* The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>. * The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables <code>d1</code> and <code>d2</code>.
* Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad. * Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.
* The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage. * The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.
* *
* \par Instance Structure * \par Instance Structure
* The coefficients and state variables for a filter are stored together in an instance data structure. * The coefficients and state variables for a filter are stored together in an instance data structure.
* A separate instance structure must be defined for each filter. * A separate instance structure must be defined for each filter.
* Coefficient arrays may be shared among several instances while state variable arrays cannot be shared. * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.
* *
* \par Init Functions * \par Init Functions
* There is also an associated initialization function. * There is also an associated initialization function.
* The initialization function performs following operations: * The initialization function performs following operations:
* - Sets the values of the internal structure fields. * - Sets the values of the internal structure fields.
* - Zeros out the values in the state buffer. * - Zeros out the values in the state buffer.
* * To do this manually without calling the init function, assign the follow subfields of the instance structure:
* \par * numStages, pCoeffs, pState. Also set all of the values in pState to zero.
* Use of the initialization function is optional. *
* However, if the initialization function is used, then the instance structure cannot be placed into a const data section. * \par
* To place an instance structure into a const data section, the instance structure must be manually initialized. * Use of the initialization function is optional.
* Set the values in the state buffer to zeros before static initialization. * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.
* For example, to statically initialize the instance structure use * To place an instance structure into a const data section, the instance structure must be manually initialized.
* <pre> * Set the values in the state buffer to zeros before static initialization.
* arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs}; * For example, to statically initialize the instance structure use
* </pre> * <pre>
* where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer. * arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};
* <code>pCoeffs</code> is the address of the coefficient buffer; * </pre>
* * where <code>numStages</code> is the number of Biquad stages in the filter; <code>pState</code> is the address of the state buffer.
*/ * <code>pCoeffs</code> is the address of the coefficient buffer;
*
*/
/** /**
* @addtogroup BiquadCascadeDF2T * @addtogroup BiquadCascadeDF2T
* @{ * @{
*/ */
/** /**
* @brief Processing function for the floating-point transposed direct form II Biquad cascade filter. * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
* @param[in] *S points to an instance of the filter data structure. * @param[in] *S points to an instance of the filter data structure.
* @param[in] *pSrc points to the block of input data. * @param[in] *pSrc points to the block of input data.
* @param[out] *pDst points to the block of output data * @param[out] *pDst points to the block of output data
* @param[in] blockSize number of samples to process. * @param[in] blockSize number of samples to process.
* @return none. * @return none.
*/ */
LOW_OPTIMIZATION_ENTER
void arm_biquad_cascade_df2T_f32( void arm_biquad_cascade_df2T_f32(
const arm_biquad_cascade_df2T_instance_f32 * S, const arm_biquad_cascade_df2T_instance_f32 * S,
float32_t * pSrc, float32_t * pSrc,
float32_t * pDst, float32_t * pDst,
uint32_t blockSize) uint32_t blockSize)
{ {
float32_t *pIn = pSrc; /* source pointer */ float32_t *pIn = pSrc; /* source pointer */
float32_t *pOut = pDst; /* destination pointer */ float32_t *pOut = pDst; /* destination pointer */
float32_t *pState = S->pState; /* State pointer */ float32_t *pState = S->pState; /* State pointer */
float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */ float32_t *pCoeffs = S->pCoeffs; /* coefficient pointer */
float32_t acc0; /* accumulator */ float32_t acc1; /* accumulator */
float32_t b0, b1, b2, a1, a2; /* Filter coefficients */ float32_t b0, b1, b2, a1, a2; /* Filter coefficients */
float32_t Xn; /* temporary input */ float32_t Xn1; /* temporary input */
float32_t d1, d2; /* state variables */ float32_t d1, d2; /* state variables */
uint32_t sample, stage = S->numStages; /* loop counters */ uint32_t sample, stage = S->numStages; /* loop counters */
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY_FAMILY
float32_t Xn1, Xn2; /* Input State variables */ float32_t Xn2, Xn3, Xn4; /* Input State variables */
float32_t acc1; /* accumulator */ float32_t acc2, acc3, acc4; /* accumulator */
float32_t p0, p1, p2, p3, p4, A1;
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
do do
{ {
/* Reading the coefficients */ /* Reading the coefficients */
b0 = *pCoeffs++; b0 = *pCoeffs++;
b1 = *pCoeffs++; b1 = *pCoeffs++;
b2 = *pCoeffs++; b2 = *pCoeffs++;
a1 = *pCoeffs++; a1 = *pCoeffs++;
a2 = *pCoeffs++; a2 = *pCoeffs++;
/*Reading the state values */ /*Reading the state values */
d1 = pState[0]; d1 = pState[0];
d2 = pState[1]; d2 = pState[1];
/* Apply loop unrolling and compute 4 output values simultaneously. */ /* Apply loop unrolling and compute 4 output values simultaneously. */
sample = blockSize >> 2u; sample = blockSize >> 2u;
/* First part of the processing with loop unrolling. Compute 4 outputs at a time. /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
** a second loop below computes the remaining 1 to 3 samples. */ ** a second loop below computes the remaining 1 to 3 samples. */
while(sample > 0u) while(sample > 0u) {
{
/* y[n] = b0 * x[n] + d1 */ /* y[n] = b0 * x[n] + d1 */
/* d1 = b1 * x[n] + a1 * y[n] + d2 */ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
/* d2 = b2 * x[n] + a2 * y[n] */ /* d2 = b2 * x[n] + a2 * y[n] */
/* Read the first input */ /* Read the four inputs */
Xn1 = *pIn++; Xn1 = pIn[0];
Xn2 = pIn[1];
Xn3 = pIn[2];
Xn4 = pIn[3];
pIn += 4;
/* y[n] = b0 * x[n] + d1 */ p0 = b0 * Xn1;
acc0 = (b0 * Xn1) + d1; p1 = b1 * Xn1;
acc1 = p0 + d1;
p0 = b0 * Xn2;
p3 = a1 * acc1;
p2 = b2 * Xn1;
A1 = p1 + p3;
p4 = a2 * acc1;
d1 = A1 + d2;
d2 = p2 + p4;
/* d1 = b1 * x[n] + d2 */ p1 = b1 * Xn2;
d1 = (b1 * Xn1) + d2; acc2 = p0 + d1;
p0 = b0 * Xn3;
p3 = a1 * acc2;
p2 = b2 * Xn2;
A1 = p1 + p3;
p4 = a2 * acc2;
d1 = A1 + d2;
d2 = p2 + p4;
/* d2 = b2 * x[n] */ p1 = b1 * Xn3;
d2 = (b2 * Xn1); acc3 = p0 + d1;
p0 = b0 * Xn4;
p3 = a1 * acc3;
p2 = b2 * Xn3;
A1 = p1 + p3;
p4 = a2 * acc3;
d1 = A1 + d2;
d2 = p2 + p4;
/* Read the second input */ acc4 = p0 + d1;
Xn2 = *pIn++; p1 = b1 * Xn4;
p3 = a1 * acc4;
p2 = b2 * Xn4;
A1 = p1 + p3;
p4 = a2 * acc4;
d1 = A1 + d2;
d2 = p2 + p4;
/* d1 = b1 * x[n] + a1 * y[n] */ pOut[0] = acc1;
d1 = (a1 * acc0) + d1; pOut[1] = acc2;
pOut[2] = acc3;
pOut[3] = acc4;
pOut += 4;
sample--;
}
/* Store the result in the accumulator in the destination buffer. */ sample = blockSize & 0x3u;
*pOut++ = acc0; while(sample > 0u) {
Xn1 = *pIn++;
d2 = (a2 * acc0) + d2; p0 = b0 * Xn1;
p1 = b1 * Xn1;
acc1 = p0 + d1;
p3 = a1 * acc1;
p2 = b2 * Xn1;
A1 = p1 + p3;
p4 = a2 * acc1;
d1 = A1 + d2;
d2 = p2 + p4;
*pOut++ = acc1;
sample--;
}
/* y[n] = b0 * x[n] + d1 */ /* Store the updated state variables back into the state array */
acc1 = (b0 * Xn2) + d1; *pState++ = d1;
*pState++ = d2;
/* Read the third input */ /* The current stage input is given as the output to the next stage */
Xn1 = *pIn++; pIn = pDst;
d1 = (b1 * Xn2) + d2; /*Reset the output working pointer */
pOut = pDst;
d2 = (b2 * Xn2);
/* Store the result in the accumulator in the destination buffer. */
*pOut++ = acc1;
d1 = (a1 * acc1) + d1;
d2 = (a2 * acc1) + d2;
/* y[n] = b0 * x[n] + d1 */
acc0 = (b0 * Xn1) + d1;
d1 = (b1 * Xn1) + d2;
d2 = (b2 * Xn1);
/* Read the fourth input */
Xn2 = *pIn++;
d1 = (a1 * acc0) + d1;
/* Store the result in the accumulator in the destination buffer. */
*pOut++ = acc0;
d2 = (a2 * acc0) + d2;
/* y[n] = b0 * x[n] + d1 */
acc1 = (b0 * Xn2) + d1;
d1 = (b1 * Xn2) + d2;
d2 = (b2 * Xn2);
/* Store the result in the accumulator in the destination buffer. */
*pOut++ = acc1;
d1 = (a1 * acc1) + d1;
d2 = (a2 * acc1) + d2;
/* decrement the loop counter */ /* decrement the loop counter */
sample--; stage--;
} } while(stage > 0u);
/* If the blockSize is not a multiple of 4, compute any remaining output samples here.
** No loop unrolling is used. */
sample = blockSize & 0x3u;
while(sample > 0u)
{
/* Read the input */
Xn = *pIn++;
/* y[n] = b0 * x[n] + d1 */
acc0 = (b0 * Xn) + d1;
/* Store the result in the accumulator in the destination buffer. */
*pOut++ = acc0;
/* Every time after the output is computed state should be updated. */
/* d1 = b1 * x[n] + a1 * y[n] + d2 */
d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
/* d2 = b2 * x[n] + a2 * y[n] */
d2 = (b2 * Xn) + (a2 * acc0);
/* decrement the loop counter */
sample--;
}
/* Store the updated state variables back into the state array */
*pState++ = d1;
*pState++ = d2;
/* The current stage input is given as the output to the next stage */
pIn = pDst;
/*Reset the output working pointer */
pOut = pDst;
/* decrement the loop counter */
stage--;
} while(stage > 0u);
#else #else
/* Run the below code for Cortex-M0 */ /* Run the below code for Cortex-M0 */
do do
{ {
/* Reading the coefficients */ /* Reading the coefficients */
b0 = *pCoeffs++; b0 = *pCoeffs++;
b1 = *pCoeffs++; b1 = *pCoeffs++;
b2 = *pCoeffs++; b2 = *pCoeffs++;
a1 = *pCoeffs++; a1 = *pCoeffs++;
a2 = *pCoeffs++; a2 = *pCoeffs++;
/*Reading the state values */ /*Reading the state values */
d1 = pState[0]; d1 = pState[0];
d2 = pState[1]; d2 = pState[1];
sample = blockSize; sample = blockSize;
while(sample > 0u) while(sample > 0u)
{ {
/* Read the input */ /* Read the input */
Xn = *pIn++; Xn1 = *pIn++;
/* y[n] = b0 * x[n] + d1 */ /* y[n] = b0 * x[n] + d1 */
acc0 = (b0 * Xn) + d1; acc1 = (b0 * Xn1) + d1;
/* Store the result in the accumulator in the destination buffer. */ /* Store the result in the accumulator in the destination buffer. */
*pOut++ = acc0; *pOut++ = acc1;
/* Every time after the output is computed state should be updated. */ /* Every time after the output is computed state should be updated. */
/* d1 = b1 * x[n] + a1 * y[n] + d2 */ /* d1 = b1 * x[n] + a1 * y[n] + d2 */
d1 = ((b1 * Xn) + (a1 * acc0)) + d2; d1 = ((b1 * Xn1) + (a1 * acc1)) + d2;
/* d2 = b2 * x[n] + a2 * y[n] */ /* d2 = b2 * x[n] + a2 * y[n] */
d2 = (b2 * Xn) + (a2 * acc0); d2 = (b2 * Xn1) + (a2 * acc1);
/* decrement the loop counter */
sample--;
}
/* Store the updated state variables back into the state array */
*pState++ = d1;
*pState++ = d2;
/* The current stage input is given as the output to the next stage */
pIn = pDst;
/*Reset the output working pointer */
pOut = pDst;
/* decrement the loop counter */ /* decrement the loop counter */
sample--; stage--;
}
/* Store the updated state variables back into the state array */ } while(stage > 0u);
*pState++ = d1;
*pState++ = d2;
/* The current stage input is given as the output to the next stage */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
pIn = pDst;
/*Reset the output working pointer */
pOut = pDst;
/* decrement the loop counter */
stage--;
} while(stage > 0u);
#endif /* #ifndef ARM_MATH_CM0 */
} }
LOW_OPTIMIZATION_EXIT
/**
/**
* @} end of BiquadCascadeDF2T group * @} end of BiquadCascadeDF2T group
*/ */

51
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
View File

@ -1,8 +1,8 @@
/*----------------------------------------------------------------------------- /*-----------------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_biquad_cascade_df2T_init_f32.c * Title: arm_biquad_cascade_df2T_init_f32.c
@ -12,26 +12,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.10 2011/7/15 * - Redistributions of source code must retain the above copyright
* Big Endian support added and Merged M0 and M3/M4 Source code. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.3 2010/11/29 * notice, this list of conditions and the following disclaimer in
* Re-organized the CMSIS folders and updated documentation. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.2 2010/11/11 * - Neither the name of ARM LIMITED nor the names of its contributors
* Documentation updated. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.1 2010/10/05 *
* Production release and review comments incorporated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.0 2010/09/20 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 0.0.7 2010/06/10 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Misra-C changes done * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* ---------------------------------------------------------------------------*/ * ---------------------------------------------------------------------------*/
#include "arm_math.h" #include "arm_math.h"

59
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------------- /* ----------------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_f32.c * Title: arm_conv_f32.c
@ -11,30 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.7 2010/06/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Misra-C changes done * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */ * -------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -129,7 +130,7 @@ void arm_conv_f32(
{ {
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -637,7 +638,7 @@ void arm_conv_f32(
pDst[i] = sum; pDst[i] = sum;
} }
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

51
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_opt_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_fast_opt_q15.c * Title: arm_conv_fast_opt_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

49
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_fast_q15.c * Title: arm_conv_fast_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
* *
* Version 1.0.10 2011/7/15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* Big Endian support added and Merged M0 and M3/M4 Source code. * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Version 1.0.3 2010/11/29 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* Re-organized the CMSIS folders and updated documentation. * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Version 1.0.2 2010/11/11 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* Documentation updated. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Version 1.0.1 2010/10/05 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* Production release and review comments incorporated. * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* * POSSIBILITY OF SUCH DAMAGE.
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

51
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_fast_q31.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_fast_q31.c * Title: arm_conv_fast_q31.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

55
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_opt_q15.c * Title: arm_conv_opt_q15.c
@ -11,30 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.7 2010/06/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Misra-C changes done * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

55
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_opt_q7.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_opt_q7.c * Title: arm_conv_opt_q7.c
@ -11,30 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.7 2010/06/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Misra-C changes done * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

59
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_f32.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------------- /* ----------------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_partial_f32.c * Title: arm_conv_partial_f32.c
@ -11,30 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* Version 0.0.7 2010/06/10 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* Misra-C changes done * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------------- */ * -------------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"
@ -102,7 +103,7 @@ arm_status arm_conv_partial_f32(
{ {
#ifndef ARM_MATH_CM0 #ifndef ARM_MATH_CM0_FAMILY
/* Run the below code for Cortex-M4 and Cortex-M3 */ /* Run the below code for Cortex-M4 and Cortex-M3 */
@ -652,7 +653,7 @@ arm_status arm_conv_partial_f32(
} }
return (status); return (status);
#endif /* #ifndef ARM_MATH_CM0 */ #endif /* #ifndef ARM_MATH_CM0_FAMILY */
} }

51
libraries/dsp/cmsis_dsp/FilteringFunctions/arm_conv_partial_fast_opt_q15.c
View File

@ -1,8 +1,8 @@
/* ---------------------------------------------------------------------- /* ----------------------------------------------------------------------
* Copyright (C) 2010 ARM Limited. All rights reserved. * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
* *
* $Date: 15. February 2012 * $Date: 17. January 2013
* $Revision: V1.1.0 * $Revision: V1.4.1
* *
* Project: CMSIS DSP Library * Project: CMSIS DSP Library
* Title: arm_conv_partial_fast_opt_q15.c * Title: arm_conv_partial_fast_opt_q15.c
@ -11,26 +11,31 @@
* *
* Target Processor: Cortex-M4/Cortex-M3 * Target Processor: Cortex-M4/Cortex-M3
* *
* Version 1.1.0 2012/02/15 * Redistribution and use in source and binary forms, with or without
* Updated with more optimizations, bug fixes and minor API changes. * modification, are permitted provided that the following conditions
* * are met:
* Version 1.0.11 2011/10/18 * - Redistributions of source code must retain the above copyright
* Bug Fix in conv, correlation, partial convolution. * notice, this list of conditions and the following disclaimer.
* * - Redistributions in binary form must reproduce the above copyright
* Version 1.0.10 2011/7/15 * notice, this list of conditions and the following disclaimer in
* Big Endian support added and Merged M0 and M3/M4 Source code. * the documentation and/or other materials provided with the
* * distribution.
* Version 1.0.3 2010/11/29 * - Neither the name of ARM LIMITED nor the names of its contributors
* Re-organized the CMSIS folders and updated documentation. * may be used to endorse or promote products derived from this
* * software without specific prior written permission.
* Version 1.0.2 2010/11/11 *
* Documentation updated. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* Version 1.0.1 2010/10/05 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* Production release and review comments incorporated. * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* Version 1.0.0 2010/09/20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* Production release and review comments incorporated. * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */ * -------------------------------------------------------------------- */
#include "arm_math.h" #include "arm_math.h"

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