diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct index 8fd5a3d43d..c6b552dce0 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_ARM/cyb06xxa_cm4.sct @@ -27,6 +27,7 @@ ;******************************************************************************* ;* \copyright ;* Copyright 2016-2020 Cypress Semiconductor Corporation +;* Copyright 2020 Arm Limited ;* SPDX-License-Identifier: Apache-2.0 ;* ;* Licensed under the Apache License, Version 2.0 (the "License"); @@ -42,8 +43,10 @@ ;* limitations under the License. ;******************************************************************************/ +#include "../../../partition/region_defs.h" + #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 + #define MBED_ROM_START NS_CODE_START #endif ;* MBED_APP_START is being used by the bootloader build script and @@ -55,7 +58,7 @@ #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001D0000 + #define MBED_ROM_SIZE NS_CODE_SIZE #endif ;* MBED_APP_SIZE is being used by the bootloader build script and @@ -67,19 +70,19 @@ #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 + #define MBED_RAM_START NS_DATA_START #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000EA000 + #define MBED_RAM_SIZE NS_DATA_SIZE #endif #if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 + #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE #endif -; The size of the stack section at the end of CM4 SRAM -#define STACK_SIZE MBED_BOOT_STACK_SIZE +; Shared memory area between Non-secure and Secure +#define MBED_DATA_SHARED_SIZE NS_DATA_SHARED_SIZE ; The defines below describe the location and size of blocks of memory in the target. ; Use these defines to specify the memory regions available for allocation. @@ -92,9 +95,6 @@ #define FLASH_START MBED_APP_START #define FLASH_SIZE MBED_APP_SIZE -; The size of the MCU boot header area at the start of FLASH -#define BOOT_HEADER_SIZE 0x00000400 - ; The following defines describe a 32K flash region used for EEPROM emulation. ; This region can also be used as the general purpose flash. ; You can assign sections to this memory region for only one of the cores. @@ -136,7 +136,7 @@ ; Cortex-M4 application flash area LR_IROM1 FLASH_START FLASH_SIZE { - ER_FLASH_VECTORS +BOOT_HEADER_SIZE + ER_FLASH_VECTORS +0 { * (RESET, +FIRST) } @@ -166,15 +166,27 @@ LR_IROM1 FLASH_START FLASH_SIZE } ; Application heap area (HEAP) - ARM_LIB_HEAP +0 EMPTY RAM_START+RAM_SIZE-STACK_SIZE-ImageLimit(RW_IRAM1) - { - } - - ; Stack region growing down - ARM_LIB_STACK RAM_START+RAM_SIZE EMPTY -STACK_SIZE + ARM_LIB_HEAP +0 ALIGN 4 EMPTY RAM_START+RAM_SIZE-MBED_BOOT_STACK_SIZE-MBED_DATA_SHARED_SIZE-ImageLimit(RW_IRAM1) { - } - + } + + ; Stack region growing down + ARM_LIB_STACK RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY -MBED_BOOT_STACK_SIZE + { + } + + ; Stack area overflowed within RAM + ScatterAssert(ImageBase(ARM_LIB_STACK) + ImageLength(ARM_LIB_STACK) == RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE) + + ; Shared region + ARM_LIB_SHARED RAM_START+RAM_SIZE-MBED_DATA_SHARED_SIZE ALIGN 4 EMPTY MBED_DATA_SHARED_SIZE + { + } + + ; Shared area overflowed within RAM + ScatterAssert(ImageBase(ARM_LIB_SHARED) + ImageLength(ARM_LIB_SHARED) == RAM_START+RAM_SIZE) + + ; Used for the digital signature of the secure application and the ; Bootloader SDK application. The size of the section depends on the required ; data size. diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld index 6b29f396c3..914ebc35fd 100644 --- a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/TOOLCHAIN_GCC_ARM/cyb06xxa_cm4.ld @@ -20,6 +20,7 @@ ******************************************************************************** * \copyright * Copyright 2016-2020 Cypress Semiconductor Corporation +* Copyright 2020 Arm Limited * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -40,8 +41,10 @@ SEARCH_DIR(.) GROUP(-lgcc -lc -lnosys) ENTRY(Reset_Handler) +#include "../../../partition/region_defs.h" + #if !defined(MBED_ROM_START) - #define MBED_ROM_START 0x10000000 + #define MBED_ROM_START NS_CODE_START #endif /* MBED_APP_START is being used by the bootloader build script and @@ -49,11 +52,11 @@ ENTRY(Reset_Handler) * is equal to MBED_ROM_START */ #if !defined(MBED_APP_START) - #define MBED_APP_START MBED_ROM_START + #define MBED_APP_START MBED_ROM_START #endif #if !defined(MBED_ROM_SIZE) - #define MBED_ROM_SIZE 0x001D0000 + #define MBED_ROM_SIZE NS_CODE_SIZE #endif /* MBED_APP_SIZE is being used by the bootloader build script and @@ -61,26 +64,24 @@ ENTRY(Reset_Handler) * is equal to MBED_ROM_SIZE */ #if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE MBED_ROM_SIZE + #define MBED_APP_SIZE MBED_ROM_SIZE #endif #if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x08000000 + #define MBED_RAM_START NS_DATA_START #endif #if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x000EA000 + #define MBED_RAM_SIZE NS_DATA_SIZE #endif +/* Size of the stack section in CM4 SRAM area */ #if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 + #define MBED_BOOT_STACK_SIZE NS_MSP_STACK_SIZE #endif -/* The size of the stack section at the end of CM4 SRAM */ -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* The size of the MCU boot header area at the start of FLASH */ -BOOT_HEADER_SIZE = 0x400; +/* Shared memory area between Non-Secure and Secure */ +#define MBED_DATA_SHARED_SIZE NS_DATA_SHARED_SIZE /* Force symbol to be entered in the output file as an undefined symbol. Doing * this may, for example, trigger linking of additional modules from standard @@ -157,7 +158,7 @@ GROUP(libgcc.a libc.a libm.a libnosys.a) SECTIONS { /* Cortex-M4 application flash area */ - .text ORIGIN(flash) + BOOT_HEADER_SIZE : + .text ORIGIN(flash) : { /* Cortex-M4 flash vector table */ . = ALIGN(4); @@ -330,20 +331,26 @@ SECTIONS __end__ = .; end = __end__; KEEP(*(.heap*)) - . = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE; + . = ORIGIN(ram) + LENGTH(ram) - MBED_BOOT_STACK_SIZE - MBED_DATA_SHARED_SIZE; + . = ALIGN(4); + __StackLimit = .; __HeapLimit = .; } > ram - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(ram) + LENGTH(ram); - __StackLimit = __StackTop - STACK_SIZE; + __StackTop = (__StackLimit + MBED_BOOT_STACK_SIZE + 3) & 0xFFFFFFFC; PROVIDE(__stack = __StackTop); - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") + .shared __StackTop (NOLOAD): + { + __SharedStart = .; + . += MBED_DATA_SHARED_SIZE; + KEEP(*(.shared*)) + __SharedLimit = .; + } > ram + /* Check if Shared area overflowed within RAM */ + ASSERT(__SharedLimit == ORIGIN(ram) + LENGTH(ram), "Shared area overflowed within RAM") /* Used for the digital signature of the secure application and the Bootloader SDK application. * The size of the section depends on the required data size. */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h new file mode 100644 index 0000000000..b9d720c2e9 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/TARGET_CY8CKIT_064S2_4343W/device/COMPONENT_CM4/device_cfg.h @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2017-2018 Arm Limited + * Copyright (c) 2020, Cypress Semiconductor Corporation. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing software + * distributed under the License is distributed on an "AS IS" BASIS + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __ARM_LTD_DEVICE_CFG_H__ +#define __ARM_LTD_DEVICE_CFG_H__ + +#ifdef TFM_MULTI_CORE_MULTI_CLIENT_CALL +#define NUM_MAILBOX_QUEUE_SLOT 4 +#endif + +#endif /* __ARM_LTD_DEVICE_CFG_H__ */ diff --git a/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/USERAPP_CM4_KEY_PRIV.pem b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/USERAPP_CM4_KEY_PRIV.pem new file mode 100644 index 0000000000..e1f8e15623 --- /dev/null +++ b/targets/TARGET_Cypress/TARGET_PSOC6/sb-tools/keys/USERAPP_CM4_KEY_PRIV.pem @@ -0,0 +1,5 @@ +-----BEGIN PRIVATE KEY----- +MIGHAgEAMBMGByqGSM49AgEGCCqGSM49AwEHBG0wawIBAQQguR/Jq6LjMgp8DVtE +7pKguttNo6L239aEcijzGOr5C72hRANCAAT/NroNASdTGo6bS8r0+C+30YcG0WLV +chWs+99DnOr3SZoalv6/pCNIVrwFv3KkJsmsZUbNNmxeMPr+IlfGGPg0 +-----END PRIVATE KEY-----