mirror of https://github.com/ARMmbed/mbed-os.git
Begin to add can_api.c to LPC11C24 codebase. Not complete yet, which is why it's #if 0ed out. Lots of build errors come up if #if0 isn't there, which is why it is for now.
Matthew Else
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790a71b041
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d29ebefbd9
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@ -0,0 +1,334 @@
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/* mbed Microcontroller Library
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* Copyright (c) 2006-2013 ARM Limited
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "can_api.h"
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#include "cmsis.h"
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#include "pinmap.h"
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#include "error.h"
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#include <math.h>
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#include <string.h>
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#warning (matthewelse) Uses LPC1768 code, and hasn't been ported yet...
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#if 0
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// Type definition to hold a CAN message
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struct CANMsg {
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unsigned int reserved1 : 16;
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unsigned int dlc : 4; // Bits 16..19: DLC - Data Length Counter
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unsigned int reserved0 : 10;
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unsigned int rtr : 1; // Bit 30: Set if this is a RTR message
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unsigned int type : 1; // Bit 31: Set if this is a 29-bit ID message
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unsigned int id; // CAN Message ID (11-bit or 29-bit)
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unsigned char data[8]; // CAN Message Data Bytes 0-7
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};
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typedef struct CANMsg CANMsg;
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static uint32_t can_irq_id = 0;
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static can_irq_handler irq_handler;
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static uint32_t can_disable(can_t *obj) {
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uint32_t sm = LPC_CAN->CNTL;
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LPC_CAN->CNTL |= 1;
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return sm;
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}
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static inline void can_enable(can_t *obj) {
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if (LPC_CAN->CNTL & 1) {
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LPC_CAN->CNTL &= ~(1);
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}
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}
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int can_mode(can_t *obj, CanMode mode)
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{
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return 0; // not implemented
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}
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static inline void can_irq(uint32_t icr, uint32_t index) {
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uint32_t i;
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for(i = 0; i < 8; i++)
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{
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if((can_irq_id != 0) && (icr & (1 << i)))
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{
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switch (i) {
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case 0: irq_handler(can_irq_id, IRQ_RX); break;
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case 1: irq_handler(can_irq_id, IRQ_TX); break;
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case 2: irq_handler(can_irq_id, IRQ_ERROR); break;
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case 3: irq_handler(can_irq_id, IRQ_OVERRUN); break;
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case 4: irq_handler(can_irq_id, IRQ_WAKEUP); break;
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case 5: irq_handler(can_irq_id, IRQ_PASSIVE); break;
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case 6: irq_handler(can_irq_id, IRQ_ARB); break;
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case 7: irq_handler(can_irq_id, IRQ_BUS); break;
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case 8: irq_handler(can_irq_id, IRQ_READY); break;
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}
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}
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}
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}
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// Have to check that the CAN block is active before reading the Interrupt
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// Control Register, or the mbed hangs
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void can_irq_n() {
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uint32_t icr;
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if(LPC_SYSCON->PCONP & (1 << 13)) {
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//icr = LPC_CAN1->ICR & 0x1FF;
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can_irq(icr, 0);
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}
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}
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// Register CAN object's irq handler
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void can_irq_init(can_t *obj, can_irq_handler handler, uint32_t id) {
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irq_handler = handler;
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can_irq_id = id;
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}
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// Unregister CAN object's irq handler
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void can_irq_free(can_t *obj) {
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LPC_CAN->CNTL &= ~(1 << 1); // Disable Interrupts :)
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can_irq_id = 0;
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NVIC_DisableIRQ(CAN_IRQn);
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}
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// Clear or set a irq
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void can_irq_set(can_t *obj, CanIrqType type, uint32_t enable) {
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uint32_t ier;
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switch (type) {
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case IRQ_RX: ier = (1 << 0); break;
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case IRQ_TX: ier = (1 << 1); break;
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case IRQ_ERROR: ier = (1 << 2); break;
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case IRQ_OVERRUN: ier = (1 << 3); break;
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case IRQ_WAKEUP: ier = (1 << 4); break;
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case IRQ_PASSIVE: ier = (1 << 5); break;
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case IRQ_ARB: ier = (1 << 6); break;
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case IRQ_BUS: ier = (1 << 7); break;
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case IRQ_READY: ier = (1 << 8); break;
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default: return;
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}
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// Put CAN in Reset Mode.
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LPC_CAN->CNTL |= 1;
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if(enable == 0) {
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LPC_CAN->CNTL &= ~(1 << ier);
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}
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else {
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LPC_CAN->CNTL &= ~(1 << ier);
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}
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// Take it out of reset...
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LPC_CAN->CNTL &= ~(1);
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// Enable NVIC if at least 1 interrupt is active
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NVIC_SetVector(CAN_IRQn, (uint32_t) &can_irq_n);
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NVIC_EnableIRQ(CAN_IRQn);
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}
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// This table has the sampling points as close to 75% as possible. The first
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// value is TSEG1, the second TSEG2.
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static const int timing_pts[23][2] = {
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{0x0, 0x0}, // 2, 50%
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{0x1, 0x0}, // 3, 67%
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{0x2, 0x0}, // 4, 75%
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{0x3, 0x0}, // 5, 80%
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{0x3, 0x1}, // 6, 67%
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{0x4, 0x1}, // 7, 71%
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{0x5, 0x1}, // 8, 75%
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{0x6, 0x1}, // 9, 78%
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{0x6, 0x2}, // 10, 70%
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{0x7, 0x2}, // 11, 73%
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{0x8, 0x2}, // 12, 75%
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{0x9, 0x2}, // 13, 77%
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{0x9, 0x3}, // 14, 71%
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{0xA, 0x3}, // 15, 73%
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{0xB, 0x3}, // 16, 75%
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{0xC, 0x3}, // 17, 76%
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{0xD, 0x3}, // 18, 78%
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{0xD, 0x4}, // 19, 74%
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{0xE, 0x4}, // 20, 75%
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{0xF, 0x4}, // 21, 76%
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{0xF, 0x5}, // 22, 73%
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{0xF, 0x6}, // 23, 70%
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{0xF, 0x7}, // 24, 67%
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};
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static unsigned int can_speed(unsigned int sclk, unsigned int cclk, unsigned char psjw) {
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#warning (matthewelse) This is the bit that I'm going to have no clue about :P
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uint32_t btr;
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uint16_t brp = 0;
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uint32_t calcbit;
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uint32_t bitwidth;
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int hit = 0;
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int bits;
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#warning the calculation of bitwidth may be wrong...
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bitwidth = sclk / cclk;
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brp = bitwidth / 0x18;
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while ((!hit) && (brp < bitwidth / 4)) {
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brp++;
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for (bits = 22; bits > 0; bits--) {
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calcbit = (bits + 3) * (brp + 1);
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if (calcbit == bitwidth) {
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hit = 1;
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break;
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}
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}
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}
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if (hit) {
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btr = ((timing_pts[bits][1] << 20) & 0x00700000)
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| ((timing_pts[bits][0] << 16) & 0x000F0000)
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| ((psjw << 14) & 0x0000C000)
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| ((brp << 0) & 0x000003FF);
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} else {
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btr = 0xFFFFFFFF;
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}
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return btr;
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}
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void can_init(can_t *obj, PinName rd, PinName td) {
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LPC_SYSCON->SYSAHBCLKCTRL |= 1 << 17;
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obj->index = 0;
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can_reset(obj);
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LPC_CAN->CNTL &= ~(1 << 2); // Disable Interrupts
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can_frequency(obj, 100000);
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// This would be the place to include filter :)
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#warning (matthewelse) This doesn't yet implement filters :(
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}
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void can_free(can_t *obj) {
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LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 17);
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}
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int can_frequency(can_t *obj, int f) {
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int btr = can_speed(SystemCoreClock, (unsigned int)f, 1);
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#if 0
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if (btr > 0) {
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uint32_t modmask = can_disable(obj);
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obj->dev->BTR = btr;
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obj->dev->MOD = modmask;
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return 1;
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} else {
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return 0;
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}
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#endif
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}
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int can_write(can_t *obj, CAN_Message msg, int cc) {
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unsigned int CANStatus;
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CANMsg m;
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can_enable(obj);
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m.id = msg.id ;
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m.dlc = msg.len & 0xF;
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m.rtr = msg.type;
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m.type = msg.format;
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memcpy(m.data, msg.data, msg.len);
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const unsigned int *buf = (const unsigned int *)&m;
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CANStatus = obj->dev->SR;
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if (CANStatus & 0x00000004) {
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obj->dev->TFI1 = buf[0] & 0xC00F0000;
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obj->dev->TID1 = buf[1];
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obj->dev->TDA1 = buf[2];
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obj->dev->TDB1 = buf[3];
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if(cc) {
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obj->dev->CMR = 0x30;
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} else {
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obj->dev->CMR = 0x21;
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}
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return 1;
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} else if (CANStatus & 0x00000400) {
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obj->dev->TFI2 = buf[0] & 0xC00F0000;
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obj->dev->TID2 = buf[1];
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obj->dev->TDA2 = buf[2];
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obj->dev->TDB2 = buf[3];
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if (cc) {
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obj->dev->CMR = 0x50;
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} else {
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obj->dev->CMR = 0x41;
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}
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return 1;
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} else if (CANStatus & 0x00040000) {
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obj->dev->TFI3 = buf[0] & 0xC00F0000;
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obj->dev->TID3 = buf[1];
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obj->dev->TDA3 = buf[2];
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obj->dev->TDB3 = buf[3];
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if (cc) {
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obj->dev->CMR = 0x90;
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} else {
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obj->dev->CMR = 0x81;
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}
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return 1;
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}
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return 0;
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}
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int can_read(can_t *obj, CAN_Message *msg) {
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CANMsg x;
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unsigned int *i = (unsigned int *)&x;
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can_enable(obj);
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if (obj->dev->GSR & 0x1) {
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*i++ = obj->dev->RFS; // Frame
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*i++ = obj->dev->RID; // ID
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*i++ = obj->dev->RDA; // Data A
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*i++ = obj->dev->RDB; // Data B
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obj->dev->CMR = 0x04; // release receive buffer
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msg->id = x.id;
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msg->len = x.dlc;
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msg->format = (x.type)? CANExtended : CANStandard;
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msg->type = (x.rtr)? CANRemote: CANData;
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memcpy(msg->data,x.data,x.dlc);
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return 1;
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}
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return 0;
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}
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void can_reset(can_t *obj) {
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can_disable(obj);
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obj->dev->GSR = 0; // Reset error counter when CAN1MOD is in reset
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}
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unsigned char can_rderror(can_t *obj) {
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return (obj->dev->GSR >> 16) & 0xFF;
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}
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unsigned char can_tderror(can_t *obj) {
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return (obj->dev->GSR >> 24) & 0xFF;
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}
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void can_monitor(can_t *obj, int silent) {
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uint32_t mod_mask = can_disable(obj);
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if (silent) {
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obj->dev->MOD |= (1 << 1);
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} else {
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obj->dev->MOD &= ~(1 << 1);
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}
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if (!(mod_mask & 1)) {
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can_enable(obj);
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}
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}
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#endif
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@ -59,6 +59,10 @@ struct spi_s {
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LPC_SSP_TypeDef *spi;
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};
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struct can_s {
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int index;
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};
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#include "gpio_object.h"
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#ifdef __cplusplus
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