mirror of https://github.com/ARMmbed/mbed-os.git
Apply astyle fix from CI
Lingkai Dong
parent
acfbca7ada
commit
d27ec8272a
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@ -68,9 +68,9 @@ static int8_t rf_extension(phy_extension_type_e extension_type, uint8_t *data_pt
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static void rf_mac_hw_init(void);
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static void rf_mac_ed_state_enable(void);
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static void rf_mac_set_pending(uint8_t status);
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static void rf_mac_set_shortAddress(uint8_t* valueAddress);
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static void rf_mac_set_panId(uint8_t* valueAddress);
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static void rf_mac_set_mac64(const uint8_t* valueAddress);
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static void rf_mac_set_shortAddress(uint8_t *valueAddress);
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static void rf_mac_set_panId(uint8_t *valueAddress);
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static void rf_mac_set_mac64(const uint8_t *valueAddress);
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static uint8_t rf_convert_energy_level(uint8_t energyLevel);
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static void rf_abort(void);
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static void rf_ack_wait_timer_start(uint16_t time);
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@ -100,8 +100,8 @@ static uint8_t PHYPAYLOAD[MAC_PACKET_SIZE];
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const phy_rf_channel_configuration_s phy_2_4ghz = {2405000000U, 5000000U, 250000U, 16U, M_OQPSK};
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const phy_device_channel_page_s phy_channel_pages[] = {
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{CHANNEL_PAGE_0, &phy_2_4ghz},
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{CHANNEL_PAGE_0, NULL}
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{CHANNEL_PAGE_0, &phy_2_4ghz},
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{CHANNEL_PAGE_0, NULL}
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};
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static phy_device_driver_s device_driver = {
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@ -109,7 +109,7 @@ static phy_device_driver_s device_driver = {
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PHY_LAYER_PAYLOAD_DATA_FLOW,
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MAC64_addr,
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PHY_MTU_SIZE,
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(char*)"NXP kw41z",
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(char *)"NXP kw41z",
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CRC_LENGTH,
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PHY_HEADER_LENGTH,
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&rf_interface_state_control,
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@ -184,9 +184,9 @@ static void rf_promiscuous(uint8_t state)
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/* FRM_VER[11:8] = b0011. Accept FrameVersion 0 and 1 packets, reject all others */
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/* Beacon, Data and MAC command frame types accepted */
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ZLL->RX_FRAME_FILTER &= ~(ZLL_RX_FRAME_FILTER_FRM_VER_FILTER_MASK |
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ZLL_RX_FRAME_FILTER_ACK_FT_MASK |
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ZLL_RX_FRAME_FILTER_NS_FT_MASK |
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ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK);
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ZLL_RX_FRAME_FILTER_ACK_FT_MASK |
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ZLL_RX_FRAME_FILTER_NS_FT_MASK |
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ZLL_RX_FRAME_FILTER_ACTIVE_PROMISCUOUS_MASK);
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ZLL->RX_FRAME_FILTER |= ZLL_RX_FRAME_FILTER_FRM_VER_FILTER(3);
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}
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}
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@ -211,8 +211,7 @@ static int8_t rf_interface_state_control(phy_interface_state_e new_state, uint8_
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{
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platform_enter_critical();
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switch (new_state)
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{
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switch (new_state) {
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/*Reset PHY driver and set to idle*/
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case PHY_INTERFACE_RESET:
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rf_abort();
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@ -294,7 +293,7 @@ static void rf_abort(void)
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if (ZLL->PHY_CTRL & ZLL_PHY_CTRL_TMRTRIGEN_MASK) {
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ZLL->PHY_CTRL &= ~ZLL_PHY_CTRL_TMRTRIGEN_MASK;
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/* give the FSM enough time to start if it was triggered */
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while( (XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) == 0) {}
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while ((XCVR_MISC->XCVR_CTRL & XCVR_CTRL_XCVR_STATUS_TSM_COUNT_MASK) == 0) {}
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}
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/* If XCVR is not idle, abort current SEQ */
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@ -347,7 +346,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
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need_ack = (*data_ptr & 0x20) == 0x20;
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/* Load data into Packet Buffer */
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pPB = (uint8_t*)ZLL->PKT_BUFFER_TX;
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pPB = (uint8_t *)ZLL->PKT_BUFFER_TX;
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tx_len = data_length + 2;
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*pPB++ = tx_len; /* including 2 bytes of FCS */
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@ -382,7 +381,7 @@ static int8_t rf_start_cca(uint8_t *data_ptr, uint16_t data_length, uint8_t tx_h
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ZLL->IRQSTS = irqSts;
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tx_warmup_time = (XCVR_TSM->END_OF_SEQ & XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_MASK) >>
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XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
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XCVR_TSM_END_OF_SEQ_END_OF_TX_WU_SHIFT;
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/* Compute warmup times (scaled to 16us) */
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if (tx_warmup_time & 0x0F) {
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@ -418,19 +417,19 @@ static int8_t rf_address_write(phy_address_type_e address_type, uint8_t *address
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platform_enter_critical();
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switch (address_type) {
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case PHY_MAC_64BIT:
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rf_mac_set_mac64(address_ptr);
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break;
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/*Set 16-bit address*/
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case PHY_MAC_16BIT:
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rf_mac_set_shortAddress(address_ptr);
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break;
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/*Set PAN Id*/
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case PHY_MAC_PANID:
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rf_mac_set_panId(address_ptr);
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break;
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default:
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ret_val = -1;
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case PHY_MAC_64BIT:
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rf_mac_set_mac64(address_ptr);
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break;
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/*Set 16-bit address*/
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case PHY_MAC_16BIT:
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rf_mac_set_shortAddress(address_ptr);
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break;
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/*Set PAN Id*/
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case PHY_MAC_PANID:
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rf_mac_set_panId(address_ptr);
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break;
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default:
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ret_val = -1;
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}
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platform_exit_critical();
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@ -495,7 +494,8 @@ static uint8_t rf_convert_energy_level(uint8_t energyLevel)
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/**
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* SET MAC 16 address to Register
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*/
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static void rf_mac_set_shortAddress(uint8_t* valueAddress) {
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static void rf_mac_set_shortAddress(uint8_t *valueAddress)
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{
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ZLL->MACSHORTADDRS0 &= ~ZLL_MACSHORTADDRS0_MACSHORTADDRS0_MASK;
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ZLL->MACSHORTADDRS0 |= ZLL_MACSHORTADDRS0_MACSHORTADDRS0(common_read_16_bit(valueAddress));
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}
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@ -503,7 +503,8 @@ static void rf_mac_set_shortAddress(uint8_t* valueAddress) {
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/**
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* SET PAN-ID to Register
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*/
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static void rf_mac_set_panId(uint8_t* valueAddress) {
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static void rf_mac_set_panId(uint8_t *valueAddress)
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{
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ZLL->MACSHORTADDRS0 &= ~ZLL_MACSHORTADDRS0_MACPANID0_MASK;
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ZLL->MACSHORTADDRS0 |= ZLL_MACSHORTADDRS0_MACPANID0(common_read_16_bit(valueAddress));
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}
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@ -511,7 +512,8 @@ static void rf_mac_set_panId(uint8_t* valueAddress) {
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/**
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* SET MAC64 address to register
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*/
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static void rf_mac_set_mac64(const uint8_t* valueAddress) {
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static void rf_mac_set_mac64(const uint8_t *valueAddress)
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{
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ZLL->MACLONGADDRS0_MSB = common_read_32_bit(valueAddress);
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valueAddress += 4;
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ZLL->MACLONGADDRS0_LSB = common_read_32_bit(valueAddress);
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@ -544,7 +546,7 @@ static uint8_t PhyPlmeGetPwrLevelRequest(void)
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static uint8_t PhyPlmeSetCurrentChannelRequest(uint8_t channel, uint8_t pan)
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{
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if((channel < 11) || (channel > 26)) {
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if ((channel < 11) || (channel > 26)) {
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return 1;
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}
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@ -591,9 +593,9 @@ static void PhyIsrSeqCleanup(void)
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irqStatus |= ZLL_IRQSTS_TMR3MSK_MASK;
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/* Clear transceiver interrupts except TMRxIRQ */
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irqStatus &= ~(ZLL_IRQSTS_TMR1IRQ_MASK |
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ZLL_IRQSTS_TMR2IRQ_MASK |
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ZLL_IRQSTS_TMR3IRQ_MASK |
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ZLL_IRQSTS_TMR4IRQ_MASK);
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ZLL_IRQSTS_TMR2IRQ_MASK |
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ZLL_IRQSTS_TMR3IRQ_MASK |
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ZLL_IRQSTS_TMR4IRQ_MASK);
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ZLL->IRQSTS = irqStatus;
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}
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@ -617,8 +619,8 @@ static void PhyIsrTimeoutCleanup(void)
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/* Mask TMR3 interrupt */
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irqStatus |= ZLL_IRQSTS_TMR3MSK_MASK;
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/* Clear transceiver interrupts except TMR1IRQ and TMR4IRQ. */
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irqStatus &= ~( ZLL_IRQSTS_TMR1IRQ_MASK |
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ZLL_IRQSTS_TMR4IRQ_MASK );
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irqStatus &= ~(ZLL_IRQSTS_TMR1IRQ_MASK |
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ZLL_IRQSTS_TMR4IRQ_MASK);
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ZLL->IRQSTS = irqStatus;
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/* The packet was transmitted successfully, but no ACK was received */
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@ -686,19 +688,19 @@ static void rf_mac_hw_init(void)
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/* Enable 16 bit mode for TC2 - TC2 prime EN, disable all timers,
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enable AUTOACK, mask all interrupts */
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ZLL->PHY_CTRL = (gCcaCCA_MODE1_c << ZLL_PHY_CTRL_CCATYPE_SHIFT) |
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ZLL_PHY_CTRL_TC2PRIME_EN_MASK |
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ZLL_PHY_CTRL_TSM_MSK_MASK |
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ZLL_PHY_CTRL_WAKE_MSK_MASK |
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ZLL_PHY_CTRL_CRC_MSK_MASK |
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ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
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ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
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ZLL_PHY_CTRL_RX_WMRK_MSK_MASK |
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ZLL_PHY_CTRL_CCAMSK_MASK |
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ZLL_PHY_CTRL_RXMSK_MASK |
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ZLL_PHY_CTRL_TXMSK_MASK |
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ZLL_PHY_CTRL_SEQMSK_MASK |
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ZLL_PHY_CTRL_AUTOACK_MASK |
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ZLL_PHY_CTRL_TRCV_MSK_MASK;
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ZLL_PHY_CTRL_TC2PRIME_EN_MASK |
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ZLL_PHY_CTRL_TSM_MSK_MASK |
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ZLL_PHY_CTRL_WAKE_MSK_MASK |
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ZLL_PHY_CTRL_CRC_MSK_MASK |
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ZLL_PHY_CTRL_PLL_UNLOCK_MSK_MASK |
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ZLL_PHY_CTRL_FILTERFAIL_MSK_MASK |
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ZLL_PHY_CTRL_RX_WMRK_MSK_MASK |
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ZLL_PHY_CTRL_CCAMSK_MASK |
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ZLL_PHY_CTRL_RXMSK_MASK |
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ZLL_PHY_CTRL_TXMSK_MASK |
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ZLL_PHY_CTRL_SEQMSK_MASK |
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ZLL_PHY_CTRL_AUTOACK_MASK |
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ZLL_PHY_CTRL_TRCV_MSK_MASK;
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/* Clear all PP IRQ bits to avoid unexpected interrupts immediately after init
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disable all timer interrupts */
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@ -927,7 +929,7 @@ static uint8_t rf_convert_LQI(uint8_t hwLqi)
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static void rf_handle_rx_end(void)
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{
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uint8_t rf_lqi = (ZLL->LQI_AND_RSSI & ZLL_LQI_AND_RSSI_LQI_VALUE_MASK) >>
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ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT;
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ZLL_LQI_AND_RSSI_LQI_VALUE_SHIFT;
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int8_t rf_rssi = 0;
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uint8_t len;
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uint8_t i;
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@ -944,7 +946,7 @@ static void rf_handle_rx_end(void)
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rf_rssi = rf_convert_LQI_to_RSSI(rf_lqi);
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/* Load data from Packet Buffer */
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pPB = (uint8_t*)ZLL->PKT_BUFFER_RX;
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pPB = (uint8_t *)ZLL->PKT_BUFFER_RX;
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for (i = 0; i < len; i++) {
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PHYPAYLOAD[i] = *pPB++;
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@ -978,8 +980,8 @@ static void handle_IRQ_events(void)
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} else {
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/* Rx Watermark IRQ */
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if((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)) &&
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(irqStatus & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)) {
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if ((!(ZLL->PHY_CTRL & ZLL_PHY_CTRL_RX_WMRK_MSK_MASK)) &&
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(irqStatus & ZLL_IRQSTS_RXWTRMRKIRQ_MASK)) {
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uint32_t rx_len = (irqStatus & ZLL_IRQSTS_RX_FRAME_LENGTH_MASK) >> ZLL_IRQSTS_RX_FRAME_LENGTH_SHIFT;
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/* Convert to symbols and add IFS and ACK duration */
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@ -1002,47 +1004,46 @@ static void handle_IRQ_events(void)
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}
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/* TMR3 timeout, the autosequence has been aborted due to TMR3 timeout */
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else if ((irqStatus & ZLL_IRQSTS_TMR3IRQ_MASK) &&
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(!(irqStatus & ZLL_IRQSTS_RXIRQ_MASK)) &&
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(xcvseqCopy != gTX_c)) {
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(!(irqStatus & ZLL_IRQSTS_RXIRQ_MASK)) &&
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(xcvseqCopy != gTX_c)) {
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PhyIsrTimeoutCleanup();
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/* Start receiver */
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rf_receive();
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} else {
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PhyIsrSeqCleanup();
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switch(xcvseqCopy)
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{
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case gTX_c:
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if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
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(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
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device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
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PHY_LINK_CCA_FAIL, 1, 1);
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} else {
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rf_handle_tx_end(false);
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}
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break;
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switch (xcvseqCopy) {
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case gTX_c:
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if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
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(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
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device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
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PHY_LINK_CCA_FAIL, 1, 1);
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} else {
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rf_handle_tx_end(false);
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}
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break;
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case gTR_c:
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if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
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(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
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device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
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PHY_LINK_CCA_FAIL, 1, 1);
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} else {
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rf_handle_tx_end((irqStatus & ZLL_IRQSTS_RX_FRM_PEND_MASK) > 0);
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}
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break;
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case gTR_c:
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if ((ZLL->PHY_CTRL & ZLL_PHY_CTRL_CCABFRTX_MASK) &&
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(irqStatus & ZLL_IRQSTS_CCA_MASK)) {
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device_driver.phy_tx_done_cb(rf_radio_driver_id, rf_mac_handle,
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PHY_LINK_CCA_FAIL, 1, 1);
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} else {
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rf_handle_tx_end((irqStatus & ZLL_IRQSTS_RX_FRM_PEND_MASK) > 0);
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}
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break;
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case gRX_c:
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rf_handle_rx_end();
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break;
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case gRX_c:
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rf_handle_rx_end();
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break;
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case gCCA_c:
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rf_ed_value = rf_convert_energy_level((ZLL->LQI_AND_RSSI &
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ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >>
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ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT);
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break;
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case gCCA_c:
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rf_ed_value = rf_convert_energy_level((ZLL->LQI_AND_RSSI &
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ZLL_LQI_AND_RSSI_CCA1_ED_FNL_MASK) >>
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ZLL_LQI_AND_RSSI_CCA1_ED_FNL_SHIFT);
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break;
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default:
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break;
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default:
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break;
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}
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}
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}
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@ -1097,7 +1098,7 @@ void NanostackRfPhyKw41z::get_mac_address(uint8_t *mac)
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{
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platform_enter_critical();
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memcpy((void*)mac, (void*)MAC64_addr, sizeof(MAC64_addr));
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memcpy((void *)mac, (void *)MAC64_addr, sizeof(MAC64_addr));
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platform_exit_critical();
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}
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@ -1111,7 +1112,7 @@ void NanostackRfPhyKw41z::set_mac_address(uint8_t *mac)
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platform_exit_critical();
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return;
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}
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memcpy((void*)MAC64_addr, (void*)mac, sizeof(MAC64_addr));
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memcpy((void *)MAC64_addr, (void *)mac, sizeof(MAC64_addr));
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platform_exit_critical();
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}
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