From d2741c1075ec962a4fb0f200eabd3a82d37455b6 Mon Sep 17 00:00:00 2001 From: MarceloSalazar Date: Tue, 21 Apr 2020 09:18:08 +0100 Subject: [PATCH] Remove LPC8x targets --- targets/TARGET_NXP/TARGET_LPC81X/PortNames.h | 30 - .../TARGET_LPC812/PeripheralNames.h | 37 - .../TARGET_LPC81X/TARGET_LPC812/PinNames.h | 116 -- .../device/TOOLCHAIN_ARM_MICRO/LPC812.sct | 48 - .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 185 --- .../device/TOOLCHAIN_GCC_ARM/LPC812.ld | 156 -- .../device/TOOLCHAIN_IAR/LPC812.icf | 39 - .../device/TOOLCHAIN_IAR/startup_LPC8xx.S | 198 --- .../TARGET_LPC812/device/system_LPC8xx.c | 381 ----- targets/TARGET_NXP/TARGET_LPC81X/device.h | 38 - .../TARGET_NXP/TARGET_LPC81X/device/LPC8xx.h | 710 --------- .../device/TOOLCHAIN_GCC_ARM/startup_LPC81X.S | 219 --- .../TARGET_NXP/TARGET_LPC81X/device/cmsis.h | 13 - .../TARGET_LPC81X/device/cmsis_nvic.h | 37 - .../TARGET_LPC81X/device/system_LPC8xx.h | 63 - targets/TARGET_NXP/TARGET_LPC81X/gpio_api.c | 70 - .../TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c | 135 -- .../TARGET_NXP/TARGET_LPC81X/gpio_object.h | 56 - targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c | 557 ------- targets/TARGET_NXP/TARGET_LPC81X/objects.h | 57 - targets/TARGET_NXP/TARGET_LPC81X/pinmap.c | 61 - targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c | 277 ---- targets/TARGET_NXP/TARGET_LPC81X/serial_api.c | 374 ----- targets/TARGET_NXP/TARGET_LPC81X/sleep.c | 82 -- targets/TARGET_NXP/TARGET_LPC81X/spi_api.c | 275 ---- targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c | 143 -- targets/TARGET_NXP/TARGET_LPC82X/PortNames.h | 30 - .../TARGET_LPC824/PeripheralNames.h | 55 - .../TARGET_LPC82X/TARGET_LPC824/PinNames.h | 135 -- .../TARGET_LPC82X/TARGET_LPC824/device.h | 38 - .../device/TOOLCHAIN_ARM_MICRO/LPC824.sct | 48 - .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 195 --- .../device/TOOLCHAIN_GCC_ARM/LPC824.ld | 156 -- .../device/TOOLCHAIN_GCC_ARM/startup_LPC824.S | 228 --- .../device/TOOLCHAIN_IAR/LPC824.icf | 39 - .../device/TOOLCHAIN_IAR/startup_LPC8xx.S | 216 --- .../TARGET_LPC824/device/system_LPC8xx.c | 389 ----- .../TARGET_SSCI824/PeripheralNames.h | 55 - .../TARGET_LPC82X/TARGET_SSCI824/PinNames.h | 135 -- .../TARGET_LPC82X/TARGET_SSCI824/device.h | 38 - .../device/TOOLCHAIN_ARM_MICRO/LPC824.sct | 48 - .../TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S | 195 --- .../device/TOOLCHAIN_GCC_ARM/LPC824.ld | 157 -- .../device/TOOLCHAIN_GCC_ARM/startup_LPC824.S | 228 --- .../TARGET_SSCI824/device/system_LPC8xx.c | 389 ----- .../TARGET_NXP/TARGET_LPC82X/analogin_api.c | 136 -- .../TARGET_NXP/TARGET_LPC82X/device/LPC82x.h | 1308 ----------------- .../TARGET_NXP/TARGET_LPC82X/device/cmsis.h | 13 - .../TARGET_LPC82X/device/cmsis_nvic.h | 37 - .../TARGET_LPC82X/device/system_LPC82x.h | 63 - targets/TARGET_NXP/TARGET_LPC82X/gpio_api.c | 72 - .../TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c | 145 -- .../TARGET_NXP/TARGET_LPC82X/gpio_object.h | 58 - targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c | 652 -------- targets/TARGET_NXP/TARGET_LPC82X/objects.h | 62 - targets/TARGET_NXP/TARGET_LPC82X/pinmap.c | 46 - targets/TARGET_NXP/TARGET_LPC82X/pwmout_api.c | 243 --- .../TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h | 127 -- targets/TARGET_NXP/TARGET_LPC82X/serial_api.c | 422 ------ targets/TARGET_NXP/TARGET_LPC82X/sleep.c | 62 - targets/TARGET_NXP/TARGET_LPC82X/spi_api.c | 289 ---- targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c | 116 -- targets/TARGET_NXP/mbed_rtx.h | 8 +- targets/targets.json | 154 +- tools/export/iar/iar_definitions.json | 3 - tools/export/lpcxpresso/__init__.py | 1 - tools/export/lpcxpresso/lpc824_cproject.tmpl | 53 - tools/export/lpcxpresso/lpc824_project.tmpl | 1 - tools/export/mcuxpresso/LPC824_cproject.tmpl | 51 - tools/resources/__init__.py | 1 - 70 files changed, 43 insertions(+), 11211 deletions(-) delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/PortNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PeripheralNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/LPC812.sct delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_GCC_ARM/LPC812.ld delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/LPC812.icf delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/startup_LPC8xx.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/system_LPC8xx.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/device.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/device/LPC8xx.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/device/TOOLCHAIN_GCC_ARM/startup_LPC81X.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/device/cmsis.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/device/cmsis_nvic.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/device/system_LPC8xx.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/gpio_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/gpio_object.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/objects.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/pinmap.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/serial_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/sleep.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/spi_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/PortNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/LPC824.ld delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/LPC824.icf delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/startup_LPC8xx.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/system_LPC8xx.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/analogin_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/device/LPC82x.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/device/cmsis.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/device/cmsis_nvic.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/device/system_LPC82x.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/gpio_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/gpio_object.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/objects.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/pinmap.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/pwmout_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/serial_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/sleep.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/spi_api.c delete mode 100644 targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c delete mode 100644 tools/export/lpcxpresso/lpc824_cproject.tmpl delete mode 100644 tools/export/lpcxpresso/lpc824_project.tmpl delete mode 100644 tools/export/mcuxpresso/LPC824_cproject.tmpl diff --git a/targets/TARGET_NXP/TARGET_LPC81X/PortNames.h b/targets/TARGET_NXP/TARGET_LPC81X/PortNames.h deleted file mode 100644 index bbd5b31103..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/PortNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PeripheralNames.h deleted file mode 100644 index 55ca9e3d2d..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PeripheralNames.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Default peripherals -#define MBED_SPI0 P0_14, P0_15, P0_12, P0_13 - -#define MBED_UART0 P0_4, P0_0 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 P0_10, P0_11 - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h deleted file mode 100644 index 59a79a82b3..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/PinNames.h +++ /dev/null @@ -1,116 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - // Not connected - NC = (int)0xFFFFFFFF, - - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - - D0 = P0_0, - D1 = P0_4, - D2 = P0_6, - D3 = P0_8, - D4 = P0_9, - D5 = NC, - D6 = NC, - - D7 = P0_7, - D8 = P0_17, - D9 = P0_16, - D10 = P0_13, - D11 = P0_14, - D12 = P0_15, - D13 = P0_12, - D14 = P0_10, - D15 = P0_11, - - A0 = NC, - A1 = NC, - A2 = NC, - A3 = NC, - A4 = P0_10, - A5 = P0_11, - - // LPC800-MAX board - LED_RED = P0_7, - LED_GREEN = P0_17, - LED_BLUE = P0_16, - - // mbed original LED naming - LED1 = LED_BLUE, - LED2 = LED_GREEN, - LED3 = LED_RED, - LED4 = LED_RED, - - // Serial to USB pins - USBTX = P0_6, - USBRX = P0_1, - -} PinName; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -typedef struct { - unsigned char n; - unsigned char offset; -} SWM_Map; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/LPC812.sct b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/LPC812.sct deleted file mode 100644 index 56c65f3f9e..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/LPC812.sct +++ /dev/null @@ -1,48 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - - -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x4000 -#endif - -; 4KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x00001000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S deleted file mode 100644 index 85beb968cb..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S +++ /dev/null @@ -1,185 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC8xx.s -; * @purpose: CMSIS Cortex-M0+ Core Device Startup File -; * for the NXP LPC8xx Device Series -; * @version: V1.0 -; * @date: 16. Aug. 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C_IRQHandler ; I2C controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD 0 ; Reserved - DCD WKT_IRQHandler ; Wakeup timer - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -; now, under COMMON lpc8xx_nmi.c and lpc8xx_nmi.h, a real NMI handler is created if NMI is enabled -; for particular peripheral. -;NMI_Handler PROC -; EXPORT NMI_Handler [WEAK] -; B . -; ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT NMI_Handler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT I2C_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT MRT_IRQHandler [WEAK] - EXPORT CMP_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - - EXPORT WKT_IRQHandler [WEAK] - - EXPORT PININT0_IRQHandler [WEAK] - EXPORT PININT1_IRQHandler [WEAK] - EXPORT PININT2_IRQHandler [WEAK] - EXPORT PININT3_IRQHandler [WEAK] - EXPORT PININT4_IRQHandler [WEAK] - EXPORT PININT5_IRQHandler [WEAK] - EXPORT PININT6_IRQHandler [WEAK] - EXPORT PININT7_IRQHandler [WEAK] - -NMI_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -WKT_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_GCC_ARM/LPC812.ld b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_GCC_ARM/LPC812.ld deleted file mode 100644 index f51f0d6dfe..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_GCC_ARM/LPC812.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* Linker script for mbed LPC812-GCC-ARM based on LPC824.ld */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* Define each memory region */ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x4000 /* 16K bytes */ - RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x1000-0xC0 /* 4K bytes */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/LPC812.icf b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/LPC812.icf deleted file mode 100644 index 51713a8e07..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/LPC812.icf +++ /dev/null @@ -1,39 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00003FFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10000FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/startup_LPC8xx.S deleted file mode 100644 index 48ead87f40..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/TOOLCHAIN_IAR/startup_LPC8xx.S +++ /dev/null @@ -1,198 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2011 IAR Systems. All rights reserved. - * - * $Revision: 47876 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C_IRQHandler ; I2C controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD 0 ; Reserved - DCD WKT_IRQHandler ; Wakeup timer - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK I2C_IRQHandler - PUBWEAK SCT_IRQHandler - PUBWEAK MRT_IRQHandler - PUBWEAK CMP_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK WKT_IRQHandler - PUBWEAK PININT0_IRQHandler - PUBWEAK PININT1_IRQHandler - PUBWEAK PININT2_IRQHandler - PUBWEAK PININT3_IRQHandler - PUBWEAK PININT4_IRQHandler - PUBWEAK PININT5_IRQHandler - PUBWEAK PININT6_IRQHandler - PUBWEAK PININT7_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB - -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -WKT_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler -Default_IRQHandler - B Default_IRQHandler - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/system_LPC8xx.c b/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/system_LPC8xx.c deleted file mode 100644 index c96d6c446b..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/TARGET_LPC812/device/system_LPC8xx.c +++ /dev/null @@ -1,381 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.c - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#include -#include "LPC8xx.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ---------------------------------- -// -// Clock Configuration -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.5 MHz -// <2=> 0.8 MHz -// <3=> 1.1 MHz -// <4=> 1.4 MHz -// <5=> 1.6 MHz -// <6=> 1.8 MHz -// <7=> 2.0 MHz -// <8=> 2.2 MHz -// <9=> 2.4 MHz -// <10=> 2.6 MHz -// <11=> 2.7 MHz -// <12=> 2.9 MHz -// <13=> 3.1 MHz -// <14=> 3.2 MHz -// <15=> 3.4 MHz -// -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC Oscillator -// <1=> System Oscillator -// <2=> Reserved -// <3=> CLKIN pin -// -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> Input Clock to System PLL -// <2=> WDT Oscillator -// <3=> System PLL Clock Out -// -// -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -// -*/ -#define CLOCK_SETUP 1 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: - -//Fixed to use PLL -#if (CLOCK_SETUP == 1) -//use PLL for IRC - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz - #define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 Select IRC - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT - #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz - -#elif (CLOCK_SETUP == 2) -//use PLL for XTAL - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000004 // Reset: 0x000 MSEL=4 => M=5; PSEL=0 => 2P=2; PLLCLKOUT = (12x5) = 60MHz - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 Select XTAL - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 MainClock = PLLCLKOUT - #define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 DIV=2 => SYSTEMCORECLK = 60 / 2 = 30MHz -#endif - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ -#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) - #define __SYS_PLLCLKIN (__CLKIN_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ -uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/ - -//Replaced SystemCoreClock with MainClock -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - MainClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - MainClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - MainClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - MainClock = 0; - break; - case 3: /* CLKIN pin */ - MainClock = __CLKIN_CLK; - break; - } - break; - case 2: /* WDT Oscillator */ - MainClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - MainClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 1: /* System oscillator */ - MainClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 2: /* Reserved */ - MainClock = 0; - break; - case 3: /* CLKIN pin */ - MainClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - } - break; - } - - SystemCoreClock = MainClock / LPC_SYSCON->SYSAHBCLKDIV; -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - volatile uint32_t i; - - /* System clock to the IOCON & the SWM need to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_IOCON->PIO0_8 &= ~(0x3 << 3); - LPC_IOCON->PIO0_9 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x3 << 4); - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; - for (i = 0; i < 200; i++) __NOP(); -#endif -#if ((SYSPLLCLKSEL_Val & 0x03) == 3) - LPC_IOCON->PIO0_1 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x1 << 7); - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0x01; /* Update Clock Source */ - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0x01; /* Update MCLK Clock Source */ - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; -#endif -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/device.h b/targets/TARGET_NXP/TARGET_LPC81X/device.h deleted file mode 100644 index 2427e752ea..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/device/LPC8xx.h b/targets/TARGET_NXP/TARGET_LPC81X/device/LPC8xx.h deleted file mode 100644 index a6df8ea120..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/device/LPC8xx.h +++ /dev/null @@ -1,710 +0,0 @@ -/**************************************************************************** - * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $ - * Project: NXP LPC8xx software example - * - * Description: - * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for - * NXP LPC800 Device Series - * - **************************************************************************** - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * products. This software is supplied "AS IS" without any warranties. - * NXP Semiconductors assumes no responsibility or liability for the - * use of the software, conveys no license or title under any patent, - * copyright, or mask work right to the product. NXP Semiconductors - * reserves the right to make changes in the software without - * notification. NXP Semiconductors also make no representation or - * warranty that such application will be suitable for the specified - * use without further testing or modification. - - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' - * relevant copyright in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. -****************************************************************************/ -#ifndef __LPC8xx_H__ -#define __LPC8xx_H__ - -#ifdef __cplusplus - extern "C" { -#endif - -/** @addtogroup LPC8xx_Definitions LPC8xx Definitions - This file defines all structures and symbols for LPC8xx: - - Registers and bitfields - - peripheral base address - - PIO definitions - @{ -*/ - - -/******************************************************************************/ -/* Processor and Core Peripherals */ -/******************************************************************************/ -/** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions - Configuration of the Cortex-M0+ Processor and Core Peripherals - @{ -*/ - -/* - * ========================================================================== - * ---------- Interrupt Number Definition ----------------------------------- - * ========================================================================== - */ -typedef enum IRQn -{ -/****** Cortex-M0 Processor Exceptions Numbers ***************************************************/ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/ - NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ - HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */ - SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */ - PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */ - SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */ - -/****** LPC8xx Specific Interrupt Numbers ********************************************************/ - SPI0_IRQn = 0, /*!< SPI0 */ - SPI1_IRQn = 1, /*!< SPI1 */ - Reserved0_IRQn = 2, /*!< Reserved Interrupt */ - UART0_IRQn = 3, /*!< USART0 */ - UART1_IRQn = 4, /*!< USART1 */ - UART2_IRQn = 5, /*!< USART2 */ - Reserved1_IRQn = 6, /*!< Reserved Interrupt */ - Reserved2_IRQn = 7, /*!< Reserved Interrupt */ - I2C_IRQn = 8, /*!< I2C */ - SCT_IRQn = 9, /*!< SCT */ - MRT_IRQn = 10, /*!< MRT */ - CMP_IRQn = 11, /*!< CMP */ - WDT_IRQn = 12, /*!< WDT */ - BOD_IRQn = 13, /*!< BOD */ - Reserved3_IRQn = 14, /*!< Reserved Interrupt */ - WKT_IRQn = 15, /*!< WKT Interrupt */ - Reserved4_IRQn = 16, /*!< Reserved Interrupt */ - Reserved5_IRQn = 17, /*!< Reserved Interrupt */ - Reserved6_IRQn = 18, /*!< Reserved Interrupt */ - Reserved7_IRQn = 19, /*!< Reserved Interrupt */ - Reserved8_IRQn = 20, /*!< Reserved Interrupt */ - Reserved9_IRQn = 21, /*!< Reserved Interrupt */ - Reserved10_IRQn = 22, /*!< Reserved Interrupt */ - Reserved11_IRQn = 23, /*!< Reserved Interrupt */ - PININT0_IRQn = 24, /*!< External Interrupt 0 */ - PININT1_IRQn = 25, /*!< External Interrupt 1 */ - PININT2_IRQn = 26, /*!< External Interrupt 2 */ - PININT3_IRQn = 27, /*!< External Interrupt 3 */ - PININT4_IRQn = 28, /*!< External Interrupt 4 */ - PININT5_IRQn = 29, /*!< External Interrupt 5 */ - PININT6_IRQn = 30, /*!< External Interrupt 6 */ - PININT7_IRQn = 31, /*!< External Interrupt 7 */ -} IRQn_Type; - -/* - * ========================================================================== - * ----------- Processor and Core Peripheral Section ------------------------ - * ========================================================================== - */ - -/* Configuration of the Cortex-M0+ Processor and Core Peripherals */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ - -/*@}*/ /* end of group LPC8xx_CMSIS */ - - -#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ -#include "system_LPC8xx.h" /* System Header */ - - -/******************************************************************************/ -/* Device Specific Peripheral Registers structures */ -/******************************************************************************/ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/*------------- System Control (SYSCON) --------------------------------------*/ -/** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block - @{ -*/ -typedef struct -{ - __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */ - __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */ - __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */ - __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */ - uint32_t RESERVED0[4]; - - __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */ - __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */ - uint32_t RESERVED1[2]; - __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */ - uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */ - __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */ - uint32_t RESERVED3[10]; - - __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */ - __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */ - __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */ - uint32_t RESERVED4[1]; - - __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */ - uint32_t RESERVED5[4]; - __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */ - uint32_t RESERVED6[18]; - - __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */ - __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */ - __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */ - uint32_t RESERVED7; - __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */ - __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */ - uint32_t RESERVED8[1]; - __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ - __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */ - uint32_t RESERVED9[12]; - __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */ - __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */ - __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */ - uint32_t RESERVED10[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - uint32_t RESERVED11[27]; - __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED12[3]; - __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */ - uint32_t RESERVED13[6]; - __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */ - __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */ - __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */ - uint32_t RESERVED14[110]; - __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */ -} LPC_SYSCON_TypeDef; -/*@}*/ /* end of group LPC8xx_SYSCON */ - - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG) - */ - -typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ - __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ - __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ - __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ - __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */ - __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */ - __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ - __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ - __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */ - __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */ - __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */ - __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */ - __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ -} LPC_IOCON_TypeDef; -/*@}*/ /* end of group LPC8xx_IOCON */ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL) - */ -typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ - __I uint32_t RESERVED2; - __I uint32_t FMSW0; -} LPC_FLASHCTRL_TypeDef; -/*@}*/ /* end of group LPC8xx_FLASHCTRL */ - - -/*------------- Power Management Unit (PMU) --------------------------*/ -/** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit - @{ -*/ -typedef struct -{ - __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */ - __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */ - __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */ - __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */ - __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */ - __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */ -} LPC_PMU_TypeDef; -/*@}*/ /* end of group LPC8xx_PMU */ - - -/*------------- Switch Matrix Port --------------------------*/ -/** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port - @{ -*/ -typedef struct -{ - union { - __IO uint32_t PINASSIGN[9]; - struct { - __IO uint32_t PINASSIGN0; - __IO uint32_t PINASSIGN1; - __IO uint32_t PINASSIGN2; - __IO uint32_t PINASSIGN3; - __IO uint32_t PINASSIGN4; - __IO uint32_t PINASSIGN5; - __IO uint32_t PINASSIGN6; - __IO uint32_t PINASSIGN7; - __IO uint32_t PINASSIGN8; - }; - }; - __I uint32_t RESERVED0[103]; - __IO uint32_t PINENABLE0; -} LPC_SWM_TypeDef; -/*@}*/ /* end of group LPC8xx_SWM */ - - -// ------------------------------------------------------------------------------------------------ -// ----- GPIO_PORT ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT) - */ - -typedef struct { - __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */ - __I uint16_t RESERVED0[2039]; - __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */ - uint32_t RESERVED1[1006]; - __IO uint32_t DIR0; /* 0x2000 */ - uint32_t RESERVED2[31]; - __IO uint32_t MASK0; /* 0x2080 */ - uint32_t RESERVED3[31]; - __IO uint32_t PIN0; /* 0x2100 */ - uint32_t RESERVED4[31]; - __IO uint32_t MPIN0; /* 0x2180 */ - uint32_t RESERVED5[31]; - __IO uint32_t SET0; /* 0x2200 */ - uint32_t RESERVED6[31]; - __O uint32_t CLR0; /* 0x2280 */ - uint32_t RESERVED7[31]; - __O uint32_t NOT0; /* 0x2300 */ - -} LPC_GPIO_PORT_TypeDef; - - -// ------------------------------------------------------------------------------------------------ -// ----- PIN_INT ----- -// ------------------------------------------------------------------------------------------------ - -/** - * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT) - */ - -typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */ - __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */ - __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */ - __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */ - __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */ - __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */ - __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */ - __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */ - __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ - __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */ - __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */ -} LPC_PIN_INT_TypeDef; - - -/*------------- CRC Engine (CRC) -----------------------------------------*/ -/** @addtogroup LPC8xx_CRC - @{ -*/ -typedef struct -{ - __IO uint32_t MODE; - __IO uint32_t SEED; - union { - __I uint32_t SUM; - __O uint32_t WR_DATA_DWORD; - __O uint16_t WR_DATA_WORD; - uint16_t RESERVED_WORD; - __O uint8_t WR_DATA_BYTE; - uint8_t RESERVED_BYTE[3]; - }; -} LPC_CRC_TypeDef; -/*@}*/ /* end of group LPC8xx_CRC */ - -/*------------- Comparator (CMP) --------------------------------------------------*/ -/** @addtogroup LPC8xx_CMP LPC8xx Comparator - @{ -*/ -typedef struct { /*!< (@ 0x40024000) CMP Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ - __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ -} LPC_CMP_TypeDef; -/*@}*/ /* end of group LPC8xx_CMP */ - - -/*------------- Wakeup Timer (WKT) --------------------------------------------------*/ -/** @addtogroup LPC8xx_WKT - @{ -*/ -typedef struct { /*!< (@ 0x40028000) WKT Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */ - uint32_t Reserved[2]; - __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */ -} LPC_WKT_TypeDef; -/*@}*/ /* end of group LPC8xx_WKT */ - -/*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/ -//New, Copied from lpc824 -/** - * @brief Multi-Rate Timer (MRT) (MRT) - */ -typedef struct { /*!< (@ 0x40004000) MRT Structure */ - __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */ - __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */ - __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */ - __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */ - __I uint32_t RESERVED0[45]; - __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns - the number of the first idle channel. */ - __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */ -} LPC_MRT_TypeDef; - -/*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/ -/** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter - @{ -*/ -/** - * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART) - */ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t CTRL; - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; /* 0x10 */ - __I uint32_t RXDATA; - __I uint32_t RXDATA_STAT; - __IO uint32_t TXDATA; - __IO uint32_t BRG; /* 0x20 */ - __IO uint32_t INTSTAT; -} LPC_USART_TypeDef; - -/*@}*/ /* end of group LPC8xx_USART */ - - -/*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/ -/** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port - @{ -*/ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t DLY; - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; /* 0x10 */ - __I uint32_t RXDAT; - __IO uint32_t TXDATCTL; - __IO uint32_t TXDAT; - __IO uint32_t TXCTRL; /* 0x20 */ - __IO uint32_t DIV; - __I uint32_t INTSTAT; -} LPC_SPI_TypeDef; -/*@}*/ /* end of group LPC8xx_SPI */ - - -/*------------- Inter-Integrated Circuit (I2C) -------------------------------*/ -/** @addtogroup LPC8xx_I2C I2C-Bus Interface - @{ -*/ -typedef struct -{ - __IO uint32_t CFG; /* 0x00 */ - __IO uint32_t STAT; - __IO uint32_t INTENSET; - __O uint32_t INTENCLR; - __IO uint32_t TIMEOUT; /* 0x10 */ - __IO uint32_t DIV; - __IO uint32_t INTSTAT; - uint32_t Reserved0[1]; - __IO uint32_t MSTCTL; /* 0x20 */ - __IO uint32_t MSTTIME; - __IO uint32_t MSTDAT; - uint32_t Reserved1[5]; - __IO uint32_t SLVCTL; /* 0x40 */ - __IO uint32_t SLVDAT; - __IO uint32_t SLVADR0; - __IO uint32_t SLVADR1; - __IO uint32_t SLVADR2; /* 0x50 */ - __IO uint32_t SLVADR3; - __IO uint32_t SLVQUAL0; - uint32_t Reserved2[9]; - __I uint32_t MONRXDAT; /* 0x80 */ -} LPC_I2C_TypeDef; - -/*@}*/ /* end of group LPC8xx_I2C */ - -/** - * @brief State Configurable Timer (SCT) (SCT) - */ - -/** - * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT) - */ - -#define CONFIG_SCT_nEV (6) /* Number of events */ -#define CONFIG_SCT_nRG (5) /* Number of match/compare registers */ -#define CONFIG_SCT_nOU (4) /* Number of outputs */ - -typedef struct -{ - __IO uint32_t CONFIG; /* 0x000 Configuration Register */ - union { - __IO uint32_t CTRL_U; /* 0x004 Control Register */ - struct { - __IO uint16_t CTRL_L; /* 0x004 low control register */ - __IO uint16_t CTRL_H; /* 0x006 high control register */ - }; - }; - __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */ - __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */ - __IO uint16_t HALT_L; /* 0x00C halt register for counter L */ - __IO uint16_t HALT_H; /* 0x00E halt register for counter H */ - __IO uint16_t STOP_L; /* 0x010 stop register for counter L */ - __IO uint16_t STOP_H; /* 0x012 stop register for counter H */ - __IO uint16_t START_L; /* 0x014 start register for counter L */ - __IO uint16_t START_H; /* 0x016 start register for counter H */ - uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */ - union { - __IO uint32_t COUNT_U; /* 0x040 counter register */ - struct { - __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */ - __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */ - }; - }; - __IO uint16_t STATE_L; /* 0x044 state register for counter L */ - __IO uint16_t STATE_H; /* 0x046 state register for counter H */ - __I uint32_t INPUT; /* 0x048 input register */ - __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */ - __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */ - __IO uint32_t OUTPUT; /* 0x050 output register */ - __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */ - __IO uint32_t RES; /* 0x058 conflict resolution register */ - uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */ - __IO uint32_t EVEN; /* 0x0F0 event enable register */ - __IO uint32_t EVFLAG; /* 0x0F4 event flag register */ - __IO uint32_t CONEN; /* 0x0F8 conflict enable register */ - __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */ - - union { - __IO union { /* 0x100-... Match / Capture value */ - uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCH[i].L Access to L value */ - uint16_t H; /* SCTMATCH[i].H Access to H value */ - }; - } MATCH[CONFIG_SCT_nRG]; - __I union { - uint32_t U; /* SCTCAP[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAP[i].L Access to H value */ - uint16_t H; /* SCTCAP[i].H Access to H value */ - }; - } CAP[CONFIG_SCT_nRG]; - }; - - - uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */ - - union { - __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */ - __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */ - }; - uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */ - union { - __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */ - __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */ - }; - - uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */ - - - union { - __IO union { /* 0x200-... Match Reload / Capture Control value */ - uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTMATCHREL[i].L Access to L value */ - uint16_t H; /* SCTMATCHREL[i].H Access to H value */ - }; - } MATCHREL[CONFIG_SCT_nRG]; - __IO union { - uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */ - struct { - uint16_t L; /* SCTCAPCTRL[i].L Access to H value */ - uint16_t H; /* SCTCAPCTRL[i].H Access to H value */ - }; - } CAPCTRL[CONFIG_SCT_nRG]; - }; - - uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */ - - union { - __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */ - __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */ - }; - uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */ - union { - __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */ - __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */ - }; - uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */ - - __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/ - uint32_t STATE; /* Event State Register */ - uint32_t CTRL; /* Event Control Register */ - } EVENT[CONFIG_SCT_nEV]; - - uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */ - - __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */ - uint32_t SET; /* Output n Set Register */ - uint32_t CLR; /* Output n Clear Register */ - } OUT[CONFIG_SCT_nOU]; - - uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */ - - __I uint32_t MODULECONTENT; /* 0x7FC Module Content */ - -} LPC_SCT_TypeDef; -/*@}*/ /* end of group LPC8xx_SCT */ - - -/*------------- Watchdog Timer (WWDT) -----------------------------------------*/ -/** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer - @{ -*/ -typedef struct -{ - __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */ - __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */ - __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */ - __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */ - uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */ - __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */ - __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */ -} LPC_WWDT_TypeDef; -/*@}*/ /* end of group LPC8xx_WDT */ - - -#if defined ( __CC_ARM ) -#pragma no_anon_unions -#endif - -/******************************************************************************/ -/* Peripheral memory map */ -/******************************************************************************/ -/* Base addresses */ -#define LPC_FLASH_BASE (0x00000000UL) -#define LPC_RAM_BASE (0x10000000UL) -#define LPC_ROM_BASE (0x1FFF0000UL) -#define LPC_APB0_BASE (0x40000000UL) -#define LPC_AHB_BASE (0x50000000UL) - -/* APB0 peripherals */ -#define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000) -#define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000) -#define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000) -#define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000) -#define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000) -#define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000) - -#define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000) -#define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000) -#define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000) -#define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000) -#define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000) -#define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000) -#define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000) -#define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000) -#define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000) - -/* AHB peripherals */ -#define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000) -#define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000) - -#define LPC_GPIO_PORT_BASE (0xA0000000) -#define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000) - -/******************************************************************************/ -/* Peripheral declaration */ -/******************************************************************************/ -#define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE ) -#define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE ) - - -#define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE ) -#define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE ) -#define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE ) -#define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE ) - -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE ) -#define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE ) -#define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE) -#define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE ) -#define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE ) -#define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE ) -#define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE ) -#define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE ) -#define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE ) - -#define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE ) -#define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE ) - -#define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE ) -#define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE ) - -#ifdef __cplusplus -} -#endif - -#endif /* __LPC8xx_H__ */ diff --git a/targets/TARGET_NXP/TARGET_LPC81X/device/TOOLCHAIN_GCC_ARM/startup_LPC81X.S b/targets/TARGET_NXP/TARGET_LPC81X/device/TOOLCHAIN_GCC_ARM/startup_LPC81X.S deleted file mode 100644 index 640b3cb3cb..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/device/TOOLCHAIN_GCC_ARM/startup_LPC81X.S +++ /dev/null @@ -1,219 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x80 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x80 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC810 interrupts */ - .long SPI0_IRQHandler // SPI0 controller - .long SPI1_IRQHandler // SPI1 controller - .long 0 // Reserved - .long UART0_IRQHandler // UART0 - .long UART1_IRQHandler // UART1 - .long UART2_IRQHandler // UART2 - .long 0 // Reserved - .long 0 // Reserved - .long I2C_IRQHandler // I2C controller - .long SCT_IRQHandler // Smart Counter Timer - .long MRT_IRQHandler // Multi-Rate Timer - .long CMP_IRQHandler // Comparator - .long WDT_IRQHandler // PIO1 (0:11) - .long BOD_IRQHandler // Brown Out Detect - .long 0 // Reserved - .long WKT_IRQHandler // Wakeup timer - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long 0 // Reserved - .long PININT0_IRQHandler // PIO INT0 - .long PININT1_IRQHandler // PIO INT1 - .long PININT2_IRQHandler // PIO INT2 - .long PININT3_IRQHandler // PIO INT3 - .long PININT4_IRQHandler // PIO INT4 - .long PININT5_IRQHandler // PIO INT5 - .long PININT6_IRQHandler // PIO INT6 - .long PININT7_IRQHandler // PIO INT7 - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler UART0_IRQHandler - def_irq_default_handler UART1_IRQHandler - def_irq_default_handler UART2_IRQHandler - def_irq_default_handler I2C_IRQHandler - def_irq_default_handler SCT_IRQHandler - def_irq_default_handler MRT_IRQHandler - def_irq_default_handler CMP_IRQHandler - def_irq_default_handler WDT_IRQHandler - def_irq_default_handler BOD_IRQHandler - def_irq_default_handler WKT_IRQHandler - def_irq_default_handler PININT0_IRQHandler - def_irq_default_handler PININT1_IRQHandler - def_irq_default_handler PININT2_IRQHandler - def_irq_default_handler PININT3_IRQHandler - def_irq_default_handler PININT4_IRQHandler - def_irq_default_handler PININT5_IRQHandler - def_irq_default_handler PININT6_IRQHandler - def_irq_default_handler PININT7_IRQHandler - - .end - diff --git a/targets/TARGET_NXP/TARGET_LPC81X/device/cmsis.h b/targets/TARGET_NXP/TARGET_LPC81X/device/cmsis.h deleted file mode 100644 index 12302cc3ad..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC8xx specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC8xx.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_LPC81X/device/cmsis_nvic.h deleted file mode 100644 index 673754cf2a..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/device/system_LPC8xx.h b/targets/TARGET_NXP/TARGET_LPC81X/device/system_LPC8xx.h deleted file mode 100644 index e95975d0ad..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/device/system_LPC8xx.h +++ /dev/null @@ -1,63 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.h - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC8xx_H -#define __SYSTEM_LPC8xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t MainClock; /*!< Main Clock Frequency */ -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC8xx_H */ diff --git a/targets/TARGET_NXP/TARGET_LPC81X/gpio_api.c b/targets/TARGET_NXP/TARGET_LPC81X/gpio_api.c deleted file mode 100644 index 2059675243..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/gpio_api.c +++ /dev/null @@ -1,70 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -static int gpio_enabled = 0; -static void gpio_enable(void) { - gpio_enabled = 1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */ - LPC_SYSCON->PRESETCTRL &= ~(0x1<<10); - LPC_SYSCON->PRESETCTRL |= (0x1<<10); -} - -uint32_t gpio_set(PinName pin) { - int f = 0; - - if (!gpio_enabled) - gpio_enable(); - - pin_function(pin, f); - - return (1 << ((int)pin & 0x1F)); -} - -void gpio_init(gpio_t *obj, PinName pin) { - obj->pin = pin; - if (pin == (PinName)NC) - return; - - obj->mask = gpio_set(pin); - - obj->reg_set = &LPC_GPIO_PORT->SET0; - obj->reg_clr = &LPC_GPIO_PORT->CLR0; - obj->reg_in = &LPC_GPIO_PORT->PIN0; - obj->reg_dir = &LPC_GPIO_PORT->DIR0; -} - -void gpio_mode(gpio_t *obj, PinMode mode) { - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) { - MBED_ASSERT(obj->pin != (PinName)NC); - switch (direction) { - case PIN_INPUT : - *obj->reg_dir &= ~obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir |= obj->mask; - break; - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c deleted file mode 100644 index cdc510cbe6..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/gpio_irq_api.c +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "mbed_error.h" - -#define CHANNEL_NUM 8 -#define LPC_GPIO_X LPC_PIN_INT -#define PININT_IRQ PININT0_IRQn - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -static inline void handle_interrupt_in(uint32_t channel) { - uint32_t ch_bit = (1 << channel); - // Return immediately if: - // * The interrupt was already served - // * There is no user handler - // * It is a level interrupt, not an edge interrupt - if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || - (channel_ids[channel] == 0 ) || - (LPC_GPIO_X->ISEL & ch_bit ) ) return; - - if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); - LPC_GPIO_X->RISE = ch_bit; - } - if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); - } - LPC_GPIO_X->IST = ch_bit; -} - -void gpio_irq0(void) {handle_interrupt_in(0);} -void gpio_irq1(void) {handle_interrupt_in(1);} -void gpio_irq2(void) {handle_interrupt_in(2);} -void gpio_irq3(void) {handle_interrupt_in(3);} -void gpio_irq4(void) {handle_interrupt_in(4);} -void gpio_irq5(void) {handle_interrupt_in(5);} -void gpio_irq6(void) {handle_interrupt_in(6);} -void gpio_irq7(void) {handle_interrupt_in(7);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) { - if (pin == NC) return -1; - - irq_handler = handler; - - int found_free_channel = 0; - int i = 0; - for (i=0; ich = i; - found_free_channel = 1; - break; - } - } - if (!found_free_channel) return -1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - LPC_SYSCON->PINTSEL[obj->ch] = pin; - - // Interrupt Wake-Up Enable - LPC_SYSCON->STARTERP0 |= 1 << obj->ch; - - void (*channels_irq)(void) = NULL; - switch (obj->ch) { - case 0: channels_irq = &gpio_irq0; break; - case 1: channels_irq = &gpio_irq1; break; - case 2: channels_irq = &gpio_irq2; break; - case 3: channels_irq = &gpio_irq3; break; - case 4: channels_irq = &gpio_irq4; break; - case 5: channels_irq = &gpio_irq5; break; - case 6: channels_irq = &gpio_irq6; break; - case 7: channels_irq = &gpio_irq7; break; - } - NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) { - channel_ids[obj->ch] = 0; - LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) { - unsigned int ch_bit = (1 << obj->ch); - - // Clear interrupt - if (!(LPC_GPIO_X->ISEL & ch_bit)) - LPC_GPIO_X->IST = ch_bit; - - // Edge trigger - LPC_GPIO_X->ISEL &= ~ch_bit; - if (event == IRQ_RISE) { - if (enable) { - LPC_GPIO_X->IENR |= ch_bit; - } else { - LPC_GPIO_X->IENR &= ~ch_bit; - } - } else { - if (enable) { - LPC_GPIO_X->IENF |= ch_bit; - } else { - LPC_GPIO_X->IENF &= ~ch_bit; - } - } -} - -void gpio_irq_enable(gpio_irq_t *obj) { - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); -} - -void gpio_irq_disable(gpio_irq_t *obj) { - NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/gpio_object.h b/targets/TARGET_NXP/TARGET_LPC81X/gpio_object.h deleted file mode 100644 index fe6d6c1e05..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/gpio_object.h +++ /dev/null @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c deleted file mode 100644 index 581f90fbb9..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/i2c_api.c +++ /dev/null @@ -1,557 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "i2c_api.h" -#include "cmsis.h" -#include "pinmap.h" - -#if DEVICE_I2C - -static const SWM_Map SWM_I2C_SDA[] = { - {7, 24}, -}; - -static const SWM_Map SWM_I2C_SCL[] = { - {8, 0}, -}; - -// Pinmap used for testing only -static const PinMap PinMap_I2C_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - - {NC, NC, 0} -}; - -static uint8_t repeated_start = 0; - -#define I2C_DAT(x) (x->i2c->MSTDAT) -#define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07)) - -static inline int i2c_status(i2c_t *obj) { - return I2C_STAT(obj); -} - -// Wait until the Serial Interrupt (SI) is set -static int i2c_wait_SI(i2c_t *obj) { - int timeout = 0; - while (!(obj->i2c->STAT & (1 << 0))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} - -static inline void i2c_interface_enable(i2c_t *obj) { - obj->i2c->CFG |= (1 << 0); -} - -static inline void i2c_power_enable(i2c_t *obj) { - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<5); - LPC_SYSCON->PRESETCTRL &= ~(0x1<<6); - LPC_SYSCON->PRESETCTRL |= (0x1<<6); -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) { - obj->i2c = (LPC_I2C_TypeDef *)LPC_I2C; - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_I2C_SDA[0]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (sda << swm->offset); - - swm = &SWM_I2C_SCL[0]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (scl << swm->offset); - - // enable power - i2c_power_enable(obj); - // set default frequency at 100k - i2c_frequency(obj, 100000); - i2c_interface_enable(obj); -} - -//Actually Wrong. Spec says: First store Address in DAT before setting STA ! -//Undefined state when using single byte I2C operations and too much delay -//between i2c_start and do_i2c_write(Address). -//Also note that lpc812 will immediately continue reading a byte when Address b0 == 1 -inline int i2c_start(i2c_t *obj) { - int status = 0; - if (repeated_start) { - obj->i2c->MSTCTL = (1 << 1) | (1 << 0); - repeated_start = 0; - } else { - obj->i2c->MSTCTL = (1 << 1); - } - return status; -} - -//Generate Stop condition and wait until bus is Idle -//Will also send NAK for previous RD -inline int i2c_stop(i2c_t *obj) { - int timeout = 0; - - obj->i2c->MSTCTL = (1 << 2) | (1 << 0); // STP bit and Continue bit. Sends NAK to complete previous RD - - //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000) - while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { - timeout ++; - if (timeout > 100000) return 1; - } - - return 0; -} - -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { - // write the data - I2C_DAT(obj) = value; - - if (!addr) - obj->i2c->MSTCTL = (1 << 0); - - // wait and return status - i2c_wait_SI(obj); - return i2c_status(obj); -} - -static inline int i2c_do_read(i2c_t *obj, int last) { - // wait for it to arrive - i2c_wait_SI(obj); - if (!last) - obj->i2c->MSTCTL = (1 << 0); - - // return the data - return (I2C_DAT(obj) & 0xFF); -} - -void i2c_frequency(i2c_t *obj, int hz) { - // No peripheral clock divider on the M0 - uint32_t PCLK = SystemCoreClock; - - uint32_t clkdiv = PCLK / (hz * 4) - 1; - - obj->i2c->DIV = clkdiv; - obj->i2c->MSTTIME = 0; -} - -// The I2C does a read or a write as a whole operation -// There are two types of error conditions it can encounter -// 1) it can not obtain the bus -// 2) it gets error responses at part of the transmission -// -// We tackle them as follows: -// 1) we retry until we get the bus. we could have a "timeout" if we can not get it -// which basically turns it in to a 2) -// 2) on error, we use the standard error mechanisms to report/debug -// -// Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically -// check for that - -//New version WH, Tested OK for Start and Repeated Start -//Old version was Wrong: Calls i2c_start without setting address, i2c_do_read continues before checking status, status check for wrong value -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count, status; - - //Store the address+RD and then generate STA - I2C_DAT(obj) = address | 0x01; - i2c_start(obj); - - // Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte - i2c_wait_SI(obj); - status = i2c_status(obj); - if (status == 0x03) { // NAK on SlaveAddress - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // Read in all except last byte - for (count = 0; count < (length-1); count++) { - - // Wait for it to arrive, note that first byte read after address+RD is already waiting - i2c_wait_SI(obj); - status = i2c_status(obj); - if (status != 0x01) { // RX RDY - i2c_stop(obj); - return count; - } - data[count] = I2C_DAT(obj) & 0xFF; // Store read byte - - obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read - } - - // Read final byte - // Wait for it to arrive - i2c_wait_SI(obj); - - status = i2c_status(obj); - if (status != 0x01) { // RX RDY - i2c_stop(obj); - return count; - } - data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); // Also sends NAK for last read byte - } else { - repeated_start = 1; - } - - return length; -} - - - -//New version WH, Tested OK for Start and Repeated Start -//Old version was Wrong: Calls i2c_start without setting address first -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i, status; - - //Store the address+/WR and then generate STA - I2C_DAT(obj) = address & 0xFE; - i2c_start(obj); - - // Wait for completion of STA and Sending of SlaveAddress+/WR - i2c_wait_SI(obj); - status = i2c_status(obj); - if (status == 0x03) { // NAK SlaveAddress - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - //Write all bytes - for (i=0; ii2c->SLVDAT) -#define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03)) -#define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01)) -//#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0)) -//#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1)) - -#if(0) -// Wait until the Slave Serial Interrupt (SI) is set -// Timeout when it takes too long. -static int i2c_wait_slave_SI(i2c_t *obj) { - int timeout = 0; - while (!(obj->i2c->STAT & (1 << 8))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} -#endif - -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - - if (enable_slave) { -// obj->i2c->CFG &= ~(1 << 0); //Disable Master mode - obj->i2c->CFG |= (1 << 1); //Enable Slave mode - } - else { -// obj->i2c->CFG |= (1 << 0); //Enable Master mode - obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode - } -} - -// Wait for next I2C event and find out what is going on -// -int i2c_slave_receive(i2c_t *obj) { - int addr; - - // Check if there is any data pending - if (! I2C_SLVSI(obj)) { - return 0; //NoData - }; - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - - // Get the received address - addr = I2C_SLVDAT(obj) & 0xFF; - // Send ACK on address and Continue - obj->i2c->SLVCTL = (1 << 0); - - if (addr == 0x00) { - return 2; //WriteGeneral - } - //check the RW bit - if ((addr & 0x01) == 0x01) { - return 1; //ReadAddressed - } - else { - return 3; //WriteAddressed - } - //break; - - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - // Oops, should never get here... - obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover... - return 0; //NoData - - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - // Oops, should never get here... - I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission - obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... - return 0; //NoData - - case 0x3: // Reserved. - default: // Oops, should never get here... - obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... - return 0; //NoData - //break; - } //switch status -} - -// The dedicated I2C Slave byte read and byte write functions need to be called -// from 'common' mbed I2CSlave API for devices that have separate Master and -// Slave engines such as the lpc812 and lpc1549. - -//Called when Slave is addressed for Write, Slave will receive Data in polling mode -//Parameter last=1 means received byte will be NACKed. -int i2c_slave_byte_read(i2c_t *obj, int last) { - int data; - - // Wait for data - while (!I2C_SLVSI(obj)); // Wait forever -//if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Dont bother to check State, were not returning it anyhow.. -//if (I2C_SLVSTAT(obj)) == 0x01) { - // Slave receive. Received data is available (Slave Receiver mode). -//}; - - data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data - if (last) { - obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue - } - else { - obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read - } - - return data; -} - - -//Called when Slave is addressed for Read, Slave will send Data in polling mode -// -int i2c_slave_byte_write(i2c_t *obj, int data) { - - // Wait until Ready - while (!I2C_SLVSI(obj)); // Wait forever -// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - // I2C Restart occurred - return -1; - //break; - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - // Should not get here... - return -2; - //break; - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission - obj->i2c->SLVCTL = (1 << 0); // Continue to send - - return 1; - //break; - case 0x3: // Reserved. - default: - // Should not get here... - return -3; - //break; - } // switch status -} - - -//Called when Slave is addressed for Write, Slave will receive Data in polling mode -//Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed. -int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count=0; - - // Read and ACK all expected bytes - while (count < length) { - // Wait for data - while (!I2C_SLVSI(obj)); // Wait forever -// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - // I2C Restart occurred - return -1; - //break; - - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data - obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read - break; - - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - case 0x3: // Reserved. - default: // Should never get here... - return -2; - //break; - } // switch status - - count++; - } // for all bytes - - return count; // Received the expected number of bytes -} - - -//Called when Slave is addressed for Read, Slave will send Data in polling mode -//Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed. -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int count; - - // Send and all bytes or Exit on NAK - for (count=0; count < length; count++) { - // Wait until Ready for data - while (!I2C_SLVSI(obj)); // Wait forever -// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - // I2C Restart occurred - return -1; - //break; - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - // Should not get here... - return -2; - //break; - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission - obj->i2c->SLVCTL = (1 << 0); // Continue to send - break; - case 0x3: // Reserved. - default: - // Should not get here... - return -3; - //break; - } // switch status - } // for all bytes - - return length; // Transmitted the max number of bytes -} - - -// Set the four slave addresses. -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register - obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register - obj->i2c->SLVADR2 = (0x01); // Disable address 2 register - obj->i2c->SLVADR3 = (0x01); // Disable address 3 register - obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match -} - -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/objects.h b/targets/TARGET_NXP/TARGET_LPC81X/objects.h deleted file mode 100644 index 819420f9a5..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/objects.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t ch; -}; - -struct serial_s { - LPC_USART_TypeDef *uart; - unsigned char index; -}; - -struct i2c_s { - LPC_I2C_TypeDef *i2c; -}; - -struct spi_s { - LPC_SPI_TypeDef *spi; - unsigned char spi_n; -}; - -struct pwmout_s { - LPC_SCT_TypeDef* pwm; - uint32_t pwm_ch; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/pinmap.c b/targets/TARGET_NXP/TARGET_LPC81X/pinmap.c deleted file mode 100644 index 5fb31fe981..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/pinmap.c +++ /dev/null @@ -1,61 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" - -__IO uint32_t* IOCON_REGISTERS[18] = { - &LPC_IOCON->PIO0_0 , &LPC_IOCON->PIO0_1 , &LPC_IOCON->PIO0_2 , - &LPC_IOCON->PIO0_3 , &LPC_IOCON->PIO0_4 , &LPC_IOCON->PIO0_5 , - &LPC_IOCON->PIO0_6 , &LPC_IOCON->PIO0_7 , &LPC_IOCON->PIO0_8 , - &LPC_IOCON->PIO0_9 , &LPC_IOCON->PIO0_10, &LPC_IOCON->PIO0_11, - &LPC_IOCON->PIO0_12, &LPC_IOCON->PIO0_13, &LPC_IOCON->PIO0_14, - &LPC_IOCON->PIO0_15, &LPC_IOCON->PIO0_16, &LPC_IOCON->PIO0_17, -}; - -void pin_function(PinName pin, int function) { - if (function == 0) { - // Disable initial fixed function for P0_2, P0_3 and P0_5 - uint32_t enable = 0; - if (pin == P0_2) - enable = 1 << 3; - else if (pin == P0_3) - enable = 1 << 2; - else if (pin == P0_5) - enable = 1 << 6; - LPC_SWM->PINENABLE0 |= enable; - } -} - -void pin_mode(PinName pin, PinMode mode) { - MBED_ASSERT(pin != (PinName)NC); - - if ((pin == 10) || (pin == 11)) { - // True open-drain pins can be configured for different I2C-bus speeds - return; - } - - __IO uint32_t *reg = IOCON_REGISTERS[pin]; - - if (mode == OpenDrain) { - *reg |= (1 << 10); - } else { - uint32_t tmp = *reg; - tmp &= ~(0x3 << 3); - tmp |= (mode & 0x3) << 3; - *reg = tmp; - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c b/targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c deleted file mode 100644 index ef135dc830..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/pwmout_api.c +++ /dev/null @@ -1,277 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -// Ported from LPC824 and adapted. - -#if DEVICE_PWMOUT - -#define PWM_IRQn SCT_IRQn - -// Bit flags for used SCT Outputs -static unsigned char sct_used = 0; -static int sct_inited = 0; - -// Pinmap used for testing only -static const PinMap PinMap_PWM_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - - {NC, NC, 0} -}; - -// Find available output channel -// Max number of PWM outputs is 4 on LPC812 -static int get_available_sct() { - int i; - -// Find available output channel 0..3 -// Also need one Match register per channel - for (i = 0; i < CONFIG_SCT_nOU; i++) { - if ((sct_used & (1 << i)) == 0) - return i; - } - return -1; -} - -// Any Port pin may be used for PWM. -// Max number of PWM outputs is 4 -void pwmout_init(pwmout_t* obj, PinName pin) { - MBED_ASSERT(pin != (PinName)NC); - - int sct_n = get_available_sct(); - if (sct_n == -1) { - error("No available SCT Output"); - } - - sct_used |= (1 << sct_n); - - obj->pwm = (LPC_SCT_TypeDef*)LPC_SCT; - obj->pwm_ch = sct_n; - - LPC_SCT_TypeDef* pwm = obj->pwm; - - // Init SCT on first use - if (! sct_inited) { - sct_inited = 1; - - // Enable the SCT clock - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); - - // Clear peripheral reset the SCT: - LPC_SYSCON->PRESETCTRL |= (1 << 8); - - // Two 16-bit counters, autolimit (ie reset on Match_0) - pwm->CONFIG |= ((0x3 << 17) | 0x01); - - // halt and clear the counter - pwm->CTRL_U |= (1 << 2) | (1 << 3); - - // System Clock (30 Mhz) -> Prescaler -> us_ticker (1 MHz) - pwm->CTRL_U &= ~(0x7F << 5); - pwm->CTRL_U |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5); - - pwm->EVENT[0].CTRL = (1 << 12) | 0; // Event_0 on Match_0 - pwm->EVENT[0].STATE = 0xFFFFFFFF; // All states - - // unhalt the counter: - // - clearing bit 2 of the CTRL register - pwm->CTRL_U &= ~(1 << 2); - - } - - // LPC81x has only one SCT and 4 Outputs - // LPC82x has only one SCT and 6 Outputs - switch(sct_n) { - case 0: - // SCTx_OUT0 - LPC_SWM->PINASSIGN[6] &= ~0xFF000000; - LPC_SWM->PINASSIGN[6] |= (pin << 24); - break; - case 1: - // SCTx_OUT1 - LPC_SWM->PINASSIGN[7] &= ~0x000000FF; - LPC_SWM->PINASSIGN[7] |= (pin); - break; - case 2: - // SCTx_OUT2 - LPC_SWM->PINASSIGN[7] &= ~0x0000FF00; - LPC_SWM->PINASSIGN[7] |= (pin << 8); - break; - case 3: - // SCTx_OUT3 - LPC_SWM->PINASSIGN[7] &= ~0x00FF0000; - LPC_SWM->PINASSIGN[7] |= (pin << 16); - break; - default: - break; - } - - pwm->EVENT[sct_n + 1].CTRL = (1 << 12) | (sct_n + 1); // Event_n on Match_n - pwm->EVENT[sct_n + 1].STATE = 0xFFFFFFFF; // All states - - pwm->OUT[sct_n].SET = (1 << 0); // All PWM channels are SET on Event_0 - pwm->OUT[sct_n].CLR = (1 << (sct_n + 1)); // PWM ch is CLRed on Event_(ch+1) - - // default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_ms(obj, 20); // 20ms period - pwmout_write (obj, 0.0); // 0ms pulsewidth, dutycycle 0 -} - -void pwmout_free(pwmout_t* obj) { - // PWM channel is now free - sct_used &= ~(1 << obj->pwm_ch); - - // Disable the SCT clock when all channels free - if (sct_used == 0) { - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); - sct_inited = 0; - }; -} - -// Set new dutycycle (0.0 .. 1.0) -void pwmout_write(pwmout_t* obj, float value) { - //value is new dutycycle - if (value < 0.0f) { - value = 0.0; - } else if (value > 1.0f) { - value = 1.0; - } - - // Match_0 is PWM period. Compute new endtime of pulse for current channel - uint32_t t_off = (uint32_t)((float)(obj->pwm->MATCHREL[0].U) * value); - obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = t_off; // New endtime - - // Clear OxRES (conflict resolution register) bit first, effect of simultaneous set and clear on output x - int offset = (obj->pwm_ch * 2); - obj->pwm->RES &= ~(0x3 << offset); - - if (value == 0.0f) { // duty is 0% - // Clear output - obj->pwm->RES |= (0x2 << offset); - // Set CLR event to be same as SET event, makes output to be 0 (low) - obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << 0); - } else { - // Set output - obj->pwm->RES |= (0x1 << offset); - // Use normal CLR event (current SCT ch + 1) - obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << ((obj->pwm_ch) + 1)); - } -} - -// Get dutycycle (0.0 .. 1.0) -float pwmout_read(pwmout_t* obj) { - uint32_t t_period = obj->pwm->MATCHREL[0].U; - - //Sanity check - if (t_period == 0) { - return 0.0; - }; - - uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U; - float v = (float)t_off/(float)t_period; - //Sanity check - return (v > 1.0f) ? (1.0f) : (v); -} - -// Set the PWM period, keeping the duty cycle the same (for this channel only!). -void pwmout_period(pwmout_t* obj, float seconds){ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -// Set the PWM period, keeping the duty cycle the same (for this channel only!). -void pwmout_period_ms(pwmout_t* obj, int ms) { - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same (for this channel only!). -void pwmout_period_us(pwmout_t* obj, int us) { - - uint32_t t_period = obj->pwm->MATCHREL[0].U; // Current PWM period - obj->pwm->MATCHREL[0].U = (uint32_t)us; // New PWM period - - // Sanity check - if (t_period == 0) { - return; - } - else { - int cnt = sct_used; - int ch = 0; - // Update match period for exising PWM channels - do { - // Get current pulse width - uint32_t t_off = obj->pwm->MATCHREL[ch + 1].U; - // Get the duty - float v = (float)t_off/(float)t_period; - // Update pulse width for this channel - obj->pwm->MATCHREL[ch + 1].U = (uint32_t)((float)us * (float)v); - // Get next used SCT channel - cnt = cnt >> 1; - ch++; - } while (cnt != 0); - } -} - - -//Set pulsewidth -void pwmout_pulsewidth(pwmout_t* obj, float seconds) { - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -//Set pulsewidth -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms){ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -//Set pulsewidth -void pwmout_pulsewidth_us(pwmout_t* obj, int us) { - if (us == 0) { // pulse width is 0 - // Set CLR event to be same as SET event, makes output to be 0 (low) - obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << 0); - } else { - // Use normal CLR event (current SCT ch + 1) - obj->pwm->OUT[(obj->pwm_ch)].CLR = (1 << ((obj->pwm_ch) + 1)); - } -//Should add Sanity check to make sure pulsewidth < period! - obj->pwm->MATCHREL[(obj->pwm_ch) + 1].U = (uint32_t)us; // New endtime for this channel -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM_testing; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/serial_api.c b/targets/TARGET_NXP/TARGET_LPC81X/serial_api.c deleted file mode 100644 index ebb6dcd24c..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/serial_api.c +++ /dev/null @@ -1,374 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include "mbed_assert.h" -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 3 - -static const SWM_Map SWM_UART_TX[] = { - {0, 0}, - {1, 8}, - {2, 16}, -}; - -static const SWM_Map SWM_UART_RX[] = { - {0, 8}, - {1, 16}, - {2, 24}, -}; - -static const SWM_Map SWM_UART_RTS[] = { - {0, 16}, - {1, 24}, - {3, 0}, -}; - -static const SWM_Map SWM_UART_CTS[] = { - {0, 24}, - {2, 0}, - {3, 8} -}; - -// Pinmap used for testing only -static const PinMap PinMap_UART_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - - {NC, NC, 0} -}; - -// bit flags for used UARTs -static unsigned char uart_used = 0; -static int get_available_uart(void) { - int i; - for (i=0; i<3; i++) { - if ((uart_used & (1 << i)) == 0) - return i; - } - return -1; -} - -#define UART_EN (0x01<<0) - -#define CTS_DELTA (0x01<<5) -#define RXBRK (0x01<<10) -#define DELTA_RXBRK (0x01<<11) - -#define RXRDY (0x01<<0) -#define TXRDY (0x01<<2) - -#define TXBRKEN (0x01<<1) -#define CTSEN (0x01<<9) - -static uint32_t UARTSysClk; - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - int is_stdio_uart = 0; - - int uart_n = get_available_uart(); - if (uart_n == -1) { - error("No available UART"); - } - obj->index = uart_n; - obj->uart = (LPC_USART_TypeDef *)(LPC_USART0_BASE + (0x4000 * uart_n)); - uart_used |= (1 << uart_n); - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_UART_TX[uart_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (tx << swm->offset); - - swm = &SWM_UART_RX[uart_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (rx << swm->offset); - - /* uart clock divided by 1 */ - LPC_SYSCON->UARTCLKDIV = 1; - - /* disable uart interrupts */ - NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); - - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n)); - - /* Peripheral reset control to UART, a "1" bring it out of reset. */ - LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n)); - LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n)); - - // Derive UART Clock from MainClock - UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV; - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - /* Clear all status bits. */ - obj->uart->STAT = CTS_DELTA | DELTA_RXBRK; - - /* enable uart interrupts */ - NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); - - /* Enable UART interrupt */ - // obj->uart->INTENSET = RXRDY | TXRDY | DELTA_RXBRK; - - /* Enable UART */ - obj->uart->CFG |= UART_EN; - - is_stdio_uart = ((tx == USBTX) && (rx == USBRX)); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) { - uart_used &= ~(1 << obj->index); - serial_irq_ids[obj->index] = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) { - /* Integer divider: - BRG = UARTSysClk/(Baudrate * 16) - 1 - - Frational divider: - FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1) - - where - FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1) - - (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB - register is 0xFF. - (2) In ADD register value, depending on the value of UartSysClk, - baudrate, BRG register value, and SUB register value, be careful - about the order of multiplier and divider and make sure any - multiplier doesn't exceed 32-bit boundary and any divider doesn't get - down below one(integer 0). - (3) ADD should be always less than SUB. - */ - obj->uart->BRG = UARTSysClk / 16 / baudrate - 1; - - LPC_SYSCON->UARTFRGDIV = 0xFF; - LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) / - (baudrate * (obj->uart->BRG + 1)) - ) - (LPC_SYSCON->UARTFRGDIV + 1); - -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) { - // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd)); - stop_bits -= 1; - data_bits -= 7; - - int paritysel = 0; - switch (parity) { - case ParityNone: paritysel = 0; break; - case ParityEven: paritysel = 2; break; - case ParityOdd : paritysel = 3; break; - default: - break; - } - - // First disable the the usart as described in documentation and then enable while updating CFG - - // 24.6.1 USART Configuration register - // Remark: If software needs to change configuration values, the following sequence should - // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable - // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3) - // Write the new configuration value, with the ENABLE bit set to 1. - obj->uart->CFG &= ~(1 << 0); - - obj->uart->CFG = (1 << 0) // this will enable the usart - | (data_bits << 2) - | (paritysel << 4) - | (stop_bits << 6); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(uint32_t iir, uint32_t index) { - // [Chapter 14] LPC17xx UART0/2/3: UARTn Interrupt Handling - SerialIrq irq_type; - switch (iir) { - case 1: irq_type = TxIrq; break; - case 2: irq_type = RxIrq; break; - default: return; - } - - if (serial_irq_ids[index] != 0) - irq_handler(serial_irq_ids[index], irq_type); -} - -void uart0_irq() {uart_irq((LPC_USART0->STAT & (1 << 2)) ? 2 : 1, 0);} -void uart1_irq() {uart_irq((LPC_USART1->STAT & (1 << 2)) ? 2 : 1, 1);} -void uart2_irq() {uart_irq((LPC_USART2->STAT & (1 << 2)) ? 2 : 1, 2);} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) { - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; - case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; - case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; - } - - if (enable) { - obj->uart->INTENSET = (1 << ((irq == RxIrq) ? 0 : 2)); - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { // disable - int all_disabled = 0; - SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq); - obj->uart->INTENSET &= ~(1 << ((irq == RxIrq) ? 0 : 2)); - all_disabled = (obj->uart->INTENSET & (1 << ((other_irq == RxIrq) ? 0 : 2))) == 0; - if (all_disabled) - NVIC_DisableIRQ(irq_n); - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) { - while (!serial_readable(obj)); - return obj->uart->RXDATA; -} - -void serial_putc(serial_t *obj, int c) { - while (!serial_writable(obj)); - obj->uart->TXDATA = c; -} - -int serial_readable(serial_t *obj) { - return obj->uart->STAT & RXRDY; -} - -int serial_writable(serial_t *obj) { - return obj->uart->STAT & TXRDY; -} - -void serial_clear(serial_t *obj) { - // [TODO] -} - -void serial_pinout_tx(PinName tx) { - -} - -void serial_break_set(serial_t *obj) { - obj->uart->CTRL |= TXBRKEN; -} - -void serial_break_clear(serial_t *obj) { - obj->uart->CTRL &= ~TXBRKEN; -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { - const SWM_Map *swm_rts, *swm_cts; - uint32_t regVal_rts, regVal_cts; - - swm_rts = &SWM_UART_RTS[obj->index]; - swm_cts = &SWM_UART_CTS[obj->index]; - regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset); - regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset); - - if (FlowControlNone == type) { - LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset); - LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset); - obj->uart->CFG &= ~CTSEN; - return; - } - if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) { - LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (rxflow << swm_rts->offset); - if (FlowControlRTS == type) { - LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset); - obj->uart->CFG &= ~CTSEN; - } - } - if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) { - LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (txflow << swm_cts->offset); - obj->uart->CFG |= CTSEN; - if (FlowControlCTS == type) { - LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset); - } - } -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_testing; -} - diff --git a/targets/TARGET_NXP/TARGET_LPC81X/sleep.c b/targets/TARGET_NXP/TARGET_LPC81X/sleep.c deleted file mode 100644 index e0c1aa5208..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/sleep.c +++ /dev/null @@ -1,82 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" - - -//#define DEEPSLEEP -#define POWERDOWN - -void hal_sleep(void) { - //Normal sleep mode for PCON: - LPC_PMU->PCON &= ~0x03; - - //Normal sleep mode for ARM core: - SCB->SCR = 0; - - //And go to sleep - __WFI(); -} - - - -//Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly - -#ifdef DEEPSLEEP -void hal_deepsleep(void) { - //Deep sleep in PCON - LPC_PMU->PCON &= ~0x03; - LPC_PMU->PCON |= 0x01; - - //If brownout detection and WDT are enabled, keep them enabled during sleep - LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG; - - //After wakeup same stuff as currently enabled: - LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG; - - //All interrupts may wake up: - LPC_SYSCON->STARTERP0 = 0xFF; - LPC_SYSCON->STARTERP1 = 0xFFFF; - - //Deep sleep for ARM core: - SCB->SCR = 1<<2; - - __WFI(); -} -#endif - -#ifdef POWERDOWN -void hal_deepsleep(void) { - //Powerdown in PCON - LPC_PMU->PCON &= ~0x03; - LPC_PMU->PCON |= 0x02; - - //If brownout detection and WDT are enabled, keep them enabled during sleep - LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG; - - //After wakeup same stuff as currently enabled: - LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG; - - //All interrupts may wake up: - LPC_SYSCON->STARTERP0 = 0xFF; - LPC_SYSCON->STARTERP1 = 0xFFFF; - - //Deep sleep for ARM core: - SCB->SCR = 1<<2; - - __WFI(); -} -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC81X/spi_api.c b/targets/TARGET_NXP/TARGET_LPC81X/spi_api.c deleted file mode 100644 index 7eaed090fb..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/spi_api.c +++ /dev/null @@ -1,275 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include - -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -static const SWM_Map SWM_SPI_SSEL[] = { - {4, 16}, - {5, 16}, -}; - -static const SWM_Map SWM_SPI_SCLK[] = { - {3, 24}, - {4, 24}, -}; - -static const SWM_Map SWM_SPI_MOSI[] = { - {4, 0}, - {5, 0}, -}; - -static const SWM_Map SWM_SPI_MISO[] = { - {4, 8}, - {5, 16}, -}; - -// Pinmap used for testing only -static const PinMap PinMap_SPI_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - - {NC, NC, 0} -}; - -// bit flags for used SPIs -static unsigned char spi_used = 0; -static int get_available_spi(void) { - int i; - for (i=0; i<2; i++) { - if ((spi_used & (1 << i)) == 0) - return i; - } - return -1; -} - -static inline int ssp_disable(spi_t *obj); -static inline int ssp_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) { - int spi_n = get_available_spi(); - if (spi_n == -1) { - error("No available SPI"); - } - obj->spi_n = spi_n; - spi_used |= (1 << spi_n); - - obj->spi = (spi_n) ? (LPC_SPI_TypeDef *)(LPC_SPI1_BASE) : (LPC_SPI_TypeDef *)(LPC_SPI0_BASE); - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_SPI_SCLK[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (sclk << swm->offset); - - swm = &SWM_SPI_MOSI[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (mosi << swm->offset); - - swm = &SWM_SPI_MISO[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (miso << swm->offset); - - swm = &SWM_SPI_SSEL[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | (ssel << swm->offset); - - // clear interrupts - obj->spi->INTENCLR = 0x3f; - - // enable power and clocking - switch (obj->spi_n) { - case 0: - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<11); - LPC_SYSCON->PRESETCTRL &= ~(0x1<<0); - LPC_SYSCON->PRESETCTRL |= (0x1<<0); - break; - case 1: - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<12); - LPC_SYSCON->PRESETCTRL &= ~(0x1<<1); - LPC_SYSCON->PRESETCTRL |= (0x1<<1); - break; - } -} - -void spi_free(spi_t *obj) {} - -void spi_format(spi_t *obj, int bits, int mode, int slave) { - MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); - ssp_disable(obj); - - int polarity = (mode & 0x2) ? 1 : 0; - int phase = (mode & 0x1) ? 1 : 0; - - // set it up - int DSS = bits - 1; // DSS (data select size) - int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity - int SPH = (phase) ? 1 : 0; // SPH - clock out phase - - uint32_t tmp = obj->spi->CFG; - tmp &= ~((1 << 2) | (1 << 4) | (1 << 5)); - tmp |= (SPH << 4) | (SPO << 5) | ((slave ? 0 : 1) << 2); - obj->spi->CFG = tmp; - - // select frame length - tmp = obj->spi->TXDATCTL; - tmp &= ~(0xf << 24); - tmp |= (DSS << 24); - obj->spi->TXDATCTL = tmp; - - ssp_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) { - ssp_disable(obj); - - uint32_t PCLK = SystemCoreClock; - - obj->spi->DIV = PCLK/hz - 1; - obj->spi->DLY = 0; - ssp_enable(obj); -} - -static inline int ssp_disable(spi_t *obj) { - return obj->spi->CFG &= ~(1 << 0); -} - -static inline int ssp_enable(spi_t *obj) { - return obj->spi->CFG |= (1 << 0); -} - -static inline int ssp_readable(spi_t *obj) { - return obj->spi->STAT & (1 << 0); -} - -static inline int ssp_writeable(spi_t *obj) { - return obj->spi->STAT & (1 << 1); -} - -static inline void ssp_write(spi_t *obj, int value) { - while (!ssp_writeable(obj)); - // end of transfer - obj->spi->TXDATCTL |= (1 << 20); - obj->spi->TXDAT = value; -} - -static inline int ssp_read(spi_t *obj) { - while (!ssp_readable(obj)); - return obj->spi->RXDAT; -} - -static inline int ssp_busy(spi_t *obj) { - // checking RXOV(Receiver Overrun interrupt flag) - return obj->spi->STAT & (1 << 2); - } - -int spi_master_write(spi_t *obj, int value) { - ssp_write(obj, value); - return ssp_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) { - return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0); -} - -int spi_slave_read(spi_t *obj) { - return obj->spi->RXDAT; -} - -void spi_slave_write(spi_t *obj, int value) { - while (ssp_writeable(obj) == 0) ; - obj->spi->TXDAT = value; -} - -int spi_busy(spi_t *obj) { - return ssp_busy(obj); -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_testing; -} diff --git a/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c b/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c deleted file mode 100644 index b99a72a474..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC81X/us_ticker.c +++ /dev/null @@ -1,143 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -//New, using MRT instead of SCT, needed to free up SCT for PWM -//Ported from LPC824 libs -static int us_ticker_inited = 0; -static int us_ticker_interrupt_inited = 0; -unsigned int ticker_fullcount_us; -unsigned long int ticker_expired_count_us = 0; -int MRT_Clock_MHz; - -#define US_TICKER_TIMER_IRQn MRT_IRQn - -void us_ticker_init(void) { - - if (us_ticker_inited) - return; - - us_ticker_inited = 1; - - // Calculate MRT clock value (MRT has no prescaler) - MRT_Clock_MHz = (SystemCoreClock / 1000000); - // Calculate fullcounter value in us (MRT has 31 bits and clock is 30 MHz) - ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz; - - // Enable the MRT clock - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); - - // Clear peripheral reset the MRT - LPC_SYSCON->PRESETCTRL |= (1 << 7); - - // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) - LPC_MRT->INTVAL0 = 0xFFFFFFFFUL; - // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt - LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0); - - // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) - LPC_MRT->INTVAL1 = 0x80000000UL; - // Disable ch1 interrupt, Mode 0 is Repeat Interrupt - LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0); -} - -void us_ticker_interrupt_init(void) { - - if (us_ticker_interrupt_inited) - return; - - us_ticker_interrupt_inited = 1; - - // Set MRT interrupt vector - NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -//TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc) -uint32_t us_ticker_read() { - - if (!us_ticker_inited) - us_ticker_init(); - - // Generate ticker value - // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer - // Calculate expected value using current count and number of expired times to mimic a 32bit timer @ 1 MHz - // - // ticker_expired_count_us - // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and - // corrects that back to us counts. - // - // (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz - // The counter is a 31bit downcounter from 7FFFFFFF so correct to actual count-up value and correct - // for 30 counts per us. - // - // Added up these 2 parts result in current us time returned as 32 bits. - return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us; -} - -//TIMER1 is used for Timestamped interrupts (Ticker(), Timeout()) -void us_ticker_set_interrupt(timestamp_t timestamp) { - - if (!us_ticker_interrupt_inited) - us_ticker_interrupt_init(); - - // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer - // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) - // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz. - // The calculated counter interval until the next timestamp will be truncated and an - // 'early' interrupt will be generated in case the max required count interval exceeds - // the available 31 bits space. However, the mbed us_ticker interrupt handler will - // check current time against the next scheduled timestamp and simply re-issue the - // same interrupt again when needed. The calculated counter interval will now be smaller. - LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL); - - // Enable interrupt - LPC_MRT->CTRL1 |= 1; -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); -} - -//Disable Timestamped interrupts triggered by TIMER1 -void us_ticker_disable_interrupt() { - //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) - LPC_MRT->CTRL1 &= ~1; -} - -void us_ticker_clear_interrupt() { - - //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) - if (LPC_MRT->STAT1 & 1) - LPC_MRT->STAT1 = 1; - - //Timer0 for us counter (31 bits downcounter @ SystemCoreClock) - if (LPC_MRT->STAT0 & 1) { - LPC_MRT->STAT0 = 1; - // ticker_expired_count_us = (ticker_expired * 0x80000000UL) / MRT_Clock_MHz - // The variable ticker_expired_count_us keeps track of the number of 31bits overflows (counted by TIMER0) and - // the multiplication/division corrects that back to us counts. - ticker_expired_count_us += ticker_fullcount_us; - } -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/PortNames.h b/targets/TARGET_NXP/TARGET_LPC82X/PortNames.h deleted file mode 100644 index bbd5b31103..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/PortNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0, -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h deleted file mode 100644 index 9cef1835a0..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PeripheralNames.h +++ /dev/null @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Default peripherals - -// SPI: MOSI, MISO, CLK, SEL -#define MBED_SPI0 P0_26, P0_25, P0_24, P0_15 - -#define MBED_UART0 P0_7, P0_18 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 P0_11, P0_10 - -typedef enum { - ADC_0 = 0, - ADC_1, - ADC_2, - ADC_3, - ADC_4, - ADC_5, - ADC_6, - ADC_7, - ADC_8, - ADC_9, - ADC_10, - ADC_11, -} ADCName; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h deleted file mode 100644 index a63498be03..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/PinNames.h +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PIN_SHIFT 8 - -typedef enum { -// LPC824 Pin Names (PIN[11:8] + IOCON offset[7:0]) - - P0_0 = ( 0 << PIN_SHIFT) | 0x44, - P0_1 = ( 1 << PIN_SHIFT) | 0x2C, - P0_2 = ( 2 << PIN_SHIFT) | 0x18, - P0_3 = ( 3 << PIN_SHIFT) | 0x14, - P0_4 = ( 4 << PIN_SHIFT) | 0x10, - P0_5 = ( 5 << PIN_SHIFT) | 0x0C, - P0_6 = ( 6 << PIN_SHIFT) | 0x40, - P0_7 = ( 7 << PIN_SHIFT) | 0x3C, - P0_8 = ( 8 << PIN_SHIFT) | 0x38, - P0_9 = ( 9 << PIN_SHIFT) | 0x34, - P0_10 = (10 << PIN_SHIFT) | 0x20, - P0_11 = (11 << PIN_SHIFT) | 0x1C, - P0_12 = (12 << PIN_SHIFT) | 0x08, - P0_13 = (13 << PIN_SHIFT) | 0x04, - P0_14 = (14 << PIN_SHIFT) | 0x48, - P0_15 = (15 << PIN_SHIFT) | 0x28, - P0_16 = (16 << PIN_SHIFT) | 0x24, - P0_17 = (17 << PIN_SHIFT) | 0x00, - P0_18 = (18 << PIN_SHIFT) | 0x78, - P0_19 = (19 << PIN_SHIFT) | 0x74, - P0_20 = (20 << PIN_SHIFT) | 0x70, - P0_21 = (21 << PIN_SHIFT) | 0x6C, - P0_22 = (22 << PIN_SHIFT) | 0x68, - P0_23 = (23 << PIN_SHIFT) | 0x64, - P0_24 = (24 << PIN_SHIFT) | 0x60, - P0_25 = (25 << PIN_SHIFT) | 0x5C, - P0_26 = (26 << PIN_SHIFT) | 0x58, - P0_27 = (27 << PIN_SHIFT) | 0x54, - P0_28 = (28 << PIN_SHIFT) | 0x50, - - D0 = P0_0, - D1 = P0_4, - D2 = P0_19, - D3 = P0_12, // LED_RED - D4 = P0_18, - D5 = P0_28, - D6 = P0_16, // LED_GREEN - D7 = P0_17, - D8 = P0_13, - D9 = P0_27, // LED_BLUE - D10 = P0_15, - D11 = P0_26, - D12 = P0_25, - D13 = P0_24, - D14 = P0_11, - D15 = P0_10, - - A0 = P0_6, - A1 = P0_14, - A2 = P0_23, - A3 = P0_22, - A4 = P0_21, - A5 = P0_20, - - // LPC824-MAX board - LED_RED = P0_12, - LED_GREEN = P0_16, - LED_BLUE = P0_27, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - // Serial to USB pins - USBTX = P0_7, - USBRX = P0_18, - - // I2C pins - SCL = P0_10, - SDA = P0_11, - I2C_SCL = P0_10, - I2C_SDA = P0_11, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -typedef struct { - unsigned char n; - unsigned char offset; -} SWM_Map; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h deleted file mode 100644 index 2427e752ea..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct deleted file mode 100644 index 8738dd7043..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct +++ /dev/null @@ -1,48 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 32K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x8000 -#endif - -; 4KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x2000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S deleted file mode 100644 index 744eda77ad..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S +++ /dev/null @@ -1,195 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC8xx.s -; * @purpose: CMSIS Cortex-M0+ Core Device Startup File -; * for the NXP LPC8xx Device Series -; * @version: V1.0 -; * @date: 16. Aug. 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C0_IRQHandler ; I2C0 controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD Flash_IRQHandler ; Flash interrupt - DCD WKT_IRQHandler ; Wakeup timer - DCD ADC_SEQA_IRQHandler ; ADC sequence A completion - DCD ADC_SEQB_IRQHandler ; ADC sequence B completion - DCD ADC_THCMP_IRQHandler ; ADC threshold compare - DCD ADC_OVR_IRQHandler ; ADC overrun - DCD DMA__RQHandler ; DMA interrupt - DCD I2C2_IRQHandler ; I2C2 controller - DCD I2C3_IRQHandler ; I2C3 controller - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT NMI_Handler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT MRT_IRQHandler [WEAK] - EXPORT CMP_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT Flash_IRQHandler [WEAK] - EXPORT WKT_IRQHandler [WEAK] - EXPORT ADC_SEQA_IRQHandler [WEAK] - EXPORT ADC_SEQB_IRQHandler [WEAK] - EXPORT ADC_THCMP_IRQHandler [WEAK] - EXPORT ADC_OVR_IRQHandler [WEAK] - EXPORT DMA__RQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT I2C3_IRQHandler [WEAK] - EXPORT PININT0_IRQHandler [WEAK] - EXPORT PININT1_IRQHandler [WEAK] - EXPORT PININT2_IRQHandler [WEAK] - EXPORT PININT3_IRQHandler [WEAK] - EXPORT PININT4_IRQHandler [WEAK] - EXPORT PININT5_IRQHandler [WEAK] - EXPORT PININT6_IRQHandler [WEAK] - EXPORT PININT7_IRQHandler [WEAK] - -NMI_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C1_IRQHandler -I2C0_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -Flash_IRQHandler -WKT_IRQHandler -ADC_SEQA_IRQHandler -ADC_SEQB_IRQHandler -ADC_THCMP_IRQHandler -ADC_OVR_IRQHandler -DMA__RQHandler -I2C2_IRQHandler -I2C3_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/LPC824.ld b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/LPC824.ld deleted file mode 100644 index 993670c7f8..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/LPC824.ld +++ /dev/null @@ -1,156 +0,0 @@ -/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* Define each memory region */ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */ - RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S deleted file mode 100644 index c4273d680b..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S +++ /dev/null @@ -1,228 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x80 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x80 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC824 interrupts */ - .long SPI0_IRQHandler // SPI0 controller - .long SPI1_IRQHandler // SPI1 controller - .long 0 // Reserved - .long UART0_IRQHandler // UART0 - .long UART1_IRQHandler // UART1 - .long UART2_IRQHandler // UART2 - .long 0 // Reserved - .long I2C1_IRQHandler // I2C ch1 controller - .long I2C0_IRQHandler // I2C ch0 controller - .long SCT_IRQHandler // Smart Counter Timer - .long MRT_IRQHandler // Multi-Rate Timer - .long CMP_IRQHandler // Comparator - .long WDT_IRQHandler // PIO1 (0:11) - .long BOD_IRQHandler // Brown Out Detect - .long Flash_IRQHandler // Flash interrupt - .long WKT_IRQHandler // Wakeup timer - .long ADC_SEQA_IRQHandler // ADC sequence A completion - .long ADC_SEQB_IRQHandler // ADC sequence B completion - .long ADC_THCMP_IRQHandler // ADC threshold compare - .long ADC_OVR_IRQHandler // ADC overrun - .long DMA_IRQHandler // DMA interrupt - .long I2C2_IRQHandler // I2C2 controller - .long I2C3_IRQHandler // I2C3 controller - .long 0 // Reserved - .long PININT0_IRQHandler // PIO INT0 - .long PININT1_IRQHandler // PIO INT1 - .long PININT2_IRQHandler // PIO INT2 - .long PININT3_IRQHandler // PIO INT3 - .long PININT4_IRQHandler // PIO INT4 - .long PININT5_IRQHandler // PIO INT5 - .long PININT6_IRQHandler // PIO INT6 - .long PININT7_IRQHandler // PIO INT7 - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler UART0_IRQHandler - def_irq_default_handler UART1_IRQHandler - def_irq_default_handler UART2_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler I2C2_IRQHandler - def_irq_default_handler I2C3_IRQHandler - def_irq_default_handler SCT_IRQHandler - def_irq_default_handler MRT_IRQHandler - def_irq_default_handler CMP_IRQHandler - def_irq_default_handler WDT_IRQHandler - def_irq_default_handler BOD_IRQHandler - def_irq_default_handler Flash_IRQHandler - def_irq_default_handler WKT_IRQHandler - def_irq_default_handler ADC_SEQA_IRQHandler - def_irq_default_handler ADC_SEQB_IRQHandler - def_irq_default_handler ADC_THCMP_IRQHandler - def_irq_default_handler ADC_OVR_IRQHandler - def_irq_default_handler DMA_IRQHandler - def_irq_default_handler PININT0_IRQHandler - def_irq_default_handler PININT1_IRQHandler - def_irq_default_handler PININT2_IRQHandler - def_irq_default_handler PININT3_IRQHandler - def_irq_default_handler PININT4_IRQHandler - def_irq_default_handler PININT5_IRQHandler - def_irq_default_handler PININT6_IRQHandler - def_irq_default_handler PININT7_IRQHandler - - .end - diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/LPC824.icf b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/LPC824.icf deleted file mode 100644 index f5a90aace8..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/LPC824.icf +++ /dev/null @@ -1,39 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00000000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x00000000; -define symbol __ICFEDIT_region_ROM_end__ = 0x00007FFF; -define symbol __ICFEDIT_region_NVIC_start__ = 0x10000000; -define symbol __ICFEDIT_region_NVIC_end__ = 0x100000BF; -define symbol __ICFEDIT_region_RAM_start__ = 0x100000C0; -define symbol __ICFEDIT_region_RAM_end__ = 0x10001FFF; -/*-Sizes-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0xA00; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __CRP_start__ = 0x000002FC; -define symbol __CRP_end__ = 0x000002FF; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__] - mem:[from __CRP_start__ to __CRP_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; -define region CRP_region = mem:[from __CRP_start__ to __CRP_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, block CSTACK }; -place in CRP_region { section .crp }; diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/startup_LPC8xx.S deleted file mode 100644 index e02868b54d..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/TOOLCHAIN_IAR/startup_LPC8xx.S +++ /dev/null @@ -1,216 +0,0 @@ -/************************************************** - * - * Part one of the system initialization code, contains low-level - * initialization, plain thumb variant. - * - * Copyright 2011 IAR Systems. All rights reserved. - * - * $Revision: 47876 $ - * - **************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C0_IRQHandler ; I2C0 controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD Flash_IRQHandler ; Flash interrupt - DCD WKT_IRQHandler ; Wakeup timer - DCD ADC_SEQA_IRQHandler ; ADC sequence A completion - DCD ADC_SEQB_IRQHandler ; ADC sequence B completion - DCD ADC_THCMP_IRQHandler ; ADC threshold compare - DCD ADC_OVR_IRQHandler ; ADC overrun - DCD DMA__RQHandler ; DMA interrupt - DCD I2C2_IRQHandler ; I2C2 controller - DCD I2C3_IRQHandler ; I2C3 controller - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; - - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - PUBWEAK HardFault_Handler - PUBWEAK SVC_Handler - PUBWEAK PendSV_Handler - PUBWEAK SysTick_Handler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK SCT_IRQHandler - PUBWEAK MRT_IRQHandler - PUBWEAK CMP_IRQHandler - PUBWEAK WDT_IRQHandler - PUBWEAK BOD_IRQHandler - PUBWEAK Flash_IRQHandler - PUBWEAK WKT_IRQHandler - PUBWEAK ADC_SEQA_IRQHandler - PUBWEAK ADC_SEQB_IRQHandler - PUBWEAK ADC_THCMP_IRQHandler - PUBWEAK ADC_OVR_IRQHandler - PUBWEAK DMA__RQHandler - PUBWEAK I2C2_IRQHandler - PUBWEAK I2C3_IRQHandler - PUBWEAK PININT0_IRQHandler - PUBWEAK PININT1_IRQHandler - PUBWEAK PININT2_IRQHandler - PUBWEAK PININT3_IRQHandler - PUBWEAK PININT4_IRQHandler - PUBWEAK PININT5_IRQHandler - PUBWEAK PININT6_IRQHandler - PUBWEAK PININT7_IRQHandler - - SECTION .text:CODE:REORDER:NOROOT(1) - THUMB - -NMI_Handler -HardFault_Handler -SVC_Handler -PendSV_Handler -SysTick_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C1_IRQHandler -I2C0_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -Flash_IRQHandler -WKT_IRQHandler -ADC_SEQA_IRQHandler -ADC_SEQB_IRQHandler -ADC_THCMP_IRQHandler -ADC_OVR_IRQHandler -DMA__RQHandler -I2C2_IRQHandler -I2C3_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler -Default_IRQHandler - B Default_IRQHandler - - SECTION .crp:CODE:ROOT(2) - DATA -/* Code Read Protection -NO_ISP 0x4E697370 - Prevents sampling of pin PIO0_1 for entering ISP mode -CRP1 0x12345678 - Write to RAM command cannot access RAM below 0x10000300. - - Copy RAM to flash command can not write to Sector 0. - - Erase command can erase Sector 0 only when all sectors - are selected for erase. - - Compare command is disabled. - - Read Memory command is disabled. -CRP2 0x87654321 - Read Memory is disabled. - - Write to RAM is disabled. - - "Go" command is disabled. - - Copy RAM to flash is disabled. - - Compare is disabled. -CRP3 0x43218765 - Access to chip via the SWD pins is disabled. ISP entry - by pulling PIO0_1 LOW is disabled if a valid user code is - present in flash sector 0. -Caution: If CRP3 is selected, no future factory testing can be -performed on the device. -*/ - DCD 0xFFFFFFFF - - END diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/system_LPC8xx.c b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/system_LPC8xx.c deleted file mode 100644 index 3deb912eb7..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_LPC824/device/system_LPC8xx.c +++ /dev/null @@ -1,389 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.c - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#include -#include "LPC82x.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ----------------------------------*/ -// -// Clock Configuration -#define CLOCK_SETUP 1 -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.6 MHz -// <2=> 1.05 MHz -// <3=> 1.4 MHz -// <4=> 1.75 MHz -// <5=> 2.1 MHz -// <6=> 2.4 MHz -// <7=> 2.7 MHz -// <8=> 3.0 MHz -// <9=> 3.25 MHz -// <10=> 3.5 MHz -// <11=> 3.75 MHz -// <12=> 4.0 MHz -// <13=> 4.2 MHz -// <14=> 4.4 MHz -// <15=> 4.6 MHz -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000 -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC -// <1=> Crystal Oscillator -// <2=> Reserved -// <3=> CLKIN. External clock input. -// -#define SYSPLLCLKSEL_Val 0x00000000 // Reset: 0x000 -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> PLL input -// <2=> Watchdog Oscillator -// <3=> PLL output -// -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 -// - -//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: - -/* -#if (CLOCK_SETUP == 0) - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#elif (CLOCK_SETUP == 2) -// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#endif -*/ - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ -#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) - #define __SYS_PLLCLKIN (__CLKIN_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ -uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - SystemCoreClock = 0; - break; - case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK; - break; - } - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 2: /* Reserved */ - SystemCoreClock = 0; - break; - case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - } - break; - } - - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - - /* System clock to the IOCON & the SWM need to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - volatile uint32_t i; - LPC_IOCON->PIO0_8 &= ~(0x3 << 3); - LPC_IOCON->PIO0_9 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */ - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ - for (i = 0; i < 200; i++) __NOP(); - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; -#endif - -#if ((SYSPLLCLKSEL_Val & 0x03) == 3) - LPC_IOCON->PIO0_1 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */ - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0; - LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */ - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ - -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0; - LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */ - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; -#endif -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h deleted file mode 100644 index 9cef1835a0..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PeripheralNames.h +++ /dev/null @@ -1,55 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -// Default peripherals - -// SPI: MOSI, MISO, CLK, SEL -#define MBED_SPI0 P0_26, P0_25, P0_24, P0_15 - -#define MBED_UART0 P0_7, P0_18 -#define MBED_UARTUSB USBTX, USBRX - -#define MBED_I2C0 P0_11, P0_10 - -typedef enum { - ADC_0 = 0, - ADC_1, - ADC_2, - ADC_3, - ADC_4, - ADC_5, - ADC_6, - ADC_7, - ADC_8, - ADC_9, - ADC_10, - ADC_11, -} ADCName; - - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h deleted file mode 100644 index e2fb12338d..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/PinNames.h +++ /dev/null @@ -1,135 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PIN_SHIFT 8 - -typedef enum { -// LPC824 Pin Names (PIN[11:8] + IOCON offset[7:0]) - - P0_0 = ( 0 << PIN_SHIFT) | 0x44, - P0_1 = ( 1 << PIN_SHIFT) | 0x2C, - P0_2 = ( 2 << PIN_SHIFT) | 0x18, - P0_3 = ( 3 << PIN_SHIFT) | 0x14, - P0_4 = ( 4 << PIN_SHIFT) | 0x10, - P0_5 = ( 5 << PIN_SHIFT) | 0x0C, - P0_6 = ( 6 << PIN_SHIFT) | 0x40, - P0_7 = ( 7 << PIN_SHIFT) | 0x3C, - P0_8 = ( 8 << PIN_SHIFT) | 0x38, - P0_9 = ( 9 << PIN_SHIFT) | 0x34, - P0_10 = (10 << PIN_SHIFT) | 0x20, - P0_11 = (11 << PIN_SHIFT) | 0x1C, - P0_12 = (12 << PIN_SHIFT) | 0x08, - P0_13 = (13 << PIN_SHIFT) | 0x04, - P0_14 = (14 << PIN_SHIFT) | 0x48, - P0_15 = (15 << PIN_SHIFT) | 0x28, - P0_16 = (16 << PIN_SHIFT) | 0x24, - P0_17 = (17 << PIN_SHIFT) | 0x00, - P0_18 = (18 << PIN_SHIFT) | 0x78, - P0_19 = (19 << PIN_SHIFT) | 0x74, - P0_20 = (20 << PIN_SHIFT) | 0x70, - P0_21 = (21 << PIN_SHIFT) | 0x6C, - P0_22 = (22 << PIN_SHIFT) | 0x68, - P0_23 = (23 << PIN_SHIFT) | 0x64, - P0_24 = (24 << PIN_SHIFT) | 0x60, - P0_25 = (25 << PIN_SHIFT) | 0x5C, - P0_26 = (26 << PIN_SHIFT) | 0x58, - P0_27 = (27 << PIN_SHIFT) | 0x54, - P0_28 = (28 << PIN_SHIFT) | 0x50, - - dp2 = P0_4, - dp3 = P0_28, - dp4 = P0_11, - dp5 = P0_10, - dp6 = P0_16, - dp7 = P0_27, - dp8 = P0_26, - dp9 = P0_25, - dp10 = P0_24, - dp11 = P0_15, - dp12 = P0_1, - - dp15 = P0_6, - dp16 = P0_0, - dp17 = P0_14, - dp18 = P0_23, - dp19 = P0_22, - dp20 = P0_21, - dp21 = P0_20, - dp22 = P0_19, - dp23 = P0_17, - dp24 = P0_13, - dp25 = P0_12, - dp26 = P0_5, - - LED_RED = P0_20, - LED_GREEN = P0_21, - LED_BLUE = P0_22, - - // mbed original LED naming - LED1 = LED_RED, - LED2 = LED_GREEN, - LED3 = LED_BLUE, - LED4 = LED_BLUE, - - // Serial to USB pins - USBTX = P0_7, - USBRX = P0_18, - - // I2C pins - SCL = P0_10, - SDA = P0_11, - I2C_SCL = P0_10, - I2C_SDA = P0_11, - - // Not connected - NC = (int)0xFFFFFFFF, -} PinName; - -typedef enum { - PullUp = 2, - PullDown = 1, - PullNone = 0, - Repeater = 3, - OpenDrain = 4, - PullDefault = PullDown -} PinMode; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX - -typedef struct { - unsigned char n; - unsigned char offset; -} SWM_Map; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h deleted file mode 100644 index 2427e752ea..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct deleted file mode 100644 index 8738dd7043..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/LPC824.sct +++ /dev/null @@ -1,48 +0,0 @@ -#! armcc -E - -#if !defined(MBED_APP_START) - #define MBED_APP_START 0x00000000 -#endif - -; 32K flash -#if !defined(MBED_APP_SIZE) - #define MBED_APP_SIZE 0x8000 -#endif - -; 4KB -#if !defined(MBED_RAM_START) - #define MBED_RAM_START 0x10000000 -#endif - -#if !defined(MBED_RAM_SIZE) - #define MBED_RAM_SIZE 0x2000 -#endif - - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -; 8_byte_aligned(48 vect * 4 bytes) = 8_byte_aligned(0xC0) = 0xC0 -#define VECTOR_SIZE 0xC0 - -#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE) - -LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region - - ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - - RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data - .ANY (+RW +ZI) - } - - ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) { - } - - ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S deleted file mode 100644 index 744eda77ad..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_ARM_MICRO/startup_LPC8xx.S +++ /dev/null @@ -1,195 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC8xx.s -; * @purpose: CMSIS Cortex-M0+ Core Device Startup File -; * for the NXP LPC8xx Device Series -; * @version: V1.0 -; * @date: 16. Aug. 2012 -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD SPI0_IRQHandler ; SPI0 controller - DCD SPI1_IRQHandler ; SPI1 controller - DCD 0 ; Reserved - DCD UART0_IRQHandler ; UART0 - DCD UART1_IRQHandler ; UART1 - DCD UART2_IRQHandler ; UART2 - DCD 0 ; Reserved - DCD I2C1_IRQHandler ; I2C1 controller - DCD I2C0_IRQHandler ; I2C0 controller - DCD SCT_IRQHandler ; Smart Counter Timer - DCD MRT_IRQHandler ; Multi-Rate Timer - DCD CMP_IRQHandler ; Comparator - DCD WDT_IRQHandler ; PIO1 (0:11) - DCD BOD_IRQHandler ; Brown Out Detect - DCD Flash_IRQHandler ; Flash interrupt - DCD WKT_IRQHandler ; Wakeup timer - DCD ADC_SEQA_IRQHandler ; ADC sequence A completion - DCD ADC_SEQB_IRQHandler ; ADC sequence B completion - DCD ADC_THCMP_IRQHandler ; ADC threshold compare - DCD ADC_OVR_IRQHandler ; ADC overrun - DCD DMA__RQHandler ; DMA interrupt - DCD I2C2_IRQHandler ; I2C2 controller - DCD I2C3_IRQHandler ; I2C3 controller - DCD 0 ; Reserved - DCD PININT0_IRQHandler ; PIO INT0 - DCD PININT1_IRQHandler ; PIO INT1 - DCD PININT2_IRQHandler ; PIO INT2 - DCD PININT3_IRQHandler ; PIO INT3 - DCD PININT4_IRQHandler ; PIO INT4 - DCD PININT5_IRQHandler ; PIO INT5 - DCD PININT6_IRQHandler ; PIO INT6 - DCD PININT7_IRQHandler ; PIO INT7 - - - IF :LNOT::DEF:NO_CRP - AREA |.ARM.__at_0x02FC|, CODE, READONLY -CRP_Key DCD 0xFFFFFFFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT NMI_Handler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT SCT_IRQHandler [WEAK] - EXPORT MRT_IRQHandler [WEAK] - EXPORT CMP_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT BOD_IRQHandler [WEAK] - EXPORT Flash_IRQHandler [WEAK] - EXPORT WKT_IRQHandler [WEAK] - EXPORT ADC_SEQA_IRQHandler [WEAK] - EXPORT ADC_SEQB_IRQHandler [WEAK] - EXPORT ADC_THCMP_IRQHandler [WEAK] - EXPORT ADC_OVR_IRQHandler [WEAK] - EXPORT DMA__RQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT I2C3_IRQHandler [WEAK] - EXPORT PININT0_IRQHandler [WEAK] - EXPORT PININT1_IRQHandler [WEAK] - EXPORT PININT2_IRQHandler [WEAK] - EXPORT PININT3_IRQHandler [WEAK] - EXPORT PININT4_IRQHandler [WEAK] - EXPORT PININT5_IRQHandler [WEAK] - EXPORT PININT6_IRQHandler [WEAK] - EXPORT PININT7_IRQHandler [WEAK] - -NMI_Handler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -I2C1_IRQHandler -I2C0_IRQHandler -SCT_IRQHandler -MRT_IRQHandler -CMP_IRQHandler -WDT_IRQHandler -BOD_IRQHandler -Flash_IRQHandler -WKT_IRQHandler -ADC_SEQA_IRQHandler -ADC_SEQB_IRQHandler -ADC_THCMP_IRQHandler -ADC_OVR_IRQHandler -DMA__RQHandler -I2C2_IRQHandler -I2C3_IRQHandler -PININT0_IRQHandler -PININT1_IRQHandler -PININT2_IRQHandler -PININT3_IRQHandler -PININT4_IRQHandler -PININT5_IRQHandler -PININT6_IRQHandler -PININT7_IRQHandler - - B . - - ENDP - - ALIGN - END diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld deleted file mode 100644 index 4817d52b1b..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/LPC824.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script for mbed LPC824-GCC-ARM based on LPC1114-GCC-ARM-LPC1114.ld */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x400 -#endif - -STACK_SIZE = MBED_BOOT_STACK_SIZE; - -/* Linker script to configure memory regions. */ -MEMORY -{ - /* Define each memory region */ - FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x8000 /* 32K bytes */ - RAM (rwx) : ORIGIN = 0x10000000+0xC0, LENGTH = 0x2000-0xC0 /* 8K bytes */ -} - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.isr_vector)) - *(.text.Reset_Handler) - *(.text.SystemInit) - . = 0x200; - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE (__fini_array_end = .); - - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - __bss_start__ = .; - *(.bss*) - *(COMMON) - __bss_end__ = .; - } > RAM - - .heap : - { - __end__ = .; - end = __end__; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy : - { - *(.stack) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S deleted file mode 100644 index c4273d680b..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/TOOLCHAIN_GCC_ARM/startup_LPC824.S +++ /dev/null @@ -1,228 +0,0 @@ -/* File: startup_ARMCM0.S - * Purpose: startup file for Cortex-M0 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V1.2 - * Date: 15 Nov 2011 - * - * Copyright (c) 2011, ARM Limited - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the ARM Limited nor the - names of its contributors may be used to endorse or promote products - derived from this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL ARM LIMITED BE LIABLE FOR ANY - * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND - * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - .syntax unified - .arch armv6-m - -/* Memory Model - The HEAP starts at the end of the DATA section and grows upward. - - The STACK starts at the end of the RAM and grows downward. - - The HEAP and stack STACK are only checked at compile time: - (DATA_SIZE + HEAP_SIZE + STACK_SIZE) < RAM_SIZE - - This is just a check for the bare minimum for the Heap+Stack area before - aborting compilation, it is not the run time limit: - Heap_Size + Stack_Size = 0x80 + 0x80 = 0x100 - */ - .section .stack - .align 3 -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 0x80 -#endif - .globl __StackTop - .globl __StackLimit -__StackLimit: - .space Stack_Size - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 -#ifdef __HEAP_SIZE - .equ Heap_Size, __HEAP_SIZE -#else - .equ Heap_Size, 0x80 -#endif - .globl __HeapBase - .globl __HeapLimit -__HeapBase: - .space Heap_Size - .size __HeapBase, . - __HeapBase -__HeapLimit: - .size __HeapLimit, . - __HeapLimit - - .section .isr_vector - .align 2 - .globl __isr_vector -__isr_vector: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - -/* LPC824 interrupts */ - .long SPI0_IRQHandler // SPI0 controller - .long SPI1_IRQHandler // SPI1 controller - .long 0 // Reserved - .long UART0_IRQHandler // UART0 - .long UART1_IRQHandler // UART1 - .long UART2_IRQHandler // UART2 - .long 0 // Reserved - .long I2C1_IRQHandler // I2C ch1 controller - .long I2C0_IRQHandler // I2C ch0 controller - .long SCT_IRQHandler // Smart Counter Timer - .long MRT_IRQHandler // Multi-Rate Timer - .long CMP_IRQHandler // Comparator - .long WDT_IRQHandler // PIO1 (0:11) - .long BOD_IRQHandler // Brown Out Detect - .long Flash_IRQHandler // Flash interrupt - .long WKT_IRQHandler // Wakeup timer - .long ADC_SEQA_IRQHandler // ADC sequence A completion - .long ADC_SEQB_IRQHandler // ADC sequence B completion - .long ADC_THCMP_IRQHandler // ADC threshold compare - .long ADC_OVR_IRQHandler // ADC overrun - .long DMA_IRQHandler // DMA interrupt - .long I2C2_IRQHandler // I2C2 controller - .long I2C3_IRQHandler // I2C3 controller - .long 0 // Reserved - .long PININT0_IRQHandler // PIO INT0 - .long PININT1_IRQHandler // PIO INT1 - .long PININT2_IRQHandler // PIO INT2 - .long PININT3_IRQHandler // PIO INT3 - .long PININT4_IRQHandler // PIO INT4 - .long PININT5_IRQHandler // PIO INT5 - .long PININT6_IRQHandler // PIO INT6 - .long PININT7_IRQHandler // PIO INT7 - - .size __isr_vector, . - __isr_vector - - .section .text.Reset_Handler - .thumb - .thumb_func - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler SVC_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - - def_irq_default_handler SPI0_IRQHandler - def_irq_default_handler SPI1_IRQHandler - def_irq_default_handler UART0_IRQHandler - def_irq_default_handler UART1_IRQHandler - def_irq_default_handler UART2_IRQHandler - def_irq_default_handler I2C0_IRQHandler - def_irq_default_handler I2C1_IRQHandler - def_irq_default_handler I2C2_IRQHandler - def_irq_default_handler I2C3_IRQHandler - def_irq_default_handler SCT_IRQHandler - def_irq_default_handler MRT_IRQHandler - def_irq_default_handler CMP_IRQHandler - def_irq_default_handler WDT_IRQHandler - def_irq_default_handler BOD_IRQHandler - def_irq_default_handler Flash_IRQHandler - def_irq_default_handler WKT_IRQHandler - def_irq_default_handler ADC_SEQA_IRQHandler - def_irq_default_handler ADC_SEQB_IRQHandler - def_irq_default_handler ADC_THCMP_IRQHandler - def_irq_default_handler ADC_OVR_IRQHandler - def_irq_default_handler DMA_IRQHandler - def_irq_default_handler PININT0_IRQHandler - def_irq_default_handler PININT1_IRQHandler - def_irq_default_handler PININT2_IRQHandler - def_irq_default_handler PININT3_IRQHandler - def_irq_default_handler PININT4_IRQHandler - def_irq_default_handler PININT5_IRQHandler - def_irq_default_handler PININT6_IRQHandler - def_irq_default_handler PININT7_IRQHandler - - .end - diff --git a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c b/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c deleted file mode 100644 index e2b4123499..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/TARGET_SSCI824/device/system_LPC8xx.c +++ /dev/null @@ -1,389 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.c - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Source File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ -#include -#include "LPC82x.h" - -/* -//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -*/ - -/*--------------------- Clock Configuration ----------------------------------*/ -// -// Clock Configuration -#define CLOCK_SETUP 1 -// System Oscillator Control Register (SYSOSCCTRL) -// BYPASS: System Oscillator Bypass Enable -// If enabled then PLL input (sys_osc_clk) is fed -// directly from XTALIN and XTALOUT pins. -// FREQRANGE: System Oscillator Frequency Range -// Determines frequency range for Low-power oscillator. -// <0=> 1 - 20 MHz -// <1=> 15 - 25 MHz -// -#define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 -// -// Watchdog Oscillator Control Register (WDTOSCCTRL) -// DIVSEL: Select Divider for Fclkana -// wdt_osc_clk = Fclkana/ (2 * (1 + DIVSEL)) -// <0-31> -// FREQSEL: Select Watchdog Oscillator Analog Output Frequency (Fclkana) -// <0=> Undefined -// <1=> 0.6 MHz -// <2=> 1.05 MHz -// <3=> 1.4 MHz -// <4=> 1.75 MHz -// <5=> 2.1 MHz -// <6=> 2.4 MHz -// <7=> 2.7 MHz -// <8=> 3.0 MHz -// <9=> 3.25 MHz -// <10=> 3.5 MHz -// <11=> 3.75 MHz -// <12=> 4.0 MHz -// <13=> 4.2 MHz -// <14=> 4.4 MHz -// <15=> 4.6 MHz -#define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 -// -// System PLL Control Register (SYSPLLCTRL) -// F_clkout = M * F_clkin = F_CCO / (2 * P) -// F_clkin must be in the range of 10 MHz to 25 MHz -// F_CCO must be in the range of 156 MHz to 320 MHz -// MSEL: Feedback Divider Selection -// M = MSEL + 1 -// <0-31> -// PSEL: Post Divider Selection -// <0=> P = 1 -// <1=> P = 2 -// <2=> P = 4 -// <3=> P = 8 -// -#define SYSPLLCTRL_Val 0x00000024 // Reset: 0x000 -// -// System PLL Clock Source Select Register (SYSPLLCLKSEL) -// SEL: System PLL Clock Source -// <0=> IRC -// <1=> Crystal Oscillator -// <2=> Reserved -// <3=> CLKIN. External clock input. -// -#define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 -// -// Main Clock Source Select Register (MAINCLKSEL) -// SEL: Clock Source for Main Clock -// <0=> IRC Oscillator -// <1=> PLL input -// <2=> Watchdog Oscillator -// <3=> PLL output -// -#define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 -// System AHB Clock Divider Register (SYSAHBCLKDIV) -// DIV: System AHB Clock Divider -// Divides main clock to provide system clock to core, memories, and peripherals. -// 0 = is disabled -// <0-255> -// -#define SYSAHBCLKDIV_Val 0x00000002 // Reset: 0x001 -// - -//#define CLOCK_SETUP 0 // 1 == IRC: 2 == System Oscillator 12Mhz Xtal: - -/* -#if (CLOCK_SETUP == 0) - #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000024 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000041 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000003 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000000 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#elif (CLOCK_SETUP == 2) -// #define SYSOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define WDTOSCCTRL_Val 0x00000000 // Reset: 0x000 - #define SYSPLLCTRL_Val 0x00000040 // Reset: 0x000 - #define SYSPLLCLKSEL_Val 0x00000001 // Reset: 0x000 - #define MAINCLKSEL_Val 0x00000003 // Reset: 0x000 - #define SYSAHBCLKDIV_Val 0x00000001 // Reset: 0x001 -#endif -*/ - -/* -//-------- <<< end of configuration section >>> ------------------------------ -*/ - -/*---------------------------------------------------------------------------- - Check the register settings - *----------------------------------------------------------------------------*/ -#define CHECK_RANGE(val, min, max) ((val < min) || (val > max)) -#define CHECK_RSVD(val, mask) (val & mask) - -/* Clock Configuration -------------------------------------------------------*/ -#if (CHECK_RSVD((SYSOSCCTRL_Val), ~0x00000003)) - #error "SYSOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((WDTOSCCTRL_Val), ~0x000001FF)) - #error "WDTOSCCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSPLLCLKSEL_Val), 0, 3)) - #error "SYSPLLCLKSEL: Value out of range!" -#endif - -#if (CHECK_RSVD((SYSPLLCTRL_Val), ~0x000001FF)) - #error "SYSPLLCTRL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RSVD((MAINCLKSEL_Val), ~0x00000003)) - #error "MAINCLKSEL: Invalid values of reserved bits!" -#endif - -#if (CHECK_RANGE((SYSAHBCLKDIV_Val), 0, 255)) - #error "SYSAHBCLKDIV: Value out of range!" -#endif - - -/*---------------------------------------------------------------------------- - DEFINES - *----------------------------------------------------------------------------*/ - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define __XTAL (12000000UL) /* Oscillator frequency */ -#define __SYS_OSC_CLK ( __XTAL) /* Main oscillator frequency */ -#define __IRC_OSC_CLK (12000000UL) /* Internal RC oscillator frequency */ -#define __CLKIN_CLK (12000000UL) /* CLKIN pin frequency */ - - -#define __FREQSEL ((WDTOSCCTRL_Val >> 5) & 0x0F) -#define __DIVSEL (((WDTOSCCTRL_Val & 0x1F) << 1) + 2) - -#if (CLOCK_SETUP) /* Clock Setup */ - #if (__FREQSEL == 0) - #define __WDT_OSC_CLK ( 0) /* undefined */ - #elif (__FREQSEL == 1) - #define __WDT_OSC_CLK ( 500000 / __DIVSEL) - #elif (__FREQSEL == 2) - #define __WDT_OSC_CLK ( 800000 / __DIVSEL) - #elif (__FREQSEL == 3) - #define __WDT_OSC_CLK (1100000 / __DIVSEL) - #elif (__FREQSEL == 4) - #define __WDT_OSC_CLK (1400000 / __DIVSEL) - #elif (__FREQSEL == 5) - #define __WDT_OSC_CLK (1600000 / __DIVSEL) - #elif (__FREQSEL == 6) - #define __WDT_OSC_CLK (1800000 / __DIVSEL) - #elif (__FREQSEL == 7) - #define __WDT_OSC_CLK (2000000 / __DIVSEL) - #elif (__FREQSEL == 8) - #define __WDT_OSC_CLK (2200000 / __DIVSEL) - #elif (__FREQSEL == 9) - #define __WDT_OSC_CLK (2400000 / __DIVSEL) - #elif (__FREQSEL == 10) - #define __WDT_OSC_CLK (2600000 / __DIVSEL) - #elif (__FREQSEL == 11) - #define __WDT_OSC_CLK (2700000 / __DIVSEL) - #elif (__FREQSEL == 12) - #define __WDT_OSC_CLK (2900000 / __DIVSEL) - #elif (__FREQSEL == 13) - #define __WDT_OSC_CLK (3100000 / __DIVSEL) - #elif (__FREQSEL == 14) - #define __WDT_OSC_CLK (3200000 / __DIVSEL) - #else - #define __WDT_OSC_CLK (3400000 / __DIVSEL) - #endif - - /* sys_pllclkin calculation */ - #if ((SYSPLLCLKSEL_Val & 0x03) == 0) - #define __SYS_PLLCLKIN (__IRC_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 1) - #define __SYS_PLLCLKIN (__SYS_OSC_CLK) - #elif ((SYSPLLCLKSEL_Val & 0x03) == 3) - #define __SYS_PLLCLKIN (__CLKIN_CLK) - #else - #define __SYS_PLLCLKIN (0) - #endif - - #define __SYS_PLLCLKOUT (__SYS_PLLCLKIN * ((SYSPLLCTRL_Val & 0x01F) + 1)) - - /* main clock calculation */ - #if ((MAINCLKSEL_Val & 0x03) == 0) - #define __MAIN_CLOCK (__IRC_OSC_CLK) - #elif ((MAINCLKSEL_Val & 0x03) == 1) - #define __MAIN_CLOCK (__SYS_PLLCLKIN) - #elif ((MAINCLKSEL_Val & 0x03) == 2) - #if (__FREQSEL == 0) - #error "MAINCLKSEL: WDT Oscillator selected but FREQSEL is undefined!" - #else - #define __MAIN_CLOCK (__WDT_OSC_CLK) - #endif - #elif ((MAINCLKSEL_Val & 0x03) == 3) - #define __MAIN_CLOCK (__SYS_PLLCLKOUT) - #else - #define __MAIN_CLOCK (0) - #endif - - #define __SYSTEM_CLOCK (__MAIN_CLOCK / SYSAHBCLKDIV_Val) - -#else - #define __SYSTEM_CLOCK (__IRC_OSC_CLK) -#endif // CLOCK_SETUP - - -/*---------------------------------------------------------------------------- - Clock Variable definitions - *----------------------------------------------------------------------------*/ -uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/ -uint32_t MainClock = __MAIN_CLOCK; /*!< Main Clock Frequency */ - -/*---------------------------------------------------------------------------- - Clock functions - *----------------------------------------------------------------------------*/ -void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */ -{ - uint32_t wdt_osc = 0; - - /* Determine clock frequency according to clock register values */ - switch ((LPC_SYSCON->WDTOSCCTRL >> 5) & 0x0F) { - case 0: wdt_osc = 0; break; - case 1: wdt_osc = 500000; break; - case 2: wdt_osc = 800000; break; - case 3: wdt_osc = 1100000; break; - case 4: wdt_osc = 1400000; break; - case 5: wdt_osc = 1600000; break; - case 6: wdt_osc = 1800000; break; - case 7: wdt_osc = 2000000; break; - case 8: wdt_osc = 2200000; break; - case 9: wdt_osc = 2400000; break; - case 10: wdt_osc = 2600000; break; - case 11: wdt_osc = 2700000; break; - case 12: wdt_osc = 2900000; break; - case 13: wdt_osc = 3100000; break; - case 14: wdt_osc = 3200000; break; - case 15: wdt_osc = 3400000; break; - } - wdt_osc /= ((LPC_SYSCON->WDTOSCCTRL & 0x1F) << 1) + 2; - - switch (LPC_SYSCON->MAINCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* Input Clock to System PLL */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK; - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK; - break; - case 2: /* Reserved */ - SystemCoreClock = 0; - break; - case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK; - break; - } - break; - case 2: /* WDT Oscillator */ - SystemCoreClock = wdt_osc; - break; - case 3: /* System PLL Clock Out */ - switch (LPC_SYSCON->SYSPLLCLKSEL & 0x03) { - case 0: /* Internal RC oscillator */ - SystemCoreClock = __IRC_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 1: /* System oscillator */ - SystemCoreClock = __SYS_OSC_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - case 2: /* Reserved */ - SystemCoreClock = 0; - break; - case 3: /* CLKIN pin */ - SystemCoreClock = __CLKIN_CLK * ((LPC_SYSCON->SYSPLLCTRL & 0x01F) + 1); - break; - } - break; - } - - SystemCoreClock /= LPC_SYSCON->SYSAHBCLKDIV; - -} - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System. - */ -void SystemInit (void) { - volatile uint32_t i; - - /* System clock to the IOCON & the SWM need to be enabled or - most of the I/O related peripherals won't work. */ - LPC_SYSCON->SYSAHBCLKCTRL |= ( (0x1 << 7) | (0x1 << 18) ); - -#if (CLOCK_SETUP) /* Clock Setup */ - -#if ((SYSPLLCLKSEL_Val & 0x03) == 1) - LPC_IOCON->PIO0_8 &= ~(0x3 << 3); - LPC_IOCON->PIO0_9 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x3 << 6); /* XTALIN and XTALOUT */ - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 5); /* Power-up System Osc */ - for (i = 0; i < 200; i++) __NOP(); - LPC_SYSCON->SYSOSCCTRL = SYSOSCCTRL_Val; -#endif - -#if ((SYSPLLCLKSEL_Val & 0x03) == 3) - LPC_IOCON->PIO0_1 &= ~(0x3 << 3); - LPC_SWM->PINENABLE0 &= ~(0x1 << 9); /* CLKIN */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up System PLL */ - LPC_SYSCON->SYSPLLCLKSEL = SYSPLLCLKSEL_Val; /* Select PLL Input */ - LPC_SYSCON->SYSPLLCLKUEN = 0; - LPC_SYSCON->SYSPLLCLKUEN = 1; /* Update Clock Source */ - while (!(LPC_SYSCON->SYSPLLCLKUEN & 0x01)); /* Wait Until Updated */ - -#if ((MAINCLKSEL_Val & 0x03) == 3) /* Main Clock is PLL Out */ - LPC_SYSCON->SYSPLLCTRL = SYSPLLCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 7); /* Power-up SYSPLL */ - while (!(LPC_SYSCON->SYSPLLSTAT & 0x01)); /* Wait Until PLL Locked */ -#endif - -#if (((MAINCLKSEL_Val & 0x03) == 2) ) - LPC_SYSCON->WDTOSCCTRL = WDTOSCCTRL_Val; - LPC_SYSCON->PDRUNCFG &= ~(0x1 << 6); /* Power-up WDT Clock */ - for (i = 0; i < 200; i++) __NOP(); -#endif - - LPC_SYSCON->MAINCLKSEL = MAINCLKSEL_Val; /* Select PLL Clock Output */ - LPC_SYSCON->MAINCLKUEN = 0; - LPC_SYSCON->MAINCLKUEN = 1; /* Update MCLK Clock Source */ - while (!(LPC_SYSCON->MAINCLKUEN & 0x01)); /* Wait Until Updated */ - - LPC_SYSCON->SYSAHBCLKDIV = SYSAHBCLKDIV_Val; -#endif -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/analogin_api.c b/targets/TARGET_NXP/TARGET_LPC82X/analogin_api.c deleted file mode 100644 index 4cf003efe4..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/analogin_api.c +++ /dev/null @@ -1,136 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "PeripheralNames.h" - -#if DEVICE_ANALOGIN - -#define ANALOGIN_MEDIAN_FILTER 1 - -#define ADC_RANGE 0xFFF - -static const PinMap PinMap_ADC[] = { - {P0_7 , ADC_0, 0}, - {P0_6 , ADC_1, 0}, - {P0_14, ADC_2, 0}, - {P0_23, ADC_3, 0}, - {P0_22, ADC_4, 0}, - {P0_21, ADC_5, 0}, - {P0_20, ADC_6, 0}, - {P0_19, ADC_7, 0}, - {P0_18, ADC_8, 0}, - {P0_17, ADC_9, 0}, - {P0_13, ADC_10,0}, - {P0_4 , ADC_11,0}, -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - LPC_SYSCON->SYSAHBCLKCTRL |= (1UL << 6); - // pin enable - LPC_SWM->PINENABLE0 &= ~(1UL << (13 + obj->adc)); - // configure GPIO as input - LPC_GPIO_PORT->DIR0 &= ~(1UL << (pin >> PIN_SHIFT)); - - LPC_SYSCON->PDRUNCFG &= ~(1 << 4); - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 24); - - __IO LPC_ADC_Type *adc_reg = LPC_ADC; - - // determine the system clock divider for a 500kHz ADC clock during calibration - uint32_t clkdiv = (SystemCoreClock / 500000) - 1; - - // perform a self-calibration - adc_reg->CTRL = (1UL << 30) | (clkdiv & 0xFF); - while ((adc_reg->CTRL & (1UL << 30)) != 0); -} - -static inline uint32_t adc_read(analogin_t *obj) -{ - uint32_t channels; - __IO LPC_ADC_Type *adc_reg = LPC_ADC; - - channels = (obj->adc & 0x1F); - - // select channel - adc_reg->SEQA_CTRL &= ~(0xFFF); - adc_reg->SEQA_CTRL |= (1UL << channels); - - // start conversion and sequence enable - adc_reg->SEQA_CTRL |= ((1UL << 26) | (1UL << 31)); - - // Repeatedly get the sample data until DONE bit - volatile uint32_t data; - do { - data = adc_reg->SEQA_GDAT; - } while ((data & (1UL << 31)) == 0); - - // Stop conversion - adc_reg->SEQA_CTRL &= ~(1UL << 31); - - return ((data >> 4) & ADC_RANGE); -} - -static inline void order(uint32_t *a, uint32_t *b) -{ - if (*a > *b) { - uint32_t t = *a; - *a = *b; - *b = t; - } -} - -static inline uint32_t adc_read_u32(analogin_t *obj) -{ - uint32_t value; -#if ANALOGIN_MEDIAN_FILTER - uint32_t v1 = adc_read(obj); - uint32_t v2 = adc_read(obj); - uint32_t v3 = adc_read(obj); - order(&v1, &v2); - order(&v2, &v3); - order(&v1, &v2); - value = v2; -#else - value = adc_read(obj); -#endif - return value; -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - uint32_t value = adc_read_u32(obj); - return (value << 4) | ((value >> 8) & 0x000F); // 12 bit -} - -float analogin_read(analogin_t *obj) -{ - uint32_t value = adc_read_u32(obj); - return (float)value * (1.0f / (float)ADC_RANGE); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/device/LPC82x.h b/targets/TARGET_NXP/TARGET_LPC82X/device/LPC82x.h deleted file mode 100644 index fee91c063a..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/device/LPC82x.h +++ /dev/null @@ -1,1308 +0,0 @@ - -/****************************************************************************************************//** - * @file LPC82x.h - * - * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for - * LPC82x from . - * - * @version V0.4 - * @date 17. June 2014 - * - * @note Generated with SVDConv V2.80 - * from CMSIS SVD File 'LPC82x.svd' Version 0.4, - *******************************************************************************************************/ - - - -/** @addtogroup (null) - * @{ - */ - -/** @addtogroup LPC82x - * @{ - */ - -#ifndef LPC82X_H -#define LPC82X_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */ - SPI0_IRQn = 0, /*!< 0 SPI0 */ - SPI1_IRQn = 1, /*!< 1 SPI1 */ - UART0_IRQn = 3, /*!< 3 UART0 */ - UART1_IRQn = 4, /*!< 4 UART1 */ - UART2_IRQn = 5, /*!< 5 UART2 */ - I2C1_IRQn = 7, /*!< 7 I2C1 */ - I2C0_IRQn = 8, /*!< 8 I2C0 */ - SCT_IRQn = 9, /*!< 9 SCT */ - MRT_IRQn = 10, /*!< 10 MRT */ - CMP_IRQn = 11, /*!< 11 CMP */ - WDT_IRQn = 12, /*!< 12 WDT */ - BOD_IRQn = 13, /*!< 13 BOD */ - FLASH_IRQn = 14, /*!< 14 FLASH */ - WKT_IRQn = 15, /*!< 15 WKT */ - ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */ - ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */ - ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */ - ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */ - DMA_IRQn = 20, /*!< 20 DMA */ - I2C2_IRQn = 21, /*!< 21 I2C2 */ - I2C3_IRQn = 22, /*!< 22 I2C3 */ - PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */ - PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */ - PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */ - PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */ - PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */ - PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */ - PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */ - PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */ -#define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -#define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */ -#include "system_LPC82x.h" /*!< LPC82x System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - - -/* ================================================================================ */ -/* ================ WWDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Windowed Watchdog Timer (WWDT) (WWDT) - */ - -typedef struct { /*!< (@ 0x40000000) WWDT Structure */ - __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains - the basic mode and status of the Watchdog Timer. */ - __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit - register determines the time-out value. */ - __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA - followed by 0x55 to this register reloads the Watchdog timer - with the value contained in WDTC. */ - __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register - reads out the current value of the Watchdog timer. */ - __I uint32_t RESERVED0; - __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */ - __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */ -} LPC_WWDT_Type; - - -/* ================================================================================ */ -/* ================ MRT ================ */ -/* ================================================================================ */ - - -/** - * @brief Multi-Rate Timer (MRT) (MRT) - */ - -typedef struct { /*!< (@ 0x40004000) MRT Structure */ - __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */ - __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */ - __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */ - __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value - is loaded into the TIMER0 register. */ - __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the - value of the down-counter. */ - __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls - the MRT0 modes. */ - __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */ - __I uint32_t RESERVED0[45]; - __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns - the number of the first idle channel. */ - __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */ -} LPC_MRT_Type; - - -/* ================================================================================ */ -/* ================ WKT ================ */ -/* ================================================================================ */ - - -/** - * @brief Self wake-up timer (WKT) (WKT) - */ - -typedef struct { /*!< (@ 0x40008000) WKT Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */ - __I uint32_t RESERVED0[2]; - __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */ -} LPC_WKT_Type; - - -/* ================================================================================ */ -/* ================ SWM ================ */ -/* ================================================================================ */ - - -/** - * @brief Switch matrix (SWM) (SWM) - */ - -typedef struct { /*!< (@ 0x4000C000) SWM Structure */ - union { - __IO uint32_t PINASSIGN[12]; - struct { - __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions - U0_TXD, U0_RXD, U0_RTS, U0_CTS. */ - __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions - U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */ - __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions - U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */ - __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function - U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */ - __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions - SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */ - __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions - SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */ - __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions - SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */ - __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions - SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */ - __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions - SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */ - __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions - SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */ - __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions - I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */ - __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions - ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */ - }; - }; - __I uint32_t RESERVED0[100]; - __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions - ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN, - VDDCMP. */ -} LPC_SWM_Type; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC) - */ - -typedef struct { /*!< (@ 0x4001C000) ADC Structure */ - __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide - value, enable bits for each sequence and the A/D power-down - bit. */ - __I uint32_t RESERVED0; - __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls - triggering and channel selection for conversion sequence-A. - Also specifies interrupt mode for sequence-A. */ - __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls - triggering and channel selection for conversion sequence-B. - Also specifies interrupt mode for sequence-B. */ - __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register - contains the result of the most recent A/D conversion performed - under sequence-A */ - __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register - contains the result of the most recent A/D conversion performed - under sequence-B */ - __I uint32_t RESERVED1[2]; - __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains - the result of the most recent conversion completed on channel - 0. */ - __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains - the lower threshold level for automatic threshold comparison - for any channels linked to threshold pair 0. */ - __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains - the lower threshold level for automatic threshold comparison - for any channels linked to threshold pair 1. */ - __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains - the upper threshold level for automatic threshold comparison - for any channels linked to threshold pair 0. */ - __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains - the upper threshold level for automatic threshold comparison - for any channels linked to threshold pair 1. */ - __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies - which set of threshold compare registers are to be used for - each channel */ - __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register - contains enable bits that enable the sequence-A, sequence-B, - threshold compare and data overrun interrupts to be generated. */ - __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt - request flags and the individual component overrun and threshold-compare - flags. (The overrun bits replicate information stored in the - result registers). */ - __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */ -} LPC_ADC_Type; - - -/* ================================================================================ */ -/* ================ PMU ================ */ -/* ================================================================================ */ - - -/** - * @brief Power Management Unit (PMU) (PMU) - */ - -typedef struct { /*!< (@ 0x40020000) PMU Structure */ - __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */ - __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */ - __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */ - __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */ - __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */ - __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes - bits for general purpose storage. */ -} LPC_PMU_Type; - - -/* ================================================================================ */ -/* ================ CMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Analog comparator (CMP) - */ - -typedef struct { /*!< (@ 0x40024000) CMP Structure */ - __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */ - __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */ -} LPC_CMP_Type; - - -/* ================================================================================ */ -/* ================ DMATRIGMUX ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA trigger mux (DMATRIGMUX) - */ - -typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */ - __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ - __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23 - connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin - interrupts, and DMA requests. */ -} LPC_DMATRIGMUX_Type; - - -/* ================================================================================ */ -/* ================ INPUTMUX ================ */ -/* ================================================================================ */ - - -/** - * @brief Input multiplexing (INPUTMUX) - */ - -typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */ - __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20. - Selects from 18 DMA trigger outputs. */ - __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20. - Selects from 18 DMA trigger outputs. */ - __I uint32_t RESERVED0[6]; - __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */ - __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */ - __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */ - __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */ -} LPC_INPUTMUX_Type; - - -/* ================================================================================ */ -/* ================ FLASHCTRL ================ */ -/* ================================================================================ */ - - -/** - * @brief Flash controller (FLASHCTRL) - */ - -typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */ - __I uint32_t RESERVED0[4]; - __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */ - __I uint32_t RESERVED1[3]; - __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */ - __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */ - __I uint32_t RESERVED2; - __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */ -} LPC_FLASHCTRL_Type; - - -/* ================================================================================ */ -/* ================ IOCON ================ */ -/* ================================================================================ */ - - -/** - * @brief I/O configuration (IOCON) (IOCON) - */ - -typedef struct { /*!< (@ 0x40044000) IOCON Structure */ - __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */ - __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */ - __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */ - __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */ - __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */ - __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */ - __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */ - __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the - pin configuration for the true open-drain pin. */ - __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the - pin configuration for the true open-drain pin. */ - __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */ - __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */ - __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */ - __I uint32_t RESERVED0; - __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */ - __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */ - __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */ - __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */ - __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */ - __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */ - __I uint32_t RESERVED1; - __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */ - __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */ - __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */ - __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */ - __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */ - __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */ - __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */ - __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */ - __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */ - __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */ - __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */ -} LPC_IOCON_Type; - - -/* ================================================================================ */ -/* ================ SYSCON ================ */ -/* ================================================================================ */ - - -/** - * @brief System configuration (SYSCON) (SYSCON) - */ - -typedef struct { /*!< (@ 0x40048000) SYSCON Structure */ - __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */ - __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */ - __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */ - __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */ - __I uint32_t RESERVED0[4]; - __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */ - __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */ - __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */ - __I uint32_t RESERVED1; - __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */ - __I uint32_t RESERVED2[3]; - __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */ - __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */ - __I uint32_t RESERVED3[10]; - __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */ - __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */ - __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */ - __I uint32_t RESERVED4; - __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */ - __I uint32_t RESERVED5[4]; - __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */ - __I uint32_t RESERVED6[18]; - __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */ - __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */ - __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */ - __I uint32_t RESERVED7; - __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator - divider value */ - __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator - multiplier value */ - __I uint32_t RESERVED8; - __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */ - __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */ - __I uint32_t RESERVED9[12]; - __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable - glitch filter */ - __I uint32_t RESERVED10[6]; - __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */ - __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */ - __I uint32_t RESERVED11[6]; - __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt - latency and determinism. */ - __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */ - union { - __IO uint32_t PINTSEL[8]; - struct { - __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */ - __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */ - }; - }; - __I uint32_t RESERVED12[27]; - __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */ - __I uint32_t RESERVED13[3]; - __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */ - __I uint32_t RESERVED14[6]; - __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */ - __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */ - __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */ - __I uint32_t RESERVED15[111]; - __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */ -} LPC_SYSCON_Type; - - -/* ================================================================================ */ -/* ================ I2C0 ================ */ -/* ================================================================================ */ - - -/** - * @brief I2C0-bus interface (I2C0) - */ - -typedef struct { /*!< (@ 0x40050000) I2C0 Structure */ - __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */ - __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor - functions. */ - __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */ - __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */ - __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */ - __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This - determines what time increments are used for the MSTTIME and - SLVTIME registers. */ - __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave, - and Monitor functions. */ - __I uint32_t RESERVED0; - __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */ - __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */ - __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data - register. */ - __I uint32_t RESERVED1[5]; - __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */ - __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data - register. */ - union { - __IO uint32_t SLVADR[4]; - struct { - __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */ - __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */ - __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */ - __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */ - }; - }; - __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */ - __I uint32_t RESERVED2[9]; - __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */ -} LPC_I2C0_Type; - - -/* ================================================================================ */ -/* ================ SPI0 ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI0 (SPI0) - */ - -typedef struct { /*!< (@ 0x40058000) SPI0 Structure */ - __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */ - __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */ - __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared - by writing a 1 to that bit position */ - __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete - value may be read from this register. Writing a 1 to any implemented - bit position causes that bit to be set. */ - __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any - implemented bit position causes the corresponding bit in INTENSET - to be cleared. */ - __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */ - __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */ - __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */ - __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */ - __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */ - __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */ -} LPC_SPI0_Type; - - -/* ================================================================================ */ -/* ================ USART0 ================ */ -/* ================================================================================ */ - - -/** - * @brief USART0 (USART0) - */ - -typedef struct { /*!< (@ 0x40064000) USART0 Structure */ - __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration - settings that typically are not changed during operation. */ - __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings - that are more likely to change during operation. */ - __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value - can be read here. Writing ones clears some bits in the register. - Some bits can be cleared by writing a 1 to them. */ - __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains - an individual interrupt enable bit for each potential USART - interrupt. A complete value may be read from this register. - Writing a 1 to any implemented bit position causes that bit - to be set. */ - __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing - any combination of bits in the INTENSET register. Writing a - 1 to any implemented bit position causes the corresponding bit - to be cleared. */ - __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character - received. */ - __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines - the last character received with the current USART receive status. - Allows DMA or software to recover incoming data and status together. */ - __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted - is written here. */ - __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer - baud rate divisor value. */ - __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts - that are currently enabled. */ - __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous - communication. */ - __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */ -} LPC_USART0_Type; - - -/* ================================================================================ */ -/* ================ CRC ================ */ -/* ================================================================================ */ - - -/** - * @brief Cyclic Redundancy Check (CRC) engine (CRC) - */ - -typedef struct { /*!< (@ 0x50000000) CRC Structure */ - __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */ - __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */ - - union { - __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */ - __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */ - }; -} LPC_CRC_Type; - - -/* ================================================================================ */ -/* ================ SCT ================ */ -/* ================================================================================ */ - - -/** - * @brief State Configurable Timer (SCT) (SCT) - */ - -typedef struct { /*!< (@ 0x50004000) SCT Structure */ - __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */ - __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */ - __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */ - __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */ - __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */ - __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */ - __I uint32_t RESERVED0[10]; - __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */ - __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */ - __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */ - __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */ - __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */ - __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */ - __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */ - __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */ - __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */ - __I uint32_t RESERVED1[35]; - __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */ - __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */ - __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */ - __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */ - -union { - union { - __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - }; - - union { - __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - }; - - union { - __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to - 7; REGMOD0 to REGMODE7 = 1 */ - __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0 - to 7; REGMOD0 to REGMODE7 = 0 */ - }; - __IO uint32_t CAP[8]; - __IO uint32_t MATCH[8]; -}; - __I uint32_t RESERVED2[56]; - - union { - struct { - union { - __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - }; - - union { - __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - - union { - __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0 - = 1 to REGMODE7 = 1 */ - __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0 - = 0 to REGMODE7 = 0 */ - }; - }; - __IO uint32_t MATCHREL[8]; - }; - __I uint32_t RESERVED3[56]; - - union { - struct { - __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */ - __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */ - __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */ - __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */ - __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */ - __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */ - __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */ - __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */ - __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */ - __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */ - __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */ - __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */ - __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */ - __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */ - __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */ - __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */ - }; - __IO struct { - uint32_t STATE; - uint32_t CTRL; - } EVENT[8]; - }; - - __I uint32_t RESERVED4[112]; - - union { - struct { - __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */ - __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */ - __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */ - __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */ - __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */ - __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */ - __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */ - __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */ - __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */ - __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */ - __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */ - __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */ - }; - __IO struct { - uint32_t SET; - uint32_t CLR; - } OUT[6]; -}; - -} LPC_SCT_Type; - - -/* ================================================================================ */ -/* ================ DMA ================ */ -/* ================================================================================ */ - - -/** - * @brief DMA controller (DMA) - */ - -typedef struct { /*!< (@ 0x50008000) DMA Structure */ - __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */ - __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */ - __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */ - __I uint32_t RESERVED0[5]; - __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */ - __I uint32_t RESERVED1; - __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */ - __I uint32_t RESERVED2; - __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */ - __I uint32_t RESERVED3; - __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */ - __I uint32_t RESERVED4; - __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */ - __I uint32_t RESERVED5; - __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */ - __I uint32_t RESERVED6; - __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */ - __I uint32_t RESERVED7; - __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */ - __I uint32_t RESERVED8; - __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */ - __I uint32_t RESERVED9; - __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */ - __I uint32_t RESERVED10; - __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */ - __I uint32_t RESERVED11; - __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */ - __I uint32_t RESERVED12[225]; - __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED13; - __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED14; - __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED15; - __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED16; - __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED17; - __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED18; - __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED19; - __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED20; - __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED21; - __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED22; - __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED23; - __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED24; - __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED25; - __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED26; - __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED27; - __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED28; - __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel - 0. */ - __I uint32_t RESERVED29; - __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */ - __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */ - __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel - 0. */ -} LPC_DMA_Type; - - -/* ================================================================================ */ -/* ================ GPIO_PORT ================ */ -/* ================================================================================ */ - - -/** - * @brief General Purpose I/O port (GPIO) (GPIO_PORT) - */ - -typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */ - __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */ - __I uint8_t RESERVED0[4067]; - __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */ - __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */ - __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */ - __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */ - __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */ - __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */ - __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */ - __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */ - __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */ - __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */ - __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */ - __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */ - __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */ - __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */ - __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */ - __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */ - __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */ - __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */ - __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */ - __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */ - __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */ - __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */ - __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */ - __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */ - __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */ - __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */ - __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */ - __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */ - __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */ - __I uint32_t RESERVED1[995]; - __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */ - __I uint32_t RESERVED2[31]; - __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */ - __I uint32_t RESERVED3[31]; - __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */ - __I uint32_t RESERVED4[31]; - __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */ - __I uint32_t RESERVED5[31]; - __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits - for port 0 */ - __I uint32_t RESERVED6[31]; - __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */ - __I uint32_t RESERVED7[31]; - __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */ - __I uint32_t RESERVED8[31]; - __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */ - __I uint32_t RESERVED9[31]; - __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */ - __I uint32_t RESERVED10[31]; - __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */ -} LPC_GPIO_PORT_Type; - - -/* ================================================================================ */ -/* ================ PIN_INT ================ */ -/* ================================================================================ */ - - -/** - * @brief Pin interrupt and pattern match engine (PIN_INT) - */ - -typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */ - __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */ - __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt - enable register */ - __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set - register */ - __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt - clear register */ - __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt - enable register */ - __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt - set register */ - __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt - clear register */ - __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */ - __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */ - __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */ - __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */ - __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source - register */ - __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration - register */ -} LPC_PIN_INT_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define LPC_WWDT_BASE 0x40000000UL -#define LPC_MRT_BASE 0x40004000UL -#define LPC_WKT_BASE 0x40008000UL -#define LPC_SWM_BASE 0x4000C000UL -#define LPC_ADC_BASE 0x4001C000UL -#define LPC_PMU_BASE 0x40020000UL -#define LPC_CMP_BASE 0x40024000UL -#define LPC_DMATRIGMUX_BASE 0x40028000UL -#define LPC_INPUTMUX_BASE 0x4002C000UL -#define LPC_FLASHCTRL_BASE 0x40040000UL -#define LPC_IOCON_BASE 0x40044000UL -#define LPC_SYSCON_BASE 0x40048000UL -#define LPC_I2C0_BASE 0x40050000UL -#define LPC_I2C1_BASE 0x40054000UL -#define LPC_SPI0_BASE 0x40058000UL -#define LPC_SPI1_BASE 0x4005C000UL -#define LPC_USART0_BASE 0x40064000UL -#define LPC_USART1_BASE 0x40068000UL -#define LPC_USART2_BASE 0x4006C000UL -#define LPC_I2C2_BASE 0x40070000UL -#define LPC_I2C3_BASE 0x40074000UL -#define LPC_CRC_BASE 0x50000000UL -#define LPC_SCT_BASE 0x50004000UL -#define LPC_DMA_BASE 0x50008000UL -#define LPC_GPIO_PORT_BASE 0xA0000000UL -#define LPC_PIN_INT_BASE 0xA0004000UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE) -#define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE) -#define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE) -#define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE) -#define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE) -#define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE) -#define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE) -#define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE) -#define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE) -#define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE) -#define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE) -#define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE) -#define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE) -#define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE) -#define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE) -#define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE) -#define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE) -#define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE) -#define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE) -#define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE) -#define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE) -#define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE) -#define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE) -#define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE) -#define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE) -#define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group LPC82x */ -/** @} */ /* End of group (null) */ - -#ifdef __cplusplus -} -#endif - - -#endif /* LPC82x_H */ - diff --git a/targets/TARGET_NXP/TARGET_LPC82X/device/cmsis.h b/targets/TARGET_NXP/TARGET_LPC82X/device/cmsis.h deleted file mode 100644 index dc68e39335..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC8xx specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "LPC82x.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/device/cmsis_nvic.h b/targets/TARGET_NXP/TARGET_LPC82X/device/cmsis_nvic.h deleted file mode 100644 index 673754cf2a..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/device/cmsis_nvic.h +++ /dev/null @@ -1,37 +0,0 @@ -/* mbed Microcontroller Library - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_RAM_VECTOR_ADDRESS 0x10000000 // Vectors positioned at start of RAM - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/device/system_LPC82x.h b/targets/TARGET_NXP/TARGET_LPC82X/device/system_LPC82x.h deleted file mode 100644 index a80f832909..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/device/system_LPC82x.h +++ /dev/null @@ -1,63 +0,0 @@ -/****************************************************************************** - * @file: system_LPC8xx.h - * @purpose: CMSIS Cortex-M0+ Device Peripheral Access Layer Header File - * for the NXP LPC8xx Device Series - * @version: V1.0 - * @date: 16. Aug. 2012 - *---------------------------------------------------------------------------- - * - * Copyright (C) 2012 ARM Limited. All rights reserved. - * - * ARM Limited (ARM) is supplying this software for use with Cortex-M0+ - * processor based microcontrollers. This file can be freely distributed - * within development tools that are supporting such ARM based processors. - * - * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED - * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF - * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. - * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR - * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. - * - ******************************************************************************/ - - -#ifndef __SYSTEM_LPC8xx_H -#define __SYSTEM_LPC8xx_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ -extern uint32_t MainClock; /*!< Main Clock Frequency */ - - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* __SYSTEM_LPC8xx_H */ diff --git a/targets/TARGET_NXP/TARGET_LPC82X/gpio_api.c b/targets/TARGET_NXP/TARGET_LPC82X/gpio_api.c deleted file mode 100644 index 8eb2a2b2f4..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/gpio_api.c +++ /dev/null @@ -1,72 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -static int gpio_enabled = 0; - -static void gpio_enable(void) -{ - gpio_enabled = 1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 6); - - /* Peripheral reset control to GPIO and GPIO INT, a "1" bring it out of reset. */ - LPC_SYSCON->PRESETCTRL &= ~(1 << 10); - LPC_SYSCON->PRESETCTRL |= (1 << 10); -} - -uint32_t gpio_set(PinName pin) -{ - if (!gpio_enabled) - gpio_enable(); - - return (1 << ((int)pin >> PIN_SHIFT)); -} - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) - return; - - obj->mask = gpio_set(pin); - - obj->reg_set = &LPC_GPIO_PORT->SET0; - obj->reg_clr = &LPC_GPIO_PORT->CLR0; - obj->reg_in = &LPC_GPIO_PORT->PIN0; - obj->reg_dir = &LPC_GPIO_PORT->DIR0; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - switch (direction) { - case PIN_INPUT : - *obj->reg_dir &= ~obj->mask; - break; - case PIN_OUTPUT: - *obj->reg_dir |= obj->mask; - break; - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c b/targets/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c deleted file mode 100644 index a8f7ab4cd8..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/gpio_irq_api.c +++ /dev/null @@ -1,145 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include - -#include "cmsis.h" -#include "gpio_irq_api.h" -#include "mbed_error.h" - -#if DEVICE_INTERRUPTIN - -#define CHANNEL_NUM 8 -#define LPC_GPIO_X LPC_PIN_INT -#define PININT_IRQ PIN_INT0_IRQn - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; -static gpio_irq_handler irq_handler; - -static inline void handle_interrupt_in(uint32_t channel) -{ - uint32_t ch_bit = (1 << channel); - // Return immediately if: - // * The interrupt was already served - // * There is no user handler - // * It is a level interrupt, not an edge interrupt - if ( ((LPC_GPIO_X->IST & ch_bit) == 0) || - (channel_ids[channel] == 0 ) || - (LPC_GPIO_X->ISEL & ch_bit ) ) return; - - if ((LPC_GPIO_X->IENR & ch_bit) && (LPC_GPIO_X->RISE & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_RISE); - LPC_GPIO_X->RISE = ch_bit; - } - if ((LPC_GPIO_X->IENF & ch_bit) && (LPC_GPIO_X->FALL & ch_bit)) { - irq_handler(channel_ids[channel], IRQ_FALL); - } - LPC_GPIO_X->IST = ch_bit; -} - -void gpio_irq0(void) {handle_interrupt_in(0);} -void gpio_irq1(void) {handle_interrupt_in(1);} -void gpio_irq2(void) {handle_interrupt_in(2);} -void gpio_irq3(void) {handle_interrupt_in(3);} -void gpio_irq4(void) {handle_interrupt_in(4);} -void gpio_irq5(void) {handle_interrupt_in(5);} -void gpio_irq6(void) {handle_interrupt_in(6);} -void gpio_irq7(void) {handle_interrupt_in(7);} - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - if (pin == NC) return -1; - - irq_handler = handler; - - int found_free_channel = 0; - int i = 0; - for (i=0; ich = i; - found_free_channel = 1; - break; - } - } - if (!found_free_channel) return -1; - - /* Enable AHB clock to the GPIO domain. */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1<<6); - - LPC_SYSCON->PINTSEL[obj->ch] = (pin >> PIN_SHIFT); - - // Interrupt Wake-Up Enable - LPC_SYSCON->STARTERP0 |= 1 << obj->ch; - - void (*channels_irq)(void) = NULL; - switch (obj->ch) { - case 0: channels_irq = &gpio_irq0; break; - case 1: channels_irq = &gpio_irq1; break; - case 2: channels_irq = &gpio_irq2; break; - case 3: channels_irq = &gpio_irq3; break; - case 4: channels_irq = &gpio_irq4; break; - case 5: channels_irq = &gpio_irq5; break; - case 6: channels_irq = &gpio_irq6; break; - case 7: channels_irq = &gpio_irq7; break; - } - NVIC_SetVector((IRQn_Type)(PININT_IRQ + obj->ch), (uint32_t)channels_irq); - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); - - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->ch] = 0; - LPC_SYSCON->STARTERP0 &= ~(1 << obj->ch); -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - unsigned int ch_bit = (1 << obj->ch); - - // Clear interrupt - if (!(LPC_GPIO_X->ISEL & ch_bit)) - LPC_GPIO_X->IST = ch_bit; - - // Edge trigger - LPC_GPIO_X->ISEL &= ~ch_bit; - if (event == IRQ_RISE) { - if (enable) { - LPC_GPIO_X->IENR |= ch_bit; - } else { - LPC_GPIO_X->IENR &= ~ch_bit; - } - } else { - if (enable) { - LPC_GPIO_X->IENF |= ch_bit; - } else { - LPC_GPIO_X->IENF &= ~ch_bit; - } - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - NVIC_EnableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - NVIC_DisableIRQ((IRQn_Type)(PININT_IRQ + obj->ch)); -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/gpio_object.h b/targets/TARGET_NXP/TARGET_LPC82X/gpio_object.h deleted file mode 100644 index eac21ab67e..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/gpio_object.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c b/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c deleted file mode 100644 index 3c0fe21901..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/i2c_api.c +++ /dev/null @@ -1,652 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include - -#include "i2c_api.h" -#include "cmsis.h" -#include "pinmap.h" - -#define LPC824_I2C0_FMPLUS 1 - -#if DEVICE_I2C - -static const SWM_Map SWM_I2C_SDA[] = { - //PINASSIGN Register ID, Pinselect bitfield position - { 9, 8}, - { 9, 24}, - {10, 8}, -}; - -static const SWM_Map SWM_I2C_SCL[] = { - //PINASSIGN Register ID, Pinselect bitfield position - { 9, 16}, - {10, 0}, - {10, 16}, -}; - -// Pinmap used for testing only -static const PinMap PinMap_I2C_testing[] = { - {P0_0, 1, 0}, - {P0_1, 1, 0}, - {P0_2, 1, 0}, - {P0_3, 1, 0}, - {P0_4, 1, 0}, - {P0_5, 1, 0}, - {P0_6, 1, 0}, - {P0_7, 1, 0}, - {P0_8, 1, 0}, - {P0_9, 1, 0}, - {P0_10, 1, 0}, - {P0_11, 1, 0}, - {P0_12, 1, 0}, - {P0_13, 1, 0}, - {P0_14, 1, 0}, - {P0_15, 1, 0}, - {P0_16, 1, 0}, - {P0_17, 1, 0}, - {P0_18, 1, 0}, - {P0_19, 1, 0}, - {P0_20, 1, 0}, - {P0_21, 1, 0}, - {P0_22, 1, 0}, - {P0_23, 1, 0}, - {P0_24, 1, 0}, - {P0_25, 1, 0}, - {P0_26, 1, 0}, - {P0_27, 1, 0}, - {P0_28, 1, 0}, - - {NC, NC, 0} -}; - -static int i2c_used = 0; -static uint8_t repeated_start = 0; - -#define I2C_DAT(x) (x->i2c->MSTDAT) -#define I2C_STAT(x) ((x->i2c->STAT >> 1) & (0x07)) - -static inline void i2c_power_enable(int ch) -{ - switch(ch) { - case 0: - // I2C0, Same as for LPC812 - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 5); - LPC_SYSCON->PRESETCTRL &= ~(1 << 6); - LPC_SYSCON->PRESETCTRL |= (1 << 6); - break; - case 1: - case 2: - case 3: - // I2C1,I2C2 or I2C3. Not available for LPC812 - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (20 + ch)); - LPC_SYSCON->PRESETCTRL &= ~(1 << (13 + ch)); - LPC_SYSCON->PRESETCTRL |= (1 << (13 + ch)); - break; - default: - break; - } -} - - -static inline void i2c_interface_enable(i2c_t *obj) { - obj->i2c->CFG |= (1 << 0); // Enable Master mode -// obj->i2c->CFG &= ~(1 << 1); // Disable Slave mode -} - - -static int get_available_i2c(void) { - int i; - for (i=0; i<3; i++) { - if ((i2c_used & (1 << i)) == 0) - return i+1; - } - return -1; -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - const SWM_Map *swm; - uint32_t regVal; - int i2c_ch = 0; - - //LPC824 - //I2C0 can support FM+ but only on P0_11 and P0_10 - if (sda == I2C_SDA && scl == I2C_SCL) { - //Select I2C mode for P0_11 and P0_10 - LPC_SWM->PINENABLE0 &= ~(0x3 << 11); - -#if(LPC824_I2C0_FMPLUS == 1) - // Enable FM+ mode on P0_11, P0_10 - LPC_IOCON->PIO0_10 &= ~(0x3 << 8); - LPC_IOCON->PIO0_10 |= (0x2 << 8); //FM+ mode - LPC_IOCON->PIO0_11 &= ~(0x3 << 8); - LPC_IOCON->PIO0_11 |= (0x2 << 8); //FM+ mode -#endif - } - else { - //Select any other pin for I2C1, I2C2 or I2C3 - i2c_ch = get_available_i2c(); - if (i2c_ch == -1) - return; - i2c_used |= (1 << (i2c_ch - 1)); - - swm = &SWM_I2C_SDA[i2c_ch - 1]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((sda >> PIN_SHIFT) << swm->offset); - - swm = &SWM_I2C_SCL[i2c_ch - 1]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((scl >> PIN_SHIFT) << swm->offset); - } - - switch(i2c_ch) { - case 0: - obj->i2c = (LPC_I2C0_Type *)LPC_I2C0; - break; - case 1: - obj->i2c = (LPC_I2C0_Type *)LPC_I2C1; - break; - case 2: - obj->i2c = (LPC_I2C0_Type *)LPC_I2C2; - break; - case 3: - obj->i2c = (LPC_I2C0_Type *)LPC_I2C3; - break; - default: - break; - } - - // enable power - i2c_power_enable(i2c_ch); - // set default frequency at 100k - i2c_frequency(obj, 100000); - i2c_interface_enable(obj); -} - - -static inline int i2c_status(i2c_t *obj) { - return I2C_STAT(obj); -} - -// Wait until the Master Serial Interrupt (SI) is set -// Timeout when it takes too long. -static int i2c_wait_SI(i2c_t *obj) { - int timeout = 0; - while (!(obj->i2c->STAT & (1 << 0))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} - - -//Attention. Spec says: First store Address in DAT before setting STA ! -//Undefined state when using single byte I2C operations and too much delay -//between i2c_start and do_i2c_write(Address). -//Also note that lpc812/824 will immediately continue reading a byte when Address b0 == 1 -inline int i2c_start(i2c_t *obj) { - int status = 0; - if (repeated_start) { - obj->i2c->MSTCTL = (1 << 1) | (1 << 0); // STA bit and Continue bit to complete previous RD or WR - repeated_start = 0; - } else { - obj->i2c->MSTCTL = (1 << 1); // STA bit - } - return status; -} - -//Generate Stop condition and wait until bus is Idle -//Will also send NAK for previous RD -inline int i2c_stop(i2c_t *obj) { - int timeout = 0; - - // STP bit and Continue bit. Sends NAK to complete previous RD - obj->i2c->MSTCTL = (1 << 2) | (1 << 0); - - //Spin until Ready (b0 == 1)and Status is Idle (b3..b1 == 000) - while ((obj->i2c->STAT & ((7 << 1) | (1 << 0))) != ((0 << 1) | (1 << 0))) { - timeout ++; - if (timeout > 100000) return 1; - } - - // repeated_start = 0; // bus free - return 0; -} - -//Spec says: first check Idle and status is Ok -static inline int i2c_do_write(i2c_t *obj, int value, uint8_t addr) { - // write the data - I2C_DAT(obj) = value; - - if (!addr) - obj->i2c->MSTCTL = (1 << 0); //Set continue for data. Should not be set for addr since that uses STA - - // wait and return status - i2c_wait_SI(obj); - return i2c_status(obj); -} - - -//Attention, correct Order: wait for data ready, read data, read status, continue, return -//Dont read DAT or STAT when not ready, so dont read after setting continue. -//Results may be invalid when next read is underway. -static inline int i2c_do_read(i2c_t *obj, int last) { - // wait for it to arrive - i2c_wait_SI(obj); - if (!last) - obj->i2c->MSTCTL = (1 << 0); //ACK and Continue - - // return the data - return (I2C_DAT(obj) & 0xFF); -} - - -void i2c_frequency(i2c_t *obj, int hz) { - // No peripheral clock divider on the M0 - uint32_t PCLK = SystemCoreClock; - - uint32_t clkdiv = PCLK / (hz * 4) - 1; - - obj->i2c->CLKDIV = clkdiv; - obj->i2c->MSTTIME = 0; -} - -// The I2C does a read or a write as a whole operation -// There are two types of error conditions it can encounter -// 1) it can not obtain the bus -// 2) it gets error responses at part of the transmission -// -// We tackle them as follows: -// 1) we retry until we get the bus. we could have a "timeout" if we can not get it -// which basically turns it in to a 2) -// 2) on error, we use the standard error mechanisms to report/debug -// -// Therefore an I2C transaction should always complete. If it doesn't it is usually -// because something is setup wrong (e.g. wiring), and we don't need to programatically -// check for that -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) { - int count, status; - - //Store the address+RD and then generate STA - I2C_DAT(obj) = address | 0x01; - i2c_start(obj); - - // Wait for completion of STA and Sending of SlaveAddress+RD and first Read byte - i2c_wait_SI(obj); - status = i2c_status(obj); - if (status == 0x03) { // NAK on SlaveAddress - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - // Read in all except last byte - for (count = 0; count < (length-1); count++) { - - // Wait for it to arrive, note that first byte read after address+RD is already waiting - i2c_wait_SI(obj); - status = i2c_status(obj); - if (status != 0x01) { // RX RDY - i2c_stop(obj); - return count; - } - data[count] = I2C_DAT(obj) & 0xFF; // Store read byte - - obj->i2c->MSTCTL = (1 << 0); // Send ACK and Continue to read - } - - // Read final byte - // Wait for it to arrive - i2c_wait_SI(obj); - - status = i2c_status(obj); - if (status != 0x01) { // RX RDY - i2c_stop(obj); - return count; - } - data[count] = I2C_DAT(obj) & 0xFF; // Store final read byte - - // If not repeated start, send stop. - if (stop) { - i2c_stop(obj); // Also sends NAK for last read byte - } else { - repeated_start = 1; - } - - return length; -} - - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) { - int i, status; - - //Store the address+/WR and then generate STA - I2C_DAT(obj) = address & 0xFE; - i2c_start(obj); - - // Wait for completion of STA and Sending of SlaveAddress+/WR - i2c_wait_SI(obj); - status = i2c_status(obj); - if (status == 0x03) { // NAK SlaveAddress - i2c_stop(obj); - return I2C_ERROR_NO_SLAVE; - } - - //Write all bytes - for (i=0; ii2c->SLVDAT) -#define I2C_SLVSTAT(x) ((x->i2c->STAT >> 9) & (0x03)) -#define I2C_SLVSI(x) ((x->i2c->STAT >> 8) & (0x01)) -//#define I2C_SLVCNT(x) (x->i2c->SLVCTL = (1 << 0)) -//#define I2C_SLVNAK(x) (x->i2c->SLVCTL = (1 << 1)) - -#if(0) -// Wait until the Slave Serial Interrupt (SI) is set -// Timeout when it takes too long. -static int i2c_wait_slave_SI(i2c_t *obj) { - int timeout = 0; - while (!(obj->i2c->STAT & (1 << 8))) { - timeout++; - if (timeout > 100000) return -1; - } - return 0; -} -#endif - -void i2c_slave_mode(i2c_t *obj, int enable_slave) { - - if (enable_slave) { -// obj->i2c->CFG &= ~(1 << 0); //Disable Master mode - obj->i2c->CFG |= (1 << 1); //Enable Slave mode - } - else { -// obj->i2c->CFG |= (1 << 0); //Enable Master mode - obj->i2c->CFG &= ~(1 << 1); //Disable Slave mode - } -} - -// Wait for next I2C event and find out what is going on -// -int i2c_slave_receive(i2c_t *obj) { - int addr; - - // Check if there is any data pending - if (! I2C_SLVSI(obj)) { - return 0; //NoData - }; - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - - // Get the received address - addr = I2C_SLVDAT(obj) & 0xFF; - // Send ACK on address and Continue - obj->i2c->SLVCTL = (1 << 0); - - if (addr == 0x00) { - return 2; //WriteGeneral - } - //check the RW bit - if ((addr & 0x01) == 0x01) { - return 1; //ReadAddressed - } - else { - return 3; //WriteAddressed - } - //break; - - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - // Oops, should never get here... - obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data, try to recover... - return 0; //NoData - - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - // Oops, should never get here... - I2C_SLVDAT(obj) = 0xFF; // Send dummy data for transmission - obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... - return 0; //NoData - - case 0x3: // Reserved. - default: // Oops, should never get here... - obj->i2c->SLVCTL = (1 << 0); // Continue and try to recover... - return 0; //NoData - //break; - } //switch status -} - -// The dedicated I2C Slave byte read and byte write functions need to be called -// from 'common' mbed I2CSlave API for devices that have separate Master and -// Slave engines such as the lpc812 and lpc1549. - -//Called when Slave is addressed for Write, Slave will receive Data in polling mode -//Parameter last=1 means received byte will be NACKed. -int i2c_slave_byte_read(i2c_t *obj, int last) { - int data; - - // Wait for data - while (!I2C_SLVSI(obj)); // Wait forever -//if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Dont bother to check State, were not returning it anyhow.. -//if (I2C_SLVSTAT(obj)) == 0x01) { - // Slave receive. Received data is available (Slave Receiver mode). -//}; - - data = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data - if (last) { - obj->i2c->SLVCTL = (1 << 1); // Send NACK on received data and Continue - } - else { - obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read - } - - return data; -} - - -//Called when Slave is addressed for Read, Slave will send Data in polling mode -// -int i2c_slave_byte_write(i2c_t *obj, int data) { - - // Wait until Ready - while (!I2C_SLVSI(obj)); // Wait forever -// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - // I2C Restart occurred - return -1; - //break; - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - // Should not get here... - return -2; - //break; - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - I2C_SLVDAT(obj) = data & 0xFF; // Store the data for transmission - obj->i2c->SLVCTL = (1 << 0); // Continue to send - - return 1; - //break; - case 0x3: // Reserved. - default: - // Should not get here... - return -3; - //break; - } // switch status -} - - -//Called when Slave is addressed for Write, Slave will receive Data in polling mode -//Parameter length (>=1) is the maximum allowable number of bytes. All bytes will be ACKed. -int i2c_slave_read(i2c_t *obj, char *data, int length) { - int count=0; - - // Read and ACK all expected bytes - while (count < length) { - // Wait for data - while (!I2C_SLVSI(obj)); // Wait forever -// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - // I2C Restart occurred - return -1; - //break; - - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - data[count] = I2C_SLVDAT(obj) & 0xFF; // Get and store the received data - obj->i2c->SLVCTL = (1 << 0); // Send ACK on data and Continue to read - break; - - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - case 0x3: // Reserved. - default: // Should never get here... - return -2; - //break; - } // switch status - - count++; - } // for all bytes - - return count; // Received the expected number of bytes -} - - -//Called when Slave is addressed for Read, Slave will send Data in polling mode -//Parameter length (>=1) is the maximum number of bytes. Exit when Slave byte is NACKed. -int i2c_slave_write(i2c_t *obj, const char *data, int length) { - int count; - - // Send and all bytes or Exit on NAK - for (count=0; count < length; count++) { - // Wait until Ready for data - while (!I2C_SLVSI(obj)); // Wait forever -// if (i2c_wait_slave_SI(obj) != 0) {return -2;} // Wait with timeout - - // Check State - switch(I2C_SLVSTAT(obj)) { - case 0x0: // Slave address plus R/W received - // At least one of the four slave addresses has been matched by hardware. - // You can figure out which address by checking Slave address match Index in STAT register. - // I2C Restart occurred - return -1; - //break; - case 0x1: // Slave receive. Received data is available (Slave Receiver mode). - // Should not get here... - return -2; - //break; - case 0x2: // Slave transmit. Data can be transmitted (Slave Transmitter mode). - I2C_SLVDAT(obj) = data[count] & 0xFF; // Store the data for transmission - obj->i2c->SLVCTL = (1 << 0); // Continue to send - break; - case 0x3: // Reserved. - default: - // Should not get here... - return -3; - //break; - } // switch status - } // for all bytes - - return length; // Transmitted the max number of bytes -} - - -// Set the four slave addresses. -void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) { - obj->i2c->SLVADR0 = (address & 0xFE); // Store address in address 0 register - obj->i2c->SLVADR1 = (0x00 & 0xFE); // Store general call write address in address 1 register - obj->i2c->SLVADR2 = (0x01); // Disable address 2 register - obj->i2c->SLVADR3 = (0x01); // Disable address 3 register - obj->i2c->SLVQUAL0 = (mask & 0xFE); // Qualifier mask for address 0 register. Any maskbit that is 1 will always be a match -} - -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/objects.h b/targets/TARGET_NXP/TARGET_LPC82X/objects.h deleted file mode 100644 index 2454b4dc10..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/objects.h +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct gpio_irq_s { - uint32_t ch; -}; - -struct serial_s { - LPC_USART0_Type *uart; - unsigned char index; -}; - -struct i2c_s { - LPC_I2C0_Type *i2c; - void *handler; -}; - -struct spi_s { - LPC_SPI0_Type *spi; - unsigned char spi_n; -}; - -struct analogin_s { - ADCName adc; -}; - -struct pwmout_s { - LPC_SCT_Type* pwm; - uint32_t pwm_ch; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/pinmap.c b/targets/TARGET_NXP/TARGET_LPC82X/pinmap.c deleted file mode 100644 index 41b2144d8e..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/pinmap.c +++ /dev/null @@ -1,46 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" - - -void pin_function(PinName pin, int function) -{ - // do nothing - return; -} - -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - if ((pin == P0_10) || (pin == P0_11)) { - // True open-drain pins can be configured for different I2C-bus speeds - return; - } - - __IO uint32_t *reg = (uint32_t *)(LPC_IOCON_BASE + (pin & 0xFF)); - - if (mode == OpenDrain) { - *reg |= (1 << 10); - } else { - uint32_t tmp = *reg; - tmp &= ~(0x3 << 3); - tmp |= (mode & 0x3) << 3; - *reg = tmp; - } -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/pwmout_api.c b/targets/TARGET_NXP/TARGET_LPC82X/pwmout_api.c deleted file mode 100644 index 5384845c5d..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/pwmout_api.c +++ /dev/null @@ -1,243 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -#if DEVICE_PWMOUT - -// bit flags for used SCTs -static unsigned char sct_used = 0; - -// Pinmap used for testing only -static const PinMap PinMap_PWM_testing[] = { - {P0_0, 1, 0}, - {P0_1, 1, 0}, - {P0_2, 1, 0}, - {P0_3, 1, 0}, - {P0_4, 1, 0}, - {P0_5, 1, 0}, - {P0_6, 1, 0}, - {P0_7, 1, 0}, - {P0_8, 1, 0}, - {P0_9, 1, 0}, - {P0_10, 1, 0}, - {P0_11, 1, 0}, - {P0_12, 1, 0}, - {P0_13, 1, 0}, - {P0_14, 1, 0}, - {P0_15, 1, 0}, - {P0_16, 1, 0}, - {P0_17, 1, 0}, - {P0_18, 1, 0}, - {P0_19, 1, 0}, - {P0_20, 1, 0}, - {P0_21, 1, 0}, - {P0_22, 1, 0}, - {P0_23, 1, 0}, - {P0_24, 1, 0}, - {P0_25, 1, 0}, - {P0_26, 1, 0}, - {P0_27, 1, 0}, - {P0_28, 1, 0}, - - {NC, NC, 0} -}; - -static int get_available_sct() -{ - int i; - for (i = 0; i < 4; i++) { - if ((sct_used & (1 << i)) == 0) - return i; - } - return -1; -} - -void pwmout_init(pwmout_t* obj, PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - - int sct_n = get_available_sct(); - if (sct_n == -1) { - error("No available SCT"); - } - - sct_used |= (1 << sct_n); - - obj->pwm = (LPC_SCT_Type*)LPC_SCT; - obj->pwm_ch = sct_n; - - LPC_SCT_Type* pwm = obj->pwm; - - // Enable the SCT clock - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); - - // Clear peripheral reset the SCT: - LPC_SYSCON->PRESETCTRL |= (1 << 8); - - switch(sct_n) { - case 0: - // SCT_OUT0 - LPC_SWM->PINASSIGN[7] &= ~0xFF000000; - LPC_SWM->PINASSIGN[7] |= ((pin >> PIN_SHIFT) << 24); - break; - case 1: - // SCT_OUT1 - LPC_SWM->PINASSIGN[8] &= ~0x000000FF; - LPC_SWM->PINASSIGN[8] |= (pin >> PIN_SHIFT); - break; - case 2: - // SCT2_OUT2 - LPC_SWM->PINASSIGN[8] &= ~0x0000FF00; - LPC_SWM->PINASSIGN[8] |= ((pin >> PIN_SHIFT) << 8); - break; - case 3: - // SCT3_OUT3 - LPC_SWM->PINASSIGN[8] &= ~0x00FF0000; - LPC_SWM->PINASSIGN[8] |= ((pin >> PIN_SHIFT) << 16); - break; - default: - break; - } - - // Unified 32-bit counter, autolimit - pwm->CONFIG |= ((0x3 << 17) | 0x01); - - // halt and clear the counter - pwm->CTRL |= (1 << 2) | (1 << 3); - - // System Clock -> us_ticker (1)MHz - pwm->CTRL &= ~(0x7F << 5); - pwm->CTRL |= (((SystemCoreClock/1000000 - 1) & 0x7F) << 5); - - // Set event number - pwm->OUT[sct_n].SET = (1 << ((sct_n * 2) + 0)); - pwm->OUT[sct_n].CLR = (1 << ((sct_n * 2) + 1)); - - pwm->EVENT[(sct_n * 2) + 0].CTRL = (1 << 12) | ((sct_n * 2) + 0); // match event - pwm->EVENT[(sct_n * 2) + 0].STATE = 0xFFFFFFFF; - pwm->EVENT[(sct_n * 2) + 1].CTRL = (1 << 12) | ((sct_n * 2) + 1); - pwm->EVENT[(sct_n * 2) + 1].STATE = 0xFFFFFFFF; - - // default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_ms(obj, 20); - pwmout_write (obj, 0); -} - -void pwmout_free(pwmout_t* obj) -{ - // Disable the SCT clock - LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); - sct_used &= ~(1 << obj->pwm_ch); -} - -void pwmout_write(pwmout_t* obj, float value) -{ - if (value < 0.0f) { - value = 0.0; - } else if (value > 1.0f) { - value = 1.0f; - } - uint32_t t_on = (uint32_t)((float)(obj->pwm->MATCHREL[obj->pwm_ch * 2] + 1) * value); - if (t_on > 0) { // duty is not 0% - if (value != 1.0f) { // duty is not 100% - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = t_on - 1; - // unhalt the counter - obj->pwm->CTRL &= ~(1 << 2); - } else { // duty is 100% - // halt and clear the counter - obj->pwm->CTRL |= (1 << 2) | (1 << 3); - // output level tied to high - obj->pwm->OUTPUT |= (1 << obj->pwm_ch); - } - } else { // duty is 0% - // halt and clear the counter - obj->pwm->CTRL |= (1 << 2) | (1 << 3); - // output level tied to low - obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch); - } -} - -float pwmout_read(pwmout_t* obj) -{ - uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1; - uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1; - float v = (float)t_on/(float)t_off; - return (v > 1.0f) ? (1.0f) : (v); -} - -void pwmout_period(pwmout_t* obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t* obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t* obj, int us) -{ - // The period are off by one for MATCHREL, so +1 to get actual value - uint32_t t_off = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] + 1; - uint32_t t_on = obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] + 1; - float v = (float)t_on/(float)t_off; - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 0] = (uint32_t)us - 1; - if (us > 0) { // PWM period is not 0 - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)((float)us * (float)v) - 1; - // unhalt the counter - obj->pwm->CTRL &= ~(1 << 2); - } else { // PWM period is 0 - // halt and clear the counter - obj->pwm->CTRL |= (1 << 2) | (1 << 3); - // output level tied to low - obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch); - } -} - -void pwmout_pulsewidth(pwmout_t* obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t* obj, int us) -{ - if (us > 0) { // PWM peried is not 0 - obj->pwm->MATCHREL[(obj->pwm_ch * 2) + 1] = (uint32_t)us - 1; - obj->pwm->CTRL &= ~(1 << 2); - } else { //PWM period is 0 - // halt and clear the counter - obj->pwm->CTRL |= (1 << 2) | (1 << 3); - // output level tied to low - obj->pwm->OUTPUT &= ~(1 << obj->pwm_ch); - } -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM_testing; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h b/targets/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h deleted file mode 100644 index 8969a6dd56..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/rom_i2c_8xx.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * @brief LPC8xx I2C ROM API declarations and functions - * - * @note - * Copyright(C) NXP Semiconductors, 2012 - * All rights reserved. - * - * @par - * Software that is described herein is for illustrative purposes only - * which provides customers with programming information regarding the - * LPC products. This software is supplied "AS IS" without any warranties of - * any kind, and NXP Semiconductors and its licensor disclaim any and - * all warranties, express or implied, including all implied warranties of - * merchantability, fitness for a particular purpose and non-infringement of - * intellectual property rights. NXP Semiconductors assumes no responsibility - * or liability for the use of the software, conveys no license or rights under any - * patent, copyright, mask work right, or any other intellectual property rights in - * or to any products. NXP Semiconductors reserves the right to make changes - * in the software without notification. NXP Semiconductors also makes no - * representation or warranty that such application will be suitable for the - * specified use without further testing or modification. - * - * @par - * Permission to use, copy, modify, and distribute this software and its - * documentation is hereby granted, under NXP Semiconductors' and its - * licensor's relevant copyrights in the software, without fee, provided that it - * is used in conjunction with NXP Semiconductors microcontrollers. This - * copyright, permission, and disclaimer notice must appear in all copies of - * this code. - */ - -#ifndef __ROM_I2C_8XX_H_ -#define __ROM_I2C_8XX_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup CHIP_I2CROM_8XX CHIP: LPC8xx I2C ROM API declarations and functions - * @ingroup CHIP_8XX_Drivers - * @{ - */ - -/** - * @brief LPC8xx I2C ROM driver handle structure - */ -typedef void *I2C_HANDLE_T; - -typedef uint32_t ErrorCode_t; - -/** - * @brief LPC8xx I2C ROM driver callback function - */ -typedef void (*I2C_CALLBK_T)(uint32_t err_code, uint32_t n); - -/** - * LPC8xx I2C ROM driver parameter structure - */ -typedef struct I2C_PARAM { - uint32_t num_bytes_send; /*!< No. of bytes to send */ - uint32_t num_bytes_rec; /*!< No. of bytes to receive */ - uint8_t *buffer_ptr_send; /*!< Pointer to send buffer */ - uint8_t *buffer_ptr_rec; /*!< Pointer to receive buffer */ - I2C_CALLBK_T func_pt; /*!< Callback function */ - uint8_t stop_flag; /*!< Stop flag */ - uint8_t dummy[3]; -} I2C_PARAM_T; - -/** - * LPC8xx I2C ROM driver result structure - */ -typedef struct I2C_RESULT { - uint32_t n_bytes_sent; /*!< No. of bytes sent */ - uint32_t n_bytes_recd; /*!< No. of bytes received */ -} I2C_RESULT_T; - -/** - * LPC8xx I2C ROM driver modes enum - */ -typedef enum CHIP_I2C_MODE { - IDLE, /*!< IDLE state */ - MASTER_SEND, /*!< Master send state */ - MASTER_RECEIVE, /*!< Master Receive state */ - SLAVE_SEND, /*!< Slave send state */ - SLAVE_RECEIVE /*!< Slave receive state */ -} CHIP_I2C_MODE_T; - -/** - * LPC8xx I2C ROM driver APIs structure - */ -typedef struct I2CD_API { - /*!< Interrupt Support Routine */ - void (*i2c_isr_handler)(I2C_HANDLE_T *handle); - - /*!< MASTER functions */ - ErrorCode_t (*i2c_master_transmit_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_receive_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_tx_rx_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_transmit_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_receive_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_master_tx_rx_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - - /*!< SLAVE functions */ - ErrorCode_t (*i2c_slave_receive_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_slave_transmit_poll)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_slave_receive_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_slave_transmit_intr)(I2C_HANDLE_T *handle, I2C_PARAM_T *param, I2C_RESULT_T *result); - ErrorCode_t (*i2c_set_slave_addr)(I2C_HANDLE_T *handle, uint32_t slave_addr_0_3, uint32_t slave_mask_0_3); - - /*!< OTHER support functions */ - uint32_t (*i2c_get_mem_size)(void); - I2C_HANDLE_T * (*i2c_setup)( uint32_t i2c_base_addr, uint32_t * start_of_ram); - ErrorCode_t (*i2c_set_bitrate)(I2C_HANDLE_T *handle, uint32_t p_clk_in_hz, uint32_t bitrate_in_bps); - uint32_t (*i2c_get_firmware_version)(void); - CHIP_I2C_MODE_T (*i2c_get_status)(I2C_HANDLE_T *handle); - ErrorCode_t (*i2c_set_timeout)(I2C_HANDLE_T *handle, uint32_t timeout); -} I2CD_API_T; - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __ROM_I2C_8XX_H_ */ diff --git a/targets/TARGET_NXP/TARGET_LPC82X/serial_api.c b/targets/TARGET_NXP/TARGET_LPC82X/serial_api.c deleted file mode 100644 index 60c27f5fad..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/serial_api.c +++ /dev/null @@ -1,422 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -#include "mbed_assert.h" -#include -#include - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -#if DEVICE_SERIAL - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 3 - -static const SWM_Map SWM_UART_TX[] = { - {0, 0}, - {1, 8}, - {2, 16}, -}; - -static const SWM_Map SWM_UART_RX[] = { - {0, 8}, - {1, 16}, - {2, 24}, -}; - -static const SWM_Map SWM_UART_RTS[] = { - {0, 16}, - {1, 24}, - {3, 0}, -}; - -static const SWM_Map SWM_UART_CTS[] = { - {0, 24}, - {2, 0}, - {3, 8} -}; - -// Pinmap used for testing only -static const PinMap PinMap_UART_testing[] = { - {P0_0, 1, 0}, - {P0_1, 1, 0}, - {P0_2, 1, 0}, - {P0_3, 1, 0}, - {P0_4, 1, 0}, - {P0_5, 1, 0}, - {P0_6, 1, 0}, - {P0_7, 1, 0}, - {P0_8, 1, 0}, - {P0_9, 1, 0}, - {P0_10, 1, 0}, - {P0_11, 1, 0}, - {P0_12, 1, 0}, - {P0_13, 1, 0}, - {P0_14, 1, 0}, - {P0_15, 1, 0}, - {P0_16, 1, 0}, - {P0_17, 1, 0}, - {P0_18, 1, 0}, - {P0_19, 1, 0}, - {P0_20, 1, 0}, - {P0_21, 1, 0}, - {P0_22, 1, 0}, - {P0_23, 1, 0}, - {P0_24, 1, 0}, - {P0_25, 1, 0}, - {P0_26, 1, 0}, - {P0_27, 1, 0}, - {P0_28, 1, 0}, - - {NC, NC, 0} -}; - -// bit flags for used UARTs -static unsigned char uart_used = 0; - -static int get_available_uart(void) -{ - int i; - for (i=0; iPINASSIGN[swm->n] & (0xFF << swm->offset); - assigned_tx = assigned_tx >> swm->offset; - // read assigned RX in the UART channel of switch matrix - swm = &SWM_UART_RX[ch]; - assigned_rx = LPC_SWM->PINASSIGN[swm->n] & (0xFF << swm->offset); - assigned_rx = assigned_rx >> swm->offset; - if ((assigned_tx == (uint32_t)(tx >> PIN_SHIFT)) && (assigned_rx == (uint32_t)(rx >> PIN_SHIFT))) { - obj->index = ch; - obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * ch)); - return 1; - } - } - return 0; -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) -{ - int is_stdio_uart = 0; - - if (check_duplication(obj, tx, rx) == 1) - return; - - int uart_n = get_available_uart(); - if (uart_n == -1) { - error("No available UART"); - } - obj->index = uart_n; - obj->uart = (LPC_USART0_Type *)(LPC_USART0_BASE + (0x4000 * uart_n)); - uart_used |= (1 << uart_n); - - const SWM_Map *swm; - uint32_t regVal; - - swm = &SWM_UART_TX[uart_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((tx >> PIN_SHIFT) << swm->offset); - - swm = &SWM_UART_RX[uart_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((rx >> PIN_SHIFT) << swm->offset); - - /* uart clock divided by 1 */ - LPC_SYSCON->UARTCLKDIV = 1; - - /* disable uart interrupts */ - NVIC_DisableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); - - /* Enable UART clock */ - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (14 + uart_n)); - - /* Peripheral reset control to UART, a "1" bring it out of reset. */ - LPC_SYSCON->PRESETCTRL &= ~(0x1 << (3 + uart_n)); - LPC_SYSCON->PRESETCTRL |= (0x1 << (3 + uart_n)); - - UARTSysClk = MainClock / LPC_SYSCON->UARTCLKDIV; - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - /* Clear all status bits. */ - obj->uart->STAT = CTS_DELTA | DELTA_RXBRK; - - /* enable uart interrupts */ - NVIC_EnableIRQ((IRQn_Type)(UART0_IRQn + uart_n)); - - /* Enable UART */ - obj->uart->CFG |= UART_EN; - - is_stdio_uart = ((tx == USBTX) && (rx == USBRX)); - - if (is_stdio_uart) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - uart_used &= ~(1 << obj->index); - serial_irq_ids[obj->index] = 0; -} - -void serial_baud(serial_t *obj, int baudrate) -{ - /* Integer divider: - BRG = UARTSysClk/(Baudrate * 16) - 1 - - Frational divider: - FRG = ((UARTSysClk / (Baudrate * 16 * (BRG + 1))) - 1) - - where - FRG = (LPC_SYSCON->UARTFRDADD + 1) / (LPC_SYSCON->UARTFRDSUB + 1) - - (1) The easiest way is set SUB value to 256, -1 encoded, thus SUB - register is 0xFF. - (2) In ADD register value, depending on the value of UartSysClk, - baudrate, BRG register value, and SUB register value, be careful - about the order of multiplier and divider and make sure any - multiplier doesn't exceed 32-bit boundary and any divider doesn't get - down below one(integer 0). - (3) ADD should be always less than SUB. - */ - obj->uart->BRG = UARTSysClk / 16 / baudrate - 1; - - LPC_SYSCON->UARTFRGDIV = 0xFF; - LPC_SYSCON->UARTFRGMULT = ( ((UARTSysClk / 16) * (LPC_SYSCON->UARTFRGDIV + 1)) / - (baudrate * (obj->uart->BRG + 1)) - ) - (LPC_SYSCON->UARTFRGDIV + 1); -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - // 0: 1 stop bits, 1: 2 stop bits - MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); - MBED_ASSERT((data_bits > 6) && (data_bits < 10)); // 0: 7 data bits ... 2: 9 data bits - MBED_ASSERT((parity == ParityNone) || (parity == ParityEven) || (parity == ParityOdd)); - stop_bits -= 1; - data_bits -= 7; - - int paritysel = 0; - switch (parity) { - case ParityNone: paritysel = 0; break; - case ParityEven: paritysel = 2; break; - case ParityOdd : paritysel = 3; break; - default: - break; - } - - // First disable the the usart as described in documentation and then enable while updating CFG - - // 24.6.1 USART Configuration register - // Remark: If software needs to change configuration values, the following sequence should - // be used: 1) Make sure the USART is not currently sending or receiving data. 2) Disable - // the USART by writing a 0 to the Enable bit (0 may be written to the entire register). 3) - // Write the new configuration value, with the ENABLE bit set to 1. - obj->uart->CFG &= ~(1 << 0); - - obj->uart->CFG = (1 << 0) // this will enable the usart - | (data_bits << 2) - | (paritysel << 4) - | (stop_bits << 6); -} - -/****************************************************************************** - * INTERRUPTS HANDLING - ******************************************************************************/ -static inline void uart_irq(SerialIrq irq_type, uint32_t index) -{ - if (serial_irq_ids[index] != 0) - irq_handler(serial_irq_ids[index], irq_type); -} - -void uart0_irq() {uart_irq((LPC_USART0->INTSTAT & RXRDY) ? RxIrq : TxIrq, 0);} -void uart1_irq() {uart_irq((LPC_USART1->INTSTAT & RXRDY) ? RxIrq : TxIrq, 1);} -void uart2_irq() {uart_irq((LPC_USART2->INTSTAT & RXRDY) ? RxIrq : TxIrq, 2);} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - uint32_t vector = 0; - switch ((int)obj->uart) { - case LPC_USART0_BASE: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break; - case LPC_USART1_BASE: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break; - case LPC_USART2_BASE: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break; - } - - if (enable) { - NVIC_DisableIRQ(irq_n); - obj->uart->INTENSET |= (1 << ((irq == RxIrq) ? 0 : 2)); - NVIC_SetVector(irq_n, vector); - NVIC_EnableIRQ(irq_n); - } else { // disable - obj->uart->INTENCLR |= (1 << ((irq == RxIrq) ? 0 : 2)); - if ( (obj->uart->INTENSET & (RXRDYEN | TXRDYEN)) == 0) { - NVIC_DisableIRQ(irq_n); - } - } -} - -/****************************************************************************** - * READ/WRITE - ******************************************************************************/ -int serial_getc(serial_t *obj) -{ - while (!serial_readable(obj)); - return obj->uart->RXDAT; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)); - obj->uart->TXDAT = c; -} - -int serial_readable(serial_t *obj) -{ - return obj->uart->STAT & RXRDY; -} - -int serial_writable(serial_t *obj) -{ - return obj->uart->STAT & TXRDY; -} - -void serial_clear(serial_t *obj) -{ - // [TODO] -} - -void serial_pinout_tx(PinName tx) -{ - -} - -void serial_break_set(serial_t *obj) -{ - obj->uart->CTL |= TXBRKEN; -} - -void serial_break_clear(serial_t *obj) -{ - obj->uart->CTL &= ~TXBRKEN; -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - const SWM_Map *swm_rts, *swm_cts; - uint32_t regVal_rts, regVal_cts; - - swm_rts = &SWM_UART_RTS[obj->index]; - swm_cts = &SWM_UART_CTS[obj->index]; - regVal_rts = LPC_SWM->PINASSIGN[swm_rts->n] & ~(0xFF << swm_rts->offset); - regVal_cts = LPC_SWM->PINASSIGN[swm_cts->n] & ~(0xFF << swm_cts->offset); - - if (FlowControlNone == type) { - LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset); - LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset); - obj->uart->CFG &= ~CTSEN; - return; - } - if ((FlowControlRTS == type || FlowControlRTSCTS == type) && (rxflow != NC)) { - LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | ((rxflow >> PIN_SHIFT) << swm_rts->offset); - if (FlowControlRTS == type) { - LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | (0xFF << swm_cts->offset); - obj->uart->CFG &= ~CTSEN; - } - } - if ((FlowControlCTS == type || FlowControlRTSCTS == type) && (txflow != NC)) { - LPC_SWM->PINASSIGN[swm_cts->n] = regVal_cts | ((txflow >> PIN_SHIFT) << swm_cts->offset); - obj->uart->CFG |= CTSEN; - if (FlowControlCTS == type) { - LPC_SWM->PINASSIGN[swm_rts->n] = regVal_rts | (0xFF << swm_rts->offset); - } - } -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_testing; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/sleep.c b/targets/TARGET_NXP/TARGET_LPC82X/sleep.c deleted file mode 100644 index 9f6deb51f8..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/sleep.c +++ /dev/null @@ -1,62 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" - - -//#define DEEPSLEEP -#define POWERDOWN - -void hal_sleep(void) -{ - //Normal sleep mode for PCON: - LPC_PMU->PCON &= ~0x03; - - //Normal sleep mode for ARM core: - SCB->SCR = 0; - - //And go to sleep - __WFI(); -} - -// Deepsleep/powerdown modes assume the device is configured to use its internal RC oscillator directly - -void hal_deepsleep(void) -{ - //Deep sleep in PCON - LPC_PMU->PCON &= ~0x03; - -#if defined(DEEPSLEEP) - LPC_PMU->PCON |= 0x01; -#elif defined(POWERDOWN) - LPC_PMU->PCON |= 0x02; -#endif - - //If brownout detection and WDT are enabled, keep them enabled during sleep - LPC_SYSCON->PDSLEEPCFG = LPC_SYSCON->PDRUNCFG; - - //After wakeup same stuff as currently enabled: - LPC_SYSCON->PDAWAKECFG = LPC_SYSCON->PDRUNCFG; - - //All interrupts may wake up: - LPC_SYSCON->STARTERP0 = 0xFF; - LPC_SYSCON->STARTERP1 = 0xFFFF; - - //Deep sleep for ARM core: - SCB->SCR = 1<<2; - - __WFI(); -} diff --git a/targets/TARGET_NXP/TARGET_LPC82X/spi_api.c b/targets/TARGET_NXP/TARGET_LPC82X/spi_api.c deleted file mode 100644 index e5704bce14..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/spi_api.c +++ /dev/null @@ -1,289 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" - -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -#if DEVICE_SPI - -static const SWM_Map SWM_SPI_SSEL[] = { - {4, 16}, - {6, 8}, -}; - -static const SWM_Map SWM_SPI_SCLK[] = { - {3, 24}, - {5, 16}, -}; - -static const SWM_Map SWM_SPI_MOSI[] = { - {4, 0}, - {5, 24}, -}; - -static const SWM_Map SWM_SPI_MISO[] = { - {4, 8}, - {6, 0}, -}; - -// Pinmap used for testing only -static const PinMap PinMap_SPI_testing[] = { - {P0_0, 1, 0}, - {P0_1, 1, 0}, - {P0_2, 1, 0}, - {P0_3, 1, 0}, - {P0_4, 1, 0}, - {P0_5, 1, 0}, - {P0_6, 1, 0}, - {P0_7, 1, 0}, - {P0_8, 1, 0}, - {P0_9, 1, 0}, - {P0_10, 1, 0}, - {P0_11, 1, 0}, - {P0_12, 1, 0}, - {P0_13, 1, 0}, - {P0_14, 1, 0}, - {P0_15, 1, 0}, - {P0_16, 1, 0}, - {P0_17, 1, 0}, - {P0_18, 1, 0}, - {P0_19, 1, 0}, - {P0_20, 1, 0}, - {P0_21, 1, 0}, - {P0_22, 1, 0}, - {P0_23, 1, 0}, - {P0_24, 1, 0}, - {P0_25, 1, 0}, - {P0_26, 1, 0}, - {P0_27, 1, 0}, - {P0_28, 1, 0}, - - {NC, NC, 0} -}; - -// bit flags for used SPIs -static unsigned char spi_used = 0; - -static int get_available_spi(void) -{ - int i; - for (i=0; i<2; i++) { - if ((spi_used & (1 << i)) == 0) - return i; - } - return -1; -} - -static inline void spi_disable(spi_t *obj); -static inline void spi_enable(spi_t *obj); - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - int spi_n = get_available_spi(); - if (spi_n == -1) { - error("No available SPI"); - } - obj->spi_n = spi_n; - spi_used |= (1 << spi_n); - - obj->spi = (spi_n) ? (LPC_SPI0_Type *)(LPC_SPI1_BASE) : (LPC_SPI0_Type *)(LPC_SPI0_BASE); - - const SWM_Map *swm; - uint32_t regVal; - - if (sclk != (PinName)NC) { - swm = &SWM_SPI_SCLK[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((sclk >> PIN_SHIFT) << swm->offset); - } - - if (mosi != (PinName)NC) { - swm = &SWM_SPI_MOSI[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((mosi >> PIN_SHIFT) << swm->offset); - } - - if (miso != (PinName)NC) { - swm = &SWM_SPI_MISO[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((miso >> PIN_SHIFT) << swm->offset); - } - - if (ssel != (PinName)NC) { - swm = &SWM_SPI_SSEL[obj->spi_n]; - regVal = LPC_SWM->PINASSIGN[swm->n] & ~(0xFF << swm->offset); - LPC_SWM->PINASSIGN[swm->n] = regVal | ((ssel >> PIN_SHIFT) << swm->offset); - } - - // clear interrupts - obj->spi->INTENCLR = 0x3f; - - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << (11 + obj->spi_n)); - LPC_SYSCON->PRESETCTRL &= ~(1 << obj->spi_n); - LPC_SYSCON->PRESETCTRL |= (1 << obj->spi_n); - - obj->spi->DLY = 2; // 2 SPI clock times pre-delay -} - -void spi_free(spi_t *obj) -{ -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - MBED_ASSERT(((bits >= 1) && (bits <= 16)) && ((mode >= 0) && (mode <= 3))); - spi_disable(obj); - - obj->spi->CFG &= ~((0x3 << 4) | (1 << 2)); - obj->spi->CFG |= ((mode & 0x3) << 4) | ((slave ? 0 : 1) << 2); - - obj->spi->TXCTL &= ~( 0xF << 24); - obj->spi->TXCTL |= ((bits - 1) << 24); - - spi_enable(obj); -} - -void spi_frequency(spi_t *obj, int hz) -{ - spi_disable(obj); - - // rise DIV value if it cannot be divided - obj->spi->DIV = (SystemCoreClock + (hz - 1))/hz - 1; - - spi_enable(obj); -} - -static inline void spi_disable(spi_t *obj) -{ - obj->spi->CFG &= ~(1 << 0); -} - -static inline void spi_enable(spi_t *obj) -{ - obj->spi->CFG |= (1 << 0); -} - -static inline int spi_readable(spi_t *obj) -{ - return obj->spi->STAT & (1 << 0); -} - -static inline int spi_writeable(spi_t *obj) -{ - return obj->spi->STAT & (1 << 1); -} - -static inline void spi_write(spi_t *obj, int value) -{ - while (!spi_writeable(obj)); - // end of transfer - obj->spi->TXCTL |= (1 << 20); - obj->spi->TXDAT = (value & 0xffff); -} - -static inline int spi_read(spi_t *obj) -{ - while (!spi_readable(obj)); - return (obj->spi->RXDAT & 0xFFFF); -} - -int spi_master_write(spi_t *obj, int value) -{ - spi_write(obj, value); - return spi_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_busy(spi_t *obj) -{ - // checking RXOV(Receiver Overrun interrupt flag) - return obj->spi->STAT & (1 << 2); -} - -int spi_slave_receive(spi_t *obj) -{ - return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0); -} - -int spi_slave_read(spi_t *obj) -{ - return (obj->spi->RXDAT & 0xFFFF); -} - -void spi_slave_write(spi_t *obj, int value) -{ - while (spi_writeable(obj) == 0); - obj->spi->TXDAT = value; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_testing; -} - -#endif diff --git a/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c b/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c deleted file mode 100644 index c4a4b03bd8..0000000000 --- a/targets/TARGET_NXP/TARGET_LPC82X/us_ticker.c +++ /dev/null @@ -1,116 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "us_ticker_api.h" -#include "PeripheralNames.h" - -static int us_ticker_inited = 0; -int MRT_Clock_MHz; -unsigned int ticker_fullcount_us; -unsigned long int ticker_expired_count_us = 0; - -#define US_TICKER_TIMER_IRQn MRT_IRQn - -void us_ticker_init(void) { - - if (us_ticker_inited) - return; - - us_ticker_inited = 1; - - // Calculate MRT clock value (MRT has no prescaler) - MRT_Clock_MHz = (SystemCoreClock / 1000000); - // Calculate fullcounter value in us (MRT has 31 bits and clock is 30MHz) - ticker_fullcount_us = 0x80000000UL/MRT_Clock_MHz; - - // Enable the MRT clock - LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); - - // Clear peripheral reset the MRT - LPC_SYSCON->PRESETCTRL |= (1 << 7); - - // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) - LPC_MRT->INTVAL0 = 0xFFFFFFFFUL; - // Enable Ch0 interrupt, Mode 0 is Repeat Interrupt - LPC_MRT->CTRL0 = (0x0 << 1) | (0x1 << 0); - - // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) - LPC_MRT->INTVAL1 = 0x80000000UL; - // Disable ch1 interrupt, Mode 0 is Repeat Interrupt - LPC_MRT->CTRL1 = (0x0 << 1) | (0x0 << 0); - - // Set MRT interrupt vector - NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); - NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); -} - -//TIMER0 is used for us ticker and timers (Timer, wait(), wait_us() etc) -uint32_t us_ticker_read() { - - if (!us_ticker_inited) - us_ticker_init(); - - // Generate ticker value - // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer - // Calculate expected value using number of expired times to mimic a 32bit timer @ 1 MHz - return (0x7FFFFFFFUL - LPC_MRT->TIMER0)/MRT_Clock_MHz + ticker_expired_count_us; -} - -//TIMER1 is used for Timestamped interrupts (Ticker(), Timeout()) -void us_ticker_set_interrupt(timestamp_t timestamp) { - - // MRT source clock is SystemCoreClock (30MHz) and MRT is a 31-bit countdown timer - // Force load interval value (Bit 0-30 is interval value, Bit 31 is Force Load bit) - // Note: The MRT has less counter headroom available than the typical mbed 32bit timer @ 1 MHz. - // The calculated counter interval until the next timestamp will be truncated and an - // 'early' interrupt will be generated in case the max required count interval exceeds - // the available 31 bits space. However, the mbed us_ticker interrupt handler will - // check current time against the next scheduled timestamp and simply re-issue the - // same interrupt again when needed. The calculated counter interval will now be smaller. - LPC_MRT->INTVAL1 = (((timestamp - us_ticker_read()) * MRT_Clock_MHz) | 0x80000000UL); - - // Enable interrupt - LPC_MRT->CTRL1 |= 1; -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(US_TICKER_TIMER_IRQn); -} - -//Disable Timestamped interrupts triggered by TIMER1 -void us_ticker_disable_interrupt() { - //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) - LPC_MRT->CTRL1 &= ~1; -} - -void us_ticker_clear_interrupt() { - - //Timer1 for Timestamped interrupts (31 bits downcounter @ SystemCoreClock) - if (LPC_MRT->STAT1 & 1) - LPC_MRT->STAT1 = 1; - - //Timer0 for us counter (31 bits downcounter @ SystemCoreClock) - if (LPC_MRT->STAT0 & 1) { - LPC_MRT->STAT0 = 1; - ticker_expired_count_us += ticker_fullcount_us; - } -} - -void us_ticker_free(void) -{ - -} diff --git a/targets/TARGET_NXP/mbed_rtx.h b/targets/TARGET_NXP/mbed_rtx.h index 7d8c64385d..15e0a8e472 100644 --- a/targets/TARGET_NXP/mbed_rtx.h +++ b/targets/TARGET_NXP/mbed_rtx.h @@ -53,13 +53,7 @@ #define INITIAL_SP (0x10008000UL) #endif -#elif defined(TARGET_LPC812) - -#ifndef INITIAL_SP -#define INITIAL_SP (0x10001000UL) -#endif - -#elif defined(TARGET_LPC824) || defined(TARGET_SSCI824) +#elif defined(TARGET_SSCI824) #ifndef INITIAL_SP #define INITIAL_SP (0x10002000UL) diff --git a/targets/targets.json b/targets/targets.json index e34535f2ce..c024e40b88 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -538,118 +538,6 @@ "1235" ] }, - "LPC812": { - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M0+", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC81X" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "uARM", - "IAR", - "GCC_ARM" - ], - "inherits": [ - "LPCTarget" - ], - "detect_code": [ - "1050" - ], - "device_has": [ - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PWMOUT", - "SERIAL", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "release_versions": [ - "2" - ], - "device_name": "LPC812M101JDH20" - }, - "LPC824": { - "supported_form_factors": [ - "ARDUINO" - ], - "core": "Cortex-M0+", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC82X" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "uARM", - "GCC_ARM", - "IAR" - ], - "inherits": [ - "LPCTarget" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "release_versions": [ - "2" - ], - "device_name": "LPC824M201JDH20", - "detect_code": [ - "0824" - ] - }, - "SSCI824": { - "inherits": [ - "LPCTarget" - ], - "core": "Cortex-M0+", - "default_toolchain": "uARM", - "extra_labels": [ - "NXP", - "LPC82X" - ], - "is_disk_virtual": true, - "supported_toolchains": [ - "uARM", - "GCC_ARM" - ], - "device_has": [ - "ANALOGIN", - "I2C", - "I2CSLAVE", - "INTERRUPTIN", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ], - "default_lib": "small", - "release_versions": [ - "2" - ], - "detect_code": [ - "1018" - ] - }, "LPC4337": { "inherits": [ "LPCTarget" @@ -690,6 +578,48 @@ "4337" ] }, + "LPC11U37H_401": { + "supported_form_factors": [ + "ARDUINO" + ], + "core": "Cortex-M0", + "default_toolchain": "uARM", + "extra_labels": [ + "NXP", + "LPC11UXX" + ], + "macros": [ + "CMSIS_VECTAB_VIRTUAL", + "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" + ], + "supported_toolchains": [ + "ARM", + "uARM", + "GCC_ARM" + ], + "inherits": [ + "LPCTarget" + ], + "device_has": [ + "ANALOGIN", + "I2C", + "I2CSLAVE", + "INTERRUPTIN", + "PORTIN", + "PORTINOUT", + "PORTOUT", + "PWMOUT", + "SERIAL", + "SLEEP", + "SPI", + "SPISLAVE" + ], + "default_lib": "small", + "release_versions": [ + "2" + ], + "device_name": "LPC11U37HFBD64/401" + }, "KL05Z": { "supported_form_factors": [ "ARDUINO" diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index d25f6e78d0..8befa22f5b 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -173,9 +173,6 @@ "FPU2": 7, "NrRegs": 1 }, - "LPC812M101JDH20": { - "OGChipSelectEditMenu": "LPC812M101\tNXP LPC812M101" - }, "STM32F746NG": { "OGChipSelectEditMenu": "STM32F746NG\tST STM32F746NG", "GBECoreSlave": 41, diff --git a/tools/export/lpcxpresso/__init__.py b/tools/export/lpcxpresso/__init__.py index c684409d09..67309898cf 100644 --- a/tools/export/lpcxpresso/__init__.py +++ b/tools/export/lpcxpresso/__init__.py @@ -34,7 +34,6 @@ class LPCXpresso(Exporter): 'ARCH_PRO', 'LPC11U68', 'LPCCAPPUCCINO', - 'LPC824', 'LPC11U37H_401', ] diff --git a/tools/export/lpcxpresso/lpc824_cproject.tmpl b/tools/export/lpcxpresso/lpc824_cproject.tmpl deleted file mode 100644 index 57343e05e5..0000000000 --- a/tools/export/lpcxpresso/lpc824_cproject.tmpl +++ /dev/null @@ -1,53 +0,0 @@ -{% extends "lpcxpresso/cproject_cortexm0_common.tmpl" %} - -{% block startup_file %}startup_LPC824_CR.cpp{% endblock %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_0="" property_2="LPC800_32.cfx" property_3="NXP" property_4="LPC824" property_count="5" version="70200"/> -<infoList vendor="NXP"><info chip="LPC824" flash_driver="LPC800_32.cfx" match_id="0x0" name="LPC824" stub="crt_emu_cm3_gen"><chip><name>LPC824</name> -<family>LPC82x</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<peripheralInstance derived_from="V6M_NVIC" determined="infoFile" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" determined="infoFile" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="WWDT" determined="infoFile" id="WWDT" location="0x40000000"/> -<peripheralInstance derived_from="MRT" determined="infoFile" id="MRT" location="0x40004000"/> -<peripheralInstance derived_from="WKT" determined="infoFile" id="WKT" location="0x40008000"/> -<peripheralInstance derived_from="SWM" determined="infoFile" id="SWM" location="0x4000c000"/> -<peripheralInstance derived_from="ADC" determined="infoFile" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" determined="infoFile" id="PMU" location="0x40020000"/> -<peripheralInstance derived_from="CMP" determined="infoFile" id="CMP" location="0x40024000"/> -<peripheralInstance derived_from="DMATRIGMUX" determined="infoFile" id="DMATRIGMUX" location="0x40028000"/> -<peripheralInstance derived_from="INPUTMUX" determined="infoFile" id="INPUTMUX" location="0x4002c000"/> -<peripheralInstance derived_from="FLASHCTRL" determined="infoFile" id="FLASHCTRL" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" determined="infoFile" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" determined="infoFile" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="I2C0" determined="infoFile" id="I2C0" location="0x40050000"/> -<peripheralInstance derived_from="I2C1" determined="infoFile" id="I2C1" location="0x40054000"/> -<peripheralInstance derived_from="SPI0" determined="infoFile" id="SPI0" location="0x40058000"/> -<peripheralInstance derived_from="SPI1" determined="infoFile" id="SPI1" location="0x4005c000"/> -<peripheralInstance derived_from="USART0" determined="infoFile" id="USART0" location="0x40064000"/> -<peripheralInstance derived_from="USART1" determined="infoFile" id="USART1" location="0x40068000"/> -<peripheralInstance derived_from="USART2" determined="infoFile" id="USART2" location="0x4006c000"/> -<peripheralInstance derived_from="I2C2" determined="infoFile" id="I2C2" location="0x40070000"/> -<peripheralInstance derived_from="I2C3" determined="infoFile" id="I2C3" location="0x40074000"/> -<peripheralInstance derived_from="CRC" determined="infoFile" id="CRC" location="0x50000000"/> -<peripheralInstance derived_from="SCT" determined="infoFile" id="SCT" location="0x50004000"/> -<peripheralInstance derived_from="DMA" determined="infoFile" id="DMA" location="0x50008000"/> -<peripheralInstance derived_from="GPIO-PORT" determined="infoFile" id="GPIO-PORT" location="0xa0000000"/> -<peripheralInstance derived_from="PIN-INT" determined="infoFile" id="PIN-INT" location="0xa0004000"/> -</chip> -<processor><name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC82x_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/export/lpcxpresso/lpc824_project.tmpl b/tools/export/lpcxpresso/lpc824_project.tmpl deleted file mode 100644 index 8b0351edb0..0000000000 --- a/tools/export/lpcxpresso/lpc824_project.tmpl +++ /dev/null @@ -1 +0,0 @@ -{% extends "lpcxpresso/project_common.tmpl" %} diff --git a/tools/export/mcuxpresso/LPC824_cproject.tmpl b/tools/export/mcuxpresso/LPC824_cproject.tmpl deleted file mode 100644 index f635ba37c0..0000000000 --- a/tools/export/mcuxpresso/LPC824_cproject.tmpl +++ /dev/null @@ -1,51 +0,0 @@ -{% extends "mcuxpresso/.cproject.tmpl" %} - -{% block cpu_config %}<?xml version="1.0" encoding="UTF-8"?> -<TargetConfig> -<Properties property_2="LPC800_32.cfx" property_3="NXP" property_4="LPC824" property_count="5" version="70200"/> -<infoList vendor="NXP"><info chip="LPC824" flash_driver="LPC800_32.cfx" match_id="0x0" name="LPC824" stub="crt_emu_cm3_gen"><chip><name>LPC824</name> -<family>LPC82x</family> -<vendor>NXP (formerly Philips)</vendor> -<reset board="None" core="Real" sys="Real"/> -<clock changeable="TRUE" freq="12MHz" is_accurate="TRUE"/> -<memory can_program="true" id="Flash" is_ro="true" type="Flash"/> -<memory id="RAM" type="RAM"/> -<memory id="Periph" is_volatile="true" type="Peripheral"/> -<memoryInstance derived_from="Flash" id="MFlash32" location="0x0" size="0x8000"/> -<memoryInstance derived_from="RAM" id="RamLoc8" location="0x10000000" size="0x2000"/> -<peripheralInstance derived_from="V6M_NVIC" id="NVIC" location="0xe000e000"/> -<peripheralInstance derived_from="V6M_DCR" id="DCR" location="0xe000edf0"/> -<peripheralInstance derived_from="WWDT" id="WWDT" location="0x40000000"/> -<peripheralInstance derived_from="MRT" id="MRT" location="0x40004000"/> -<peripheralInstance derived_from="WKT" id="WKT" location="0x40008000"/> -<peripheralInstance derived_from="SWM" id="SWM" location="0x4000c000"/> -<peripheralInstance derived_from="ADC" id="ADC" location="0x4001c000"/> -<peripheralInstance derived_from="PMU" id="PMU" location="0x40020000"/> -<peripheralInstance derived_from="CMP" id="CMP" location="0x40024000"/> -<peripheralInstance derived_from="DMATRIGMUX" id="DMATRIGMUX" location="0x40028000"/> -<peripheralInstance derived_from="INPUTMUX" id="INPUTMUX" location="0x4002c000"/> -<peripheralInstance derived_from="FLASHCTRL" id="FLASHCTRL" location="0x40040000"/> -<peripheralInstance derived_from="IOCON" id="IOCON" location="0x40044000"/> -<peripheralInstance derived_from="SYSCON" id="SYSCON" location="0x40048000"/> -<peripheralInstance derived_from="I2C0" id="I2C0" location="0x40050000"/> -<peripheralInstance derived_from="I2C1" id="I2C1" location="0x40054000"/> -<peripheralInstance derived_from="SPI0" id="SPI0" location="0x40058000"/> -<peripheralInstance derived_from="SPI1" id="SPI1" location="0x4005c000"/> -<peripheralInstance derived_from="USART0" id="USART0" location="0x40064000"/> -<peripheralInstance derived_from="USART1" id="USART1" location="0x40068000"/> -<peripheralInstance derived_from="USART2" id="USART2" location="0x4006c000"/> -<peripheralInstance derived_from="I2C2" id="I2C2" location="0x40070000"/> -<peripheralInstance derived_from="I2C3" id="I2C3" location="0x40074000"/> -<peripheralInstance derived_from="CRC" id="CRC" location="0x50000000"/> -<peripheralInstance derived_from="SCT" id="SCT" location="0x50004000"/> -<peripheralInstance derived_from="DMA" id="DMA" location="0x50008000"/> -<peripheralInstance derived_from="GPIO-PORT" id="GPIO-PORT" location="0xa0000000"/> -<peripheralInstance derived_from="PIN-INT" id="PIN-INT" location="0xa0004000"/> -</chip> -<processor><name gcc_name="cortex-m0">Cortex-M0</name> -<family>Cortex-M</family> -</processor> -<link href="LPC82x_peripheral.xme" show="embed" type="simple"/> -</info> -</infoList> -</TargetConfig>{% endblock %} diff --git a/tools/resources/__init__.py b/tools/resources/__init__.py index 602e0fc163..8e0887ae15 100644 --- a/tools/resources/__init__.py +++ b/tools/resources/__init__.py @@ -52,7 +52,6 @@ LEGACY_IGNORE_DIRS = set([ 'LPC11U24', 'LPC1768', 'LPC2368', - 'LPC812', 'KL25Z', # Legacy Toolchains