mirror of https://github.com/ARMmbed/mbed-os.git
Stop using device_has for non-mbed options
As asked by @0xc0170 in PR #3934, we won't be using device_has for indicating RF/Crypto features any longer. RF config options moved to the SL_RAIL lib.json, crypto config options will come with mbedTLS integration.pull/3934/head
parent
b3883115e6
commit
d2173574d0
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@ -80,7 +80,7 @@ static const RAIL_ChannelConfigEntry_t entry[] = {
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};
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#if MBED_CONF_SL_RAIL_BAND == 868
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#ifndef DEVICE_RF_SUBGHZ
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#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
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#error "Sub-Gigahertz band is not supported on this target."
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#endif
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static const RAIL_ChannelConfig_t channels = {
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@ -88,7 +88,7 @@ static const RAIL_ChannelConfig_t channels = {
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1
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};
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#elif MBED_CONF_SL_RAIL_BAND == 915
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#ifndef DEVICE_RF_SUBGHZ
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#ifndef MBED_CONF_SL_RAIL_HAS_SUBGIG
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#error "Sub-Gigahertz band is not supported on this target."
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#endif
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static const RAIL_ChannelConfig_t channels = {
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@ -96,7 +96,7 @@ static const RAIL_ChannelConfig_t channels = {
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1
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};
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#elif MBED_CONF_SL_RAIL_BAND == 2400
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#ifndef DEVICE_RF_2P4GHZ
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#ifndef MBED_CONF_SL_RAIL_HAS_2P4
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#error "2.4GHz band is not supported on this target."
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#endif
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static const RAIL_ChannelConfig_t channels = {
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@ -113,7 +113,7 @@ static const RAIL_IEEE802154_Config_t config = { false, false,
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static const RAIL_Init_t railInitParams = { 140, 38400000, RAIL_CAL_ALL_PENDING };
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#if defined (DEVICE_RF_2P4GHZ)
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#if defined (MBED_CONF_SL_RAIL_HAS_2P4)
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// Set up the PA for 2.4 GHz operation
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static const RADIO_PAInit_t paInit2p4 = {
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PA_SEL_2P4_HP, /* Power Amplifier mode */
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@ -124,7 +124,7 @@ static const RADIO_PAInit_t paInit2p4 = {
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};
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#endif
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#if defined (DEVICE_RF_SUBGHZ)
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#if defined (MBED_CONF_SL_RAIL_HAS_SUBGIG)
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// Set up the PA for sub-GHz operation
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static const RADIO_PAInit_t paInitSubGhz = {
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PA_SEL_SUBGIG, /* Power Amplifier mode */
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@ -175,21 +175,19 @@ static int8_t rf_device_register(void)
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#endif
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// Set up PTI since it makes life so much easier
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#if defined(DEVICE_SL_PTI)
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#if defined(MBED_CONF_SL_RAIL_PTI) && (MBED_CONF_SL_RAIL_PTI == 1)
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RADIO_PTIInit_t ptiInit = {
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RADIO_PTI_MODE_UART,
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1600000,
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6,
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// TODO: Configure PTI pinout using config system.
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// Not very urgent, since all boards use the same pins now.
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gpioPortB,
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12,
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6,
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gpioPortB,
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11,
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6,
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gpioPortB,
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13,
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MBED_CONF_SL_RAIL_PTI_MODE,
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MBED_CONF_SL_RAIL_PTI_BAUDRATE,
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MBED_CONF_SL_RAIL_PTI_DOUT_LOCATION,
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MBED_CONF_SL_RAIL_PTI_DOUT_PORT,
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MBED_CONF_SL_RAIL_PTI_DOUT_PIN,
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MBED_CONF_SL_RAIL_PTI_DCLK_LOCATION,
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MBED_CONF_SL_RAIL_PTI_DCLK_PORT,
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MBED_CONF_SL_RAIL_PTI_DCLK_PIN,
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MBED_CONF_SL_RAIL_PTI_DFRAME_LOCATION,
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MBED_CONF_SL_RAIL_PTI_DFRAME_PORT,
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MBED_CONF_SL_RAIL_PTI_DFRAME_PIN
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};
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RADIO_PTI_Init(&ptiInit);
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@ -198,13 +196,13 @@ static int8_t rf_device_register(void)
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// Set up RAIL
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RAIL_RfInit(&railInitParams);
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RAIL_ChannelConfig(&channels);
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#if MBED_CONF_SL_RAIL_BAND == 2400
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#if (MBED_CONF_SL_RAIL_BAND == 2400)
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RAIL_RadioConfig((void*) ieee802154_config_base);
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channel = 11;
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#elif (MBED_CONF_SL_RAIL_BAND == 915)
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RAIL_RadioConfig((void*) ieee802154_config_915);
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channel = 1;
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#elif MBED_CONF_SL_RAIL_BAND == 868
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#elif (MBED_CONF_SL_RAIL_BAND == 868)
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RAIL_RadioConfig((void*) ieee802154_config_863);
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channel = 0;
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#endif
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@ -42,7 +42,7 @@ void mbed_sdk_init()
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EMU_DCDCInit_TypeDef dcdcInit = EMU_DCDCINIT_DEFAULT;
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EMU_DCDCInit(&dcdcInit);
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#if defined(DEVICE_RF_2P4GHZ) || defined(DEVICE_RF_SUBGHZ)
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#if defined(_EFR_DEVICE)
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CMU_HFXOInit_TypeDef hfxoInit = CMU_HFXOINIT_WSTK_DEFAULT;
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// Initialize the HFXO using the settings from the WSTK bspconfig.h
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// Note: This configures things like the capacitive tuning CTUNE variable
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@ -1,6 +1,35 @@
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{
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"name": "sl-rail",
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"config": {
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"band": 2400
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"band": {
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"help" : "Configure this to 2400, 915 or 868 depending on which band you want to run on (and have available on the board)",
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"value" : 2400
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},
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"PTI": true,
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"has-2p4": false,
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"has-subgig": false,
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"pti-mode": "RADIO_PTI_MODE_UART",
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"pti-baudrate" : 1600000,
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"pti-dout-location": 6,
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"pti-dout-port": "gpioPortB",
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"pti-dout-pin": 12,
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"pti-dclk-location": 6,
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"pti-dclk-port": "gpioPortB",
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"pti-dclk-pin": 11,
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"pti-dframe-location": 6,
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"pti-dframe-port": "gpioPortB",
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"pti-dframe-pin": 13
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},
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"target_overrides": {
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"THUNDERBOARD_SENSE": {
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"sl-rail.has-2p4": true
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},
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"THUNDERBOARD_SENSE_12": {
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"sl-rail.has-2p4": true
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},
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"EFR32MG1_BRD4150": {
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"sl-rail.has-2p4": true,
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"sl-rail.has-subgig": true
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}
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}
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}
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@ -1920,7 +1920,7 @@
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},
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"EFM32GG990F1024": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32GG", "1024K"],
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"extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
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"core": "Cortex-M3",
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"macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -1973,7 +1973,7 @@
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},
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"EFM32LG990F256": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32LG", "256K"],
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"extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
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"core": "Cortex-M3",
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"macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2026,7 +2026,7 @@
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},
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"EFM32WG990F256": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32WG", "256K"],
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"extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
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"core": "Cortex-M4F",
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"macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2079,7 +2079,7 @@
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},
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"EFM32ZG222F32": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32ZG", "32K"],
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"extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
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"core": "Cortex-M0+",
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"default_toolchain": "uARM",
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"macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
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@ -2133,7 +2133,7 @@
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},
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"EFM32HG322F64": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32HG", "64K"],
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"extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
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"core": "Cortex-M0+",
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"default_toolchain": "uARM",
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"macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
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@ -2187,7 +2187,7 @@
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},
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"EFM32PG1B100F256GM32": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32PG", "256K"],
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"extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
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"core": "Cortex-M4F",
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"macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2239,7 +2239,7 @@
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},
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"EFR32MG1P132F256GM48": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"],
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"extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
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"core": "Cortex-M4F",
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"macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2249,7 +2249,7 @@
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},
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"EFR32MG1P233F256GM48": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL"],
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"extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
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"core": "Cortex-M4F",
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"macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2258,7 +2258,7 @@
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},
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"EFR32MG1_BRD4150": {
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"inherits": ["EFR32MG1P132F256GM48"],
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"device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "RF_SUBGHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"forced_reset_timeout": 2,
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"config": {
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"hf_clock_src": {
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@ -2301,7 +2301,7 @@
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},
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"THUNDERBOARD_SENSE": {
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"inherits": ["EFR32MG1P233F256GM48"],
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"device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"forced_reset_timeout": 5,
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"config": {
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"hf_clock_src": {
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@ -2338,7 +2338,7 @@
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},
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"EFM32PG12B500F1024GL125": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFM32PG12", "1024K"],
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"extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
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"core": "Cortex-M4F",
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"macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2347,7 +2347,7 @@
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},
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"EFM32PG12_STK3402": {
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"inherits": ["EFM32PG12B500F1024GL125"],
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"device_has": ["AES", "SHA", "ECC", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"forced_reset_timeout": 2,
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"config": {
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"hf_clock_src": {
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@ -2389,7 +2389,7 @@
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},
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"EFR32MG12P332F1024GL125": {
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"inherits": ["EFM32"],
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"extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL"],
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"extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
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"core": "Cortex-M4F",
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"macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
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"supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
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@ -2398,7 +2398,7 @@
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},
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"THUNDERBOARD_SENSE_12": {
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"inherits": ["EFR32MG12P332F1024GL125"],
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"device_has": ["AES", "SHA", "ECC", "SL_PTI", "RF_2P4GHZ", "ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
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"forced_reset_timeout": 5,
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"config": {
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"hf_clock_src": {
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