Update NRF51 link and startup sequence.

* Update softdevice offset so they match the offset of sd 2.0.
* Update RAM initialization sequence.
* Import fs_data section in final binary

hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld

@@ -2,8 +2,8 @@
 
 MEMORY
 {
-  FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000
-  RAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0x5800
+  FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000
+  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0x5108
 }
 
 OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
@@ -114,6 +114,15 @@ SECTIONS
 
 	} > RAM
 
+    __edata = .;
+
+    .fs_data :
+    {
+      PROVIDE(__start_fs_data = .);
+      KEEP(*(.fs_data))
+      PROVIDE(__stop_fs_data = .);
+    } > RAM
+
 	.bss :
 	{
 		. = ALIGN(4);

hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822/TOOLCHAIN_GCC_ARM/startup_NRF51822.S

@@ -117,8 +117,9 @@ __Vectors:
 
 /* Reset Handler */
 
-    .equ    NRF_POWER_RAMON_ADDRESS,            0x40000524
-    .equ    NRF_POWER_RAMON_RAMxON_ONMODE_Msk,  0x3
+    .equ    NRF_POWER_RAMON_ADDRESS,             0x40000524
+    .equ    NRF_POWER_RAMONB_ADDRESS,            0x40000554
+    .equ    NRF_POWER_RAMONx_RAMxON_ONMODE_Msk,  0x3  
 
     .text
     .thumb
@@ -129,10 +130,14 @@ __Vectors:
 Reset_Handler:
     .fnstart
 
-/* Make sure ALL RAM banks are powered on */
+    MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
     LDR     R0, =NRF_POWER_RAMON_ADDRESS
     LDR     R2, [R0]
-    MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+    ORRS    R2, R1
+    STR     R2, [R0]
+
+    LDR     R0, =NRF_POWER_RAMONB_ADDRESS
+    LDR     R2, [R0]
     ORRS    R2, R1
     STR     R2, [R0]
 

hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld

@@ -83,7 +83,6 @@ SECTIONS
         KEEP(*(.eh_frame*))
     } > FLASH
 
-
     .ARM.extab :
     {
         *(.ARM.extab* .gnu.linkonce.armextab.*)