mirror of https://github.com/ARMmbed/mbed-os.git
QSPI: initial HAL nrf52840 version
This commit adds QSPI HAL implementation for nrf52840 MCU targetspull/7783/head
Martin Kojtal
Maciej Bocianski
parent
a3c8117b0e
commit
d1b51b6328
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@ -2748,6 +2748,136 @@
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// </e>
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// <e> QSPI_ENABLED - nrf_drv_qspi - QSPI peripheral driver.
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//==========================================================
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#ifndef QSPI_ENABLED
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#define QSPI_ENABLED 1
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#endif
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#if QSPI_ENABLED
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// <o> QSPI_CONFIG_SCK_DELAY - tSHSL, tWHSL and tSHWL in number of 16 MHz periods (62.5 ns). <0-255>
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#ifndef QSPI_CONFIG_SCK_DELAY
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#define QSPI_CONFIG_SCK_DELAY 1
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#endif
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// <o> QSPI_CONFIG_READOC - Number of data lines and opcode used for reading.
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// <0=> FastRead
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// <1=> Read2O
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// <2=> Read2IO
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// <3=> Read4O
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// <4=> Read4IO
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#ifndef QSPI_CONFIG_READOC
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#define QSPI_CONFIG_READOC 4
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#endif
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// <o> QSPI_CONFIG_WRITEOC - Number of data lines and opcode used for writing.
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// <0=> PP
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// <1=> PP2O
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// <2=> PP4O
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// <3=> PP4IO
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#ifndef QSPI_CONFIG_WRITEOC
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#define QSPI_CONFIG_WRITEOC 3
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#endif
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// <o> QSPI_CONFIG_ADDRMODE - Addressing mode.
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// <0=> 24bit
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// <1=> 32bit
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#ifndef QSPI_CONFIG_ADDRMODE
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#define QSPI_CONFIG_ADDRMODE 0
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#endif
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// <o> QSPI_CONFIG_MODE - SPI mode.
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// <0=> Mode 0
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// <1=> Mode 1
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#ifndef QSPI_CONFIG_MODE
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#define QSPI_CONFIG_MODE 0
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#endif
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// <o> QSPI_CONFIG_FREQUENCY - Frequency divider.
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// <0=> 32MHz/1
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// <1=> 32MHz/2
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// <2=> 32MHz/3
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// <3=> 32MHz/4
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// <4=> 32MHz/5
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// <5=> 32MHz/6
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// <6=> 32MHz/7
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// <7=> 32MHz/8
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// <8=> 32MHz/9
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// <9=> 32MHz/10
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// <10=> 32MHz/11
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// <11=> 32MHz/12
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// <12=> 32MHz/13
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// <13=> 32MHz/14
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// <14=> 32MHz/15
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// <15=> 32MHz/16
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#ifndef QSPI_CONFIG_FREQUENCY
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#define QSPI_CONFIG_FREQUENCY 1
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#endif
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// <s> QSPI_PIN_SCK - SCK pin value.
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#ifndef QSPI_PIN_SCK
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#define QSPI_PIN_SCK NRF_QSPI_PIN_NOT_CONNECTED
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#endif
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// <s> QSPI_PIN_CSN - CSN pin value.
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#ifndef QSPI_PIN_CSN
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#define QSPI_PIN_CSN NRF_QSPI_PIN_NOT_CONNECTED
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#endif
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// <s> QSPI_PIN_IO0 - IO0 pin value.
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#ifndef QSPI_PIN_IO0
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#define QSPI_PIN_IO0 NRF_QSPI_PIN_NOT_CONNECTED
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#endif
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// <s> QSPI_PIN_IO1 - IO1 pin value.
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#ifndef QSPI_PIN_IO1
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#define QSPI_PIN_IO1 NRF_QSPI_PIN_NOT_CONNECTED
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#endif
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// <s> QSPI_PIN_IO2 - IO2 pin value.
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#ifndef QSPI_PIN_IO2
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#define QSPI_PIN_IO2 NRF_QSPI_PIN_NOT_CONNECTED
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#endif
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// <s> QSPI_PIN_IO3 - IO3 pin value.
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#ifndef QSPI_PIN_IO3
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#define QSPI_PIN_IO3 NRF_QSPI_PIN_NOT_CONNECTED
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#endif
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// <o> QSPI_CONFIG_IRQ_PRIORITY - Interrupt priority
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// <i> Priorities 0,2 (nRF51) and 0,1,4,5 (nRF52) are reserved for SoftDevice
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// <0=> 0 (highest)
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// <1=> 1
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// <2=> 2
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// <3=> 3
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// <4=> 4
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// <5=> 5
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// <6=> 6
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// <7=> 7
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#ifndef QSPI_CONFIG_IRQ_PRIORITY
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#define QSPI_CONFIG_IRQ_PRIORITY 7
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#endif
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#endif //QSPI_ENABLED
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// </e>
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// </e>
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// <e> TIMER_ENABLED - nrf_drv_timer - TIMER periperal driver
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//==========================================================
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#ifndef TIMER_ENABLED
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@ -142,6 +142,17 @@ struct flash_s {
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uint32_t placeholder;
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};
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#if DEVICE_QSPI
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// #include "nrf_drv_qspi.h"
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struct qspi_s {
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uint32_t placeholder;
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// nrf_drv_qspi_config_t config;
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};
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#endif
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#include "gpio_object.h"
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#ifdef __cplusplus
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@ -0,0 +1,214 @@
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/*
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* Copyright (c) 2017 Nordic Semiconductor ASA
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* 1. Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
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* integrated circuit in a product or a software update for such product, must reproduce
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* the above copyright notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the distribution.
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*
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* 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
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* used to endorse or promote products derived from this software without specific prior
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* written permission.
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*
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* 4. This software, with or without modification, must only be used with a
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* Nordic Semiconductor ASA integrated circuit.
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*
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* 5. Any software provided in binary or object form under this license must not be reverse
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* engineered, decompiled, modified and/or disassembled.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#include "qspi_api.h"
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#if DEVICE_QSPI
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#include "nrf_drv_common.h"
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#include "nrf_drv_qspi.h"
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/*
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TODO
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- config inside obj - nordic headers have some problems with inclusion
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- free - is it really empty, nothing to do there?
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- prepare command - support more protocols that nordic can do (now limited)
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- nordic does not support
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- alt
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- dummy cycles
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*/
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#define MBED_HAL_QSPI_HZ_TO_CONFIG(hz) ((32000000/(hz))-1)
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#define MBED_HAL_QSPI_MAX_FREQ 32000000UL
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static nrf_drv_qspi_config_t config;
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qspi_status_t qspi_prepare_command(qspi_t *obj, const qspi_command_t *command, bool write)
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{
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// we need to remap to command-address-data - x_x_x
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// most commmon are 1-1-1, 1-1-4, 1-4-4
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// 1-1-1
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if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
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command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
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command->data.bus_width == QSPI_CFG_BUS_SINGLE) {
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if (write) {
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config.prot_if.writeoc = NRF_QSPI_WRITEOC_PP;
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} else {
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config.prot_if.readoc = NRF_QSPI_READOC_FASTREAD;
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}
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// 1-1-4
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} else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
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command->address.bus_width == QSPI_CFG_BUS_SINGLE &&
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command->data.bus_width == QSPI_CFG_BUS_QUAD) {
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// 1_1_4
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if (write) {
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config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP4O;
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} else {
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config.prot_if.readoc = NRF_QSPI_READOC_READ4O;
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}
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// 1-4-4
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} else if (command->instruction.bus_width == QSPI_CFG_BUS_SINGLE &&
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command->address.bus_width == QSPI_CFG_BUS_QUAD &&
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command->data.bus_width == QSPI_CFG_BUS_QUAD) {
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// 1_4_4
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if (write) {
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config.prot_if.writeoc = QSPI_IFCONFIG0_WRITEOC_PP4IO;
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} else {
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config.prot_if.readoc = NRF_QSPI_READOC_READ4IO;
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}
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}
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qspi_status_t ret = QSPI_STATUS_OK;
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// supporting only 24 or 32 bit address
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if (command->address.size == QSPI_CFG_ADDR_SIZE_24) {
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config.prot_if.addrmode = NRF_QSPI_ADDRMODE_24BIT;
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} else if (command->address.size == QSPI_CFG_ADDR_SIZE_32) {
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config.prot_if.addrmode = QSPI_CFG_ADDR_SIZE_32;
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} else {
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ret = QSPI_STATUS_INVALID_PARAMETER;
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}
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return ret;
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}
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qspi_status_t qspi_init(qspi_t *obj, PinName io0, PinName io1, PinName io2, PinName io3, PinName sclk, PinName ssel, uint32_t hz, uint8_t mode)
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{
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(void)(obj);
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if (hz > MBED_HAL_QSPI_MAX_FREQ) {
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return QSPI_STATUS_INVALID_PARAMETER;
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}
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// memset(config, 0, sizeof(config));
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config.pins.sck_pin = (uint32_t)sclk;
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config.pins.csn_pin = (uint32_t)ssel;
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config.pins.io0_pin = (uint32_t)io0;
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config.pins.io1_pin = (uint32_t)io1;
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config.pins.io2_pin = (uint32_t)io2;
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config.pins.io3_pin = (uint32_t)io3;
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config.irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY;
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config.phy_if.sck_freq = MBED_HAL_QSPI_HZ_TO_CONFIG(hz),
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config.phy_if.sck_delay = 0x05,
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config.phy_if.dpmen = false;
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config.phy_if.spi_mode = mode == 0 ? NRF_QSPI_MODE_0 : NRF_QSPI_MODE_1;
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nrf_drv_qspi_init(&config, NULL , NULL);
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return 0;
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}
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qspi_status_t qspi_free(qspi_t *obj)
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{
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(void)(obj);
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// possibly here uninit from SDK driver
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return QSPI_STATUS_OK;
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}
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qspi_status_t qspi_frequency(qspi_t *obj, int hz)
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{
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config.phy_if.sck_freq = MBED_HAL_QSPI_HZ_TO_CONFIG(hz);
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// use sync version, no handler
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ret_code_t ret = nrf_drv_qspi_init(&config, NULL , NULL);
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if (ret == NRF_SUCCESS ) {
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return QSPI_STATUS_OK;
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} else if (ret == NRF_ERROR_INVALID_PARAM) {
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return QSPI_STATUS_INVALID_PARAMETER;
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} else {
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return QSPI_STATUS_ERROR;
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}
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}
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qspi_status_t qspi_write(qspi_t *obj, const qspi_command_t *command, const void *data, size_t *length)
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{
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qspi_status_t status = qspi_prepare_command(obj, command, true);
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if (status != QSPI_STATUS_OK) {
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return status;
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}
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// write here does not return how much it transfered, we return transfered all
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ret_code_t ret = nrf_drv_qspi_write(data, *length, command->address.value);
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if (ret == NRF_SUCCESS ) {
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return QSPI_STATUS_OK;
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} else {
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return QSPI_STATUS_ERROR;
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}
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}
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qspi_status_t qspi_read(qspi_t *obj, const qspi_command_t *command, void *data, size_t *length)
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{
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qspi_status_t status = qspi_prepare_command(obj, command, false);
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if (status != QSPI_STATUS_OK) {
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return status;
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}
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ret_code_t ret = nrf_drv_qspi_read(data, *length, command->address.value);
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if (ret == NRF_SUCCESS ) {
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return QSPI_STATUS_OK;
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} else {
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return QSPI_STATUS_ERROR;
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}
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}
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// they provide 2 functions write or nrf_drv_qspi_cinstr_xfer
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// nrf_drv_qspi_cinstr_xfer seems like it accepts simplified config that is very simplified
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// and might not be useful for us.
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// write on other hand, needs to write some data (errors if buffer is NULL!)
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qspi_status_t qspi_write_command(qspi_t *obj, const qspi_command_t *command)
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{
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// use simplified API, as we are sending only instruction here
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nrf_qspi_cinstr_conf_t config;
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config.length = NRF_QSPI_CINSTR_LEN_1B; // no data
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config.opcode = command->instruction.value;
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config.io2_level = false;
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config.io3_level = false;
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config.wipwait = false;
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config.wren = false;
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// no data phase, send only config
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ret_code_t ret = nrf_drv_qspi_cinstr_xfer(&config, NULL, NULL);
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if (ret == NRF_SUCCESS ) {
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return QSPI_STATUS_OK;
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} else {
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return QSPI_STATUS_ERROR;
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}
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}
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#endif
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/** @}*/
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@ -3873,7 +3873,8 @@
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"SPI_ASYNCH",
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"STCLK_OFF_DURING_SLEEP",
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"TRNG",
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"USTICKER"
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"USTICKER",
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"QSPI"
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],
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"extra_labels": [
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"NORDIC",
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