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Merge pull request #4572 from bcostm/add_usb_disco_l072cz 

DISCO_L072CZ_LRWAN1: Add support of USB Device
pull/4639/head
Jimmy Brisson 2017-06-26 10:28:31 -05:00 committed by GitHub
parent 17a88a80ef cc47104059
commit d103979e92
4 changed files with 181 additions and 15 deletions
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131
features/unsupported/USBDevice/USBDevice/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/USBHAL_STM32L072CZ.h Normal file
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@ -0,0 +1,131 @@
/* Copyright (c) 2016 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef USBHAL_STM32L072CZ_H
#define USBHAL_STM32L072CZ_H
#define USBHAL_IRQn USB_IRQn
/* must be multiple of 4 bytes */
#define NB_ENDPOINT 8
#define MAXTRANSFER_SIZE 0x200
#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
#if (FIFO_USB_RAM_SIZE > 0x500)
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
void (USBHAL::*sof)(int frame);
void (USBHAL::*connect_change)(unsigned int connected);
void (USBHAL::*suspend_change)(unsigned int suspended);
void (USBHAL::*ep0_setup)(void);
void (USBHAL::*ep0_in)(void);
void (USBHAL::*ep0_out)(void);
void (USBHAL::*ep0_read)(void);
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
bool (USBHAL::*epCallback[6])(void);
uint8_t epComplete[2*NB_ENDPOINT];
/* memorize dummy buffer used for reception */
uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
gpio_t usb_switch;
}USBHAL_Private_t;
uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
{
return 1024;
}
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
gpio_write(&(priv->usb_switch),state);
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN;
void (USBHAL::*func)(int frame) = priv->sof;
(obj->*func)(sofnum);
}
USBHAL * USBHAL::instance;
USBHAL::USBHAL(void)
{
/* init parameter */
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
hpcd.Instance = USB;
/* initialized Init to zero (constructor does not zero initialized the
* area */
/* initialized all field of init including 0 field */
/* constructor does not fill with zero */
memset(&hpcd.Init, 0, sizeof(hpcd.Init));
hpcd.Init.dev_endpoints = NB_ENDPOINT;
hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd.Init.Sof_enable = 1;
hpcd.Init.speed = PCD_SPEED_FULL;
/* pass instance for usage inside call back */
HALPriv->inst = this;
HALPriv->bus_reset = &USBHAL::busReset;
HALPriv->suspend_change = &USBHAL::suspendStateChanged;
HALPriv->connect_change = &USBHAL::connectStateChanged;
HALPriv->sof = &USBHAL::SOF;
HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
HALPriv->ep_realise = &USBHAL::realiseEndpoint;
HALPriv->ep0_in = &USBHAL::EP0in;
HALPriv->ep0_out = &USBHAL::EP0out;
HALPriv->ep0_read = &USBHAL::EP0read;
hpcd.pData = (void*)HALPriv;
HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
instance = this;
/* Configure USB DM pin. This is optional, and maintained only for user guidance. */
__HAL_RCC_GPIOA_CLK_ENABLE();
pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB));
pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF2_USB));
/* Enable USB Clock */
__HAL_RCC_USB_CLK_ENABLE();
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
hpcd.State = HAL_PCD_STATE_RESET;
HAL_PCD_Init(&hpcd);
/* hardcoded size of FIFO according definition*/
HAL_PCDEx_PMAConfig(&hpcd , 0x00 , PCD_SNG_BUF, 0x30);
HAL_PCDEx_PMAConfig(&hpcd , 0x80 , PCD_SNG_BUF, 0x70);
HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_DBL_BUF, 0x018000b0);
HAL_PCDEx_PMAConfig(&hpcd , 0x83, PCD_SNG_BUF, 0xb0);
NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
NVIC_SetPriority(USBHAL_IRQn, 1);
HAL_PCD_Start(&hpcd);
}
#endif

18
features/unsupported/USBDevice/USBDevice/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/USBHAL_STM_TARGET.h Normal file
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@ -0,0 +1,18 @@
/* Copyright (c) 2016 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#include "USBHAL_STM32L072CZ.h"

45
targets/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L072CZ_LRWAN1/device/system_stm32l0xx.c
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@ -405,17 +405,23 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
/******************************************************************************/
uint8_t SetSysClock_PLL_HSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
RCC_CRSInitTypeDef RCC_CRSInitStruct = {0};
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__HAL_RCC_PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
__HAL_RCC_PWR_CLK_DISABLE();
/* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
#if !defined (STM32L031xx) && !defined (STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx) && \
!defined (STM32L011xx) && !defined (STM32L021xx)
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
#endif
RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
// PLLCLK = (16 MHz * 6)/3 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
@ -427,14 +433,10 @@ uint8_t SetSysClock_PLL_HSI(void)
return 0; // FAIL
}
/* The voltage scaling allows optimizing the power consumption when the device is
clocked below the maximum system frequency, to update the voltage scaling value
regarding system frequency refer to product datasheet. */
__PWR_CLK_ENABLE();
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
/* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
/* Select HSI48 as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
@ -447,6 +449,21 @@ uint8_t SetSysClock_PLL_HSI(void)
return 0; // FAIL
}
/* Configure the clock recovery system (CRS) ********************************/
/* Enable CRS Clock */
__HAL_RCC_CRS_CLK_ENABLE();
/* Default Synchro Signal division factor (not divided) */
RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
/* Set the SYNCSRC[1:0] bits according to CRS_Source value */
RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_USB;
/* HSI48 is synchronized with USB SOF at 1KHz rate */
RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 1000);
RCC_CRSInitStruct.ErrorLimitValue = RCC_CRS_ERRORLIMIT_DEFAULT;
/* Set the TRIM[5:0] to the default value */
RCC_CRSInitStruct.HSI48CalibrationValue = 0x20;
/* Start automatic synchronization */
HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz

2
tools/build_travis.py
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@ -86,7 +86,7 @@ build_list = (
{ "target": "DISCO_F769NI", "toolchains": "GCC_ARM", "libs": ["dsp"] },
{ "target": "DISCO_L475VG_IOT01A", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
{ "target": "DISCO_L476VG", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
{ "target": "DISCO_L072CZ_LRWAN1", "toolchains": "GCC_ARM", "libs": ["dsp"] },
{ "target": "DISCO_L072CZ_LRWAN1", "toolchains": "GCC_ARM", "libs": ["dsp", "usb"] },
{ "target": "LPC1114", "toolchains": "GCC_ARM", "libs": ["dsp"] },
{ "target": "LPC11U35_401", "toolchains": "GCC_ARM", "libs": ["dsp"] },