diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h index 5db4fc14d1..3e1e921801 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PeripheralNames.h @@ -61,31 +61,6 @@ typedef enum { SPI_NC = (SPI_4 + 1) } SPIName; -typedef enum { - PWM_1 = 0, - PWM_2, - PWM_3, - PWM_4, - PWM_5, - PWM_6, - PWM_7, - PWM_8, - PWM_9, - PWM_10, - PWM_11 -} PWMName; - -#define STDIO_UART_TX USBTX -#define STDIO_UART_RX USBRX -#define STDIO_UART UART_1 - -#define MBED_UART0 MCC_TX, MCC_RX -#define MBED_UART1 USBTX, USBRX -#define MBED_UART2 XB_TX, XB_RX -#define MBED_UART3 SH0_TX, SH0_RX -#define MBED_UART4 SH1_TX, SH1_RX -#define MBED_UARTUSB USBTX, USBRX - #ifdef __cplusplus } #endif diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h index 86013fb904..89d5431f47 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/PinNames.h @@ -18,6 +18,10 @@ #include "cmsis.h" +/* Pins used by mbed OS to identify STDIO UART pins */ +#define STDIO_UART_TX USBTX +#define STDIO_UART_RX USBRX + #ifdef __cplusplus extern "C" { #endif @@ -27,8 +31,6 @@ typedef enum { PIN_OUTPUT } PinDirection; -#define PORT_SHIFT 5 - typedef enum { /* MPS2 EXP Pin Names */ EXP0 = 0, diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.c deleted file mode 100644 index a0111474c6..0000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.c +++ /dev/null @@ -1,90 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * ---------------------------------------------------------------- - * File: fpga.c - * Release: Version 1.0 - * ---------------------------------------------------------------- - */ - -/* - * Code implementation file for the fpga functions. - */ - -#include "SMM_MPS2.h" // MPS2 common header - -// Function to delay n*ticks (25MHz = 40nS per tick) -// Used for I2C drivers -void i2c_delay(unsigned int tick) -{ - unsigned int end; - unsigned int start; - - start = MPS2_FPGAIO->COUNTER; - end = start + (tick); - - if(end >= start) - { - while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); - } - else - { - while (MPS2_FPGAIO->COUNTER >= start); - while (MPS2_FPGAIO->COUNTER < end); - } -} - -/* Sleep function to delay n*mS - * Uses FPGA counter. - */ -void Sleepms(unsigned int msec) -{ - unsigned int end; - unsigned int start; - - start = MPS2_FPGAIO->COUNTER; - end = start + (25 * msec * 1000); - - if(end >= start) - { - while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); - } - else - { - while (MPS2_FPGAIO->COUNTER >= start); - while (MPS2_FPGAIO->COUNTER < end); - } -} - -/* Sleep function to delay n*uS - */ -void Sleepus(unsigned int usec) -{ - unsigned int end; - unsigned int start; - - start = MPS2_FPGAIO->COUNTER; - end = start + (25 * usec); - - if(end >= start) - { - while (MPS2_FPGAIO->COUNTER >= start && MPS2_FPGAIO->COUNTER < end); - } - else - { - while (MPS2_FPGAIO->COUNTER >= start); - while (MPS2_FPGAIO->COUNTER < end); - } -} - diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.h deleted file mode 100644 index bf23ce9f1c..0000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/fpga.h +++ /dev/null @@ -1,34 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -/* - * Code implementation file for the fpga functions. - */ - -#include "SMM_MPS2.h" // MPS2 common header - -// Function to delay n*ticks (25MHz = 40nS per tick) -// Used for I2C drivers -void i2c_delay(unsigned int tick); - -/* Sleep function to delay n*mS - * Uses FPGA counter. - */ -void Sleepms(unsigned int msec); - -/* Sleep function to delay n*uS - */ -void Sleepus(unsigned int usec); diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/cmsdk_ticker.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/cmsdk_ticker.h index 93f75c75b1..ecf59a0b0c 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/cmsdk_ticker.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/cmsdk_ticker.h @@ -32,7 +32,7 @@ #include -#include "CMSDK_CM3DS.h" +#include "CM3DS.h" #include "timer_cmsdk_drv.h" #define SEC_TO_USEC_MULTIPLIER 1000000U diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device.h index 8e966848ff..24f0b5b5ea 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device.h @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2006-2017 ARM Limited + * Copyright (c) 2006-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -13,6 +13,10 @@ * See the License for the specific language governing permissions and * limitations under the License. */ + +/* + * This file is included by every HAL implementations. + */ #ifndef MBED_DEVICE_H #define MBED_DEVICE_H diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CM3DS.h similarity index 70% rename from targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h rename to targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CM3DS.h index a9bb5d828c..6682da9a6d 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CMSDK_CM3DS.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/CM3DS.h @@ -14,12 +14,21 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * - * This file is derivative of CMSIS V5.00 ARMCM3.h */ -#ifndef CMSDK_CM3DS_H -#define CMSDK_CM3DS_H +/* + * This file is derivative of CMSIS V5.00 ARMCM3.h + * + * This file has merged with the former SMM_MPS2.h file, derivative from the + * MPS2 Selftest implementation. + * MPS2 Selftest: https://silver.arm.com/browse/VEI10 -> + * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\SMM_MPS2.h + * + * It includes code implementation file for the LAN Ethernet interface. + */ + +#ifndef CM3DS_H +#define CM3DS_H #ifdef __cplusplus extern "C" { @@ -40,7 +49,7 @@ typedef enum IRQn PendSV_IRQn = -2, /* 14 Pend SV Interrupt */ SysTick_IRQn = -1, /* 15 System Tick Interrupt */ -/* ---------------------- CMSDK_CM3 Specific Interrupt Numbers ------------------ */ +/* ---------------------- CM3DS Specific Interrupt Numbers ---------------------- */ UART0_IRQn = 0, /* UART 0 RX and TX Combined Interrupt */ Spare_IRQn = 1, /* Undefined */ UART1_IRQn = 2, /* UART 1 RX and TX Combined Interrupt */ @@ -105,7 +114,7 @@ typedef enum IRQn /* ================================================================================ */ /* -------- Configuration of the Cortex-M3 Processor and Core Peripherals ------- */ -#define __CM3DS_REV 0x0201U /* Core revision r2p1 */ +#define __CM3DS_REV 0x0201U /* Core revision r2p1 */ #define __MPU_PRESENT 1 /* MPU present or not */ #define __VTOR_PRESENT 1 /* VTOR present or not */ #define __NVIC_PRIO_BITS 3 /* Number of Bits used for Priority Levels */ @@ -122,7 +131,7 @@ typedef enum IRQn /* ------------------- Start of section using anonymous unions ------------------ */ #if defined ( __CC_ARM ) #pragma push -#pragma anon_unions + #pragma anon_unions #elif defined(__ICCARM__) #pragma language=extended #elif defined(__GNUC__) @@ -221,53 +230,6 @@ typedef struct #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2 #define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */ -/*------------------- WATCHDOG ----------------------------------------------*/ -typedef struct -{ - - __IO uint32_t LOAD; /* Offset: 0x000 (R/W) Watchdog Load Register */ - __I uint32_t VALUE; /* Offset: 0x004 (R/ ) Watchdog Value Register */ - __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Watchdog Control Register */ - __O uint32_t INTCLR; /* Offset: 0x00C ( /W) Watchdog Clear Interrupt Register */ - __I uint32_t RAWINTSTAT; /* Offset: 0x010 (R/ ) Watchdog Raw Interrupt Status Register */ - __I uint32_t MASKINTSTAT; /* Offset: 0x014 (R/ ) Watchdog Interrupt Status Register */ - uint32_t RESERVED0[762]; - __IO uint32_t LOCK; /* Offset: 0xC00 (R/W) Watchdog Lock Register */ - uint32_t RESERVED1[191]; - __IO uint32_t ITCR; /* Offset: 0xF00 (R/W) Watchdog Integration Test Control Register */ - __O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */ -}CMSDK_WATCHDOG_TypeDef; - -#define CMSDK_WATCHDOG_LOAD_Pos 0 /* CMSDK_WATCHDOG LOAD: LOAD Position */ -#define CMSDK_WATCHDOG_LOAD_Msk (0xFFFFFFFFul << CMSDK_WATCHDOG_LOAD_Pos) /* CMSDK_WATCHDOG LOAD: LOAD Mask */ - -#define CMSDK_WATCHDOG_VALUE_Pos 0 /* CMSDK_WATCHDOG VALUE: VALUE Position */ -#define CMSDK_WATCHDOG_VALUE_Msk (0xFFFFFFFFul << CMSDK_WATCHDOG_VALUE_Pos) /* CMSDK_WATCHDOG VALUE: VALUE Mask */ - -#define CMSDK_WATCHDOG_CTRL_RESEN_Pos 1 /* CMSDK_WATCHDOG CTRL_RESEN: Enable Reset Output Position */ -#define CMSDK_WATCHDOG_CTRL_RESEN_Msk (0x1ul << CMSDK_WATCHDOG_CTRL_RESEN_Pos) /* CMSDK_WATCHDOG CTRL_RESEN: Enable Reset Output Mask */ - -#define CMSDK_WATCHDOG_CTRL_INTEN_Pos 0 /* CMSDK_WATCHDOG CTRL_INTEN: Int Enable Position */ -#define CMSDK_WATCHDOG_CTRL_INTEN_Msk (0x1ul << CMSDK_WATCHDOG_CTRL_INTEN_Pos) /* CMSDK_WATCHDOG CTRL_INTEN: Int Enable Mask */ - -#define CMSDK_WATCHDOG_INTCLR_Pos 0 /* CMSDK_WATCHDOG INTCLR: Int Clear Position */ -#define CMSDK_WATCHDOG_INTCLR_Msk (0x1ul << CMSDK_WATCHDOG_INTCLR_Pos) /* CMSDK_WATCHDOG INTCLR: Int Clear Mask */ - -#define CMSDK_WATCHDOG_RAWINTSTAT_Pos 0 /* CMSDK_WATCHDOG RAWINTSTAT: Raw Int Status Position */ -#define CMSDK_WATCHDOG_RAWINTSTAT_Msk (0x1ul << CMSDK_WATCHDOG_RAWINTSTAT_Pos) /* CMSDK_WATCHDOG RAWINTSTAT: Raw Int Status Mask */ - -#define CMSDK_WATCHDOG_MASKINTSTAT_Pos 0 /* CMSDK_WATCHDOG MASKINTSTAT: Mask Int Status Position */ -#define CMSDK_WATCHDOG_MASKINTSTAT_Msk (0x1ul << CMSDK_WATCHDOG_MASKINTSTAT_Pos) /* CMSDK_WATCHDOG MASKINTSTAT: Mask Int Status Mask */ - -#define CMSDK_WATCHDOG_LOCK_Pos 0 /* CMSDK_WATCHDOG LOCK: LOCK Position */ -#define CMSDK_WATCHDOG_LOCK_Msk (0x1ul << CMSDK_WATCHDOG_LOCK_Pos) /* CMSDK_WATCHDOG LOCK: LOCK Mask */ - -#define CMSDK_WATCHDOG_INTEGTESTEN_Pos 0 /* CMSDK_WATCHDOG INTEGTESTEN: Integration Test Enable Position */ -#define CMSDK_WATCHDOG_INTEGTESTEN_Msk (0x1ul << CMSDK_WATCHDOG_INTEGTESTEN_Pos) /* CMSDK_WATCHDOG INTEGTESTEN: Integration Test Enable Mask */ - -#define CMSDK_WATCHDOG_INTEGTESTOUTSET_Pos 1 /* CMSDK_WATCHDOG INTEGTESTOUTSET: Integration Test Output Set Position */ -#define CMSDK_WATCHDOG_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_WATCHDOG_INTEGTESTOUTSET_Pos) /* CMSDK_WATCHDOG INTEGTESTOUTSET: Integration Test Output Set Mask */ - /*------------------------- Real Time Clock(RTC) ----------------------------------------------*/ typedef struct { @@ -284,6 +246,93 @@ typedef struct #define CMSDK_RTC_ENABLE_Pos 0 /* CMSDK_RTC Enable: Real Time Clock Enable Position */ #define CMSDK_RTC_ENABLE_Msk (0x1ul << CMSDK_RTC_ENABLE_Pos) /* CMSDK_RTC Enable: Real Time Clock Enable Mask */ +/******************************************************************************/ +/* Audio and Touch Screen (I2C) Peripheral declaration */ +/******************************************************************************/ + +typedef struct +{ + union { + __O uint32_t CONTROLS; // Offset: 0x000 CONTROL Set Register ( /W) + __I uint32_t CONTROL; // Offset: 0x000 CONTROL Status Register (R/ ) + }; + __O uint32_t CONTROLC; // Offset: 0x004 CONTROL Clear Register ( /W) +} MPS2_I2C_TypeDef; + +/******************************************************************************/ +/* SMSC9220 Register Definitions */ +/******************************************************************************/ + +typedef struct // SMSC LAN9220 +{ +__I uint32_t RX_DATA_PORT; // Receive FIFO Ports (offset 0x0) + uint32_t RESERVED1[0x7]; +__O uint32_t TX_DATA_PORT; // Transmit FIFO Ports (offset 0x20) + uint32_t RESERVED2[0x7]; + +__I uint32_t RX_STAT_PORT; // Receive FIFO status port (offset 0x40) +__I uint32_t RX_STAT_PEEK; // Receive FIFO status peek (offset 0x44) +__I uint32_t TX_STAT_PORT; // Transmit FIFO status port (offset 0x48) +__I uint32_t TX_STAT_PEEK; // Transmit FIFO status peek (offset 0x4C) + +__I uint32_t ID_REV; // Chip ID and Revision (offset 0x50) +__IO uint32_t IRQ_CFG; // Main Interrupt Configuration (offset 0x54) +__IO uint32_t INT_STS; // Interrupt Status (offset 0x58) +__IO uint32_t INT_EN; // Interrupt Enable Register (offset 0x5C) + uint32_t RESERVED3; // Reserved for future use (offset 0x60) +__I uint32_t BYTE_TEST; // Read-only byte order testing register 87654321h (offset 0x64) +__IO uint32_t FIFO_INT; // FIFO Level Interrupts (offset 0x68) +__IO uint32_t RX_CFG; // Receive Configuration (offset 0x6C) +__IO uint32_t TX_CFG; // Transmit Configuration (offset 0x70) +__IO uint32_t HW_CFG; // Hardware Configuration (offset 0x74) +__IO uint32_t RX_DP_CTL; // RX Datapath Control (offset 0x78) +__I uint32_t RX_FIFO_INF; // Receive FIFO Information (offset 0x7C) +__I uint32_t TX_FIFO_INF; // Transmit FIFO Information (offset 0x80) +__IO uint32_t PMT_CTRL; // Power Management Control (offset 0x84) +__IO uint32_t GPIO_CFG; // General Purpose IO Configuration (offset 0x88) +__IO uint32_t GPT_CFG; // General Purpose Timer Configuration (offset 0x8C) +__I uint32_t GPT_CNT; // General Purpose Timer Count (offset 0x90) + uint32_t RESERVED4; // Reserved for future use (offset 0x94) +__IO uint32_t ENDIAN; // WORD SWAP Register (offset 0x98) +__I uint32_t FREE_RUN; // Free Run Counter (offset 0x9C) +__I uint32_t RX_DROP; // RX Dropped Frames Counter (offset 0xA0) +__IO uint32_t MAC_CSR_CMD; // MAC CSR Synchronizer Command (offset 0xA4) +__IO uint32_t MAC_CSR_DATA; // MAC CSR Synchronizer Data (offset 0xA8) +__IO uint32_t AFC_CFG; // Automatic Flow Control Configuration (offset 0xAC) +__IO uint32_t E2P_CMD; // EEPROM Command (offset 0xB0) +__IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4) + +} SMSC9220_TypeDef; + +// SMSC9220 MAC Registers Indices +#define SMSC9220_MAC_CR 0x1 +#define SMSC9220_MAC_ADDRH 0x2 +#define SMSC9220_MAC_ADDRL 0x3 +#define SMSC9220_MAC_HASHH 0x4 +#define SMSC9220_MAC_HASHL 0x5 +#define SMSC9220_MAC_MII_ACC 0x6 +#define SMSC9220_MAC_MII_DATA 0x7 +#define SMSC9220_MAC_FLOW 0x8 +#define SMSC9220_MAC_VLAN1 0x9 +#define SMSC9220_MAC_VLAN2 0xA +#define SMSC9220_MAC_WUFF 0xB +#define SMSC9220_MAC_WUCSR 0xC + +// SMSC9220 PHY Registers Indices +#define SMSC9220_PHY_BCONTROL 0x0 +#define SMSC9220_PHY_BSTATUS 0x1 +#define SMSC9220_PHY_ID1 0x2 +#define SMSC9220_PHY_ID2 0x3 +#define SMSC9220_PHY_ANEG_ADV 0x4 +#define SMSC9220_PHY_ANEG_LPA 0x5 +#define SMSC9220_PHY_ANEG_EXP 0x6 +#define SMSC9220_PHY_MCONTROL 0x17 +#define SMSC9220_PHY_MSTATUS 0x18 +#define SMSC9220_PHY_CSINDICATE 0x27 +#define SMSC9220_PHY_INTSRC 0x29 +#define SMSC9220_PHY_INTMASK 0x30 +#define SMSC9220_PHY_CS 0x31 + /* -------------------- End of section using anonymous unions ------------------- */ #if defined ( __CC_ARM ) #pragma pop @@ -303,50 +352,52 @@ typedef struct /* ================ Peripheral memory map ================ */ /* ================================================================================ */ -/* Peripheral and SRAM base address */ -#define CMSDK_FLASH_BASE (0x00000000UL) -#define CMSDK_SRAM_BASE (0x20000000UL) -#define CMSDK_PERIPH_BASE (0x40000000UL) - -#define CMSDK_RAM_BASE (0x20000000UL) -#define CMSDK_APB_BASE (0x40000000UL) -#define CMSDK_AHB_BASE (0x40010000UL) - -/* APB peripherals */ -#define CMSDK_TIMER0_BASE (CMSDK_APB_BASE + 0x0000UL) -#define CMSDK_TIMER1_BASE (CMSDK_APB_BASE + 0x1000UL) -#define CMSDK_DUALTIMER_BASE (CMSDK_APB_BASE + 0x2000UL) -#define CMSDK_DUALTIMER_1_BASE (CMSDK_DUALTIMER_BASE) -#define CMSDK_DUALTIMER_2_BASE (CMSDK_DUALTIMER_BASE + 0x20UL) -#define CMSDK_UART0_BASE (CMSDK_APB_BASE + 0x4000UL) -#define CMSDK_UART1_BASE (CMSDK_APB_BASE + 0x5000UL) -#define CMSDK_UART2_BASE (0x4002C000UL) -#define CMSDK_UART3_BASE (0x4002D000UL) -#define CMSDK_UART4_BASE (0x4002E000UL) -#define CMSDK_RTC_BASE (CMSDK_APB_BASE + 0x6000UL) -#define CMSDK_WATCHDOG_BASE (CMSDK_APB_BASE + 0x8000UL) - -/* AHB peripherals */ -#define CMSDK_GPIO0_BASE (CMSDK_AHB_BASE + 0x0000UL) -#define CMSDK_GPIO1_BASE (CMSDK_AHB_BASE + 0x1000UL) -#define CMSDK_GPIO2_BASE (CMSDK_AHB_BASE + 0x2000UL) -#define CMSDK_GPIO3_BASE (CMSDK_AHB_BASE + 0x3000UL) -#define CMSDK_GPIO4_BASE (0x40030000UL) -#define CMSDK_GPIO5_BASE (0x40031000UL) -#define CMSDK_SYSCTRL_BASE (CMSDK_AHB_BASE + 0xF000UL) - - +#define CMSDK_TIMER0_BASE 0x40000000UL +#define CMSDK_TIMER1_BASE 0x40001000UL +#define CMSDK_DUALTIMER_BASE 0x40002000UL +#define CMSDK_DUALTIMER_1_BASE 0x40002000UL +#define CMSDK_DUALTIMER_2_BASE 0x40002020UL +#define CMSDK_UART0_BASE 0x40004000UL +#define CMSDK_UART1_BASE 0x40005000UL +#define CMSDK_RTC_BASE 0x40006000UL +#define CMSDK_WATCHDOG_BASE 0x40008000UL +#define TRNG_BASE 0x4000F000UL +#define CMSDK_GPIO0_BASE 0x40010000UL +#define CMSDK_GPIO1_BASE 0x40011000UL +#define CMSDK_GPIO2_BASE 0x40012000UL +#define CMSDK_GPIO3_BASE 0x40013000UL +#define CMSDK_SYSCTRL_BASE 0x4001F000UL +#define MPS2_SSP0_BASE 0x40020000UL /* User SSP Base Address */ +#define MPS2_SSP1_BASE 0x40021000UL /* CLCD SSP Base Address */ +#define MPS2_TSC_I2C_BASE 0x40022000UL /* Touch Screen I2C Base Address */ +#define MPS2_AAIC_I2C_BASE 0x40023000UL /* Audio Interface I2C Base Address */ +#define MPS2_AAIC_I2S_BASE 0x40024000UL /* Audio Interface I2S Base Address */ +#define MPS2_SSP2_BASE 0x40025000UL /* ADC SSP Base Address */ +#define MPS2_SSP3_BASE 0x40026000UL /* Shield 0 SSP Base Address */ +#define MPS2_SSP4_BASE 0x40027000UL /* Shield 1 SSP Base Address */ +#define MPS2_FPGAIO_BASE 0x40028000UL /* FPGAIO Base Address */ +#define MPS2_SHIELD0_I2C_BASE 0x40029000UL /* I2C shield 0 Base Address */ +#define MPS2_SHIELD1_I2C_BASE 0x4002A000UL /* I2C shield 1 Base Address */ +#define CMSDK_UART2_BASE 0x4002C000UL +#define CMSDK_UART3_BASE 0x4002D000UL +#define CMSDK_UART4_BASE 0x4002E000UL +#define MPS2_SCC_BASE 0x4002F000UL /* SCC Base Address */ +#define CMSDK_GPIO4_BASE 0x40030000UL +#define CMSDK_GPIO5_BASE 0x40031000UL +#define SMSC9220_BASE 0x40200000UL /* Ethernet SMSC9220 Base Address */ +#define MPS2_VGA_TEXT_BUFFER 0x41000000UL /* VGA Text Buffer Address */ +#define MPS2_VGA_BUFFER 0x41100000UL /* VGA Buffer Base Address */ /* ================================================================================ */ /* ================ Peripheral declaration ================ */ /* ================================================================================ */ #define CMSDK_RTC ((CMSDK_RTC_TypeDef *) CMSDK_RTC_BASE ) -#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE ) #define CMSDK_SYSCON ((CMSDK_SYSCON_TypeDef *) CMSDK_SYSCTRL_BASE ) +#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE ) #ifdef __cplusplus } #endif -#endif /* CMSDK_CM3DS_H */ +#endif /* CM3DS_H */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h deleted file mode 100644 index 462e740ea9..0000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/SMM_MPS2.h +++ /dev/null @@ -1,445 +0,0 @@ -/* MPS2 CMSIS Library - * - * Copyright (c) 2006-2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * Code implementation file for the LAN Ethernet interface. - * - * This file is derivative from the MPS2 Selftest's ethernet implementation - * MPS2 Selftest: https://silver.arm.com/browse/VEI10 -> - * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\SMM_MPS2.h - * - ******************************************************************************* - * File: smm_mps2.h - * Release: Version 1.1 - *******************************************************************************/ - -#ifndef __SMM_MPS2_H -#define __SMM_MPS2_H - -#include "peripherallink.h" /* device specific header file */ - -#if defined ( __CC_ARM ) -#pragma anon_unions -#endif - -/******************************************************************************/ -/* FPGA System Register declaration */ -/******************************************************************************/ - -typedef struct -{ - __IO uint32_t LED; // Offset: 0x000 (R/W) LED connections - // [31:2] : Reserved - // [1:0] : LEDs - uint32_t RESERVED1[1]; - __IO uint32_t BUTTON; // Offset: 0x008 (R/W) Buttons - // [31:2] : Reserved - // [1:0] : Buttons - uint32_t RESERVED2[1]; - __IO uint32_t CLK1HZ; // Offset: 0x010 (R/W) 1Hz up counter - __IO uint32_t CLK100HZ; // Offset: 0x014 (R/W) 100Hz up counter - __IO uint32_t COUNTER; // Offset: 0x018 (R/W) Cycle Up Counter - // Increments when 32-bit prescale counter reach zero - __IO uint32_t PRESCALE; // Offset: 0x1C (R/W) Prescaler - // Bit[31:0] : reload value for prescale counter - __IO uint32_t PSCNTR; // Offset: 0x020 (R/W) 32-bit Prescale counter - // current value of the pre-scaler counter - // The Cycle Up Counter increment when the prescale down counter reach 0 - // The pre-scaler counter is reloaded with PRESCALE after reaching 0. - uint32_t RESERVED4[10]; - __IO uint32_t MISC; // Offset: 0x04C (R/W) Misc control */ - // [31:10] : Reserved - // [9] : SHIELD_1_SPI_nCS - // [8] : SHIELD_0_SPI_nCS - // [7] : ADC_SPI_nCS - // [6] : CLCD_BL_CTRL - // [5] : CLCD_RD - // [4] : CLCD_RS - // [3] : CLCD_RESET - // [2] : RESERVED - // [1] : SPI_nSS - // [0] : CLCD_CS -} MPS2_FPGAIO_TypeDef; - -// MISC register bit definitions - -#define CLCD_CS_Pos 0 -#define CLCD_CS_Msk (1UL< CONTROL - // TX Enable - // <0=> TX disabled - // <1=> TX enabled - // TX IRQ Enable - // <0=> TX IRQ disabled - // <1=> TX IRQ enabled - // RX Enable - // <0=> RX disabled - // <1=> RX enabled - // RX IRQ Enable - // <0=> RX IRQ disabled - // <1=> RX IRQ enabled - // TX Buffer Water Level - // <0=> / IRQ triggers when any space available - // <1=> / IRQ triggers when more than 1 space available - // <2=> / IRQ triggers when more than 2 space available - // <3=> / IRQ triggers when more than 3 space available - // <4=> Undefined! - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // RX Buffer Water Level - // <0=> Undefined! - // <1=> / IRQ triggers when less than 1 space available - // <2=> / IRQ triggers when less than 2 space available - // <3=> / IRQ triggers when less than 3 space available - // <4=> / IRQ triggers when less than 4 space available - // <5=> Undefined! - // <6=> Undefined! - // <7=> Undefined! - // FIFO reset - // <0=> Normal operation - // <1=> FIFO reset - // Audio Codec reset - // <0=> Normal operation - // <1=> Assert audio Codec reset - /*!< Offset: 0x004 STATUS Register (R/ ) */ - __I uint32_t STATUS; // STATUS - // TX Buffer alert - // <0=> TX buffer don't need service yet - // <1=> TX buffer need service - // RX Buffer alert - // <0=> RX buffer don't need service yet - // <1=> RX buffer need service - // TX Buffer Empty - // <0=> TX buffer have data - // <1=> TX buffer empty - // TX Buffer Full - // <0=> TX buffer not full - // <1=> TX buffer full - // RX Buffer Empty - // <0=> RX buffer have data - // <1=> RX buffer empty - // RX Buffer Full - // <0=> RX buffer not full - // <1=> RX buffer full - union { - /*!< Offset: 0x008 Error Status Register (R/ ) */ - __I uint32_t ERROR; // ERROR - // TX error - // <0=> Okay - // <1=> TX overrun/underrun - // RX error - // <0=> Okay - // <1=> RX overrun/underrun - /*!< Offset: 0x008 Error Clear Register ( /W) */ - __O uint32_t ERRORCLR; // ERRORCLR - // TX error - // <0=> Okay - // <1=> Clear TX error - // RX error - // <0=> Okay - // <1=> Clear RX error - }; - /*!< Offset: 0x00C Divide ratio Register (R/W) */ - __IO uint32_t DIVIDE; // Divide ratio for Left/Right clock - // TX error (default 0x80) - /*!< Offset: 0x010 Transmit Buffer ( /W) */ - __O uint32_t TXBUF; // Transmit buffer - // Right channel - // Left channel - /*!< Offset: 0x014 Receive Buffer (R/ ) */ - __I uint32_t RXBUF; // Receive buffer - // Right channel - // Left channel - uint32_t RESERVED1[186]; - __IO uint32_t ITCR; // Integration Test Control Register - // ITEN - // <0=> Normal operation - // <1=> Integration Test mode enable - __O uint32_t ITIP1; // Integration Test Input Register 1 - // SDIN - __O uint32_t ITOP1; // Integration Test Output Register 1 - // SDOUT - // SCLK - // LRCK - // IRQOUT -} MPS2_I2S_TypeDef; - -#define I2S_CONTROL_TXEN_Pos 0 -#define I2S_CONTROL_TXEN_Msk (1UL<cfg->base; + enum arm_uart_irq_t intrstatus = ARM_UART_IRQ_NONE; if(dev->data->state & ARM_UART_INITIALIZED) { switch(p_uart->intr_reg.intrstatus) { case ARM_UART_TX_INTR: - return ARM_UART_IRQ_TX; + intrstatus = ARM_UART_IRQ_TX; break; case ARM_UART_RX_INTR: - return ARM_UART_IRQ_RX; + intrstatus = ARM_UART_IRQ_RX; break; case ARM_UART_TX_INTR | ARM_UART_RX_INTR: - return ARM_UART_IRQ_COMBINED; + intrstatus = ARM_UART_IRQ_COMBINED; + break; + default: break; - /* default: not defined to force all cases to be handled */ } } - return ARM_UART_IRQ_NONE; + + return intrstatus; } diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c similarity index 99% rename from targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c rename to targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c index 5c8c356004..0fee077abf 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.c @@ -26,7 +26,7 @@ #include "mbed_retarget.h" #include "mbed_wait_api.h" -#include "SMM_MPS2.h" +#include "CM3DS.h" #include "smsc9220_eth.h" #define REG_WRITE_TIME_OUT 50 @@ -623,7 +623,7 @@ int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, unsigned int dwords_to_write = 0; unsigned int xmit_inf = 0; unsigned int tx_buffer_free_space = 0; - volatile unsigned int xmit_stat = 0; + unsigned int xmit_stat = 0; if (!data) { return -1; /* Invalid input parameter */ @@ -677,7 +677,9 @@ int smsc9220_send_by_chunks(unsigned int total_packet_length, int is_new_packet, /* pop status port */ /* for error check it should be checked "at a later time" according to data sheet */ xmit_stat = SMSC9220->TX_STAT_PORT; + (void)xmit_stat; } + ongoing_packet_length_sent += current_size; return 0; } diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h similarity index 100% rename from targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/SDK/smsc9220_eth.h rename to targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/drivers/smsc9220_eth.h diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h index 7d0fca598b..0e67c01ac0 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/memory_zones.h @@ -12,7 +12,9 @@ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * + */ + +/* * This file contains the information of memory zones for code and data on * CM3DS. * It is used in startup code and linker scripts of supported compilers (ARM and diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/peripherallink.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/peripherallink.h deleted file mode 100644 index 69ebc650cc..0000000000 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/peripherallink.h +++ /dev/null @@ -1,35 +0,0 @@ -/* MPS2 CMSIS Library - * - * Copyright (c) 2006-2017 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - * - * This file is derivative from the MPS2 Selftest implementation - * MPS2 Selftest: https://silver.arm.com/browse/VEI10 -> - * \ISCM-1-0\AN491\software\Selftest\v2m_mps2\peripherallink.h - * - ******************************************************************************* - * Name: peripherallink.h - * Purpose: Include the correct device header file - *******************************************************************************/ - -#ifndef __DEVICE_H -#define __DEVICE_H - -#if defined CMSDK_CM3DS - #include "CMSDK_CM3DS.h" /* device specific header file */ -#else - #warning "no appropriate header file found!" -#endif - -#endif /* __DEVICE_H */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c index 51170c9e84..53524a3594 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.c @@ -15,7 +15,8 @@ */ #include "platform_devices.h" -#include "SMM_MPS2.h" +/* Base addresses of peripherals */ +#include "CM3DS.h" /* ARM CMSDK Timer driver structures */ #ifdef ARM_CMSDK_TIMER0 diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h index d6a7fb2a8a..c33f07e25b 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/platform_devices.h @@ -17,6 +17,7 @@ #ifndef __ARM_LTD_PLATFORM_DEVICES_H__ #define __ARM_LTD_PLATFORM_DEVICES_H__ +/* ======= Configures the peripheral set ======= */ #include "device_cfg.h" /* ======= Includes generic driver headers ======= */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.c index 2e6ea2e276..b9b50b15e3 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2009-2017 ARM Limited. All rights reserved. + * Copyright (c) 2009-2018 ARM Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -14,7 +14,9 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * + */ + +/* * This file is derivative of CMSIS V5.00 system_ARMCM3.c */ @@ -23,7 +25,7 @@ /*---------------------------------------------------------------------------- * Define clocks *----------------------------------------------------------------------------*/ -#define __XTAL (48000000UL) /* Oscillator frequency */ +#define __XTAL (50000000UL) /* Oscillator frequency */ #define __SYSTEM_CLOCK (__XTAL / 2) diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.h index be75446f59..4f45c15746 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/device/system_CMSDK_CM3DS.h @@ -14,7 +14,9 @@ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. * See the License for the specific language governing permissions and * limitations under the License. - * + */ + +/* * This file is derivative of CMSIS V5.00 system_ARMCM3.h */ diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/i2c_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/i2c_api.c index 1496610a5c..0ecff72280 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/i2c_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/i2c_api.c @@ -1,5 +1,5 @@ /* mbed Microcontroller Library - * Copyright (c) 2017 ARM Limited + * Copyright (c) 2017-2018 ARM Limited * * Licensed under the Apache License, Version 2.0 (the "License"); * you may not use this file except in compliance with the License. @@ -17,7 +17,7 @@ #include "cmsis.h" #include "mbed_error.h" #include "mbed_wait_api.h" -#include "SMM_MPS2.h" +#include "CM3DS.h" #include "pinmap.h" /* diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h index bc073a30c4..308e9d45f9 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/objects.h @@ -58,15 +58,6 @@ struct i2c_s { uint32_t freq_us; /* Stores I2C frequency in microseconds */ }; -struct tsc_s { - MPS2_I2C_TypeDef *tsc; -}; - -struct audio_s { - MPS2_I2S_TypeDef *audio_I2S; - MPS2_I2C_TypeDef *audio_I2C; -}; - struct spi_s { struct spi_pl022_dev_t *spi; }; diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c index 3f96b55c80..11692bbb3d 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/port_api.c @@ -25,7 +25,7 @@ PinName port_pin(PortName port, int pin_n) return NC; } - return (PINS_PER_GPIO * port + pin_n); + return (PinName)(PINS_PER_GPIO * port + pin_n); } void port_init(port_t *obj, PortName port, int mask, PinDirection dir) diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c index 06895656a5..ab97bc2627 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/serial_api.c @@ -76,8 +76,9 @@ static uint32_t fill_serial_object(struct serial_s *serial_obj, PinName tx, return 1; } - uart_peripheral = pinmap_merge(pinmap_peripheral(tx, PinMap_UART_TX), - pinmap_peripheral(rx, PinMap_UART_RX)); + uart_peripheral = (UARTName)pinmap_merge( + pinmap_peripheral(tx, PinMap_UART_TX), + pinmap_peripheral(rx, PinMap_UART_RX)); switch (uart_peripheral) { #ifdef ARM_UART0 diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c index f546a3aa1e..0eba70a2fa 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/trng_api.c @@ -18,8 +18,6 @@ #include "tztrng.h" #define BITS_PER_BYTE 8 -/* Base address of the TRNG peripheral */ -#define TRNG_BASE 0x4000F000 void trng_init(trng_t *obj) { diff --git a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c index 3f90820686..e45dd8cfec 100644 --- a/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c +++ b/targets/TARGET_ARM_SSG/TARGET_CM3DS_MPS2/us_ticker.c @@ -23,30 +23,37 @@ #include "us_ticker_api.h" #include "platform_devices.h" +/* + * The CMSDK Ticker counts on 32 bits. + */ +#define CMSDK_TICKER_COUNTER_BITS 32U + /** - * \brief Convert clocks to us + * \brief Pass-through function to make the US ticker HAL only work in the tick + * domain. This function is needed by the CMSDK Ticker layer. * - * \param[in] tick Number of clocks + * \param[in] tick Number of clock ticks * - * \return Number of usec, relative to the timer frequency, - * that a given ammount of ticks equates to. + * \return The number of ticks given. */ static uint32_t convert_tick_to_us(uint32_t tick) { - return (tick / (SystemCoreClock / SEC_TO_USEC_MULTIPLIER)); + /* Work only in the tick domain. */ + return tick; } /** - * \brief Convert us to clock ticks + * \brief Pass-through function to make the US ticker HAL only work in the tick + * domain. This function is needed by the CMSDK Ticker layer. * - * \param[in] us Time to convert to clock ticks + * \param[in] us Number of us * - * \return Number of clock ticks relative to the timer frequency, - * that a given period of usec equates to. + * \return The number of us given. */ static uint32_t convert_us_to_tick(uint32_t us) { - return (us * (SystemCoreClock / SEC_TO_USEC_MULTIPLIER)); + /* Work only in the tick domain. */ + return us; } static const struct tick_cfg_t cfg = @@ -109,3 +116,18 @@ void TIMER0_IRQHandler(void) { cmsdk_ticker_irq_handler(&timer_data); } + +const ticker_info_t* us_ticker_get_info(void) +{ + static ticker_info_t us_ticker_info = { + .bits = CMSDK_TICKER_COUNTER_BITS + }; + + /* + * SystemCoreClock is not a constant so it cannot be used to initialize the + * ticker_info_t structure. + */ + us_ticker_info.frequency = SystemCoreClock; + + return &us_ticker_info; +}