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Add Atmel RF driver v3.0.4

pull/7814/head
Seppo Takalo 2018-08-17 13:27:53 +03:00 committed by Cruz Monrreal II
parent 710d1bb00a
commit d02097f97c
10 changed files with 2923 additions and 0 deletions
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components/802.15.4_RF/atmel-rf-driver/.gitignore vendored Normal file
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*~
*.swo
*.swp
build
yotta_modules
yotta_targets

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components/802.15.4_RF/atmel-rf-driver/LICENSE Normal file
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Unless specifically indicated otherwise in a file, files are licensed
under the Apache 2.0 license, as can be found in: apache-2.0.txt

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components/802.15.4_RF/atmel-rf-driver/README.md Normal file
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# Example RF driver for Atmel 802.15.4 transceivers #
Support for:
* AT86RF233
* AT86RF212B
This driver is used with 6LoWPAN stack.

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components/802.15.4_RF/atmel-rf-driver/apache-2.0.txt Normal file
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Apache License
Version 2.0, January 2004
http://www.apache.org/licenses/
TERMS AND CONDITIONS FOR USE, REPRODUCTION, AND DISTRIBUTION
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END OF TERMS AND CONDITIONS

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components/802.15.4_RF/atmel-rf-driver/atmel-rf-driver/NanostackRfPhyAtmel.h Normal file
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/*
* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef NANOSTACK_RF_PHY_ATMEL_H_
#define NANOSTACK_RF_PHY_ATMEL_H_
#include "at24mac.h"
#include "PinNames.h"
#ifdef MBED_CONF_NANOSTACK_CONFIGURATION
#include "NanostackRfPhy.h"
// Arduino pin defaults for convenience
#if !defined(ATMEL_SPI_MOSI)
#define ATMEL_SPI_MOSI D11
#endif
#if !defined(ATMEL_SPI_MISO)
#define ATMEL_SPI_MISO D12
#endif
#if !defined(ATMEL_SPI_SCLK)
#define ATMEL_SPI_SCLK D13
#endif
#if !defined(ATMEL_SPI_CS)
#define ATMEL_SPI_CS D10
#endif
#if !defined(ATMEL_SPI_RST)
#define ATMEL_SPI_RST D5
#endif
#if !defined(ATMEL_SPI_SLP)
#define ATMEL_SPI_SLP D7
#endif
#if !defined(ATMEL_SPI_IRQ)
#define ATMEL_SPI_IRQ D9
#endif
#if !defined(ATMEL_I2C_SDA)
#define ATMEL_I2C_SDA D14
#endif
#if !defined(ATMEL_I2C_SCL)
#define ATMEL_I2C_SCL D15
#endif
class RFBits;
class NanostackRfPhyAtmel : public NanostackRfPhy {
public:
NanostackRfPhyAtmel(PinName spi_mosi, PinName spi_miso,
PinName spi_sclk, PinName spi_cs, PinName spi_rst, PinName spi_slp, PinName spi_irq,
PinName i2c_sda, PinName i2c_scl);
virtual ~NanostackRfPhyAtmel();
virtual int8_t rf_register();
virtual void rf_unregister();
virtual void get_mac_address(uint8_t *mac);
virtual void set_mac_address(uint8_t *mac);
private:
AT24Mac _mac;
uint8_t _mac_addr[8];
RFBits *_rf;
bool _mac_set;
const PinName _spi_mosi;
const PinName _spi_miso;
const PinName _spi_sclk;
const PinName _spi_cs;
const PinName _spi_rst;
const PinName _spi_slp;
const PinName _spi_irq;
};
#endif /* MBED_CONF_NANOSTACK_CONFIGURATION */
#endif /* NANOSTACK_RF_PHY_ATMEL_H_ */

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components/802.15.4_RF/atmel-rf-driver/mbed_lib.json Normal file
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{
"name": "atmel-rf",
"config": {
"full-spi-speed": {
"help": "Maximum SPI clock speed (Hz), as long as sufficient inter-byte spacing",
"value": 7500000
},
"full-spi-speed-byte-spacing": {
"help": "Required byte spacing in nanoseconds if full SPI speed is in use",
"value": 250
},
"low-spi-speed": {
"help": "Maximum SPI clock speed (Hz) if no inter-byte spacing",
"value": 3750000
},
"use-spi-spacing-api": {
"help": "Use SPI spacing API proposed in https://github.com/ARMmbed/mbed-os/pull/5353 to ensure spacing between bytes - either run at full speed with spacing, or low with no spacing",
"value": false
},
"assume-spaced-spi": {
"help": "If not using SPI spacing API, assume platform has widely-spaced bytes in bursts, so use full clock speed rather than low.",
"value": false
},
"provide-default": {
"help": "Provide default NanostackRfpy. [true/false]",
"value": false
}
},
"target_overrides": {
"STM": {
"assume-spaced-spi": true
}
}
}

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components/802.15.4_RF/atmel-rf-driver/source/AT86RFReg.h Normal file
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/*
* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef AT86RFREG_H_
#define AT86RFREG_H_
#ifdef __cplusplus
extern "C" {
#endif
/*AT86RF212 PHY Modes*/
#define BPSK_20 0x00
#define BPSK_40 0x04
#define BPSK_40_ALT 0x14
#define OQPSK_SIN_RC_100 0x08
#define OQPSK_SIN_RC_200 0x09
#define OQPSK_RC_100 0x18
#define OQPSK_RC_200 0x19
#define OQPSK_SIN_250 0x0c
#define OQPSK_SIN_500 0x0d
#define OQPSK_SIN_500_ALT 0x0f
#define OQPSK_RC_250 0x1c
#define OQPSK_RC_500 0x1d
#define OQPSK_RC_500_ALT 0x1f
#define OQPSK_SIN_RC_400_SCR_ON 0x2A
#define OQPSK_SIN_RC_400_SCR_OFF 0x0A
#define OQPSK_RC_400_SCR_ON 0x3A
#define OQPSK_RC_400_SCR_OFF 0x1A
#define OQPSK_SIN_1000_SCR_ON 0x2E
#define OQPSK_SIN_1000_SCR_OFF 0x0E
#define OQPSK_RC_1000_SCR_ON 0x3E
#define OQPSK_RC_1000_SCR_OFF 0x1E
/*Supported transceivers*/
#define PART_AT86RF231 0x03
#define PART_AT86RF212 0x07
#define PART_AT86RF233 0x0B
#define VERSION_AT86RF212 0x01
#define VERSION_AT86RF212B 0x03
/*RF Configuration Registers*/
#define TRX_STATUS 0x01
#define TRX_STATE 0x02
#define TRX_CTRL_0 0x03
#define TRX_CTRL_1 0x04
#define PHY_TX_PWR 0x05
#define PHY_RSSI 0x06
#define PHY_ED_LEVEL 0x07
#define PHY_CC_CCA 0x08
#define RX_CTRL 0x0A
#define SFD_VALUE 0x0B
#define TRX_CTRL_2 0x0C
#define ANT_DIV 0x0D
#define IRQ_MASK 0x0E
#define IRQ_STATUS 0x0F
#define VREG_CTRL 0x10
#define BATMON 0x11
#define XOSC_CTRL 0x12
#define CC_CTRL_0 0x13
#define CC_CTRL_1 0x14
#define RX_SYN 0x15
#define TRX_RPC 0x16
#define RF_CTRL_0 0x16
#define XAH_CTRL_1 0x17
#define FTN_CTRL 0x18
#define PLL_CF 0x1A
#define PLL_DCU 0x1B
#define PART_NUM 0x1C
#define VERSION_NUM 0x1D
#define MAN_ID_0 0x1E
#define MAN_ID_1 0x1F
#define SHORT_ADDR_0 0x20
#define SHORT_ADDR_1 0x21
#define PAN_ID_0 0x22
#define PAN_ID_1 0x23
#define IEEE_ADDR_0 0x24
#define IEEE_ADDR_1 0x25
#define IEEE_ADDR_2 0x26
#define IEEE_ADDR_3 0x27
#define IEEE_ADDR_4 0x28
#define IEEE_ADDR_5 0x29
#define IEEE_ADDR_6 0x2A
#define IEEE_ADDR_7 0x2B
#define XAH_CTRL_0 0x2C
#define CSMA_SEED_0 0x2D
#define CSMA_SEED_1 0x2E
#define CSMA_BE 0x2F
/* CSMA_SEED_1*/
#define AACK_FVN_MODE1 7
#define AACK_FVN_MODE0 6
#define AACK_SET_PD 5
#define AACK_DIS_ACK 4
#define AACK_I_AM_COORD 3
#define CSMA_SEED_12 2
#define CSMA_SEED_11 1
#define CSMA_SEED_10 0
/*TRX_STATUS bits*/
#define CCA_STATUS 0x40
#define CCA_DONE 0x80
/*PHY_CC_CCA bits*/
#define CCA_REQUEST 0x80
#define CCA_MODE_3A 0x00
#define CCA_MODE_1 0x20
#define CCA_MODE_2 0x40
#define CCA_MODE_3B 0x60
#define CCA_MODE_MASK 0x60
#define CCA_CHANNEL_MASK 0x1F
/*IRQ_MASK bits*/
#define RX_START 0x04
#define TRX_END 0x08
#define CCA_ED_DONE 0x10
#define AMI 0x20
#define TRX_UR 0x40
/*ANT_DIV bits*/
#define ANT_DIV_EN 0x08
#define ANT_EXT_SW_EN 0x04
#define ANT_CTRL_DEFAULT 0x03
/*TRX_CTRL_1 bits*/
#define PA_EXT_EN 0x80
#define TX_AUTO_CRC_ON 0x20
#define SPI_CMD_MODE_TRX_STATUS 0x04
#define SPI_CMD_MODE_PHY_RSSI 0x08
#define SPI_CMD_MODE_IRQ_STATUS 0x0C
/*TRX_CTRL_2 bits*/
#define RX_SAFE_MODE 0x80
/*FTN_CTRL bits*/
#define FTN_START 0x80
/*PHY_RSSI bits*/
#define CRC_VALID 0x80
/*RX_SYN bits*/
#define RX_PDT_DIS 0x80
/*TRX_RPC bits */
#define RX_RPC_CTRL 0xC0
#define RX_RPC_EN 0x20
#define PDT_RPC_EN 0x10
#define PLL_RPC_EN 0x08
#define XAH_TX_RPC_EN 0x04
#define IPAN_RPC_EN 0x02
#define TRX_RPC_RSVD_1 0x01
/*XAH_CTRL_1 bits*/
#define AACK_PROM_MODE 0x02
#ifdef __cplusplus
}
#endif
#endif /* AT86RFREG_H_ */

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components/802.15.4_RF/atmel-rf-driver/source/NanostackRfPhyAtmel.cpp Normal file
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components/802.15.4_RF/atmel-rf-driver/source/at24mac.cpp Normal file
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/*
* Copyright (c) 2016-2016 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "at24mac.h"
/* Device addressing */
#define AT24MAC_EEPROM_ADDRESS (0x0A<<4)
#define AT24MAC_RW_PROTECT_ADDRESS (0x06<<4)
#define AT24MAC_SERIAL_ADDRESS (0x0B<<4)
/* Known memory blocks */
#define AT24MAC_SERIAL_OFFSET (0x80)
#define AT24MAC_EUI64_OFFSET (0x98)
#define AT24MAC_EUI48_OFFSET (0x9A)
#define SERIAL_LEN 16
#define EUI64_LEN 8
#define EUI48_LEN 6
AT24Mac::I2CReset::I2CReset(PinName sda, PinName scl)
{
mbed::DigitalInOut SDA(sda, PIN_OUTPUT, PullUp, 1);
mbed::DigitalInOut SCL(scl, PIN_OUTPUT, PullUp, 0);
//generate 9 clocks for worst-case scenario
for (int i = 0; i < 10; ++i) {
SCL = 1;
wait_us(5);
SCL = 0;
wait_us(5);
}
//generate a STOP condition
SDA = 0;
wait_us(5);
SCL = 1;
wait_us(5);
SDA = 1;
wait_us(5);
}
/*I2C needs to be reset before constructing the I2C object (in case I2C is stuck)
because they use the same pins, therefore i2c_reset has to be before _i2c
in the initializer list*/
AT24Mac::AT24Mac(PinName sda, PinName scl) : i2c_reset(sda, scl), _i2c(sda, scl)
{
// Do nothing
}
int AT24Mac::read_serial(void *buf)
{
char offset = AT24MAC_SERIAL_OFFSET;
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true))
return -1; //No ACK
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, SERIAL_LEN);
}
int AT24Mac::read_eui64(void *buf)
{
char offset = AT24MAC_EUI64_OFFSET;
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true))
return -1; //No ACK
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, EUI64_LEN);
}
int AT24Mac::read_eui48(void *buf)
{
char offset = AT24MAC_EUI48_OFFSET;
if (_i2c.write(AT24MAC_SERIAL_ADDRESS, &offset, 1, true))
return -1; //No ACK
return _i2c.read(AT24MAC_SERIAL_ADDRESS, (char*)buf, EUI48_LEN);
}

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components/802.15.4_RF/atmel-rf-driver/source/at24mac.h Normal file
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/*
* Copyright (c) 2014-2015 ARM Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef AT24MAC_H
#define AT24MAC_H
#include "PinNames.h"
#include "I2C.h"
#include "drivers/DigitalInOut.h"
#include "platform/mbed_wait_api.h"
/*
* AT24MAC drivers.
*
* This is a EEPROM chip designed to contain factory programmed read-only EUI-64 or EUI-48,
* a 128bit serial number and some user programmable EEPROM.
*
* AT24MAC602 contains EUI-64, use read_eui64()
* AT24MAC402 contains EUI-64, use read_eui48()
*
* NOTE: You cannot use both EUI-64 and EUI-48. Chip contains only one of those.
*/
class AT24Mac {
public:
AT24Mac(PinName sda, PinName scl);
/**
* Read unique serial number from chip.
* \param buf pointer to write serial number to. Must have space for 16 bytes.
* \return zero on success, negative number on failure
*/
int read_serial(void *buf);
/**
* Read EUI-64 from chip.
* \param buf pointer to write EUI-64 to. Must have space for 8 bytes.
* \return zero on success, negative number on failure
*/
int read_eui64(void *buf);
/**
* Read EUI-48 from chip.
* \param buf pointer to write EUI-48 to. Must have space for 6 bytes.
* \return zero on success, negative number on failure
*/
int read_eui48(void *buf);
private:
/*
* Dummy class to allow us to reset I2C before the I2C constructor is called in
* the initializer list of AT24Mac's constructor
*/
class I2CReset {
public:
I2CReset(PinName sda, PinName scl);
};
I2CReset i2c_reset;
mbed::I2C _i2c;
};
#endif /* AT24MAC_H */