ARMmbed
/
mbed-os
mirror of https://github.com/ARMmbed/mbed-os.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

STM32H7 astyle

pull/14699/head
jeromecoutant 2021-05-25 14:33:09 +02:00
parent 9cadad3dcf
commit cfd86882d3
3 changed files with 65 additions and 64 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
View File

@ -61,8 +61,7 @@
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth) void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{ {
GPIO_InitTypeDef GPIO_InitStruct; GPIO_InitTypeDef GPIO_InitStruct;
if(heth->Instance == ETH) if (heth->Instance == ETH) {
{
enableEthPowerSupply(); enableEthPowerSupply();
#if !(defined(DUAL_CORE) && defined(CORE_CM4)) #if !(defined(DUAL_CORE) && defined(CORE_CM4))
@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
*/ */
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth) void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{ {
if(heth->Instance == ETH) if (heth->Instance == ETH) {
{
/* Peripheral clock disable */ /* Peripheral clock disable */
__HAL_RCC_ETH1MAC_CLK_DISABLE(); __HAL_RCC_ETH1MAC_CLK_DISABLE();
__HAL_RCC_ETH1TX_CLK_DISABLE(); __HAL_RCC_ETH1TX_CLK_DISABLE();

15
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c
View File

@ -95,11 +95,13 @@ void SetSysClock(void)
} }
static const uint32_t _keep; static const uint32_t _keep;
bool isBootloader() { bool isBootloader()
{
return ((uint32_t)&_keep < 0x8040000); return ((uint32_t)&_keep < 0x8040000);
} }
bool isBetaBoard() { bool isBetaBoard()
{
uint8_t *bootloader_data = (uint8_t *)(0x801F000); uint8_t *bootloader_data = (uint8_t *)(0x801F000);
if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) { if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
return true; return true;
@ -122,8 +124,7 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) { if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) {
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK; RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI; RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
{
return 0; return 0;
} }
} }
@ -203,12 +204,14 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (lowspeed) { if (lowspeed) {
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
return 0; // FAIL return 0; // FAIL
}
} else { } else {
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
return 0; // FAIL return 0; // FAIL
} }
}
// HAL_RCCEx_EnableBootCore(RCC_BOOT_C2); // HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);