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STM32H7 astyle

pull/14699/head
jeromecoutant 2021-05-25 14:33:09 +02:00
parent 9cadad3dcf
commit cfd86882d3
3 changed files with 65 additions and 64 deletions
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24
connectivity/drivers/emac/TARGET_STM/TARGET_STM32H7/TARGET_PORTENTA_H7/stm32h7_eth_init.c
View File

@ -61,14 +61,13 @@
void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
{
GPIO_InitTypeDef GPIO_InitStruct;
if(heth->Instance == ETH)
{
if (heth->Instance == ETH) {
enableEthPowerSupply();
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
#if !(defined(DUAL_CORE) && defined(CORE_CM4))
/* Disable DCache for STM32H7 family */
SCB_DisableDCache();
#endif
#endif
/* GPIO Ports Clock Enable */
__HAL_RCC_GPIOA_CLK_ENABLE();
@ -118,21 +117,21 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
PC4 ------> ETH_RXD0
PC5 ------> ETH_RXD1
*/
GPIO_InitStruct.Pin = ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin;
GPIO_InitStruct.Pin = ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOG, &GPIO_InitStruct);
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin;
GPIO_InitStruct.Pin = ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Alternate = GPIO_AF11_ETH;
HAL_GPIO_Init(GPIOC, &GPIO_InitStruct);
GPIO_InitStruct.Pin = ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin;
GPIO_InitStruct.Pin = ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
@ -146,8 +145,7 @@ void HAL_ETH_MspInit(ETH_HandleTypeDef *heth)
*/
void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
{
if(heth->Instance == ETH)
{
if (heth->Instance == ETH) {
/* Peripheral clock disable */
__HAL_RCC_ETH1MAC_CLK_DISABLE();
__HAL_RCC_ETH1TX_CLK_DISABLE();
@ -164,11 +162,11 @@ void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth)
PC4 ------> ETH_RXD0
PC5 ------> ETH_RXD1
*/
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin|ETH_TXD1_Pin|ETH_TXD0_Pin);
HAL_GPIO_DeInit(GPIOG, ETH_TX_EN_Pin | ETH_TXD1_Pin | ETH_TXD0_Pin);
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin|ETH_RXD0_Pin|ETH_RXD1_Pin);
HAL_GPIO_DeInit(GPIOC, ETH_MDC_SAI4_D1_Pin | ETH_RXD0_Pin | ETH_RXD1_Pin);
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin|ETH_REF_CLK_Pin|ETH_CRS_DV_Pin);
HAL_GPIO_DeInit(GPIOA, ETH_MDIO_Pin | ETH_REF_CLK_Pin | ETH_CRS_DV_Pin);
HAL_GPIO_WritePin(GPIOJ, GPIO_PIN_15, 0);
}

42
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/portenta_power.cpp
View File

@ -26,27 +26,27 @@
******************************************************************************/
void enableEthPowerSupply(void)
{
/* Ensure ETH power supply */
mbed::I2C i2c(PB_7, PB_6);
char data[2];
/* Ensure ETH power supply */
mbed::I2C i2c(PB_7, PB_6);
// LDO3 to 1.2V
data[0]=0x52;
data[1]=0x9;
i2c.write(8 << 1, data, sizeof(data));
data[0]=0x53;
data[1]=0xF;
i2c.write(8 << 1, data, sizeof(data));
// SW2 to 3.3V (SW2_VOLT)
data[0]=0x3B;
data[1]=0xF;
i2c.write(8 << 1, data, sizeof(data));
char data[2];
// LDO3 to 1.2V
data[0] = 0x52;
data[1] = 0x9;
i2c.write(8 << 1, data, sizeof(data));
data[0] = 0x53;
data[1] = 0xF;
i2c.write(8 << 1, data, sizeof(data));
// SW2 to 3.3V (SW2_VOLT)
data[0] = 0x3B;
data[1] = 0xF;
i2c.write(8 << 1, data, sizeof(data));
// SW1 to 3.0V (SW1_VOLT)
data[0] = 0x35;
data[1] = 0xF;
i2c.write(8 << 1, data, sizeof(data));
// SW1 to 3.0V (SW1_VOLT)
data[0]=0x35;
data[1]=0xF;
i2c.write(8 << 1, data, sizeof(data));
}

63
targets/TARGET_STM/TARGET_STM32H7/TARGET_STM32H747xI/TARGET_PORTENTA_H7/system_clock_override.c
View File

@ -68,9 +68,9 @@ uint8_t SetSysClock_PLL_HSI(void);
void SetSysClock(void)
{
bool lowspeed = false;
bool lowspeed = false;
#if defined(LOWSPEED) && (LOWSPEED == 1)
lowspeed = true;
lowspeed = true;
#endif
#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
@ -95,17 +95,19 @@ void SetSysClock(void)
}
static const uint32_t _keep;
bool isBootloader() {
return ((uint32_t)&_keep < 0x8040000);
bool isBootloader()
{
return ((uint32_t)&_keep < 0x8040000);
}
bool isBetaBoard() {
uint8_t* bootloader_data = (uint8_t*)(0x801F000);
if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
return true;
} else {
return (bootloader_data[10] == 27);
}
bool isBetaBoard()
{
uint8_t *bootloader_data = (uint8_t *)(0x801F000);
if (bootloader_data[0] != 0xA0 || bootloader_data[1] < 14) {
return true;
} else {
return (bootloader_data[10] == 27);
}
}
#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
@ -118,14 +120,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
// If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
// If we are reconfiguring the clock, select CSI as system clock source to allow modification of the PLL configuration
if (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE) {
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
{
return 0;
}
RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK;
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_CSI;
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) {
return 0;
}
}
/* Enable oscillator pin */
@ -148,9 +149,9 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
/* Configure the main internal regulator output voltage */
if (lowspeed) {
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE3);
} else {
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
__HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
}
while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
@ -167,17 +168,17 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC_OscInitStruct.PLL.PLLM = 5;
if (lowspeed) {
RCC_OscInitStruct.PLL.PLLN = 40;
RCC_OscInitStruct.PLL.PLLN = 40;
} else {
RCC_OscInitStruct.PLL.PLLN = 160;
RCC_OscInitStruct.PLL.PLLN = 160;
}
#if HSE_VALUE == 27000000
RCC_OscInitStruct.PLL.PLLM = 9;
if (lowspeed) {
RCC_OscInitStruct.PLL.PLLN = 80;
RCC_OscInitStruct.PLL.PLLN = 80;
} else {
RCC_OscInitStruct.PLL.PLLN = 300;
RCC_OscInitStruct.PLL.PLLN = 300;
}
#endif
@ -203,11 +204,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass, bool lowspeed)
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
if (lowspeed) {
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK)
return 0; // FAIL
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) {
return 0; // FAIL
}
} else {
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
return 0; // FAIL
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK) {
return 0; // FAIL
}
}
// HAL_RCCEx_EnableBootCore(RCC_BOOT_C2);
@ -294,13 +297,13 @@ uint8_t SetSysClock_PLL_HSI(void)
#if defined (CORE_CM4)
void HSEM2_IRQHandler(void)
{
HAL_HSEM_IRQHandler();
HAL_HSEM_IRQHandler();
}
#endif
#if defined (CORE_CM7)
void HSEM1_IRQHandler(void)
{
HAL_HSEM_IRQHandler();
HAL_HSEM_IRQHandler();
}
#endif