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Merge pull request #1001 from mfiore02/3_25_15_dragonfly_mdot_pullrequest 

Updated hal & cmsis support for MTS Dragonfly and MTS mDot
pull/1005/head
Martin Kojtal 2015-03-27 15:47:58 +00:00
parent d836f53d42 54f4391f79
commit cfb9dd117e
20 changed files with 197 additions and 72 deletions
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6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
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@ -28,9 +28,11 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
LR_IROM1 0x08000000 0x80000 { ; load region size_region
; FIRST 64 KB FLASH FOR BOOTLOADER
; REST 448 KB FLASH FOR APPLICATION
LR_IROM1 0x08010000 0x70000 { ; load region size_region
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
ER_IROM1 0x08010000 0x70000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct
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@ -28,9 +28,11 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
LR_IROM1 0x08000000 0x80000 { ; load region size_region
; FIRST 64 KB FLASH FOR BOOTLOADER
; REST 448 KB FLASH FOR APPLICATION
LR_IROM1 0x08010000 0x70000 { ; load region size_region
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
ER_IROM1 0x08010000 0x70000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_GCC_ARM/NUCLEO_F411RE.ld
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@ -3,7 +3,9 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
/* First 64kB of flash reserved for bootloader */
/* Other 448kB for application */
FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K
/* CCM (rwx) : ORIGIN = 0x10000000, LENGTH = 64K */
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
}

11
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf
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@ -1,6 +1,6 @@
/* [ROM = 512kb = 0x80000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __intvec_start__ = 0x08010000;
define symbol __region_ROM_start__ = 0x08010000;
define symbol __region_ROM_end__ = 0x0807FFFF;
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */
@ -15,9 +15,10 @@ define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__]
define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
/* Stack and Heap */
/*Heap 1/4 of ram and stack 1/8*/
define symbol __size_cstack__ = 0x4000;
define symbol __size_heap__ = 0x8000;
/* Stack: 4kB - 408B for vector table */
/* Heap: 96kB */
define symbol __size_cstack__ = 0xe68;
define symbol __size_heap__ = 0x18000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/cmsis_nvic.c
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@ -31,7 +31,7 @@
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
#define NVIC_FLASH_VECTOR_ADDRESS (FLASH_BASE | VECT_TAB_OFFSET) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/system_stm32f4xx.c
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@ -124,8 +124,10 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif
/******************************************************************************/
/**

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_MICRO/stm32f411re.sct
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@ -28,9 +28,11 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
LR_IROM1 0x08000000 0x80000 { ; load region size_region
; FIRST 64 KB FLASH FOR BOOTLOADER
; REST 448 KB FLASH FOR APPLICATION
LR_IROM1 0x08010000 0x70000 { ; load region size_region
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
ER_IROM1 0x08010000 0x70000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_ARM_STD/stm32f411re.sct
View File

@ -28,9 +28,11 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; STM32F411RE: 512 KB FLASH (0x80000) + 128 KB SRAM (0x20000)
LR_IROM1 0x08000000 0x80000 { ; load region size_region
; FIRST 64 KB FLASH FOR BOOTLOADER
; REST 448 KB FLASH FOR APPLICATION
LR_IROM1 0x08010000 0x70000 { ; load region size_region
ER_IROM1 0x08000000 0x80000 { ; load address = execution address
ER_IROM1 0x08010000 0x70000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)

6
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_GCC_ARM/STM32F411XE.ld
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@ -1,8 +1,10 @@
/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512K
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
/* First 64kB of flash reserved for bootloader */
/* Other 448kB for application */
FLASH (rx) : ORIGIN = 0x08010000, LENGTH = 448K
RAM (rwx) : ORIGIN = 0x20000198, LENGTH = 128k - 0x198
}
/* Linker script to place sections and symbol values. Should be used together

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/TOOLCHAIN_IAR/stm32f411xe.icf
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@ -1,6 +1,6 @@
/* [ROM = 512kb = 0x80000] */
define symbol __intvec_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08000000;
define symbol __region_ROM_start__ = 0x08010000;
define symbol __region_ROM_end__ = 0x0807FFFF;
/* [RAM = 128kb = 0x20000] Vector table dynamic copy: 102 vectors = 408 bytes (0x198) to be reserved in RAM */

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/cmsis_nvic.c
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@ -31,7 +31,7 @@
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000) // Initial vector position in flash
#define NVIC_FLASH_VECTOR_ADDRESS (FLASH_BASE | VECT_TAB_OFFSET) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
uint32_t *vectors = (uint32_t *)SCB->VTOR;

2
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c
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@ -125,8 +125,10 @@
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
/* #define VECT_TAB_SRAM */
#ifndef VECT_TAB_OFFSET
#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
#endif
/******************************************************************************/
/**

21
libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/PinNames.h
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@ -150,13 +150,24 @@ typedef enum {
LED2 = D3,
LED3 = D3,
LED4 = D3,
USER_BUTTON = PC_13,
SERIAL_TX = PB_6,
SERIAL_RX = PB_7,
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
SERIAL_TX = D1,
SERIAL_RX = D0,
SERIAL_RTS = A1,
SERIAL_CTS = A0,
SERIAL_DCD = D5,
SERIAL_DSR = D8,
SERIAL_DTR = D4,
SERIAL_RI = D9,
USBTX = PB_6,
USBRX = PB_7,
RADIO_TX = PC_7,
RADIO_RX = PC_6,
RADIO_RTS = PB_10,
RADIO_CTS = PB_12,
RADIO_DCD = D5,
RADIO_DSR = D8,
RADIO_DTR = D4,
RADIO_RI = D9,
I2C_SCL = D15,
I2C_SDA = D14,
SPI_MOSI = PC_12,

6
libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PeripheralNames.h
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@ -46,9 +46,9 @@ typedef enum {
UART_6 = (int)USART6_BASE
} UARTName;
#define STDIO_UART_TX PA_2
#define STDIO_UART_RX PA_3
#define STDIO_UART UART_2
#define STDIO_UART_TX PA_9
#define STDIO_UART_RX PA_10
#define STDIO_UART UART_1
typedef enum {
SPI_1 = (int)SPI1_BASE,

109
libraries/mbed/targets/hal/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/PinNames.h
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@ -122,48 +122,79 @@ typedef enum {
PH_1 = 0x71,
// Generic signals namings
DOUT = PA_2,
DIN = PA_3,
AD0 = PB_1,
AD1 = PB_0,
AD2 = PA_5,
AD3 = PA_4,
AD4 = PA_7,
AD5 = PC_1,
AD6 = PA_1,
DIO0 = PB_1,
DIO1 = PB_0,
DIO2 = PA_5,
DIO3 = PA_4,
DIO4 = PA_7,
DIO5 = PC_1,
DIO6 = PA_1,
DO8 = PA_6,
DI8 = PA_11,
PWM0 = PA_8,
PWM1 = PC_9,
NCTS = PA_0,
RTS = PA_1,
NDTR = PA_11,
RSSI = PA_8,
SLEEPRQ = PA_11,
ON_SLEEP = PA_12,
ASSOCIATE = PC_1,
XBEE_DOUT = PA_2,
XBEE_DIN = PA_3,
XBEE_AD0 = PB_1,
XBEE_AD1 = PB_0,
XBEE_AD2 = PA_5,
XBEE_AD3 = PA_4,
XBEE_AD4 = PA_7,
XBEE_AD5 = PC_1,
XBEE_AD6 = PA_1,
XBEE_DIO0 = PB_1,
XBEE_DIO1 = PB_0,
XBEE_DIO2 = PA_5,
XBEE_DIO3 = PA_4,
XBEE_DIO4 = PA_7,
XBEE_DIO5 = PC_1,
XBEE_DIO6 = PA_1,
XBEE_DO8 = PA_6,
XBEE_DI8 = PA_11,
XBEE_PWM0 = PA_8,
XBEE_PWM1 = PC_9,
XBEE_CTS = PA_0,
XBEE_RTS = PA_1,
XBEE_DTR = PA_11,
XBEE_RSSI = PA_8,
XBEE_SLEEPRQ = PA_11,
XBEE_ON_SLEEP = PC_13,
XBEE_ASSOCIATE = PC_1,
XBEE_USB_RES = PA_12,
LED1 = PA_2,
LED2 = PA_2,
LED3 = PA_2,
LED4 = PA_2,
SERIAL_TX = PA_9,
SERIAL_RX = PA_10,
USBTX = PA_2,
USBRX = PA_3,
// needed for mbed to build tests
LED1 = PA_0,
// XBEE_DOUT/DIN, RS232 port on UDK board
SERIAL_TX = PA_2,
SERIAL_RX = PA_3,
// DB_TX/RX, USB port on UDK board
DB_TX = PA_9,
DB_RX = PA_10,
USBTX = PA_9,
USBRX = PA_10,
// Multiplexed with XBEE pins
I2C_SCL = PA_8,
I2C_SDA = PC_9,
SPI_MOSI = PA_7,
SPI_MISO = PA_6,
SPI_SCK = PA_5,
SPI_CS = PA_4,
SPI1_MOSI = PA_7,
SPI1_MISO = PA_6,
SPI1_SCK = PA_5,
SPI1_CS = PA_4,
// SPI flash
SPI3_MOSI = PC_12,
SPI3_MISO = PC_11,
SPI3_SCK = PC_10,
SPI3_CS = PC_6,
FLASH_HOLD = PC_7,
FLASH_WP = PC_8,
// LoRa
LORA_RESET = PC_0,
LORA_RXCTL = PC_2,
LORA_TXCTL = PC_3,
LORA_DIO0 = PB_5,
LORA_DIO1 = PB_6,
LORA_DIO2 = PB_7,
LORA_DIO3 = PB_8,
LORA_DIO4 = PB_9,
LORA_DIO5 = PB_10,
// LoRa/SPI2
LORA_NSS = PB_12,
LORA_SCK = PB_13,
LORA_MISO = PB_14,
LORA_MOSI = PB_15,
// Not connected
NC = (int)0xFFFFFFFF

BIN
workspace_tools/bootloaders/MTS_DRAGONFLY_F411RE/bootloader.bin Executable file
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Binary file not shown.

BIN
workspace_tools/bootloaders/MTS_MDOT_F411RE/bootloader.bin Executable file
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Binary file not shown.

8
workspace_tools/export/iar_mts_dragonfly_f411re.ewp.tmpl
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@ -593,11 +593,11 @@
</option>
<option>
<name>OCOutputOverride</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>OOCOutputFile</name>
<state>{{name}}.bin</state>
<state>application.bin</state>
</option>
<option>
<name>OOCCommandLineProducer</name>
@ -627,7 +627,7 @@
<archiveVersion>1</archiveVersion>
<data>
<prebuild></prebuild>
<postbuild></postbuild>
<postbuild>"$PROJ_DIR$\post-build.bat" "$TARGET_DIR$"</postbuild>
</data>
</settings>
<settings>
@ -711,7 +711,7 @@
</option>
<option>
<name>IlinkIcfOverride</name>
<state>0</state>
<state>1</state>
</option>
<option>
<name>IlinkIcfFile</name>

1
workspace_tools/paths.py
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@ -28,6 +28,7 @@ LIB_DIR = join(ROOT, "libraries")
TOOLS = join(ROOT, "workspace_tools")
TOOLS_DATA = join(TOOLS, "data")
TOOLS_BOOTLOADERS = join(TOOLS, "bootloaders")
# mbed libraries
MBED_BASE = join(LIB_DIR, "mbed")

69
workspace_tools/targets.py
View File

@ -29,8 +29,11 @@ CORE_LABELS = {
}
import os
import binascii
import struct
import shutil
from workspace_tools.patch import patch
from paths import TOOLS_BOOTLOADERS
class Target:
def __init__(self):
@ -702,19 +705,81 @@ class MTS_MDOT_F411RE(Target):
Target.__init__(self)
self.core = "Cortex-M4F"
self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE']
self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=96000000', 'USE_PLL_HSE_EXTC=0']
self.macros = ['HSE_VALUE=26000000', 'OS_CLOCK=96000000', 'USE_PLL_HSE_EXTC=0', 'VECT_TAB_OFFSET=0x00010000']
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
self.default_toolchain = "uARM"
def init_hooks(self, hook, toolchain_name):
if toolchain_name in ['GCC_ARM', 'ARM_STD', 'ARM_MICRO']:
hook.hook_add_binary("post", self.combine_bins)
# combine application binary with bootloader
# bootloader + padding to 64kB + application + md5sum (16 bytes)
@staticmethod
def combine_bins(t_self, resources, elf, binf):
loader = os.path.join(TOOLS_BOOTLOADERS, "MTS_MDOT_F411RE", "bootloader.bin")
target = binf + ".tmp"
if not os.path.exists(loader):
print "Can't find bootloader binary: " + loader
return
outbin = open(target, 'w+b')
part = open(loader, 'rb')
data = part.read()
outbin.write(data)
outbin.write('\xFF' * (64*1024 - len(data)))
part.close()
part = open(binf, 'rb')
data = part.read()
outbin.write(data)
part.close()
outbin.seek(0, 0)
data = outbin.read()
crc = struct.pack('<I', binascii.crc32(data) & 0xFFFFFFFF)
outbin.write(crc)
outbin.close()
os.remove(binf)
os.rename(target, binf)
class MTS_DRAGONFLY_F411RE(Target):
def __init__(self):
Target.__init__(self)
self.core = "Cortex-M4F"
self.extra_labels = ['STM', 'STM32F4', 'STM32F411RE']
self.macros = ['HSE_VALUE=26000000']
self.macros = ['HSE_VALUE=26000000', 'VECT_TAB_OFFSET=0x08010000']
self.supported_toolchains = ["ARM", "uARM", "GCC_ARM", "IAR"]
self.default_toolchain = "ARM"
def init_hooks(self, hook, toolchain_name):
if toolchain_name in ['GCC_ARM', 'ARM_STD', 'ARM_MICRO']:
hook.hook_add_binary("post", self.combine_bins)
# combine application binary with bootloader
# bootloader + padding to 64kB + application + md5sum (16 bytes)
@staticmethod
def combine_bins(t_self, resources, elf, binf):
loader = os.path.join(TOOLS_BOOTLOADERS, "MTS_DRAGONFLY_F411RE", "bootloader.bin")
target = binf + ".tmp"
if not os.path.exists(loader):
print "Can't find bootloader binary: " + loader
return
outbin = open(target, 'w+b')
part = open(loader, 'rb')
data = part.read()
outbin.write(data)
outbin.write('\xFF' * (64*1024 - len(data)))
part.close()
part = open(binf, 'rb')
data = part.read()
outbin.write(data)
part.close()
outbin.seek(0, 0)
data = outbin.read()
crc = struct.pack('<I', binascii.crc32(data) & 0xFFFFFFFF)
outbin.write(crc)
outbin.close()
os.remove(binf)
os.rename(target, binf)
class DISCO_F401VC(Target):
def __init__(self):
Target.__init__(self)