diff --git a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
index 1b8e784872..dd8a9a975e 100644
--- a/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
+++ b/targets/TARGET_STM/TARGET_STM32WL/CMakeLists.txt
@@ -16,6 +16,7 @@ target_sources(mbed-stm32wl
         pwmout_device.c
         serial_device.c
         spi_api.c
+        system_clock.c
 )
 
 target_include_directories(mbed-stm32wl
diff --git a/targets/TARGET_STM/TARGET_STM32WL/system_clock.c b/targets/TARGET_STM/TARGET_STM32WL/system_clock.c
new file mode 100644
index 0000000000..70d3920250
--- /dev/null
+++ b/targets/TARGET_STM/TARGET_STM32WL/system_clock.c
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * SPDX-License-Identifier: BSD-3-Clause
+ ******************************************************************************
+ *
+ * Copyright (c) 2021 STMicroelectronics.
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ *                        opensource.org/licenses/BSD-3-Clause
+ *
+ ******************************************************************************
+*/
+
+/**
+  * This file configures the system clock as follows:
+  *-----------------------------------------------------------------------------
+  * System clock source | HSE (external 32 MHz clock)
+  *-----------------------------------------------------------------------------
+  * SYSCLK(MHz)         | 48
+  * AHBCLK (MHz)        | 48
+  * APB1CLK (MHz)       | 48
+  * APB2CLK (MHz)       | 48
+  * USB capable         | NO
+  *-----------------------------------------------------------------------------
+**/
+
+#include "mbed_assert.h"
+#include "objects.h"
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, AHB/APBx prescalers
+  * @note   This function should be called only once the RCC clock configuration
+  *         is reset to the default reset state (done in SystemInit() function).
+  * @param  None
+  * @retval None
+  */
+
+MBED_WEAK void SetSysClock(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct = {0};
+    RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
+
+    /** Configure the main internal regulator output voltage
+    */
+    __HAL_RCC_PWR_CLK_ENABLE();
+    __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
+    /** Initializes the CPU, AHB and APB busses clocks
+    */
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI;
+    RCC_OscInitStruct.MSIState = RCC_MSI_ON;
+    RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
+    RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
+    RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
+    MBED_ASSERT(HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK);
+    /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers
+    */
+    RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3 | RCC_CLOCKTYPE_HCLK
+                                  | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1
+                                  | RCC_CLOCKTYPE_PCLK2;
+    RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI;
+    RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+    RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+    RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1;
+    MBED_ASSERT(HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) == HAL_OK);
+    /* Peripheral clock enable */
+}