mirror of https://github.com/ARMmbed/mbed-os.git
Merge branch '1549' of https://github.com/Kazu-zamasu/mbed into Kazu-zamasu-1549
0xc0170
commit
cf3b3d5a87
|
|
@ -0,0 +1,235 @@
|
|||
/*Based on following file*/
|
||||
/*
|
||||
* GENERATED FILE - DO NOT EDIT
|
||||
* (c) Code Red Technologies Ltd, 2008-13
|
||||
* (c) NXP Semiconductors 2013-2014
|
||||
* Generated linker script file for LPC11U68
|
||||
* Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
|
||||
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
|
||||
Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
|
||||
Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
|
||||
Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
|
||||
|
||||
|
||||
}
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__top_MFlash256 = 0x0 + 0x40000;
|
||||
__top_Ram0_32 = 0x10000000 + 0x8000;
|
||||
__top_Ram1_2 = 0x20000000 + 0x800;
|
||||
__top_Ram2USB_2 = 0x20004000 + 0x800;
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
__vectors_start__ = ABSOLUTE(.) ;
|
||||
KEEP(*(.isr_vector))
|
||||
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data));
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM2));
|
||||
LONG( ADDR(.data_RAM2));
|
||||
LONG( SIZEOF(.data_RAM2));
|
||||
LONG(LOADADDR(.data_RAM3));
|
||||
LONG( ADDR(.data_RAM3));
|
||||
LONG( SIZEOF(.data_RAM3));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM2));
|
||||
LONG( SIZEOF(.bss_RAM2));
|
||||
LONG( ADDR(.bss_RAM3));
|
||||
LONG( SIZEOF(.bss_RAM3));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
*(.text*)
|
||||
*(.rodata .rodata.*)
|
||||
. = ALIGN(4);
|
||||
|
||||
/* C++ constructors etc */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
KEEP(*(.fini));
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
} > MFlash256
|
||||
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > MFlash256
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > MFlash256
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
/* possible MTB section for Ram1_2 */
|
||||
.mtb_buffer_RAM2 (NOLOAD) :
|
||||
{
|
||||
KEEP(*(.mtb.$RAM2*))
|
||||
KEEP(*(.mtb.$RAM1_2*))
|
||||
} > Ram1_2
|
||||
|
||||
/* DATA section for Ram1_2 */
|
||||
.data_RAM2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.ramfunc.$RAM2)
|
||||
*(.ramfunc.$Ram1_2)
|
||||
*(.data.$RAM2*)
|
||||
*(.data.$Ram1_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_2 AT>MFlash256
|
||||
/* possible MTB section for Ram2USB_2 */
|
||||
.mtb_buffer_RAM3 (NOLOAD) :
|
||||
{
|
||||
KEEP(*(.mtb.$RAM3*))
|
||||
KEEP(*(.mtb.$RAM2USB_2*))
|
||||
} > Ram2USB_2
|
||||
|
||||
/* DATA section for Ram2USB_2 */
|
||||
.data_RAM3 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$Ram2USB_2)
|
||||
*(.data.$RAM3*)
|
||||
*(.data.$Ram2USB_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2USB_2 AT>MFlash256
|
||||
|
||||
/* MAIN DATA SECTION */
|
||||
|
||||
/* Default MTB section */
|
||||
.mtb_buffer_default (NOLOAD) :
|
||||
{
|
||||
KEEP(*(.mtb*))
|
||||
} > Ram0_32
|
||||
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > Ram0_32
|
||||
|
||||
|
||||
/* Main DATA section (Ram0_32) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
} > Ram0_32 AT>MFlash256
|
||||
|
||||
/* BSS section for Ram1_2 */
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM2*)
|
||||
*(.bss.$Ram1_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_2
|
||||
/* BSS section for Ram2USB_2 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM3*)
|
||||
*(.bss.$Ram2USB_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2USB_2
|
||||
|
||||
/* MAIN BSS SECTION */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(end = .);
|
||||
__end__ = .;
|
||||
} > Ram0_32
|
||||
|
||||
/* NOINIT section for Ram1_2 */
|
||||
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM2*)
|
||||
*(.noinit.$Ram1_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_2
|
||||
/* NOINIT section for Ram2USB_2 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM3*)
|
||||
*(.noinit.$Ram2USB_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2USB_2
|
||||
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > Ram0_32
|
||||
|
||||
PROVIDE(_pvHeapStart = .);
|
||||
PROVIDE(_vStackTop = __top_Ram0_32 - 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,181 @@
|
|||
extern "C" {
|
||||
|
||||
#include "LPC11U6x.h"
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
|
||||
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern int main(void);
|
||||
extern void _vStackTop(void);
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
|
||||
void ResetISR(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void SVC_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
|
||||
void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
// Core Level - CM0
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// Chip Level - LPC11U68
|
||||
PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
|
||||
PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
|
||||
PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
|
||||
PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
|
||||
PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
|
||||
PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
|
||||
PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
|
||||
PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
|
||||
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
|
||||
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
|
||||
I2C1_IRQHandler, // 10 - I2C1
|
||||
USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
|
||||
USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
|
||||
SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
|
||||
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
|
||||
I2C0_IRQHandler, // 15 - I2C0
|
||||
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
|
||||
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
|
||||
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
|
||||
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
|
||||
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
|
||||
USART0_IRQHandler, // 21 - USART0
|
||||
USB_IRQHandler, // 22 - USB IRQ
|
||||
USB_FIQHandler, // 23 - USB FIQ
|
||||
ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
|
||||
RTC_IRQHandler, // 25 - Real Time CLock interrpt
|
||||
BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
|
||||
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
|
||||
DMA_IRQHandler, // 28 - DMA interrupt
|
||||
ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
|
||||
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
|
||||
0, // 31 - Reserved
|
||||
};
|
||||
/* End Vector */
|
||||
|
||||
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
|
||||
}
|
||||
|
||||
|
||||
/* Reset entry point*/
|
||||
extern "C" void software_init_hook(void) __attribute__((weak));
|
||||
|
||||
AFTER_VECTORS void ResetISR(void) {
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
SystemInit();
|
||||
if (software_init_hook)
|
||||
software_init_hook();
|
||||
else {
|
||||
__libc_init_array();
|
||||
main();
|
||||
}
|
||||
while (1) {;}
|
||||
}
|
||||
|
||||
AFTER_VECTORS void NMI_Handler (void) {}
|
||||
AFTER_VECTORS void HardFault_Handler (void) {}
|
||||
AFTER_VECTORS void MemManage_Handler (void) {}
|
||||
AFTER_VECTORS void BusFault_Handler (void) {}
|
||||
AFTER_VECTORS void UsageFault_Handler(void) {}
|
||||
AFTER_VECTORS void SVC_Handler (void) {}
|
||||
AFTER_VECTORS void DebugMon_Handler (void) {}
|
||||
AFTER_VECTORS void PendSV_Handler (void) {}
|
||||
AFTER_VECTORS void SysTick_Handler (void) {}
|
||||
AFTER_VECTORS void IntDefaultHandler (void) {}
|
||||
|
||||
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
|
||||
}
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
void *operator new(size_t size) {return malloc(size);}
|
||||
void *operator new[](size_t size){return malloc(size);}
|
||||
|
||||
void operator delete(void *p) {free(p);}
|
||||
void operator delete[](void *p) {free(p);}
|
||||
|
|
@ -0,0 +1,237 @@
|
|||
/*Based on following file*/
|
||||
/*
|
||||
* GENERATED FILE - DO NOT EDIT
|
||||
* (c) Code Red Technologies Ltd, 2008-13
|
||||
* (c) NXP Semiconductors 2013-2014
|
||||
* Generated linker script file for LPC11U68
|
||||
* Created from LibIncTemplate.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
|
||||
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Sat Jun 14 15:26:54 JST 2014
|
||||
*/
|
||||
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
|
||||
Ram0_32 (rwx) : ORIGIN = 0x10000000+0x100, LENGTH = 0x8000-0x100 /* 32K bytes */
|
||||
Ram1_2 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x800 /* 2K bytes */
|
||||
Ram2USB_2 (rwx) : ORIGIN = 0x20004000, LENGTH = 0x800 /* 2K bytes */
|
||||
|
||||
|
||||
}
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__top_MFlash256 = 0x0 + 0x40000;
|
||||
__top_Ram0_32 = 0x10000000+0x100 + 0x8000-0x100;
|
||||
__top_Ram1_2 = 0x20000000 + 0x800;
|
||||
__top_Ram2USB_2 = 0x20004000 + 0x800;
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
KEEP(*(.isr_vector))
|
||||
*(.text.ResetISR)
|
||||
*(.text.SystemInit)
|
||||
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data));
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM2));
|
||||
LONG( ADDR(.data_RAM2));
|
||||
LONG( SIZEOF(.data_RAM2));
|
||||
LONG(LOADADDR(.data_RAM3));
|
||||
LONG( ADDR(.data_RAM3));
|
||||
LONG( SIZEOF(.data_RAM3));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM2));
|
||||
LONG( SIZEOF(.bss_RAM2));
|
||||
LONG( ADDR(.bss_RAM3));
|
||||
LONG( SIZEOF(.bss_RAM3));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
*(.text*)
|
||||
*(.rodata .rodata.*)
|
||||
. = ALIGN(4);
|
||||
|
||||
/* C++ constructors etc */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
KEEP(*(.fini));
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
} > MFlash256
|
||||
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > MFlash256
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > MFlash256
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
/* possible MTB section for Ram1_2 */
|
||||
.mtb_buffer_RAM2 (NOLOAD) :
|
||||
{
|
||||
KEEP(*(.mtb.$RAM2*))
|
||||
KEEP(*(.mtb.$RAM1_2*))
|
||||
} > Ram1_2
|
||||
|
||||
/* DATA section for Ram1_2 */
|
||||
.data_RAM2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.ramfunc.$RAM2)
|
||||
*(.ramfunc.$Ram1_2)
|
||||
*(.data.$RAM2*)
|
||||
*(.data.$Ram1_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_2 AT>MFlash256
|
||||
/* possible MTB section for Ram2USB_2 */
|
||||
.mtb_buffer_RAM3 (NOLOAD) :
|
||||
{
|
||||
KEEP(*(.mtb.$RAM3*))
|
||||
KEEP(*(.mtb.$RAM2USB_2*))
|
||||
} > Ram2USB_2
|
||||
|
||||
/* DATA section for Ram2USB_2 */
|
||||
.data_RAM3 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$Ram2USB_2)
|
||||
*(.data.$RAM3*)
|
||||
*(.data.$Ram2USB_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2USB_2 AT>MFlash256
|
||||
|
||||
/* MAIN DATA SECTION */
|
||||
|
||||
/* Default MTB section */
|
||||
.mtb_buffer_default (NOLOAD) :
|
||||
{
|
||||
KEEP(*(.mtb*))
|
||||
} > Ram0_32
|
||||
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > Ram0_32
|
||||
|
||||
|
||||
/* Main DATA section (Ram0_32) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
} > Ram0_32 AT>MFlash256
|
||||
|
||||
/* BSS section for Ram1_2 */
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM2*)
|
||||
*(.bss.$Ram1_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_2
|
||||
/* BSS section for Ram2USB_2 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM3*)
|
||||
*(.bss.$Ram2USB_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2USB_2
|
||||
|
||||
/* MAIN BSS SECTION */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(end = .);
|
||||
__end__ = .;
|
||||
} > Ram0_32
|
||||
|
||||
/* NOINIT section for Ram1_2 */
|
||||
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM2*)
|
||||
*(.noinit.$Ram1_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_2
|
||||
/* NOINIT section for Ram2USB_2 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM3*)
|
||||
*(.noinit.$Ram2USB_2*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2USB_2
|
||||
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > Ram0_32
|
||||
|
||||
PROVIDE(_pvHeapStart = .);
|
||||
PROVIDE(_vStackTop = __top_Ram0_32 - 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
//*****************************************************************************
|
||||
// aeabi_romdiv_patch.s
|
||||
// - Provides "patch" versions of the aeabi integer divide functions to
|
||||
// replace the standard ones pulled in from the C library, which vector
|
||||
// integer divides onto the rom division functions contained in
|
||||
// specific NXP MCUs such as LPC11Uxx and LPC12xx.
|
||||
// - Note that this patching will only occur if "__USE_ROMDIVIDE" is
|
||||
// defined for the project build for both the compiler and assembler.
|
||||
//*****************************************************************************
|
||||
//
|
||||
// Copyright(C) NXP Semiconductors, 2013
|
||||
// All rights reserved.
|
||||
//
|
||||
// Software that is described herein is for illustrative purposes only
|
||||
// which provides customers with programming information regarding the
|
||||
// LPC products. This software is supplied "AS IS" without any warranties of
|
||||
// any kind, and NXP Semiconductors and its licensor disclaim any and
|
||||
// all warranties, express or implied, including all implied warranties of
|
||||
// merchantability, fitness for a particular purpose and non-infringement of
|
||||
// intellectual property rights. NXP Semiconductors assumes no responsibility
|
||||
// or liability for the use of the software, conveys no license or rights under any
|
||||
// patent, copyright, mask work right, or any other intellectual property rights in
|
||||
// or to any products. NXP Semiconductors reserves the right to make changes
|
||||
// in the software without notification. NXP Semiconductors also makes no
|
||||
// representation or warranty that such application will be suitable for the
|
||||
// specified use without further testing or modification.
|
||||
//
|
||||
// Permission to use, copy, modify, and distribute this software and its
|
||||
// documentation is hereby granted, under NXP Semiconductors' and its
|
||||
// licensor's relevant copyrights in the software, without fee, provided that it
|
||||
// is used in conjunction with NXP Semiconductors microcontrollers. This
|
||||
// copyright, permission, and disclaimer notice must appear in all copies of
|
||||
// this code.
|
||||
//*****************************************************************************
|
||||
#if defined(__USE_ROMDIVIDE)
|
||||
|
||||
// Note that the romdivide "divmod" functions are not actually called from
|
||||
// the below code, as these functions are actually just wrappers to the
|
||||
// main romdivide "div" functions which push the quotient and remainder onto
|
||||
// the stack, so as to be compatible with the way that C returns structures.
|
||||
//
|
||||
// This is not needed for the aeabi "divmod" functions, as the compiler
|
||||
// automatically generates code that handles the return values being passed
|
||||
// back in registers when it generates inline calls to __aeabi_idivmod and
|
||||
// __aeabi_uidivmod routines.
|
||||
|
||||
.syntax unified
|
||||
.text
|
||||
|
||||
// ========= __aeabi_idiv & __aeabi_idivmod =========
|
||||
.align 2
|
||||
.section .text.__aeabi_idiv
|
||||
|
||||
.global __aeabi_idiv
|
||||
.set __aeabi_idivmod, __aeabi_idiv // make __aeabi_uidivmod an alias
|
||||
.global __aeabi_idivmod
|
||||
.global pDivRom_idiv // pointer to the romdivide 'idiv' functione
|
||||
.func
|
||||
.thumb_func
|
||||
.type __aeabi_idiv, %function
|
||||
|
||||
__aeabi_idiv:
|
||||
push {r4, lr}
|
||||
ldr r3, =pDivRom_idiv
|
||||
ldr r3, [r3, #0] // Load address of function
|
||||
blx r3 // Call divide function
|
||||
pop {r4, pc}
|
||||
|
||||
.endfunc
|
||||
|
||||
// ======== __aeabi_uidiv & __aeabi_uidivmod ========
|
||||
.align 2
|
||||
|
||||
.section .text.__aeabi_uidiv
|
||||
|
||||
.global __aeabi_uidiv
|
||||
.set __aeabi_uidivmod, __aeabi_uidiv // make __aeabi_uidivmod an alias
|
||||
.global __aeabi_uidivmod
|
||||
.global pDivRom_uidiv // pointer to the romdivide 'uidiv' function
|
||||
.func
|
||||
.thumb_func
|
||||
.type __aeabi_uidiv, %function
|
||||
|
||||
__aeabi_uidiv:
|
||||
push {r4, lr}
|
||||
ldr r3, =pDivRom_uidiv
|
||||
ldr r3, [r3, #0] // Load address of function
|
||||
blx r3 // Call divide function
|
||||
pop {r4, pc}
|
||||
|
||||
.endfunc
|
||||
|
||||
#endif // (__USE_ROMDIVIDE)
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
//*****************************************************************************
|
||||
// +--+
|
||||
// | ++----+
|
||||
// +-++ |
|
||||
// | |
|
||||
// +-+--+ |
|
||||
// | +--+--+
|
||||
// +----+ Copyright (c) 2013 Code Red Technologies Ltd.
|
||||
//
|
||||
// mtb.c
|
||||
//
|
||||
// Optionally defines an array to be used as a buffer for Micro Trace
|
||||
// Buffer (MTB) instruction trace on Cortex-M0+ parts
|
||||
//
|
||||
// Version : 130502
|
||||
//
|
||||
// Software License Agreement
|
||||
//
|
||||
// The software is owned by Code Red Technologies and/or its suppliers, and is
|
||||
// protected under applicable copyright laws. All rights are reserved. Any
|
||||
// use in violation of the foregoing restrictions may subject the user to criminal
|
||||
// sanctions under applicable laws, as well as to civil liability for the breach
|
||||
// of the terms and conditions of this license.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
|
||||
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
|
||||
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
|
||||
// USE OF THIS SOFTWARE FOR COMMERCIAL DEVELOPMENT AND/OR EDUCATION IS SUBJECT
|
||||
// TO A CURRENT END USER LICENSE AGREEMENT (COMMERCIAL OR EDUCATIONAL) WITH
|
||||
// CODE RED TECHNOLOGIES LTD.
|
||||
//
|
||||
//*****************************************************************************
|
||||
|
||||
/*******************************************************************
|
||||
* Symbols controlling behavior of this code...
|
||||
*
|
||||
* __MTB_DISABLE
|
||||
* If this symbol is defined, then the buffer array for the MTB
|
||||
* will not be created.
|
||||
*
|
||||
* __MTB_BUFFER_SIZE
|
||||
* Symbol specifying the sizer of the buffer array for the MTB.
|
||||
* This must be a power of 2 in size, and fit into the available
|
||||
* RAM. The MTB buffer will also be aligned to its 'size'
|
||||
* boundary and be placed at the start of a RAM bank (which
|
||||
* should ensure minimal or zero padding due to alignment).
|
||||
*
|
||||
* __MTB_RAM_BANK
|
||||
* Allows MTB Buffer to be placed into specific RAM bank. When
|
||||
* this is not defined, the "default" (first if there are
|
||||
* several) RAM bank is used.
|
||||
*******************************************************************/
|
||||
|
||||
// Ignore with none Code Red tools
|
||||
#if defined (__CODE_RED)
|
||||
|
||||
// Allow MTB to be removed by setting a define (via command line)
|
||||
#if !defined (__MTB_DISABLE)
|
||||
|
||||
// Allow for MTB buffer size being set by define set via command line
|
||||
// Otherwise provide small default buffer
|
||||
#if !defined (__MTB_BUFFER_SIZE)
|
||||
#define __MTB_BUFFER_SIZE 128
|
||||
#endif
|
||||
|
||||
// Check that buffer size requested is >0 bytes in size
|
||||
#if (__MTB_BUFFER_SIZE > 0)
|
||||
// Pull in MTB related macros
|
||||
#include <cr_mtb_buffer.h>
|
||||
|
||||
// Check if MYTB buffer is to be placed in specific RAM bank
|
||||
#if defined(__MTB_RAM_BANK)
|
||||
// Place MTB buffer into explicit bank of RAM
|
||||
__CR_MTB_BUFFER_EXT(__MTB_BUFFER_SIZE,__MTB_RAM_BANK);
|
||||
#else
|
||||
// Place MTB buffer into 'default' bank of RAM
|
||||
__CR_MTB_BUFFER(__MTB_BUFFER_SIZE);
|
||||
|
||||
#endif // defined(__MTB_RAM_BANK)
|
||||
|
||||
#endif // (__MTB_BUFFER_SIZE > 0)
|
||||
|
||||
#endif // !defined (__MTB_DISABLE)
|
||||
|
||||
#endif // defined (__CODE_RED)
|
||||
|
|
@ -0,0 +1,201 @@
|
|||
extern "C" {
|
||||
|
||||
#include "LPC11U6x.h"
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
|
||||
|
||||
// Patch the AEABI integer divide functions to use MCU's romdivide library
|
||||
#ifdef __USE_ROMDIVIDE
|
||||
// Location in memory that holds the address of the ROM Driver table
|
||||
#define PTR_ROM_DRIVER_TABLE ((unsigned int *)(0x1FFF1FF8))
|
||||
// Variables to store addresses of idiv and udiv functions within MCU ROM
|
||||
unsigned int *pDivRom_idiv;
|
||||
unsigned int *pDivRom_uidiv;
|
||||
#endif
|
||||
|
||||
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern int main(void);
|
||||
extern void _vStackTop(void);
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
|
||||
void ResetISR(void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void SVC_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
|
||||
void PIN_INT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT2_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT5_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT6_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT7_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void GINT0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void GINT1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void I2C1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USART1_4_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USART2_3_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SCT0_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SSP1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void I2C0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER16_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER16_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER32_0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void TIMER32_1_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void SSP0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USART0_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USB_FIQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void ADCA_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void RTC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void BOD_WDT_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void FMC_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void DMA_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void ADCB_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
void USBWakeup_IRQHandler (void) ALIAS(IntDefaultHandler);
|
||||
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
// Core Level - CM0
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// Chip Level - LPC11U68
|
||||
PIN_INT0_IRQHandler, // 0 - GPIO pin interrupt 0
|
||||
PIN_INT1_IRQHandler, // 1 - GPIO pin interrupt 1
|
||||
PIN_INT2_IRQHandler, // 2 - GPIO pin interrupt 2
|
||||
PIN_INT3_IRQHandler, // 3 - GPIO pin interrupt 3
|
||||
PIN_INT4_IRQHandler, // 4 - GPIO pin interrupt 4
|
||||
PIN_INT5_IRQHandler, // 5 - GPIO pin interrupt 5
|
||||
PIN_INT6_IRQHandler, // 6 - GPIO pin interrupt 6
|
||||
PIN_INT7_IRQHandler, // 7 - GPIO pin interrupt 7
|
||||
GINT0_IRQHandler, // 8 - GPIO GROUP0 interrupt
|
||||
GINT1_IRQHandler, // 9 - GPIO GROUP1 interrupt
|
||||
I2C1_IRQHandler, // 10 - I2C1
|
||||
USART1_4_IRQHandler, // 11 - combined USART1 & 4 interrupt
|
||||
USART2_3_IRQHandler, // 12 - combined USART2 & 3 interrupt
|
||||
SCT0_1_IRQHandler, // 13 - combined SCT0 and 1 interrupt
|
||||
SSP1_IRQHandler, // 14 - SPI/SSP1 Interrupt
|
||||
I2C0_IRQHandler, // 15 - I2C0
|
||||
TIMER16_0_IRQHandler, // 16 - CT16B0 (16-bit Timer 0)
|
||||
TIMER16_1_IRQHandler, // 17 - CT16B1 (16-bit Timer 1)
|
||||
TIMER32_0_IRQHandler, // 18 - CT32B0 (32-bit Timer 0)
|
||||
TIMER32_1_IRQHandler, // 19 - CT32B1 (32-bit Timer 1)
|
||||
SSP0_IRQHandler, // 20 - SPI/SSP0 Interrupt
|
||||
USART0_IRQHandler, // 21 - USART0
|
||||
USB_IRQHandler, // 22 - USB IRQ
|
||||
USB_FIQHandler, // 23 - USB FIQ
|
||||
ADCA_IRQHandler, // 24 - ADC A(A/D Converter)
|
||||
RTC_IRQHandler, // 25 - Real Time CLock interrpt
|
||||
BOD_WDT_IRQHandler, // 25 - Combined Brownout/Watchdog interrupt
|
||||
FMC_IRQHandler, // 27 - IP2111 Flash Memory Controller
|
||||
DMA_IRQHandler, // 28 - DMA interrupt
|
||||
ADCB_IRQHandler, // 24 - ADC B (A/D Converter)
|
||||
USBWakeup_IRQHandler, // 30 - USB wake-up interrupt
|
||||
0, // 31 - Reserved
|
||||
};
|
||||
/* End Vector */
|
||||
|
||||
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
|
||||
}
|
||||
|
||||
|
||||
/* Reset entry point*/
|
||||
extern "C" void software_init_hook(void) __attribute__((weak));
|
||||
|
||||
AFTER_VECTORS void ResetISR(void) {
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
// Patch the AEABI integer divide functions to use MCU's romdivide library
|
||||
#ifdef __USE_ROMDIVIDE
|
||||
// Get address of Integer division routines function table in ROM
|
||||
unsigned int *div_ptr = (unsigned int *)((unsigned int *)*(PTR_ROM_DRIVER_TABLE))[4];
|
||||
// Get addresses of integer divide routines in ROM
|
||||
// These address are then used by the code in aeabi_romdiv_patch.s
|
||||
pDivRom_idiv = (unsigned int *)div_ptr[0];
|
||||
pDivRom_uidiv = (unsigned int *)div_ptr[1];
|
||||
#endif
|
||||
|
||||
|
||||
SystemInit();
|
||||
if (software_init_hook)
|
||||
software_init_hook();
|
||||
else {
|
||||
__libc_init_array();
|
||||
main();
|
||||
}
|
||||
while (1) {;}
|
||||
}
|
||||
|
||||
AFTER_VECTORS void NMI_Handler (void) {}
|
||||
AFTER_VECTORS void HardFault_Handler (void) {}
|
||||
AFTER_VECTORS void MemManage_Handler (void) {}
|
||||
AFTER_VECTORS void BusFault_Handler (void) {}
|
||||
AFTER_VECTORS void UsageFault_Handler(void) {}
|
||||
AFTER_VECTORS void SVC_Handler (void) {}
|
||||
AFTER_VECTORS void DebugMon_Handler (void) {}
|
||||
AFTER_VECTORS void PendSV_Handler (void) {}
|
||||
AFTER_VECTORS void SysTick_Handler (void) {}
|
||||
AFTER_VECTORS void IntDefaultHandler (void) {}
|
||||
|
||||
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
|
||||
}
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
void *operator new(size_t size) {return malloc(size);}
|
||||
void *operator new[](size_t size){return malloc(size);}
|
||||
|
||||
void operator delete(void *p) {free(p);}
|
||||
void operator delete[](void *p) {free(p);}
|
||||
|
|
@ -0,0 +1,214 @@
|
|||
/*Based on following file*/
|
||||
/*
|
||||
* GENERATED FILE - DO NOT EDIT
|
||||
* (c) Code Red Technologies Ltd, 2008-13
|
||||
* (c) NXP Semiconductors 2013-2014
|
||||
* Generated linker script file for LPC1549
|
||||
* Created from generic_c.ld (LPCXpresso v7.2 (0 [Build 153] [2014-05-19] ))
|
||||
* By LPCXpresso v7.2.0 [Build 153] [2014-05-19] on Tue Jun 10 00:20:53 JST 2014
|
||||
*/
|
||||
|
||||
GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* Define each memory region */
|
||||
MFlash256 (rx) : ORIGIN = 0x0, LENGTH = 0x40000 /* 256K bytes */
|
||||
Ram0_16 (rwx) : ORIGIN = 0x2000000+0x100, LENGTH = 0x4000-0x100 /* 16K bytes */
|
||||
Ram1_16 (rwx) : ORIGIN = 0x2004000, LENGTH = 0x4000 /* 16K bytes */
|
||||
Ram2_4 (rwx) : ORIGIN = 0x2008000, LENGTH = 0x1000 /* 4K bytes */
|
||||
|
||||
}
|
||||
/* Define a symbol for the top of each memory region */
|
||||
__top_MFlash256 = 0x0 + 0x40000;
|
||||
__top_Ram0_16 = 0x2000000 + 0x4000;
|
||||
__top_Ram1_16 = 0x2004000 + 0x4000;
|
||||
__top_Ram2_4 = 0x2008000 + 0x1000;
|
||||
|
||||
ENTRY(ResetISR)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
/* MAIN TEXT SECTION */
|
||||
.text : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
KEEP(*(.isr_vector))
|
||||
|
||||
/* Global Section Table */
|
||||
. = ALIGN(4) ;
|
||||
__section_table_start = .;
|
||||
__data_section_table = .;
|
||||
LONG(LOADADDR(.data));
|
||||
LONG( ADDR(.data));
|
||||
LONG( SIZEOF(.data));
|
||||
LONG(LOADADDR(.data_RAM2));
|
||||
LONG( ADDR(.data_RAM2));
|
||||
LONG( SIZEOF(.data_RAM2));
|
||||
LONG(LOADADDR(.data_RAM3));
|
||||
LONG( ADDR(.data_RAM3));
|
||||
LONG( SIZEOF(.data_RAM3));
|
||||
__data_section_table_end = .;
|
||||
__bss_section_table = .;
|
||||
LONG( ADDR(.bss));
|
||||
LONG( SIZEOF(.bss));
|
||||
LONG( ADDR(.bss_RAM2));
|
||||
LONG( SIZEOF(.bss_RAM2));
|
||||
LONG( ADDR(.bss_RAM3));
|
||||
LONG( SIZEOF(.bss_RAM3));
|
||||
__bss_section_table_end = .;
|
||||
__section_table_end = . ;
|
||||
/* End of Global Section Table */
|
||||
|
||||
|
||||
*(.after_vectors*)
|
||||
|
||||
*(.text*)
|
||||
*(.rodata .rodata.*)
|
||||
. = ALIGN(4);
|
||||
|
||||
/* C++ constructors etc */
|
||||
. = ALIGN(4);
|
||||
KEEP(*(.init))
|
||||
|
||||
. = ALIGN(4);
|
||||
__preinit_array_start = .;
|
||||
KEEP (*(.preinit_array))
|
||||
__preinit_array_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__init_array_start = .;
|
||||
KEEP (*(SORT(.init_array.*)))
|
||||
KEEP (*(.init_array))
|
||||
__init_array_end = .;
|
||||
|
||||
KEEP(*(.fini));
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*crtend.o(.ctors))
|
||||
|
||||
. = ALIGN(0x4);
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*crtend.o(.dtors))
|
||||
} > MFlash256
|
||||
|
||||
/*
|
||||
* for exception handling/unwind - some Newlib functions (in common
|
||||
* with C++ and STDC++) use this.
|
||||
*/
|
||||
.ARM.extab : ALIGN(4)
|
||||
{
|
||||
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||
} > MFlash256
|
||||
__exidx_start = .;
|
||||
|
||||
.ARM.exidx : ALIGN(4)
|
||||
{
|
||||
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||
} > MFlash256
|
||||
__exidx_end = .;
|
||||
|
||||
_etext = .;
|
||||
|
||||
/* DATA section for Ram1_16 */
|
||||
.data_RAM2 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.ramfunc.$RAM2)
|
||||
*(.ramfunc.$Ram1_16)
|
||||
*(.data.$RAM2*)
|
||||
*(.data.$Ram1_16*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_16 AT>MFlash256
|
||||
|
||||
/* DATA section for Ram2_4 */
|
||||
.data_RAM3 : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
*(.ramfunc.$RAM3)
|
||||
*(.ramfunc.$Ram2_4)
|
||||
*(.data.$RAM3*)
|
||||
*(.data.$Ram2_4*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2_4 AT>MFlash256
|
||||
|
||||
/* MAIN DATA SECTION */
|
||||
.uninit_RESERVED : ALIGN(4)
|
||||
{
|
||||
KEEP(*(.bss.$RESERVED*))
|
||||
. = ALIGN(4) ;
|
||||
_end_uninit_RESERVED = .;
|
||||
} > Ram0_16
|
||||
|
||||
/* Main DATA section (Ram0_16) */
|
||||
.data : ALIGN(4)
|
||||
{
|
||||
FILL(0xff)
|
||||
_data = . ;
|
||||
*(vtable)
|
||||
*(.ramfunc*)
|
||||
*(.data*)
|
||||
. = ALIGN(4) ;
|
||||
_edata = . ;
|
||||
} > Ram0_16 AT>MFlash256
|
||||
|
||||
/* BSS section for Ram1_16 */
|
||||
.bss_RAM2 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM2*)
|
||||
*(.bss.$Ram1_16*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_16
|
||||
/* BSS section for Ram2_4 */
|
||||
.bss_RAM3 : ALIGN(4)
|
||||
{
|
||||
*(.bss.$RAM3*)
|
||||
*(.bss.$Ram2_4*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2_4
|
||||
|
||||
/* MAIN BSS SECTION */
|
||||
.bss : ALIGN(4)
|
||||
{
|
||||
_bss = .;
|
||||
*(.bss*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4) ;
|
||||
_ebss = .;
|
||||
PROVIDE(end = .);
|
||||
__end__ = .;
|
||||
} > Ram0_16
|
||||
|
||||
/* NOINIT section for Ram1_16 */
|
||||
.noinit_RAM2 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM2*)
|
||||
*(.noinit.$Ram1_16*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram1_16
|
||||
/* NOINIT section for Ram2_4 */
|
||||
.noinit_RAM3 (NOLOAD) : ALIGN(4)
|
||||
{
|
||||
*(.noinit.$RAM3*)
|
||||
*(.noinit.$Ram2_4*)
|
||||
. = ALIGN(4) ;
|
||||
} > Ram2_4
|
||||
|
||||
/* DEFAULT NOINIT SECTION */
|
||||
.noinit (NOLOAD): ALIGN(4)
|
||||
{
|
||||
_noinit = .;
|
||||
*(.noinit*)
|
||||
. = ALIGN(4) ;
|
||||
_end_noinit = .;
|
||||
} > Ram0_16
|
||||
|
||||
PROVIDE(_pvHeapStart = .);
|
||||
PROVIDE(_vStackTop = __top_Ram0_16 - 0);
|
||||
}
|
||||
|
|
@ -0,0 +1,219 @@
|
|||
extern "C" {
|
||||
|
||||
#include "LPC15xx.h"
|
||||
|
||||
#define WEAK __attribute__ ((weak))
|
||||
#define ALIAS(f) __attribute__ ((weak, alias (#f)))
|
||||
#define AFTER_VECTORS __attribute__ ((section(".after_vectors")))void ResetISR(void);
|
||||
|
||||
extern unsigned int __data_section_table;
|
||||
extern unsigned int __data_section_table_end;
|
||||
extern unsigned int __bss_section_table;
|
||||
extern unsigned int __bss_section_table_end;
|
||||
|
||||
|
||||
extern void __libc_init_array(void);
|
||||
extern int main(void);
|
||||
extern void _vStackTop(void);
|
||||
extern void (* const g_pfnVectors[])(void);
|
||||
|
||||
void ResetISR (void);
|
||||
WEAK void NMI_Handler(void);
|
||||
WEAK void HardFault_Handler(void);
|
||||
WEAK void MemManage_Handler(void);
|
||||
WEAK void BusFault_Handler(void);
|
||||
WEAK void UsageFault_Handler(void);
|
||||
WEAK void SVC_Handler(void);
|
||||
WEAK void DebugMon_Handler(void);
|
||||
WEAK void PendSV_Handler(void);
|
||||
WEAK void SysTick_Handler(void);
|
||||
WEAK void IntDefaultHandler(void);
|
||||
|
||||
|
||||
void WDT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void BOD_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void FMC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void EEPROM_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void DMA_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GINT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void GINT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT4_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT5_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT6_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void PIN_INT7_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RIT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SCT0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SCT1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SCT2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SCT3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void MRT_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void UART2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void I2C0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SPI0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void SPI1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void CAN_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USB_FIQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void USBWakeup_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC0A_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC0B_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC0_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC0_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC1A_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC1B_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC1_THCMP_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ADC1_OVR_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void DAC_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ACMP0_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ACMP1_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ACMP2_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void ACMP3_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void QEI_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RTC_ALARM_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
void RTC_WAKE_IRQHandler(void) ALIAS(IntDefaultHandler);
|
||||
|
||||
|
||||
__attribute__ ((section(".isr_vector")))
|
||||
void (* const g_pfnVectors[])(void) = {
|
||||
// Core Level - CM3
|
||||
&_vStackTop, // The initial stack pointer
|
||||
ResetISR, // The reset handler
|
||||
NMI_Handler, // The NMI handler
|
||||
HardFault_Handler, // The hard fault handler
|
||||
MemManage_Handler, // The MPU fault handler
|
||||
BusFault_Handler, // The bus fault handler
|
||||
UsageFault_Handler, // The usage fault handler
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
0, // Reserved
|
||||
SVC_Handler, // SVCall handler
|
||||
DebugMon_Handler, // Debug monitor handler
|
||||
0, // Reserved
|
||||
PendSV_Handler, // The PendSV handler
|
||||
SysTick_Handler, // The SysTick handler
|
||||
|
||||
// Chip Level - LPC15xx
|
||||
WDT_IRQHandler, // 0 - Windowed watchdog timer
|
||||
BOD_IRQHandler, // 1 - BOD
|
||||
FMC_IRQHandler, // 2 - Flash controller
|
||||
EEPROM_IRQHandler, // 3 - EEPROM controller
|
||||
DMA_IRQHandler, // 4 - DMA
|
||||
GINT0_IRQHandler, // 5 - GINT0
|
||||
GINT1_IRQHandler, // 6 - GINT1
|
||||
PIN_INT0_IRQHandler, // 7 - PIO INT0
|
||||
PIN_INT1_IRQHandler, // 8 - PIO INT1
|
||||
PIN_INT2_IRQHandler, // 9 - PIO INT2
|
||||
PIN_INT3_IRQHandler, // 10 - PIO INT3
|
||||
PIN_INT4_IRQHandler, // 11 - PIO INT4
|
||||
PIN_INT5_IRQHandler, // 12 - PIO INT5
|
||||
PIN_INT6_IRQHandler, // 13 - PIO INT6
|
||||
PIN_INT7_IRQHandler, // 14 - PIO INT7
|
||||
RIT_IRQHandler, // 15 - RIT
|
||||
SCT0_IRQHandler, // 16 - State configurable timer
|
||||
SCT1_IRQHandler, // 17 - State configurable timer
|
||||
SCT2_IRQHandler, // 18 - State configurable timer
|
||||
SCT3_IRQHandler, // 19 - State configurable timer
|
||||
MRT_IRQHandler, // 20 - Multi-Rate Timer
|
||||
UART0_IRQHandler, // 21 - UART0
|
||||
UART1_IRQHandler, // 22 - UART1
|
||||
UART2_IRQHandler, // 23 - UART2
|
||||
I2C0_IRQHandler, // 24 - I2C0 controller
|
||||
SPI0_IRQHandler, // 25 - SPI0 controller
|
||||
SPI1_IRQHandler, // 26 - SPI1 controller
|
||||
CAN_IRQHandler, // 27 - C_CAN0
|
||||
USB_IRQHandler, // 28 - USB IRQ
|
||||
USB_FIQHandler, // 29 - USB FIQ
|
||||
USBWakeup_IRQHandler, // 30 - USB wake-up
|
||||
ADC0A_IRQHandler, // 31 - ADC0 sequence A completion
|
||||
ADC0B_IRQHandler, // 32 - ADC0 sequence B completion
|
||||
ADC0_THCMP_IRQHandler, // 33 - ADC0 threshold compare
|
||||
ADC0_OVR_IRQHandler, // 34 - ADC0 overrun
|
||||
ADC1A_IRQHandler, // 35 - ADC1 sequence A completion
|
||||
ADC1B_IRQHandler, // 36 - ADC1 sequence B completion
|
||||
ADC1_THCMP_IRQHandler, // 37 - ADC1 threshold compare
|
||||
ADC1_OVR_IRQHandler, // 38 - ADC1 overrun
|
||||
DAC_IRQHandler, // 39 - DAC
|
||||
ACMP0_IRQHandler, // 40 - Analog Comparator 0
|
||||
ACMP1_IRQHandler, // 41 - Analog Comparator 1
|
||||
ACMP2_IRQHandler, // 42 - Analog Comparator 2
|
||||
ACMP3_IRQHandler, // 43 - Analog Comparator 3
|
||||
QEI_IRQHandler, // 44 - QEI
|
||||
RTC_ALARM_IRQHandler, // 45 - RTC alarm
|
||||
RTC_WAKE_IRQHandler, // 46 - RTC wake-up
|
||||
|
||||
};
|
||||
/* End Vector */
|
||||
|
||||
AFTER_VECTORS void data_init(unsigned int romstart, unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int *pulSrc = (unsigned int*) romstart;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = *pulSrc++;
|
||||
}
|
||||
|
||||
AFTER_VECTORS void bss_init(unsigned int start, unsigned int len) {
|
||||
unsigned int *pulDest = (unsigned int*) start;
|
||||
unsigned int loop;
|
||||
for (loop = 0; loop < len; loop = loop + 4) *pulDest++ = 0;
|
||||
}
|
||||
|
||||
|
||||
/* Reset entry point*/
|
||||
extern "C" void software_init_hook(void) __attribute__((weak));
|
||||
|
||||
AFTER_VECTORS void ResetISR(void) {
|
||||
unsigned int LoadAddr, ExeAddr, SectionLen;
|
||||
unsigned int *SectionTableAddr;
|
||||
|
||||
SectionTableAddr = &__data_section_table;
|
||||
|
||||
while (SectionTableAddr < &__data_section_table_end) {
|
||||
LoadAddr = *SectionTableAddr++;
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
data_init(LoadAddr, ExeAddr, SectionLen);
|
||||
}
|
||||
while (SectionTableAddr < &__bss_section_table_end) {
|
||||
ExeAddr = *SectionTableAddr++;
|
||||
SectionLen = *SectionTableAddr++;
|
||||
bss_init(ExeAddr, SectionLen);
|
||||
}
|
||||
|
||||
SystemInit();
|
||||
if (software_init_hook)
|
||||
software_init_hook();
|
||||
else {
|
||||
__libc_init_array();
|
||||
main();
|
||||
}
|
||||
while (1) {;}
|
||||
}
|
||||
|
||||
AFTER_VECTORS void NMI_Handler (void) {}
|
||||
AFTER_VECTORS void HardFault_Handler (void) {}
|
||||
AFTER_VECTORS void MemManage_Handler (void) {}
|
||||
AFTER_VECTORS void BusFault_Handler (void) {}
|
||||
AFTER_VECTORS void UsageFault_Handler(void) {}
|
||||
AFTER_VECTORS void SVC_Handler (void) {}
|
||||
AFTER_VECTORS void DebugMon_Handler (void) {}
|
||||
AFTER_VECTORS void PendSV_Handler (void) {}
|
||||
AFTER_VECTORS void SysTick_Handler (void) {}
|
||||
AFTER_VECTORS void IntDefaultHandler (void) {}
|
||||
|
||||
int __aeabi_atexit(void *object, void (*destructor)(void *), void *dso_handle) {return 0;}
|
||||
}
|
||||
|
||||
#include <stdlib.h>
|
||||
|
||||
void *operator new(size_t size) {return malloc(size);}
|
||||
void *operator new[](size_t size){return malloc(size);}
|
||||
|
||||
void operator delete(void *p) {free(p);}
|
||||
void operator delete[](void *p) {free(p);}
|
||||
|
|
@ -423,3 +423,4 @@ __noreturn __stackless void __cmain(void) {
|
|||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -269,3 +269,4 @@ void sysThreadError(osStatus status) {
|
|||
/*----------------------------------------------------------------------------
|
||||
* end of file
|
||||
*---------------------------------------------------------------------------*/
|
||||
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
|||
('LPC11U24', ('ARM', 'uARM', 'GCC_ARM')),
|
||||
('LPC1768', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
|
||||
('UBLOX_C027', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
|
||||
('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
|
||||
('ARCH_PRO', ('ARM', 'GCC_ARM', 'GCC_CR', 'GCC_CS', 'IAR')),
|
||||
('LPC2368', ('ARM',)),
|
||||
('LPC812', ('uARM',)),
|
||||
('LPC1347', ('ARM',)),
|
||||
|
|
@ -38,7 +38,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
|||
('LPC1114', ('uARM','GCC_ARM')),
|
||||
('LPC11U35_401', ('ARM', 'uARM','GCC_ARM','GCC_CR')),
|
||||
('LPC11U35_501', ('ARM', 'uARM','GCC_ARM','GCC_CR')),
|
||||
('LPC1549', ('uARM',)),
|
||||
('LPC1549', ('uARM','GCC_CR')),
|
||||
|
||||
('KL05Z', ('ARM', 'uARM', 'GCC_ARM')),
|
||||
('KL25Z', ('ARM', 'GCC_ARM')),
|
||||
|
|
@ -55,7 +55,7 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
|
|||
|
||||
('NRF51822', ('ARM', )),
|
||||
|
||||
('LPC11U68', ('uARM',)),
|
||||
('LPC11U68', ('uARM','GCC_ARM','GCC_CR')),
|
||||
)
|
||||
|
||||
|
||||
|
|
@ -93,3 +93,4 @@ if __name__ == '__main__':
|
|||
if failures:
|
||||
print "\n\nBuild failures:"
|
||||
print "\n".join([" * %s" % f for f in failures])
|
||||
|
||||
|
|
|
|||
|
|
@ -6,7 +6,7 @@ Licensed under the Apache License, Version 2.0 (the "License");
|
|||
you may not use this file except in compliance with the License.
|
||||
You may obtain a copy of the License at
|
||||
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
http://www.apache.org/licenses/LICENSE-2.0
|
||||
|
||||
Unless required by applicable law or agreed to in writing, software
|
||||
distributed under the License is distributed on an "AS IS" BASIS,
|
||||
|
|
@ -30,6 +30,8 @@ class CodeRed(Exporter):
|
|||
'LPC11U35_501',
|
||||
'UBLOX_C027',
|
||||
'ARCH_PRO',
|
||||
'LPC1549',
|
||||
'LPC11U68',
|
||||
]
|
||||
|
||||
def generate(self):
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,84 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>{{name}}</name>
|
||||
<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red</comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>make</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${workspace_loc:/{{name}}/Debug}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,84 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<projectDescription>
|
||||
<name>{{name}}</name>
|
||||
<comment>This file was automagically generated by mbed.org. For more information, see http://mbed.org/handbook/Exporting-To-Code-Red</comment>
|
||||
<projects>
|
||||
</projects>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
|
||||
<arguments>
|
||||
<dictionary>
|
||||
<key>?name?</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.append_environment</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.autoBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildArguments</key>
|
||||
<value></value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildCommand</key>
|
||||
<value>make</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.buildLocation</key>
|
||||
<value>${workspace_loc:/{{name}}/Debug}</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.cleanBuildTarget</key>
|
||||
<value>clean</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.contents</key>
|
||||
<value>org.eclipse.cdt.make.core.activeConfigSettings</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableAutoBuild</key>
|
||||
<value>false</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableCleanBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.enableFullBuild</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.fullBuildTarget</key>
|
||||
<value>all</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.stopOnError</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
<dictionary>
|
||||
<key>org.eclipse.cdt.make.core.useDefaultBuildCmd</key>
|
||||
<value>true</value>
|
||||
</dictionary>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
|
||||
<arguments>
|
||||
</arguments>
|
||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.core.ccnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
|
||||
</natures>
|
||||
</projectDescription>
|
||||
|
||||
|
|
@ -89,6 +89,8 @@ if __name__ == '__main__':
|
|||
('lpcxpresso', 'LPC1768'), ('lpcxpresso', 'LPC4088'),('lpcxpresso', 'LPC1114'),
|
||||
('lpcxpresso', 'LPC11U35_401'),
|
||||
('lpcxpresso', 'LPC11U35_501'),
|
||||
('lpcxpresso', 'LPC1549'),
|
||||
('lpcxpresso', 'LPC11U68'),
|
||||
# Linux path: /home/emimon01/bin/gcc-cs/bin/
|
||||
# Windows path: "C:/Program Files (x86)/CodeSourcery/Sourcery_CodeBench_Lite_for_ARM_EABI/bin/"
|
||||
('codesourcery', 'LPC1768'),
|
||||
|
|
|
|||
|
|
@ -559,7 +559,7 @@ class LPC1549(Target):
|
|||
|
||||
self.extra_labels = ['NXP', 'LPC15XX']
|
||||
|
||||
self.supported_toolchains = ["uARM"]
|
||||
self.supported_toolchains = ["uARM","GCC_CR"]
|
||||
|
||||
self.supported_form_factors = ["ARDUINO"]
|
||||
|
||||
|
|
@ -574,7 +574,7 @@ class LPC11U68(Target):
|
|||
|
||||
self.extra_labels = ['NXP', 'LPC11U6X']
|
||||
|
||||
self.supported_toolchains = ["uARM"]
|
||||
self.supported_toolchains = ["uARM","GCC_CR","GCC_ARM"]
|
||||
|
||||
self.supported_form_factors = ["ARDUINO"]
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue