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Merge pull request #12283 from jeromecoutant/PR_STM32WB 

STM32WB - Update CubeDriver from v1.0.0 to v1.4.0
pull/12315/head
Anna Bridge 2020-01-25 11:54:29 +00:00 committed by GitHub
parent f45a5a78b5 25da13bc18
commit ceaf562a11
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
223 changed files with 23733 additions and 8095 deletions
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329
features/FEATURE_BLE/targets/TARGET_STM/TARGET_NUCLEO_WB55RG/hw_ipcc.c
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@ -1,329 +0,0 @@
/**
******************************************************************************
* File Name : Target/hw_ipcc.c
* Description : Hardware IPCC source file for BLE
* middleWare.
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "app_common.h"
#include "mbox_def.h"
/* Global variables ---------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
#define HW_IPCC_TX_PENDING( channel ) ( !(LL_C1_IPCC_IsActiveFlag_CHx( IPCC, channel )) ) && (((~(IPCC->C1MR)) & (channel << 16U)))
#define HW_IPCC_RX_PENDING( channel ) (LL_C2_IPCC_IsActiveFlag_CHx( IPCC, channel )) && (((~(IPCC->C1MR)) & (channel << 0U)))
/* Private macros ------------------------------------------------------------*/
/* Private typedef -----------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
static void (*FreeBufCb)( void );
/* Private function prototypes -----------------------------------------------*/
static void HW_IPCC_BLE_EvtHandler( void );
static void HW_IPCC_BLE_AclDataEvtHandler( void );
static void HW_IPCC_MM_FreeBufHandler( void );
static void HW_IPCC_SYS_CmdEvtHandler( void );
static void HW_IPCC_SYS_EvtHandler( void );
static void HW_IPCC_TRACES_EvtHandler( void );
static void HW_IPCC_OT_CmdEvtHandler( void );
static void HW_IPCC_THREAD_NotEvtHandler( void );
static void HW_IPCC_THREAD_CliNotEvtHandler( void );
/* Public function definition -----------------------------------------------*/
/******************************************************************************
* INTERRUPT HANDLER
******************************************************************************/
void HW_IPCC_Rx_Handler( void )
{
if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL ))
{
HW_IPCC_THREAD_NotEvtHandler();
}
else if (HW_IPCC_RX_PENDING( HW_IPCC_BLE_EVENT_CHANNEL ))
{
HW_IPCC_BLE_EvtHandler();
}
else if (HW_IPCC_RX_PENDING( HW_IPCC_SYSTEM_EVENT_CHANNEL ))
{
HW_IPCC_SYS_EvtHandler();
}
else if (HW_IPCC_RX_PENDING( HW_IPCC_TRACES_CHANNEL ))
{
HW_IPCC_TRACES_EvtHandler();
}
else if (HW_IPCC_RX_PENDING( HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL ))
{
HW_IPCC_THREAD_CliNotEvtHandler();
}
return;
}
void HW_IPCC_Tx_Handler( void )
{
if (HW_IPCC_TX_PENDING( HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL ))
{
HW_IPCC_OT_CmdEvtHandler();
}
else if (HW_IPCC_TX_PENDING( HW_IPCC_SYSTEM_CMD_RSP_CHANNEL ))
{
HW_IPCC_SYS_CmdEvtHandler();
}
else if (HW_IPCC_TX_PENDING( HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ))
{
HW_IPCC_MM_FreeBufHandler();
}
else if (HW_IPCC_TX_PENDING( HW_IPCC_HCI_ACL_DATA_CHANNEL ))
{
HW_IPCC_BLE_AclDataEvtHandler();
}
return;
}
/******************************************************************************
* GENERAL
******************************************************************************/
void HW_IPCC_Enable( void )
{
LL_PWR_EnableBootC2();
return;
}
void HW_IPCC_Init( void )
{
LL_AHB3_GRP1_EnableClock( LL_AHB3_GRP1_PERIPH_IPCC );
LL_C1_IPCC_EnableIT_RXO( IPCC );
LL_C1_IPCC_EnableIT_TXF( IPCC );
HAL_NVIC_EnableIRQ(IPCC_C1_RX_IRQn);
HAL_NVIC_EnableIRQ(IPCC_C1_TX_IRQn);
return;
}
/******************************************************************************
* BLE
******************************************************************************/
void HW_IPCC_BLE_Init( void )
{
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
return;
}
void HW_IPCC_BLE_SendCmd( void )
{
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_BLE_CMD_CHANNEL );
return;
}
static void HW_IPCC_BLE_EvtHandler( void )
{
HW_IPCC_BLE_RxEvtNot();
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_BLE_EVENT_CHANNEL );
return;
}
void HW_IPCC_BLE_SendAclData( void )
{
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
return;
}
static void HW_IPCC_BLE_AclDataEvtHandler( void )
{
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_HCI_ACL_DATA_CHANNEL );
HW_IPCC_BLE_AclDataAckNot();
return;
}
__weak void HW_IPCC_BLE_AclDataAckNot( void ){};
__weak void HW_IPCC_BLE_RxEvtNot( void ){};
/******************************************************************************
* SYSTEM
******************************************************************************/
void HW_IPCC_SYS_Init( void )
{
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
return;
}
void HW_IPCC_SYS_SendCmd( void )
{
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
return;
}
static void HW_IPCC_SYS_CmdEvtHandler( void )
{
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_SYSTEM_CMD_RSP_CHANNEL );
HW_IPCC_SYS_CmdEvtNot();
return;
}
static void HW_IPCC_SYS_EvtHandler( void )
{
HW_IPCC_SYS_EvtNot();
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_SYSTEM_EVENT_CHANNEL );
return;
}
__weak void HW_IPCC_SYS_CmdEvtNot( void ){};
__weak void HW_IPCC_SYS_EvtNot( void ){};
/******************************************************************************
* THREAD
******************************************************************************/
void HW_IPCC_THREAD_Init( void )
{
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
return;
}
void HW_IPCC_OT_SendCmd( void )
{
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
return;
}
void HW_IPCC_CLI_SendCmd( void )
{
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_CMD_CHANNEL );
return;
}
void HW_IPCC_THREAD_SendAck( void )
{
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
return;
}
void HW_IPCC_THREAD_CliSendAck( void )
{
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
return;
}
static void HW_IPCC_OT_CmdEvtHandler( void )
{
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_THREAD_OT_CMD_RSP_CHANNEL );
HW_IPCC_OT_CmdEvtNot();
return;
}
static void HW_IPCC_THREAD_NotEvtHandler( void )
{
LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_NOTIFICATION_ACK_CHANNEL );
HW_IPCC_THREAD_EvtNot();
return;
}
static void HW_IPCC_THREAD_CliNotEvtHandler( void )
{
LL_C1_IPCC_DisableReceiveChannel( IPCC, HW_IPCC_THREAD_CLI_NOTIFICATION_ACK_CHANNEL );
HW_IPCC_THREAD_CliEvtNot();
return;
}
__weak void HW_IPCC_OT_CmdEvtNot( void ){};
__weak void HW_IPCC_CLI_CmdEvtNot( void ){};
__weak void HW_IPCC_THREAD_EvtNot( void ){};
/******************************************************************************
* MEMORY MANAGER
******************************************************************************/
void HW_IPCC_MM_SendFreeBuf( void (*cb)( void ) )
{
if ( LL_C1_IPCC_IsActiveFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL ) )
{
FreeBufCb = cb;
LL_C1_IPCC_EnableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
}
else
{
cb();
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
}
return;
}
static void HW_IPCC_MM_FreeBufHandler( void )
{
LL_C1_IPCC_DisableTransmitChannel( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
FreeBufCb();
LL_C1_IPCC_SetFlag_CHx( IPCC, HW_IPCC_MM_RELEASE_BUFFER_CHANNEL );
return;
}
/******************************************************************************
* TRACES
******************************************************************************/
void HW_IPCC_TRACES_Init( void )
{
LL_C1_IPCC_EnableReceiveChannel( IPCC, HW_IPCC_TRACES_CHANNEL );
return;
}
static void HW_IPCC_TRACES_EvtHandler( void )
{
HW_IPCC_TRACES_EvtNot();
LL_C1_IPCC_ClearFlag_CHx( IPCC, HW_IPCC_TRACES_CHANNEL );
return;
}
__weak void HW_IPCC_TRACES_EvtNot( void ){};
/******************* (C) COPYRIGHT 2019 STMicroelectronics *****END OF FILE****/

224
features/FEATURE_BLE/targets/TARGET_STM/TARGET_NUCLEO_WB55RG/shci.c
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/**
******************************************************************************
* @file shci.c
* @author MCD Application Team
* @brief HCI command for the system channel
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32_wpan_common.h"
#include "shci_tl.h"
#include "shci.h"
/* Private typedef -----------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Global variables ----------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Local Functions Definition ------------------------------------------------------*/
/* Public Functions Definition ------------------------------------------------------*/
/**
* C2 COMMAND
*/
SHCI_CmdStatus_t SHCI_C2_FUS_Get_State( void )
{
/**
* Buffer is large enough to hold either a command with no parameter
* or a command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_FUS_GET_STATE;
p_cmd->cmdserial.cmd.plen = 0 ;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket )
{
/**
* Buffer is large enough to hold a command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
((TL_CmdPacket_t *)pCmdPacket)->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_BLE_INIT;
((TL_CmdPacket_t *)pCmdPacket)->cmdserial.cmd.plen = sizeof( SHCI_C2_Ble_Init_Cmd_Param_t ) ;
shci_send( (TL_CmdPacket_t *)pCmdPacket, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void )
{
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_THREAD_INIT;
p_cmd->cmdserial.cmd.plen = 0 ;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket )
{
/**
* Buffer is large enough to hold a command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
((TL_CmdPacket_t *)pCmdPacket)->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_DEBUG_INIT;
((TL_CmdPacket_t *)pCmdPacket)->cmdserial.cmd.plen = sizeof( SHCI_C2_DEBUG_Init_Cmd_Packet_t ) ;
shci_send( (TL_CmdPacket_t *)pCmdPacket, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FLASH_Erase_Activity( SHCI_C2_FLASH_Erase_Activity_Cmd_Packet_t *pCmdPacket )
{
/**
* Buffer is large enough to hold a command complete without payload
*/
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_EvtPacket_t * p_rsp;
p_rsp = (TL_EvtPacket_t *)local_buffer;
((TL_CmdPacket_t *)pCmdPacket)->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY;
((TL_CmdPacket_t *)pCmdPacket)->cmdserial.cmd.plen = sizeof( SHCI_C2_FLASH_Erase_Activity_Cmd_Packet_t ) ;
shci_send( (TL_CmdPacket_t *)pCmdPacket, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode )
{
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_CONCURRENT_SET_MODE;
p_cmd->cmdserial.cmd.plen = 1;
p_cmd->cmdserial.cmd.payload[0] = Mode;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip )
{
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_FLASH_STORE_DATA;
p_cmd->cmdserial.cmd.plen = 1;
p_cmd->cmdserial.cmd.payload[0] = Ip;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip )
{
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_FLASH_ERASE_DATA;
p_cmd->cmdserial.cmd.plen = 1;
p_cmd->cmdserial.cmd.payload[0] = Ip;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn)
{
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER;
p_cmd->cmdserial.cmd.plen = 2;
p_cmd->cmdserial.cmd.payload[0] = Ip;
p_cmd->cmdserial.cmd.payload[1] = FlagRadioLowPowerOn;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void )
{
uint8_t local_buffer[TL_BLEEVT_CS_BUFFER_SIZE];
TL_CmdPacket_t * p_cmd;
TL_EvtPacket_t * p_rsp;
p_cmd = (TL_CmdPacket_t *)local_buffer;
p_rsp = (TL_EvtPacket_t *)local_buffer;
p_cmd->cmdserial.cmd.cmdcode = SHCI_OPCODE_C2_MAC_802_15_4_INIT;
p_cmd->cmdserial.cmd.plen = 0 ;
shci_send( p_cmd, p_rsp );
return (SHCI_CmdStatus_t)(((TL_CcEvt_t*)(p_rsp->evtserial.evt.payload))->payload[0]);
}
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

394
features/FEATURE_BLE/targets/TARGET_STM/TARGET_NUCLEO_WB55RG/shci.h
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@ -1,394 +0,0 @@
/**
******************************************************************************
* @file shci.h
* @author MCD Application Team
* @brief HCI command for the system channel
******************************************************************************
* @attention
*
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2>
*
* This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __SHCI_H
#define __SHCI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
/* Exported types ------------------------------------------------------------*/
/* SYSTEM EVENT */
typedef enum
{
WIRELESS_FW_RUNNING = 0x00,
RSS_FW_RUNNING = 0x01,
} SHCI_SysEvt_Ready_Rsp_t;
#define SHCI_EVTCODE ( 0xFF )
#define SHCI_SUB_EVT_CODE_BASE ( 0x9200 )
/**
* THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU1 DEFINITION
*/
typedef enum
{
SHCI_SUB_EVT_CODE_READY = SHCI_SUB_EVT_CODE_BASE,
} SHCI_SUB_EVT_CODE_t;
typedef PACKED_STRUCT{
SHCI_SysEvt_Ready_Rsp_t sysevt_ready_rsp;
} SHCI_C2_Ready_Evt_t;
/* SYSTEM COMMAND */
typedef PACKED_STRUCT
{
uint32_t MetaData[3];
} SHCI_Header_t;
typedef enum
{
SHCI_Success = 0x00,
SHCI_Unknown_Command = 0x01,
SHCI_ERR_UNSUPPORTED_FEATURE = 0x11,
SHCI_ERR_INVALID_HCI_CMD_PARAMS = 0x12,
SHCI_FUS_Command_Not_Supported = 0xFF,
} SHCI_CmdStatus_t;
typedef enum
{
SHCI_8bits = 0x01,
SHCI_16bits = 0x02,
SHCI_32bits = 0x04,
} SHCI_Busw_t;
typedef enum
{
erase_activity_OFF = 0x00,
erase_activity_ON = 0x01,
} SHCI_Erase_Activity_t;
#define SHCI_OGF ( 0x3F )
#define SHCI_OCF_BASE ( 0x50 )
/**
* THE ORDER SHALL NOT BE CHANGED TO GUARANTEE COMPATIBILITY WITH THE CPU2 DEFINITION
*/
typedef enum
{
SHCI_OCF_C2_RESERVED1 = SHCI_OCF_BASE,
SHCI_OCF_C2_RESERVED2,
SHCI_OCF_C2_FUS_GET_STATE,
SHCI_OCF_C2_FUS_GET_UUID64,
SHCI_OCF_C2_FUS_FIRMWARE_UPGRADE,
SHCI_OCF_C2_FUS_REMOVE_WIRELESS_STACK,
SHCI_OCF_C2_FUS_UPDATE_AUTHENTICATION_KEY,
SHCI_OCF_C2_FUS_LOCK_AUTHENTICATION_KEY,
SHCI_OCF_C2_FUS_WRITE_USER_KEY_IN_MEMORY,
SHCI_OCF_C2_FUS_WRITE_USER_KEY_IN_AES,
SHCI_OCF_C2_FUS_START_WIRELESS_STACK,
SHCI_OCF_C2_FUS_UPGRADE,
SHCI_OCF_C2_FUS_ABORT,
SHCI_OCF_C2_FUS_RESERVED1,
SHCI_OCF_C2_FUS_RESERVED2,
SHCI_OCF_C2_FUS_RESERVED3,
SHCI_OCF_C2_FUS_RESERVED4,
SHCI_OCF_C2_FUS_RESERVED5,
SHCI_OCF_C2_FUS_RESERVED6,
SHCI_OCF_C2_FUS_RESERVED7,
SHCI_OCF_C2_FUS_RESERVED8,
SHCI_OCF_C2_FUS_RESERVED9,
SHCI_OCF_C2_BLE_init,
SHCI_OCF_C2_Thread_init,
SHCI_OCF_C2_Debug_init,
SHCI_OCF_C2_FLASH_erase_activity,
SHCI_OCF_C2_Concurrent_Set_Mode,
SHCI_OCF_C2_FLASH_store_data,
SHCI_OCF_C2_FLASH_erase_data,
SHCI_OCF_C2_RADIO_Allow_Low_Power,
SHCI_OCF_C2_Mac_802_15_4_init,
} SHCI_OCF_t;
#define SHCI_OPCODE_C2_FUS_GET_STATE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_STATE)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_GET_UUID64 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_GET_UUID64)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_FIRMWARE_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_FIRMWARE_UPGRADE)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_REMOVE_WIRELESS_STACK (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_REMOVE_WIRELESS_STACK)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_UPDATE_AUTHENTICATION_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPDATE_AUTHENTICATION_KEY)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_LOCK_AUTHENTICATION_KEY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_LOCK_AUTHENTICATION_KEY)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_WRITE_USER_KEY_IN_MEMORY (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_WRITE_USER_KEY_IN_MEMORY)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_WRITE_USER_KEY_IN_AES (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_WRITE_USER_KEY_IN_AES)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_START_WIRELESS_STACK (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_START_WIRELESS_STACK)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_UPGRADE (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_UPGRADE)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_ABORT (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_ABORT)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED1 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED1)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED2 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED2)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED3 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED3)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED4 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED4)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED5 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED5)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED6 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED6)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED7 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED7)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED8 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED8)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_FUS_RESERVED9 (( SHCI_OGF << 10) + SHCI_OCF_C2_FUS_RESERVED9)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_BLE_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_BLE_init)
/** THE ORDER SHALL NOT BE CHANGED */
typedef PACKED_STRUCT{
uint8_t* pBleBufferAddress; /**< NOT USED CURRENTLY */
uint32_t BleBufferSize; /**< Size of the Buffer allocated in pBleBufferAddress */
uint16_t NumAttrRecord;
uint16_t NumAttrServ;
uint16_t AttrValueArrSize;
uint8_t NumOfLinks;
uint8_t ExtendedPacketLengthEnable;
uint8_t PrWriteListSize;
uint8_t MblockCount;
uint16_t AttMtu;
uint16_t SlaveSca;
uint8_t MasterSca;
uint8_t LsSource;
uint32_t MaxConnEventLength;
uint16_t HsStartupTime;
uint8_t ViterbiEnable;
uint8_t LlOnly;
uint8_t HwVersion;
} SHCI_C2_Ble_Init_Cmd_Param_t;
typedef PACKED_STRUCT{
SHCI_Header_t Header; /** Does not need to be initialized by the user */
SHCI_C2_Ble_Init_Cmd_Param_t Param;
} SHCI_C2_Ble_Init_Cmd_Packet_t;
/** No response parameters*/
#define SHCI_OPCODE_C2_THREAD_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_Thread_init)
/** No command parameters */
/** No response parameters*/
#define SHCI_OPCODE_C2_DEBUG_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_Debug_init)
/** Command parameters */
typedef PACKED_STRUCT{
uint8_t *pGpioConfig;
uint8_t *pTracesConfig;
uint8_t *pGeneralConfig;
uint8_t GpioConfigSize;
uint8_t TracesConfigSize;
uint8_t GeneralConfigSize;
} SHCI_C2_DEBUG_init_Cmd_Param_t;
typedef PACKED_STRUCT{
SHCI_Header_t Header; /** Does not need to be initialized by the user */
SHCI_C2_DEBUG_init_Cmd_Param_t Param;
} SHCI_C2_DEBUG_Init_Cmd_Packet_t;
/** No response parameters*/
#define SHCI_OPCODE_C2_FLASH_ERASE_ACTIVITY (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_erase_activity)
/** Command parameters */
typedef PACKED_STRUCT{
SHCI_Erase_Activity_t EraseActivity;
} SHCI_C2_FLASH_Erase_Activity_Cmd_Param_t;
typedef PACKED_STRUCT{
SHCI_Header_t Header; /** Does not need to be initialized by the user */
SHCI_C2_FLASH_Erase_Activity_Cmd_Param_t Param;
} SHCI_C2_FLASH_Erase_Activity_Cmd_Packet_t;
/** No response parameters*/
#define SHCI_OPCODE_C2_CONCURRENT_SET_MODE (( SHCI_OGF << 10) + SHCI_OCF_C2_Concurrent_Set_Mode)
/** command parameters */
typedef enum
{
BLE_ENABLE,
THREAD_ENABLE,
} SHCI_C2_CONCURRENT_Mode_Param_t;
#define SHCI_OPCODE_C2_FLASH_STORE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_store_data)
#define SHCI_OPCODE_C2_FLASH_ERASE_DATA (( SHCI_OGF << 10) + SHCI_OCF_C2_FLASH_erase_data)
/** command parameters */
typedef enum
{
BLE_IP,
THREAD_IP,
} SHCI_C2_FLASH_Ip_t;
#define SHCI_OPCODE_C2_RADIO_ALLOW_LOW_POWER (( SHCI_OGF << 10) + SHCI_OCF_C2_RADIO_Allow_Low_Power)
#define SHCI_OPCODE_C2_MAC_802_15_4_INIT (( SHCI_OGF << 10) + SHCI_OCF_C2_Mac_802_15_4_init)
/** No command parameters */
/** No response parameters*/
/* Exported constants --------------------------------------------------------*/
/* External variables --------------------------------------------------------*/
/* Exported macros -----------------------------------------------------------*/
/* Exported functions ------------------------------------------------------- */
/**
* SHCI_C2_FUS_Get_State
* @brief Read the RSS
* When the wireless FW is running on the CPU2, the command returns SHCI_FUS_Command_Not_Supported
* When any RSS command is sent after the SHCI_FUS_Command_Not_Supported has been returned after sending one RSS command,
* the CPU2 switches on the RSS ( This reboots automatically the device )
*
* @param None
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_FUS_Get_State( void );
/**
* SHCI_C2_BLE_Init
* @brief Provides parameters and starts the BLE Stack
*
* @param pCmdPacket : Parameters to be provided to the BLE Stack
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_BLE_Init( SHCI_C2_Ble_Init_Cmd_Packet_t *pCmdPacket );
/**
* SHCI_C2_THREAD_Init
* @brief Starts the THREAD Stack
*
* @param None
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_THREAD_Init( void );
/**
* SHCI_C2_DEBUG_Init
* @brief Starts the Traces
*
* @param None
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_DEBUG_Init( SHCI_C2_DEBUG_Init_Cmd_Packet_t *pCmdPacket );
/**
* SHCI_C2_FLASH_Erase_Activity
* @brief Provides the information of the start and the end of a flash erase window on the CPU1
*
* @param pCmdPacket: Start/End of erase activity
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_FLASH_Erase_Activity( SHCI_C2_FLASH_Erase_Activity_Cmd_Packet_t *pCmdPacket );
/**
* SHCI_C2_CONCURRENT_SetMode
* @brief Enable/Disable Thread on CPU2 (M0+)
*
* @param Mode: BLE or Thread enable flag
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_CONCURRENT_SetMode( SHCI_C2_CONCURRENT_Mode_Param_t Mode );
/**
* SHCI_C2_FLASH_StoreData
* @brief Store Data in Flash
*
* @param Ip: BLE or THREAD
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_FLASH_StoreData( SHCI_C2_FLASH_Ip_t Ip );
/**
* SHCI_C2_FLASH_EraseData
* @brief Erase Data in Flash
*
* @param Ip: BLE or THREAD
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_FLASH_EraseData( SHCI_C2_FLASH_Ip_t Ip );
/**
* SHCI_C2_RADIO_AllowLowPower
* @brief Allow or forbid IP_radio (802_15_4 or BLE) to enter in low power mode.
*
* @param Ip: BLE or 802_15_5
* @param FlagRadioLowPowerOn: True or false
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_RADIO_AllowLowPower( SHCI_C2_FLASH_Ip_t Ip,uint8_t FlagRadioLowPowerOn);
/**
* SHCI_C2_MAC_802_15_4_Init
* @brief Starts the MAC 802.15.4 on M0
*
* @param None
* @retval None
*/
SHCI_CmdStatus_t SHCI_C2_MAC_802_15_4_Init( void );
#ifdef __cplusplus
}
#endif
#endif /*__SHCI_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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features/FEATURE_BLE/targets/TARGET_STM/TARGET_NUCLEO_WB55RG/stm32wb_HCIDriver.cpp
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@ -1,888 +0,0 @@
/*
* Copyright (c) 2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include "CordioBLE.h"
#include "CordioHCIDriver.h"
#include "CordioHCITransportDriver.h"
#include "mbed.h"
#include "hci_api.h"
#include "hci_cmd.h"
#include "hci_core.h"
#include "dm_api.h"
#include "bstream.h"
#include "hci_mbed_os_adaptation.h"
#include "mbed-trace/mbed_trace.h"
/* STM32WB include files */
#include "stm32wbxx_ll_ipcc.h"
#include "stm32wbxx_ll_system.h"
#include "tl.h"
#include "shci.h"
#include "shci_tl.h"
#include "hw.h"
#include "app_conf.h"
#include "otp.h"
#define TRACE_GROUP "BLE_WB"
/******************************************************************************
* BLE config parameters
******************************************************************************/
/* Defined from WB Cube reference SW */
#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255 /**< Set to 255 with the memory manager and the mailbox */
#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4))
#define CONFIG_DATA_PUBADDR_OFFSET (0x00) /**< Bluetooth public address */
#define CONFIG_DATA_PUBADDR_LEN (6)
/* HCI related defines */
#define HCI_RESET_RAND_CNT 4
#define VENDOR_SPECIFIC_EVENT 0xFF
#define ACI_HAL_SET_TX_POWER_LEVEL 0xFC0F
#define ACI_WRITE_CONFIG_DATA_OPCODE 0xFC0C
#define ACI_READ_CONFIG_DATA_OPCODE 0xFC0D
#define MAX_HCI_ACL_PACKET_SIZE (sizeof(TL_PacketHeader_t) + 5 + 251)
#define MAX_HACI_EVT_SIZE (255+5)
/* activate to add debug traces */
#define PRINT_HCI_DATA 1
/******************************************************************************
* BLE config parameters
******************************************************************************/
static void evt_received(TL_EvtPacket_t *hcievt);
static void syscmd_status_not( SHCI_TL_CmdStatus_t status );
static void sysevt_received(void *pdata);
static void acl_data_ack(void);
static bool acl_data_wait(void);
static void init_debug( void );
static bool get_bd_address( uint8_t* bd_addr );
static bool sysevt_wait( void);
static bool sysevt_check( void);
namespace ble {
namespace vendor {
namespace stm32wb {
/**
* stm32wb HCI driver implementation
* @see cordio::CordioHCIDriver
*/
class HCIDriver : public cordio::CordioHCIDriver
{
public:
/**
* Construction of the HCIDriver.
* @param transport: Transport of the HCI commands.
* @param rst: Name of the reset pin
*/
HCIDriver(
cordio::CordioHCITransportDriver& transport_driver
) : cordio::CordioHCIDriver(transport_driver) { }
virtual cordio::buf_pool_desc_t get_buffer_pool_description();
/**
* @see CordioHCIDriver::do_initialize
*/
virtual void do_initialize() {
// Nothig needed, init is only at transpot layer level
}
/**
* @see CordioHCIDriver::do_terminate
*/
virtual void do_terminate() {
// Nothig needed, init is only at transpot layer level
}
/**
* @see CordioHCIDriver::start_reset_sequence
*/
virtual void start_reset_sequence() {
/* send an HCI Reset command to start the sequence */
HciResetCmd();
}
/**
* @see CordioHCIDriver::handle_reset_sequence
*/
virtual void handle_reset_sequence(uint8_t *pMsg) {
uint16_t opcode;
static uint8_t randCnt;
/* if event is a command complete event */
if (*pMsg == HCI_CMD_CMPL_EVT) {
#if (PRINT_HCI_DATA == 1)
tr_debug("Command complete event\r\n");
tr_debug("Command >> ");
for (uint8_t i = 0; i < 20; i++) {
tr_debug("%2X ", *((uint8_t *)pMsg + i));
}
tr_debug("\r\n");
/* parse parameters */
tr_debug("HCI_EVT_HDR_LEN=%d\r\n", HCI_EVT_HDR_LEN);
#endif
pMsg += HCI_EVT_HDR_LEN;
pMsg++; /* skip num packets */
BSTREAM_TO_UINT16(opcode, pMsg);
pMsg++; /* skip status */
/* decode opcode */
switch (opcode) {
case HCI_OPCODE_RESET:
/* initialize rand command count */
randCnt = 0;
tr_debug("WB Reset Received\r\n");
/* Once reset complete evet is received we need
* to send a few more commands:
* Tx power and set bd addr
*/
if(get_bd_address(bd_addr)) {
aciWriteConfigData(CONFIG_DATA_PUBADDR_OFFSET, bd_addr);
tr_debug("Setting Bdaddr: %2x:%2x:%2x:%2x:%2x:%2x\r\n",
bd_addr[0],
bd_addr[1],
bd_addr[2],
bd_addr[3],
bd_addr[4],
bd_addr[5]);
} else {
tr_debug("could not find BDaddr\r\n");
/* Skip to next step */
aciSetTxPowerLevel();
}
break;
case ACI_WRITE_CONFIG_DATA_OPCODE:
tr_debug("BD address set\r\n");
/* set the event mask to control which events are generated by the
* controller for the host */
tr_debug("ACI_HAL_SET_TX_POWER_LEVEL\r\n");
aciSetTxPowerLevel();
break;
case ACI_HAL_SET_TX_POWER_LEVEL:
tr_debug("Tx Power Level set\r\n");
//signal_reset_sequence_done();
HciSetEventMaskCmd((uint8_t *) hciEventMask);
break;
case HCI_OPCODE_SET_EVENT_MASK:
// set the event mask to control which LE events are generated by
// the controller for the host
HciLeSetEventMaskCmd((uint8_t *) hciLeEventMask);
break;
case HCI_OPCODE_LE_SET_EVENT_MASK:
/* below command is not supported */
#if COMMAND_NOT_SUPPORTED_SKIP_STEP
// set the event mask to control which events are generated by the
// controller for the host (2nd page of flags )
HciSetEventMaskPage2Cmd((uint8_t *) hciEventMaskPage2);
break;
case HCI_OPCODE_SET_EVENT_MASK_PAGE2:
#endif
// Ask the Bluetooth address of the controller
HciReadBdAddrCmd();
break;
case HCI_OPCODE_READ_BD_ADDR:
// Store the Bluetooth address in the stack runtime parameter
BdaCpy(hciCoreCb.bdAddr, pMsg);
// Read the size of the buffer of the controller
HciLeReadBufSizeCmd();
break;
case HCI_OPCODE_LE_READ_BUF_SIZE:
// Store the buffer parameters in the stack runtime parameters
BSTREAM_TO_UINT16(hciCoreCb.bufSize, pMsg);
BSTREAM_TO_UINT8(hciCoreCb.numBufs, pMsg);
/* initialize ACL buffer accounting */
hciCoreCb.availBufs = hciCoreCb.numBufs;
// read the states and state combinations supported by the link
// layer of the controller
HciLeReadSupStatesCmd();
break;
case HCI_OPCODE_LE_READ_SUP_STATES:
// store supported state and combination in the runtime parameters
// of the stack
memcpy(hciCoreCb.leStates, pMsg, HCI_LE_STATES_LEN);
// read the total of whitelist entries that can be stored in the
// controller.
HciLeReadWhiteListSizeCmd();
break;
case HCI_OPCODE_LE_READ_WHITE_LIST_SIZE:
// store the number of whitelist entries in the stack runtime
// parameters
BSTREAM_TO_UINT8(hciCoreCb.whiteListSize, pMsg);
// Read the LE features supported by the controller
HciLeReadLocalSupFeatCmd();
break;
case HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT:
// Store the set of LE features supported by the controller
BSTREAM_TO_UINT16(hciCoreCb.leSupFeat, pMsg);
// read the total number of address translation entries which can be
// stored in the controller resolving list.
hciCoreReadResolvingListSize();
break;
case HCI_OPCODE_LE_READ_RES_LIST_SIZE:
// store the number of address translation entries in the stack
// runtime parameter
BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg);
// read the Controller's maximum supported payload octets and packet
// duration times for transmission and reception
hciCoreReadMaxDataLen();
break;
case HCI_OPCODE_LE_READ_MAX_DATA_LEN:
{
// store payload definition in the runtime stack parameters.
uint16_t maxTxOctets;
uint16_t maxTxTime;
BSTREAM_TO_UINT16(maxTxOctets, pMsg);
BSTREAM_TO_UINT16(maxTxTime, pMsg);
/* use Controller's maximum supported payload octets and packet duration times
* for transmission as Host's suggested values for maximum transmission number
* of payload octets and maximum packet transmission time for new connections.
*/
HciLeWriteDefDataLen(maxTxOctets, maxTxTime);
}
break;
case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN:
if (hciCoreCb.extResetSeq) {
HciReadLocalVerInfoCmd();
} else {
/* initialize extended parameters */
hciCoreCb.maxAdvDataLen = 0;
hciCoreCb.numSupAdvSets = 0;
hciCoreCb.perAdvListSize = 0;
/* send next command in sequence */
HciLeRandCmd();
}
break;
case HCI_OPCODE_READ_LOCAL_VER_INFO:
case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN:
case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS:
case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE:
// handle extended command
if (hciCoreCb.extResetSeq) {
/* send next extended command in sequence */
(*hciCoreCb.extResetSeq)(pMsg, opcode);
}
break;
case HCI_OPCODE_LE_RAND:
/* check if need to send second rand command */
if (randCnt < (HCI_RESET_RAND_CNT-1)) {
randCnt++;
HciLeRandCmd();
} else {
uint8_t addr[6] = { 0 };
memcpy(addr, pMsg, sizeof(addr));
DM_RAND_ADDR_SET(addr, DM_RAND_ADDR_STATIC);
// note: will invoke set rand address
cordio::BLE::deviceInstance().getGap().setAddress(
BLEProtocol::AddressType::RANDOM_STATIC,
addr
);
}
break;
case HCI_OPCODE_LE_SET_RAND_ADDR:
/* send next command in sequence */
signal_reset_sequence_done();
break;
default:
tr_debug("Complete Event in reset seq with unknown opcode =0x%4X\r\n", opcode);
break;
}
} else if (*pMsg == HCI_CMD_STATUS_EVT) {
uint8_t status;
/* get status */
/* parse parameters */
pMsg += HCI_EVT_HDR_LEN;
status = *pMsg;
pMsg++;
pMsg++; /* skip num packets */
BSTREAM_TO_UINT16(opcode, pMsg);
tr_debug("Command Status event, status:%d, opcode=0x%4X\r\n", status, opcode);
} else {
/**
* vendor specific event
*/
if (pMsg[0] == VENDOR_SPECIFIC_EVENT) {
/* parse parameters */
pMsg += HCI_EVT_HDR_LEN;
BSTREAM_TO_UINT16(opcode, pMsg);
tr_debug("Vendor specific event, opcode=0x%4X\r\n", opcode);
} else {
tr_debug("Unknown event %d!\r\n", pMsg[0]);
}
}
}
private:
uint8_t bd_addr[6];
void aciSetTxPowerLevel() {
uint8_t *pBuf = hciCmdAlloc(ACI_HAL_SET_TX_POWER_LEVEL, 2);
if (!pBuf) {
return;
}
pBuf[HCI_CMD_HDR_LEN] = 0x1;
pBuf[HCI_CMD_HDR_LEN+1] = 0x18;
hciCmdSend(pBuf);
}
void aciReadConfigParameter(uint8_t offset) {
uint8_t *pBuf = hciCmdAlloc(ACI_READ_CONFIG_DATA_OPCODE, 1);
if (!pBuf) {
return;
}
pBuf[3] = offset;
hciCmdSend(pBuf);
}
template<size_t N>
void aciWriteConfigData(uint8_t offset, uint8_t (&buf)[N]) {
uint8_t *pBuf = hciCmdAlloc(ACI_WRITE_CONFIG_DATA_OPCODE, 2 + N);
if (!pBuf) {
return;
}
pBuf[3] = offset;
pBuf[4] = N;
memcpy(pBuf + 5, buf, N);
hciCmdSend(pBuf);
}
void hciCoreReadResolvingListSize(void) {
/* if LL Privacy is supported by Controller and included */
if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) &&
(hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY)) {
/* send next command in sequence */
HciLeReadResolvingListSize();
} else {
hciCoreCb.resListSize = 0;
/* send next command in sequence */
hciCoreReadMaxDataLen();
}
}
void hciCoreReadMaxDataLen(void) {
/* if LE Data Packet Length Extensions is supported by Controller and included */
if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) &&
(hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT)) {
/* send next command in sequence */
HciLeReadMaxDataLen();
} else {
/* send next command in sequence */
HciLeRandCmd();
}
}
};
ble::vendor::cordio::buf_pool_desc_t ble::vendor::stm32wb::HCIDriver::get_buffer_pool_description() {
// Use default buffer pool
return ble::vendor::cordio::CordioHCIDriver::get_default_buffer_pool_description();
}
class TransportDriver : public cordio::CordioHCITransportDriver {
public:
TransportDriver(TL_CmdPacket_t *BleCmdBuffer, TL_CmdPacket_t *SystemCmdBuffer, uint8_t *EvtPool, uint8_t *SystemSpareEvtBuffer, uint8_t *BleSpareEvtBuffer, uint8_t *HciAclDataBuffer) {
bleCmdBuf = BleCmdBuffer;
sysCmdBuf = SystemCmdBuffer;
evtPool = EvtPool;
sysSpareEvtBuf = SystemSpareEvtBuffer;
bleSpareEvtBuf = BleSpareEvtBuffer;
aclDataBuffer = HciAclDataBuffer;
}
virtual ~TransportDriver() { }
/**
* @see CordioHCITransportDriver::initialize
*/
virtual void initialize() {
/* Check whether M0 sub-system was started already by
* checking if the system event was already received
* before. If it was not, then go thru all init. */
if(!sysevt_check()) {
init_debug();
stm32wb_reset();
transport_init();
}
}
/**
* @see CordioHCITransportDriver::terminate
*/
virtual void terminate() { }
/**
* @see CordioHCITransportDriver::write
*/
virtual uint16_t write(uint8_t type, uint16_t len, uint8_t *pData) {
return mbox_write(type, len, pData);
}
private:
void transport_init(void) {
TL_MM_Config_t tl_mm_config;
TL_BLE_InitConf_t tl_ble_Config;
/* STM32WB offers a System Channel HCI interface for
offering system services, with proprietary commands.
System Channel must be used as well for starting up
BLE service so we need to initialize it. */
SHCI_TL_HciInitConf_t shci_init_config;
/**< Reference table initialization */
TL_Init();
/**< System channel initialization */
shci_init_config.p_cmdbuffer = (uint8_t*)sysCmdBuf;
shci_init_config.StatusNotCallBack = syscmd_status_not;
shci_init(sysevt_received, (void*) &shci_init_config);
/**< Memory Manager channel initialization */
tl_mm_config.p_BleSpareEvtBuffer = bleSpareEvtBuf;
tl_mm_config.p_SystemSpareEvtBuffer = sysSpareEvtBuf;
tl_mm_config.p_AsynchEvtPool = evtPool;
tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
TL_MM_Init(&tl_mm_config);
TL_Enable();
/* At this stage, we'll need to wait for ready event,
* passed thru TL_SYS_EvtReceived */
if(!sysevt_wait()) {
tr_debug("ERROR booting WB controler\r\n");
return;
}
// TO DO : check if we need to disable LPM
// requires to import as well all lpm driver
tl_ble_Config.p_AclDataBuffer = aclDataBuffer;
tl_ble_Config.IoBusAclDataTxAck = acl_data_ack;
tl_ble_Config.p_cmdbuffer = (uint8_t *)bleCmdBuf;
tl_ble_Config.IoBusEvtCallBack = evt_received;
TL_BLE_Init(&tl_ble_Config);
/* Now start BLE service on firmware side, using Vendor specific
* command on the System Channe
*/
stm32wb_start_ble();
}
uint16_t mbox_write(uint8_t type, uint16_t len, uint8_t *pData) {
// Note: Until enum is avalable
// type 01 Command
// type 02 ACL DATA
// type 03 SCO Voice (not supported)
// type 04 event - uplink (not suported)
#if (PRINT_HCI_DATA == 1)
tr_debug("mbox_write type:%d, len:%d\r\n", type, len);
#endif
/* TO DO : MANAGE ACL DATA CASE in separate buffer */
switch(type) {
case 1://BLE command
bleCmdBuf->cmdserial.type = type; // for now this param is overwritten in TL_BLE_SendCmd
memcpy( (void*) &bleCmdBuf->cmdserial.cmd, pData, len );
#if (PRINT_HCI_DATA == 1)
/* We're tracing here the command, after copy in shared mem but before
* * M0 trigger. */
tr_debug("TX>> BLE CMD: ");
/* Trace the buffer including Type (+1 on lngth) */
tr_debug("Type %2X ", bleCmdBuf->cmdserial.type);
tr_debug("Cmd %4X ", bleCmdBuf->cmdserial.cmd.cmdcode);
tr_debug("Len %2X ", bleCmdBuf->cmdserial.cmd.plen);
tr_debug("Payload ");
for (uint8_t i = 0; i < bleCmdBuf->cmdserial.cmd.plen; i++) {
tr_debug("%2X ", *(((uint8_t *)&bleCmdBuf->cmdserial.cmd.payload) + i));
}
tr_debug("\r\n");
#endif
TL_BLE_SendCmd(NULL,0); // unused parameters for now
break;
case 2://ACL DATA
if (!acl_data_wait()) {
#if (PRINT_HCI_DATA == 1)
tr_debug("ERROR: previous ACL message not ACK'd\r\n");
#endif
/* return number of bytes sent, 0 in this error case */
return 0;
}
TL_AclDataSerial_t* aclDataSerial = (TL_AclDataSerial_t*) (aclDataBuffer + sizeof(TL_PacketHeader_t));
aclDataSerial->type = type; // for now this param is overwritten in TL_BLE_SendCmd
memcpy(aclDataBuffer + + sizeof(TL_PacketHeader_t) + sizeof(type), pData, len);
TL_BLE_SendAclData(NULL, 0); // unused parameters for now
#if (PRINT_HCI_DATA == 1)
tr_debug(" TX>> BLE ACL: ");
/* Trace the buffer for debug purpose */
for (uint8_t i = 0; i < len+1+8; i++) {
tr_debug("%2X ", *(((uint8_t*) aclDataBuffer) + i));
}
tr_debug("\r\n");
#endif
break;
}
return len;
}
void stm32wb_reset(void) {
// Reset IPCC
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
LL_C1_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
/* Set IPCC default IRQ handlers */
NVIC_SetVector(IPCC_C1_TX_IRQn, (uint32_t)HW_IPCC_Tx_Handler);
NVIC_SetVector(IPCC_C1_RX_IRQn, (uint32_t)HW_IPCC_Rx_Handler);
return;
} // stm32wb_reset
void stm32wb_start_ble(void) {
SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet =
{
0,0,0, /**< Header unused */
0, /** pBleBufferAddress not used */
0, /** BleBufferSize not used */
CFG_BLE_NUM_GATT_ATTRIBUTES,
CFG_BLE_NUM_GATT_SERVICES,
CFG_BLE_ATT_VALUE_ARRAY_SIZE,
CFG_BLE_NUM_LINK,
CFG_BLE_DATA_LENGTH_EXTENSION,
CFG_BLE_PREPARE_WRITE_LIST_SIZE,
CFG_BLE_MBLOCK_COUNT,
CFG_BLE_MAX_ATT_MTU,
CFG_BLE_SLAVE_SCA,
CFG_BLE_MASTER_SCA,
CFG_BLE_LSE_SOURCE,
CFG_BLE_MAX_CONN_EVENT_LENGTH,
CFG_BLE_HSE_STARTUP_TIME,
CFG_BLE_VITERBI_MODE,
CFG_BLE_LL_ONLY,
0 /** TODO Should be read from HW */
};
/**
* Starts the BLE Stack on CPU2
*/
SHCI_C2_BLE_Init( &ble_init_cmd_packet );
}
TL_CmdPacket_t *bleCmdBuf;
TL_CmdPacket_t *sysCmdBuf;
uint8_t *evtPool;
uint8_t *sysSpareEvtBuf;
uint8_t *aclDataBuffer;
uint8_t *bleSpareEvtBuf;
}; // class TransportDriver
} // namespace stm32wb
} // namespace vendor
} // namespace ble
/* There must be only 1 instance of the Transport Driver in STM32WB
* and the command buffers needs to be located in correct memory areas
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t HciAclDataBuffer[MAX_HCI_ACL_PACKET_SIZE];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
/**
* Cordio HCI driver factory
*/
ble::vendor::cordio::CordioHCIDriver& ble_cordio_get_hci_driver() {
static ble::vendor::stm32wb::TransportDriver transport_driver(
&BleCmdBuffer,
&SystemCmdBuffer,
EvtPool,
SystemSpareEvtBuffer,
BleSpareEvtBuffer,
HciAclDataBuffer
);
static ble::vendor::stm32wb::HCIDriver hci_driver (
transport_driver /* other hci driver parameters */
);
return hci_driver;
}
static void evt_received(TL_EvtPacket_t *hcievt) {
uint16_t len = 0;
// We need to memcpy the data before passing to higher layers.
switch (hcievt->evtserial.type) {
case TL_BLEEVT_PKT_TYPE:
len = hcievt->evtserial.evt.plen + TL_EVT_HDR_SIZE;
ble::vendor::stm32wb::TransportDriver::on_data_received((uint8_t *)&hcievt->evtserial, len);
break;
case TL_ACL_DATA_PKT_TYPE:
{
TL_AclDataSerial_t *acl = &(((TL_AclDataPacket_t *)hcievt)->AclDataSerial);
len = acl->length + 5;
ble::vendor::stm32wb::TransportDriver::on_data_received((uint8_t *)acl, len);
}
break;
default:
// should not happen - let's block to check
tr_error("BLE TL evt_received, wrong type:%d \r\n");
break;
}
/* In case Event belongs to the Evt Pool we need to inform */
if (((uint8_t*)hcievt >= EvtPool) && ((uint8_t*)hcievt < (EvtPool + POOL_SIZE))) {
/* Free the message from shared memory */
TL_MM_EvtDone(hcievt);
}
}
/**
* TL Mailbox synchronisation means
*/
/* Using Semaphore to implemented blocking cmd/resp on system channel */
static rtos::Semaphore sys_event_sem(0, 1);
static rtos::Semaphore sys_resp_sem(0, 1);
static rtos::Semaphore acl_ack_sem(1, 1);
static void acl_data_ack(void) {
/**
* The current implementation assumes the tackGUI will not send a new HCI ACL DATA packet before this ack is received
* ( which means the CPU2 has handled the previous packet )
* In order to implement a secure mechanism, it is required either
* - a flow control with the stack
* - a local pool of buffer to store packets received from the stack
*/
acl_ack_sem.release();
return;
}
static bool acl_data_wait(void) {
/* Wait 10 sec for previous ACL command to be ack'ed by Low Layers
* before sending the next one */
if(acl_ack_sem.wait(10000) < 1) {
return false;
} else {
return true;
}
}
/* WEAK callbacks from the BLE TL driver - will be called under Interrupt */
static void sysevt_received( void* pdata) {
/* For now only READY event is received, so we know this is it */
sys_event_sem.release();
/* But later on ... we'll have to parse the answer */
return;
}
/* returns true if ssyevt was received, false otherwise */
static bool sysevt_wait( void) {
/* Wait for 10sec max - if not return an error */
if(sys_event_sem.wait(10000) < 1) {
return false;
} else {
/* release immmediately, now that M0 runs */
sys_event_sem.release();
return true;
}
}
/* returns true if ssyevt was already received, which means M0 core is
* already up and running */
static bool sysevt_check( void) {
/* Check if system is UP and runing already */
if(sys_event_sem.wait(10) < 1) {
return false;
} else {
/* release immmediately as M0 already runs */
sys_event_sem.release();
return true;
}
}
static void syscmd_status_not( SHCI_TL_CmdStatus_t status ) {
tr_debug("syscmd_status_not, status:%d\r\n", status);
return;
}
void shci_notify_asynch_evt(void* pdata) {
/* Need to parse data in future version */
shci_user_evt_proc();
return;
}
void shci_cmd_resp_release(uint32_t flag) {
sys_resp_sem.release();
return;
}
void shci_cmd_resp_wait(uint32_t timeout) {
/* TO DO: manage timeouts if we can return an error */
if(sys_resp_sem.wait(timeout) < 1) {
tr_error("shci_cmd_resp_wait timed out\r\n");
}
}
void shci_register_io_bus(tSHciIO* fops) {
/* Register IO bus services */
fops->Init = TL_SYS_Init;
fops->Send = TL_SYS_SendCmd;
}
/**
* Few utilities functions
*/
static void init_debug( void ) {
tr_debug("WB init_debug: ");
/* In case of MBED debug profile, configure debugger support */
#if (defined(MBED_DEBUG) || (CFG_DEBUGGER_SUPPORTED == 1))
/**
* Keep debugger enabled while in any low power mode
*/
HAL_DBGMCU_EnableDBGSleepMode();
HAL_DBGMCU_EnableDBGStopMode();
HAL_DBGMCU_EnableDBGStandbyMode();
/***************** ENABLE DEBUGGER *************************************/
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
#else
tr_debug("DISABLED\r\n");
GPIO_InitTypeDef gpio_config = {0};
gpio_config.Pull = GPIO_NOPULL;
gpio_config.Mode = GPIO_MODE_ANALOG;
gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
__HAL_RCC_GPIOA_CLK_ENABLE();
HAL_GPIO_Init(GPIOA, &gpio_config);
gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
__HAL_RCC_GPIOB_CLK_ENABLE();
HAL_GPIO_Init(GPIOB, &gpio_config);
HAL_DBGMCU_DisableDBGSleepMode();
HAL_DBGMCU_DisableDBGStopMode();
HAL_DBGMCU_DisableDBGStandbyMode();
#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
return;
}
/* This function fills in a BD address table */
bool get_bd_address( uint8_t* bd_addr ) {
uint8_t *otp_addr;
uint32_t udn;
uint32_t company_id;
uint32_t device_id;
bool bd_found;
udn = LL_FLASH_GetUDN();
if(udn != 0xFFFFFFFF) {
tr_debug("Found UDN: 0x%8lX\r\n", udn);
company_id = LL_FLASH_GetSTCompanyID();
device_id = LL_FLASH_GetDeviceID();
bd_addr[0] = (uint8_t)(udn & 0x000000FF);
bd_addr[1] = (uint8_t)( (udn & 0x0000FF00) >> 8 );
bd_addr[2] = (uint8_t)( (udn & 0x00FF0000) >> 16 );
bd_addr[3] = (uint8_t)device_id;
bd_addr[4] = (uint8_t)(company_id & 0x000000FF);
bd_addr[5] = (uint8_t)( (company_id & 0x0000FF00) >> 8 );
bd_found = true;
} else {
otp_addr = OTP_Read(0);
if(otp_addr) {
memcpy(bd_addr, ((OTP_ID0_t*)otp_addr)->bd_address, CONFIG_DATA_PUBADDR_LEN);
bd_found = false;
} else {
tr_debug("Cannot find BD ADDRESS to program - will leave hw default\r\n");
bd_found = true;
}
}
return bd_found;
}

915
features/FEATURE_BLE/targets/TARGET_STM/TARGET_STM32WB/HCIDriver.cpp Normal file
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@ -0,0 +1,915 @@
/*
* Copyright (c) 2019 ARM Limited
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stdio.h>
#include "CordioBLE.h"
#include "CordioHCIDriver.h"
#include "CordioHCITransportDriver.h"
#include "mbed.h"
#include "hci_api.h"
#include "hci_cmd.h"
#include "hci_core.h"
#include "dm_api.h"
#include "bstream.h"
#include "hci_mbed_os_adaptation.h"
#include "mbed-trace/mbed_trace.h"
/* STM32WB include files */
#include "stm32wbxx_ll_ipcc.h"
#include "stm32wbxx_ll_system.h"
#include "tl.h"
#include "shci.h"
#include "shci_tl.h"
#include "hw.h"
#include "app_conf.h"
#include "otp.h"
#define TRACE_GROUP "BLE_WB"
/******************************************************************************
* BLE config parameters
******************************************************************************/
/* Defined from WB Cube reference SW */
#define CFG_TLBLE_EVT_QUEUE_LENGTH 5
#define CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE 255 /**< Set to 255 with the memory manager and the mailbox */
#define TL_BLE_EVENT_FRAME_SIZE ( TL_EVT_HDR_SIZE + CFG_TLBLE_MOST_EVENT_PAYLOAD_SIZE )
#define POOL_SIZE (CFG_TLBLE_EVT_QUEUE_LENGTH*4*DIVC(( sizeof(TL_PacketHeader_t) + TL_BLE_EVENT_FRAME_SIZE ), 4))
#define CONFIG_DATA_PUBADDR_OFFSET (0x00) /**< Bluetooth public address */
#define CONFIG_DATA_PUBADDR_LEN (6)
/* HCI related defines */
#define HCI_RESET_RAND_CNT 4
#define VENDOR_SPECIFIC_EVENT 0xFF
#define ACI_HAL_SET_TX_POWER_LEVEL 0xFC0F
#define ACI_WRITE_CONFIG_DATA_OPCODE 0xFC0C
#define ACI_READ_CONFIG_DATA_OPCODE 0xFC0D
#define MAX_HCI_ACL_PACKET_SIZE (sizeof(TL_PacketHeader_t) + 5 + 251)
#define MAX_HACI_EVT_SIZE (255+5)
/* activate to add debug traces */
#define PRINT_HCI_DATA 1
/******************************************************************************
* BLE config parameters
******************************************************************************/
static void evt_received(TL_EvtPacket_t *hcievt);
static void syscmd_status_not(SHCI_TL_CmdStatus_t status);
static void sysevt_received(void *pdata);
static void acl_data_ack(void);
static bool acl_data_wait(void);
static void init_debug(void);
static bool get_bd_address(uint8_t *bd_addr);
static bool sysevt_wait(void);
static bool sysevt_check(void);
namespace ble {
namespace vendor {
namespace stm32wb {
/**
* stm32wb HCI driver implementation
* @see cordio::CordioHCIDriver
*/
class HCIDriver : public cordio::CordioHCIDriver {
public:
/**
* Construction of the HCIDriver.
* @param transport: Transport of the HCI commands.
* @param rst: Name of the reset pin
*/
HCIDriver(
cordio::CordioHCITransportDriver &transport_driver
) : cordio::CordioHCIDriver(transport_driver) { }
virtual cordio::buf_pool_desc_t get_buffer_pool_description();
/**
* @see CordioHCIDriver::do_initialize
*/
virtual void do_initialize()
{
// Nothig needed, init is only at transpot layer level
}
/**
* @see CordioHCIDriver::do_terminate
*/
virtual void do_terminate()
{
// Nothig needed, init is only at transpot layer level
}
/**
* @see CordioHCIDriver::start_reset_sequence
*/
virtual void start_reset_sequence()
{
/* send an HCI Reset command to start the sequence */
HciResetCmd();
}
/**
* @see CordioHCIDriver::handle_reset_sequence
*/
virtual void handle_reset_sequence(uint8_t *pMsg)
{
uint16_t opcode;
static uint8_t randCnt;
/* if event is a command complete event */
if (*pMsg == HCI_CMD_CMPL_EVT) {
#if (PRINT_HCI_DATA == 1)
tr_debug("Command complete event\r\n");
tr_debug("Command >> ");
for (uint8_t i = 0; i < 20; i++) {
tr_debug("%2X ", *((uint8_t *)pMsg + i));
}
tr_debug("\r\n");
/* parse parameters */
tr_debug("HCI_EVT_HDR_LEN=%d\r\n", HCI_EVT_HDR_LEN);
#endif
pMsg += HCI_EVT_HDR_LEN;
pMsg++; /* skip num packets */
BSTREAM_TO_UINT16(opcode, pMsg);
pMsg++; /* skip status */
/* decode opcode */
switch (opcode) {
case HCI_OPCODE_RESET:
/* initialize rand command count */
randCnt = 0;
tr_debug("WB Reset Received\r\n");
/* Once reset complete evet is received we need
* to send a few more commands:
* Tx power and set bd addr
*/
if (get_bd_address(bd_addr)) {
aciWriteConfigData(CONFIG_DATA_PUBADDR_OFFSET, bd_addr);
tr_debug("Setting Bdaddr: %2x:%2x:%2x:%2x:%2x:%2x\r\n",
bd_addr[0],
bd_addr[1],
bd_addr[2],
bd_addr[3],
bd_addr[4],
bd_addr[5]);
} else {
tr_debug("could not find BDaddr\r\n");
/* Skip to next step */
aciSetTxPowerLevel();
}
break;
case ACI_WRITE_CONFIG_DATA_OPCODE:
tr_debug("BD address set\r\n");
/* set the event mask to control which events are generated by the
* controller for the host */
tr_debug("ACI_HAL_SET_TX_POWER_LEVEL\r\n");
aciSetTxPowerLevel();
break;
case ACI_HAL_SET_TX_POWER_LEVEL:
tr_debug("Tx Power Level set\r\n");
//signal_reset_sequence_done();
HciSetEventMaskCmd((uint8_t *) hciEventMask);
break;
case HCI_OPCODE_SET_EVENT_MASK:
// set the event mask to control which LE events are generated by
// the controller for the host
HciLeSetEventMaskCmd((uint8_t *) hciLeEventMask);
break;
case HCI_OPCODE_LE_SET_EVENT_MASK:
/* below command is not supported */
#if COMMAND_NOT_SUPPORTED_SKIP_STEP
// set the event mask to control which events are generated by the
// controller for the host (2nd page of flags )
HciSetEventMaskPage2Cmd((uint8_t *) hciEventMaskPage2);
break;
case HCI_OPCODE_SET_EVENT_MASK_PAGE2:
#endif
// Ask the Bluetooth address of the controller
HciReadBdAddrCmd();
break;
case HCI_OPCODE_READ_BD_ADDR:
// Store the Bluetooth address in the stack runtime parameter
BdaCpy(hciCoreCb.bdAddr, pMsg);
// Read the size of the buffer of the controller
HciLeReadBufSizeCmd();
break;
case HCI_OPCODE_LE_READ_BUF_SIZE:
// Store the buffer parameters in the stack runtime parameters
BSTREAM_TO_UINT16(hciCoreCb.bufSize, pMsg);
BSTREAM_TO_UINT8(hciCoreCb.numBufs, pMsg);
/* initialize ACL buffer accounting */
hciCoreCb.availBufs = hciCoreCb.numBufs;
// read the states and state combinations supported by the link
// layer of the controller
HciLeReadSupStatesCmd();
break;
case HCI_OPCODE_LE_READ_SUP_STATES:
// store supported state and combination in the runtime parameters
// of the stack
memcpy(hciCoreCb.leStates, pMsg, HCI_LE_STATES_LEN);
// read the total of whitelist entries that can be stored in the
// controller.
HciLeReadWhiteListSizeCmd();
break;
case HCI_OPCODE_LE_READ_WHITE_LIST_SIZE:
// store the number of whitelist entries in the stack runtime
// parameters
BSTREAM_TO_UINT8(hciCoreCb.whiteListSize, pMsg);
// Read the LE features supported by the controller
HciLeReadLocalSupFeatCmd();
break;
case HCI_OPCODE_LE_READ_LOCAL_SUP_FEAT:
// Store the set of LE features supported by the controller
BSTREAM_TO_UINT16(hciCoreCb.leSupFeat, pMsg);
// read the total number of address translation entries which can be
// stored in the controller resolving list.
hciCoreReadResolvingListSize();
break;
case HCI_OPCODE_LE_READ_RES_LIST_SIZE:
// store the number of address translation entries in the stack
// runtime parameter
BSTREAM_TO_UINT8(hciCoreCb.resListSize, pMsg);
// read the Controller's maximum supported payload octets and packet
// duration times for transmission and reception
hciCoreReadMaxDataLen();
break;
case HCI_OPCODE_LE_READ_MAX_DATA_LEN: {
// store payload definition in the runtime stack parameters.
uint16_t maxTxOctets;
uint16_t maxTxTime;
BSTREAM_TO_UINT16(maxTxOctets, pMsg);
BSTREAM_TO_UINT16(maxTxTime, pMsg);
/* use Controller's maximum supported payload octets and packet duration times
* for transmission as Host's suggested values for maximum transmission number
* of payload octets and maximum packet transmission time for new connections.
*/
HciLeWriteDefDataLen(maxTxOctets, maxTxTime);
}
break;
case HCI_OPCODE_LE_WRITE_DEF_DATA_LEN:
if (hciCoreCb.extResetSeq) {
HciReadLocalVerInfoCmd();
} else {
/* initialize extended parameters */
hciCoreCb.maxAdvDataLen = 0;
hciCoreCb.numSupAdvSets = 0;
hciCoreCb.perAdvListSize = 0;
/* send next command in sequence */
HciLeRandCmd();
}
break;
case HCI_OPCODE_READ_LOCAL_VER_INFO:
case HCI_OPCODE_LE_READ_MAX_ADV_DATA_LEN:
case HCI_OPCODE_LE_READ_NUM_SUP_ADV_SETS:
case HCI_OPCODE_LE_READ_PER_ADV_LIST_SIZE:
// handle extended command
if (hciCoreCb.extResetSeq) {
/* send next extended command in sequence */
(*hciCoreCb.extResetSeq)(pMsg, opcode);
}
break;
case HCI_OPCODE_LE_RAND:
/* check if need to send second rand command */
if (randCnt < (HCI_RESET_RAND_CNT - 1)) {
randCnt++;
HciLeRandCmd();
} else {
uint8_t addr[6] = { 0 };
memcpy(addr, pMsg, sizeof(addr));
DM_RAND_ADDR_SET(addr, DM_RAND_ADDR_STATIC);
// note: will invoke set rand address
cordio::BLE::deviceInstance().getGap().setAddress(
BLEProtocol::AddressType::RANDOM_STATIC,
addr
);
}
break;
case HCI_OPCODE_LE_SET_RAND_ADDR:
/* send next command in sequence */
signal_reset_sequence_done();
break;
default:
tr_debug("Complete Event in reset seq with unknown opcode =0x%4X\r\n", opcode);
break;
}
} else if (*pMsg == HCI_CMD_STATUS_EVT) {
uint8_t status;
/* get status */
/* parse parameters */
pMsg += HCI_EVT_HDR_LEN;
status = *pMsg;
pMsg++;
pMsg++; /* skip num packets */
BSTREAM_TO_UINT16(opcode, pMsg);
tr_debug("Command Status event, status:%d, opcode=0x%4X\r\n", status, opcode);
} else {
/**
* vendor specific event
*/
if (pMsg[0] == VENDOR_SPECIFIC_EVENT) {
/* parse parameters */
pMsg += HCI_EVT_HDR_LEN;
BSTREAM_TO_UINT16(opcode, pMsg);
tr_debug("Vendor specific event, opcode=0x%4X\r\n", opcode);
} else {
tr_debug("Unknown event %d!\r\n", pMsg[0]);
}
}
}
private:
uint8_t bd_addr[6];
void aciSetTxPowerLevel()
{
uint8_t *pBuf = hciCmdAlloc(ACI_HAL_SET_TX_POWER_LEVEL, 2);
if (!pBuf) {
return;
}
pBuf[HCI_CMD_HDR_LEN] = 0x1;
pBuf[HCI_CMD_HDR_LEN + 1] = 0x18;
hciCmdSend(pBuf);
}
void aciReadConfigParameter(uint8_t offset)
{
uint8_t *pBuf = hciCmdAlloc(ACI_READ_CONFIG_DATA_OPCODE, 1);
if (!pBuf) {
return;
}
pBuf[3] = offset;
hciCmdSend(pBuf);
}
template<size_t N>
void aciWriteConfigData(uint8_t offset, uint8_t (&buf)[N])
{
uint8_t *pBuf = hciCmdAlloc(ACI_WRITE_CONFIG_DATA_OPCODE, 2 + N);
if (!pBuf) {
return;
}
pBuf[3] = offset;
pBuf[4] = N;
memcpy(pBuf + 5, buf, N);
hciCmdSend(pBuf);
}
void hciCoreReadResolvingListSize(void)
{
/* if LL Privacy is supported by Controller and included */
if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_PRIVACY) &&
(hciLeSupFeatCfg & HCI_LE_SUP_FEAT_PRIVACY)) {
/* send next command in sequence */
HciLeReadResolvingListSize();
} else {
hciCoreCb.resListSize = 0;
/* send next command in sequence */
hciCoreReadMaxDataLen();
}
}
void hciCoreReadMaxDataLen(void)
{
/* if LE Data Packet Length Extensions is supported by Controller and included */
if ((hciCoreCb.leSupFeat & HCI_LE_SUP_FEAT_DATA_LEN_EXT) &&
(hciLeSupFeatCfg & HCI_LE_SUP_FEAT_DATA_LEN_EXT)) {
/* send next command in sequence */
HciLeReadMaxDataLen();
} else {
/* send next command in sequence */
HciLeRandCmd();
}
}
};
ble::vendor::cordio::buf_pool_desc_t ble::vendor::stm32wb::HCIDriver::get_buffer_pool_description()
{
// Use default buffer pool
return ble::vendor::cordio::CordioHCIDriver::get_default_buffer_pool_description();
}
class TransportDriver : public cordio::CordioHCITransportDriver {
public:
TransportDriver(TL_CmdPacket_t *BleCmdBuffer, TL_CmdPacket_t *SystemCmdBuffer, uint8_t *EvtPool, uint8_t *SystemSpareEvtBuffer, uint8_t *BleSpareEvtBuffer, uint8_t *HciAclDataBuffer)
{
bleCmdBuf = BleCmdBuffer;
sysCmdBuf = SystemCmdBuffer;
evtPool = EvtPool;
sysSpareEvtBuf = SystemSpareEvtBuffer;
bleSpareEvtBuf = BleSpareEvtBuffer;
aclDataBuffer = HciAclDataBuffer;
}
virtual ~TransportDriver() { }
/**
* @see CordioHCITransportDriver::initialize
*/
virtual void initialize()
{
/* Check whether M0 sub-system was started already by
* checking if the system event was already received
* before. If it was not, then go thru all init. */
if (!sysevt_check()) {
init_debug();
stm32wb_reset();
transport_init();
}
}
/**
* @see CordioHCITransportDriver::terminate
*/
virtual void terminate() { }
/**
* @see CordioHCITransportDriver::write
*/
virtual uint16_t write(uint8_t type, uint16_t len, uint8_t *pData)
{
return mbox_write(type, len, pData);
}
private:
void transport_init(void)
{
TL_MM_Config_t tl_mm_config;
TL_BLE_InitConf_t tl_ble_Config;
/* STM32WB offers a System Channel HCI interface for
offering system services, with proprietary commands.
System Channel must be used as well for starting up
BLE service so we need to initialize it. */
SHCI_TL_HciInitConf_t shci_init_config;
/**< Reference table initialization */
TL_Init();
/**< System channel initialization */
shci_init_config.p_cmdbuffer = (uint8_t *)sysCmdBuf;
shci_init_config.StatusNotCallBack = syscmd_status_not;
shci_init(sysevt_received, (void *) &shci_init_config);
/**< Memory Manager channel initialization */
tl_mm_config.p_BleSpareEvtBuffer = bleSpareEvtBuf;
tl_mm_config.p_SystemSpareEvtBuffer = sysSpareEvtBuf;
tl_mm_config.p_AsynchEvtPool = evtPool;
tl_mm_config.AsynchEvtPoolSize = POOL_SIZE;
TL_MM_Init(&tl_mm_config);
TL_Enable();
/* At this stage, we'll need to wait for ready event,
* passed thru TL_SYS_EvtReceived */
if (!sysevt_wait()) {
tr_debug("ERROR booting WB controler\r\n");
return;
}
// TO DO : check if we need to disable LPM
// requires to import as well all lpm driver
tl_ble_Config.p_AclDataBuffer = aclDataBuffer;
tl_ble_Config.IoBusAclDataTxAck = acl_data_ack;
tl_ble_Config.p_cmdbuffer = (uint8_t *)bleCmdBuf;
tl_ble_Config.IoBusEvtCallBack = evt_received;
TL_BLE_Init(&tl_ble_Config);
/* Now start BLE service on firmware side, using Vendor specific
* command on the System Channe
*/
stm32wb_start_ble();
}
uint16_t mbox_write(uint8_t type, uint16_t len, uint8_t *pData)
{
// Note: Until enum is avalable
// type 01 Command
// type 02 ACL DATA
// type 03 SCO Voice (not supported)
// type 04 event - uplink (not suported)
#if (PRINT_HCI_DATA == 1)
tr_debug("mbox_write type:%d, len:%d\r\n", type, len);
#endif
/* TO DO : MANAGE ACL DATA CASE in separate buffer */
switch (type) {
case 1://BLE command
bleCmdBuf->cmdserial.type = type; // for now this param is overwritten in TL_BLE_SendCmd
memcpy((void *) &bleCmdBuf->cmdserial.cmd, pData, len);
#if (PRINT_HCI_DATA == 1)
/* We're tracing here the command, after copy in shared mem but before
* * M0 trigger. */
tr_debug("TX>> BLE CMD: ");
/* Trace the buffer including Type (+1 on lngth) */
tr_debug("Type %2X ", bleCmdBuf->cmdserial.type);
tr_debug("Cmd %4X ", bleCmdBuf->cmdserial.cmd.cmdcode);
tr_debug("Len %2X ", bleCmdBuf->cmdserial.cmd.plen);
tr_debug("Payload ");
for (uint8_t i = 0; i < bleCmdBuf->cmdserial.cmd.plen; i++) {
tr_debug("%2X ", *(((uint8_t *)&bleCmdBuf->cmdserial.cmd.payload) + i));
}
tr_debug("\r\n");
#endif
TL_BLE_SendCmd(NULL, 0); // unused parameters for now
break;
case 2://ACL DATA
if (!acl_data_wait()) {
#if (PRINT_HCI_DATA == 1)
tr_debug("ERROR: previous ACL message not ACK'd\r\n");
#endif
/* return number of bytes sent, 0 in this error case */
return 0;
}
TL_AclDataSerial_t *aclDataSerial = (TL_AclDataSerial_t *)(aclDataBuffer + sizeof(TL_PacketHeader_t));
aclDataSerial->type = type; // for now this param is overwritten in TL_BLE_SendCmd
memcpy(aclDataBuffer + + sizeof(TL_PacketHeader_t) + sizeof(type), pData, len);
TL_BLE_SendAclData(NULL, 0); // unused parameters for now
#if (PRINT_HCI_DATA == 1)
tr_debug(" TX>> BLE ACL: ");
/* Trace the buffer for debug purpose */
for (uint8_t i = 0; i < len + 1 + 8; i++) {
tr_debug("%2X ", *(((uint8_t *) aclDataBuffer) + i));
}
tr_debug("\r\n");
#endif
break;
}
return len;
}
void stm32wb_reset(void)
{
// Reset IPCC
LL_AHB3_GRP1_EnableClock(LL_AHB3_GRP1_PERIPH_IPCC);
LL_C1_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_ClearFlag_CHx(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableTransmitChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C1_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
LL_C2_IPCC_DisableReceiveChannel(
IPCC,
LL_IPCC_CHANNEL_1 | LL_IPCC_CHANNEL_2 | LL_IPCC_CHANNEL_3 | LL_IPCC_CHANNEL_4
| LL_IPCC_CHANNEL_5 | LL_IPCC_CHANNEL_6);
/* Set IPCC default IRQ handlers */
NVIC_SetVector(IPCC_C1_TX_IRQn, (uint32_t)HW_IPCC_Tx_Handler);
NVIC_SetVector(IPCC_C1_RX_IRQn, (uint32_t)HW_IPCC_Rx_Handler);
return;
} // stm32wb_reset
void stm32wb_start_ble(void)
{
SHCI_C2_Ble_Init_Cmd_Packet_t ble_init_cmd_packet = {
0, 0, 0, /**< Header unused */
0, /** pBleBufferAddress not used */
0, /** BleBufferSize not used */
CFG_BLE_NUM_GATT_ATTRIBUTES,
CFG_BLE_NUM_GATT_SERVICES,
CFG_BLE_ATT_VALUE_ARRAY_SIZE,
CFG_BLE_NUM_LINK,
CFG_BLE_DATA_LENGTH_EXTENSION,
CFG_BLE_PREPARE_WRITE_LIST_SIZE,
CFG_BLE_MBLOCK_COUNT,
CFG_BLE_MAX_ATT_MTU,
CFG_BLE_SLAVE_SCA,
CFG_BLE_MASTER_SCA,
CFG_BLE_LSE_SOURCE,
CFG_BLE_MAX_CONN_EVENT_LENGTH,
CFG_BLE_HSE_STARTUP_TIME,
CFG_BLE_VITERBI_MODE,
CFG_BLE_LL_ONLY,
0 /** TODO Should be read from HW */
};
/**
* Starts the BLE Stack on CPU2
*/
SHCI_C2_BLE_Init(&ble_init_cmd_packet);
}
TL_CmdPacket_t *bleCmdBuf;
TL_CmdPacket_t *sysCmdBuf;
uint8_t *evtPool;
uint8_t *sysSpareEvtBuf;
uint8_t *aclDataBuffer;
uint8_t *bleSpareEvtBuf;
}; // class TransportDriver
} // namespace stm32wb
} // namespace vendor
} // namespace ble
/* There must be only 1 instance of the Transport Driver in STM32WB
* and the command buffers needs to be located in correct memory areas
*/
/* Private macros ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
PLACE_IN_SECTION("MB_MEM1") ALIGN(4) static TL_CmdPacket_t BleCmdBuffer;
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t HciAclDataBuffer[MAX_HCI_ACL_PACKET_SIZE];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t EvtPool[POOL_SIZE];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static TL_CmdPacket_t SystemCmdBuffer;
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t SystemSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
PLACE_IN_SECTION("MB_MEM2") ALIGN(4) static uint8_t BleSpareEvtBuffer[sizeof(TL_PacketHeader_t) + TL_EVT_HDR_SIZE + 255];
/**
* Cordio HCI driver factory
*/
ble::vendor::cordio::CordioHCIDriver &ble_cordio_get_hci_driver()
{
static ble::vendor::stm32wb::TransportDriver transport_driver(
&BleCmdBuffer,
&SystemCmdBuffer,
EvtPool,
SystemSpareEvtBuffer,
BleSpareEvtBuffer,
HciAclDataBuffer
);
static ble::vendor::stm32wb::HCIDriver hci_driver(
transport_driver /* other hci driver parameters */
);
return hci_driver;
}
static void evt_received(TL_EvtPacket_t *hcievt)
{
uint16_t len = 0;
// We need to memcpy the data before passing to higher layers.
switch (hcievt->evtserial.type) {
case TL_BLEEVT_PKT_TYPE:
len = hcievt->evtserial.evt.plen + TL_EVT_HDR_SIZE;
ble::vendor::stm32wb::TransportDriver::on_data_received((uint8_t *)&hcievt->evtserial, len);
break;
case TL_ACL_DATA_PKT_TYPE: {
TL_AclDataSerial_t *acl = &(((TL_AclDataPacket_t *)hcievt)->AclDataSerial);
len = acl->length + 5;
ble::vendor::stm32wb::TransportDriver::on_data_received((uint8_t *)acl, len);
}
break;
default:
// should not happen - let's block to check
tr_error("BLE TL evt_received, wrong type:%d \r\n");
break;
}
/* In case Event belongs to the Evt Pool we need to inform */
if (((uint8_t *)hcievt >= EvtPool) && ((uint8_t *)hcievt < (EvtPool + POOL_SIZE))) {
/* Free the message from shared memory */
TL_MM_EvtDone(hcievt);
}
}
/**
* TL Mailbox synchronisation means
*/
/* Using Semaphore to implemented blocking cmd/resp on system channel */
static rtos::Semaphore sys_event_sem(0, 1);
static rtos::Semaphore sys_resp_sem(0, 1);
static rtos::Semaphore acl_ack_sem(1, 1);
static void acl_data_ack(void)
{
/**
* The current implementation assumes the tackGUI will not send a new HCI ACL DATA packet before this ack is received
* ( which means the CPU2 has handled the previous packet )
* In order to implement a secure mechanism, it is required either
* - a flow control with the stack
* - a local pool of buffer to store packets received from the stack
*/
acl_ack_sem.release();
return;
}
static bool acl_data_wait(void)
{
/* Wait 10 sec for previous ACL command to be ack'ed by Low Layers
* before sending the next one */
if (acl_ack_sem.wait(10000) < 1) {
return false;
} else {
return true;
}
}
/* WEAK callbacks from the BLE TL driver - will be called under Interrupt */
static void sysevt_received(void *pdata)
{
/* For now only READY event is received, so we know this is it */
sys_event_sem.release();
/* But later on ... we'll have to parse the answer */
return;
}
/* returns true if ssyevt was received, false otherwise */
static bool sysevt_wait(void)
{
/* Wait for 10sec max - if not return an error */
if (sys_event_sem.wait(10000) < 1) {
return false;
} else {
/* release immmediately, now that M0 runs */
sys_event_sem.release();
return true;
}
}
/* returns true if ssyevt was already received, which means M0 core is
* already up and running */
static bool sysevt_check(void)
{
/* Check if system is UP and runing already */
if (sys_event_sem.wait(10) < 1) {
return false;
} else {
/* release immmediately as M0 already runs */
sys_event_sem.release();
return true;
}
}
static void syscmd_status_not(SHCI_TL_CmdStatus_t status)
{
tr_debug("syscmd_status_not, status:%d\r\n", status);
return;
}
void shci_notify_asynch_evt(void *pdata)
{
/* Need to parse data in future version */
shci_user_evt_proc();
return;
}
void shci_cmd_resp_release(uint32_t flag)
{
sys_resp_sem.release();
return;
}
void shci_cmd_resp_wait(uint32_t timeout)
{
/* TO DO: manage timeouts if we can return an error */
if (sys_resp_sem.wait(timeout) < 1) {
tr_error("shci_cmd_resp_wait timed out\r\n");
}
}
void shci_register_io_bus(tSHciIO *fops)
{
/* Register IO bus services */
fops->Init = TL_SYS_Init;
fops->Send = TL_SYS_SendCmd;
}
/**
* Few utilities functions
*/
static void init_debug(void)
{
tr_debug("WB init_debug: ");
/* In case of MBED debug profile, configure debugger support */
#if (defined(MBED_DEBUG) || (CFG_DEBUGGER_SUPPORTED == 1))
/**
* Keep debugger enabled while in any low power mode
*/
HAL_DBGMCU_EnableDBGSleepMode();
HAL_DBGMCU_EnableDBGStopMode();
HAL_DBGMCU_EnableDBGStandbyMode();
/***************** ENABLE DEBUGGER *************************************/
LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_48);
#else
tr_debug("DISABLED\r\n");
GPIO_InitTypeDef gpio_config = {0};
gpio_config.Pull = GPIO_NOPULL;
gpio_config.Mode = GPIO_MODE_ANALOG;
gpio_config.Pin = GPIO_PIN_15 | GPIO_PIN_14 | GPIO_PIN_13;
__HAL_RCC_GPIOA_CLK_ENABLE();
HAL_GPIO_Init(GPIOA, &gpio_config);
gpio_config.Pin = GPIO_PIN_4 | GPIO_PIN_3;
__HAL_RCC_GPIOB_CLK_ENABLE();
HAL_GPIO_Init(GPIOB, &gpio_config);
HAL_DBGMCU_DisableDBGSleepMode();
HAL_DBGMCU_DisableDBGStopMode();
HAL_DBGMCU_DisableDBGStandbyMode();
#endif /* (CFG_DEBUGGER_SUPPORTED == 1) */
return;
}
/* This function fills in a BD address table */
bool get_bd_address(uint8_t *bd_addr)
{
uint8_t *otp_addr;
uint32_t udn;
uint32_t company_id;
uint32_t device_id;
bool bd_found;
udn = LL_FLASH_GetUDN();
if (udn != 0xFFFFFFFF) {
tr_debug("Found UDN: 0x%8lX\r\n", udn);
company_id = LL_FLASH_GetSTCompanyID();
device_id = LL_FLASH_GetDeviceID();
bd_addr[0] = (uint8_t)(udn & 0x000000FF);
bd_addr[1] = (uint8_t)((udn & 0x0000FF00) >> 8);
bd_addr[2] = (uint8_t)((udn & 0x00FF0000) >> 16);
bd_addr[3] = (uint8_t)device_id;
bd_addr[4] = (uint8_t)(company_id & 0x000000FF);
bd_addr[5] = (uint8_t)((company_id & 0x0000FF00) >> 8);
bd_found = true;
} else {
otp_addr = OTP_Read(0);
if (otp_addr) {
memcpy(bd_addr, ((OTP_ID0_t *)otp_addr)->bd_address, CONFIG_DATA_PUBADDR_LEN);
bd_found = false;
} else {
tr_debug("Cannot find BD ADDRESS to program - will leave hw default\r\n");
bd_found = true;
}
}
return bd_found;
}

11205
targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb50xx.h Normal file
View File

File diff suppressed because it is too large Load Diff

142
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/stm32wb55xx.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wb55xx.h
View File

@ -302,7 +302,7 @@ typedef struct
typedef struct typedef struct
{ {
__IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */ __IO uint32_t ACR; /*!< FLASH Access control register, Address offset: 0x00 */
__IO uint32_t PDKEYR; /*!< FLASH Power-down in run mode flash key Address offset: 0x04 */ __IO uint32_t RESERVED; /*!< Reserved, Address offset: 0x04 */
__IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */
__IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
__IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */
@ -401,15 +401,15 @@ typedef struct
__IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */ __IO uint32_t SR1; /*!< PWR Power Status Register 1, Address offset: 0x10 */
__IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */ __IO uint32_t SR2; /*!< PWR Power Status Register 2, Address offset: 0x14 */
__IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */ __IO uint32_t SCR; /*!< PWR Power Status Reset Register, Address offset: 0x18 */
__IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */ __IO uint32_t CR5; /*!< PWR Power Control Register 5, Address offset: 0x1C */
__IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */ __IO uint32_t PUCRA; /*!< PWR Pull-Up Control Register of port A, Address offset: 0x20 */
__IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */ __IO uint32_t PDCRA; /*!< PWR Pull-Down Control Register of port A, Address offset: 0x24 */
__IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */ __IO uint32_t PUCRB; /*!< PWR Pull-Up Control Register of port B, Address offset: 0x28 */
__IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */ __IO uint32_t PDCRB; /*!< PWR Pull-Down Control Register of port B, Address offset: 0x2C */
__IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */ __IO uint32_t PUCRC; /*!< PWR Pull-Up Control Register of port C, Address offset: 0x30 */
__IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */ __IO uint32_t PDCRC; /*!< PWR Pull-Down Control Register of port C, Address offset: 0x34 */
__IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */ __IO uint32_t PUCRD; /*!< PWR Pull-Up Control Register of port D, Address offset: 0x38 */
__IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */ __IO uint32_t PDCRD; /*!< PWR Pull-Down Control Register of port D, Address offset: 0x3C */
__IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */ __IO uint32_t PUCRE; /*!< PWR Pull-Up Control Register of port E, Address offset: 0x40 */
__IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */ __IO uint32_t PDCRE; /*!< PWR Pull-Down Control Register of port E, Address offset: 0x44 */
uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */ uint32_t RESERVED0[4]; /*!< Reserved, Address offset: 0x48-0x54 */
@ -441,7 +441,6 @@ typedef struct
__IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */ __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
} QUADSPI_TypeDef; } QUADSPI_TypeDef;
/** /**
* @brief Reset and Clock Control * @brief Reset and Clock Control
*/ */
@ -456,7 +455,7 @@ uint32_t RESERVED0; /*!< Reserved,
__IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */
__IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */
__IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */
__IO uint32_t SMPSCR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x24 */ __IO uint32_t SMPSCR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x24 */
__IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */ __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x28 */
__IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */ __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x2C */
__IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */ __IO uint32_t AHB3RSTR; /*!< RCC AHB3 & AHB4 peripheral reset register, Address offset: 0x30 */
@ -710,7 +709,6 @@ typedef struct
__IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */ __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
} RNG_TypeDef; } RNG_TypeDef;
/** /**
* @brief Touch Sensing Controller (TSC) * @brief Touch Sensing Controller (TSC)
*/ */
@ -732,7 +730,6 @@ typedef struct
__IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */ __IO uint32_t IOGXCR[7]; /*!< TSC I/O group x counter register, Address offset: 0x34-4C */
} TSC_TypeDef; } TSC_TypeDef;
/** /**
* @brief LCD * @brief LCD
*/ */
@ -794,7 +791,6 @@ typedef struct
__IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */ __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
} CRS_TypeDef; } CRS_TypeDef;
/** /**
* @brief Inter-Processor Communication * @brief Inter-Processor Communication
*/ */
@ -936,7 +932,8 @@ typedef struct
#define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */ #define SRAM2A_BASE (SRAM_BASE + 0x00030000UL)/*!< SRAM2A(32 KB) base address */
#define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */ #define SRAM2B_BASE (SRAM_BASE + 0x00038000UL)/*!< SRAM2B(32 KB) base address */
/* Size SRAMx */ /* Memory Size */
#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U)
#define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */ #define SRAM1_SIZE 0x00030000UL /*!< SRAM1 default size : 192 kB */
#define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */ #define SRAM2A_SIZE 0x00008000UL /*!< SRAM2a default size : 32 kB */
#define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */ #define SRAM2B_SIZE 0x00008000UL /*!< SRAM2b default size : 32 kB */
@ -3029,6 +3026,9 @@ typedef struct
#define EXTI_RTSR1_RT16_Pos (16U) #define EXTI_RTSR1_RT16_Pos (16U)
#define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR1_RT16_Msk (0x1UL << EXTI_RTSR1_RT16_Pos) /*!< 0x00010000 */
#define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */ #define EXTI_RTSR1_RT16 EXTI_RTSR1_RT16_Msk /*!< Rising trigger event configuration bit of line 16 */
#define EXTI_RTSR1_RT17_Pos (17U)
#define EXTI_RTSR1_RT17_Msk (0x1UL << EXTI_RTSR1_RT17_Pos) /*!< 0x00020000 */
#define EXTI_RTSR1_RT17 EXTI_RTSR1_RT17_Msk /*!< Rising trigger event configuration bit of line 17 */
#define EXTI_RTSR1_RT18_Pos (18U) #define EXTI_RTSR1_RT18_Pos (18U)
#define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR1_RT18_Msk (0x1UL << EXTI_RTSR1_RT18_Pos) /*!< 0x00040000 */
#define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */ #define EXTI_RTSR1_RT18 EXTI_RTSR1_RT18_Msk /*!< Rising trigger event configuration bit of line 18 */
@ -3297,8 +3297,8 @@ typedef struct
/****************** Bit definition for EXTI_SWIER2 register *****************/ /****************** Bit definition for EXTI_SWIER2 register *****************/
#define EXTI_SWIER2_SWI_Pos (0U) #define EXTI_SWIER2_SWI_Pos (0U)
#define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */ #define EXTI_SWIER2_SWI_Msk (0x302UL << EXTI_SWIER2_SWI_Pos) /*!< 0x00000302 */
#define EXTI_SWIER2_SWI EXTI_SWIER2_SWIER_Msk /*!< Falling trigger event configuration bit */ #define EXTI_SWIER2_SWI EXTI_SWIER2_SWI_Msk /*!< Falling trigger event configuration bit */
#define EXTI_SWIER2_SWI33_Pos (1U) #define EXTI_SWIER2_SWI33_Pos (1U)
#define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */ #define EXTI_SWIER2_SWI33_Msk (0x1UL << EXTI_SWIER2_SWI33_Pos) /*!< 0x00000002 */
#define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */ #define EXTI_SWIER2_SWI33 EXTI_SWIER2_SWI33_Msk /*!< Software Interrupt on line 33 */
@ -3405,12 +3405,6 @@ typedef struct
#define EXTI_IMR1_IM25_Pos (25U) #define EXTI_IMR1_IM25_Pos (25U)
#define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */ #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */ #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< CPU1 Interrupt Mask on line 25 */
#define EXTI_IMR1_IM26_Pos (26U)
#define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< CPU1 Interrupt Mask on line 26 */
#define EXTI_IMR1_IM27_Pos (27U)
#define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< CPU1 Interrupt Mask on line 27 */
#define EXTI_IMR1_IM28_Pos (28U) #define EXTI_IMR1_IM28_Pos (28U)
#define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */ #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */ #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< CPU1 Interrupt Mask on line 28 */
@ -3496,18 +3490,9 @@ typedef struct
#define EXTI_IMR2_Pos (0U) #define EXTI_IMR2_Pos (0U)
#define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */ #define EXTI_IMR2_Msk (0x0001FFFFUL << EXTI_IMR2_Pos) /*!< 0x0001FFFF */
#define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */ #define EXTI_IMR2_IM EXTI_IMR2_Msk /*!< CPU1 Interrupt Mask */
#define EXTI_IMR2_IM32_Pos (0U) #define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< CPU1 Interrupt Mask on line 32 */
#define EXTI_IMR2_IM33_Pos (1U)
#define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */ #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */ #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< CPU1 Interrupt Mask on line 33 */
#define EXTI_IMR2_IM34_Pos (2U)
#define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< CPU1 Interrupt Mask on line 34 */
#define EXTI_IMR2_IM35_Pos (3U)
#define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< CPU1 Interrupt Mask on line 35 */
#define EXTI_IMR2_IM36_Pos (4U) #define EXTI_IMR2_IM36_Pos (4U)
#define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */ #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */ #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< CPU1 Interrupt Mask on line 36 */
@ -3541,9 +3526,6 @@ typedef struct
#define EXTI_IMR2_IM46_Pos (14U) #define EXTI_IMR2_IM46_Pos (14U)
#define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */ #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< CPU1 Interrupt Mask on line 46 */
#define EXTI_IMR2_IM47_Pos (15U)
#define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< CPU1 Interrupt Mask on line 47 */
#define EXTI_IMR2_IM48_Pos (16U) #define EXTI_IMR2_IM48_Pos (16U)
#define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */ #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */ #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< CPU1 Interrupt Mask on line 48 */
@ -3641,12 +3623,6 @@ typedef struct
#define EXTI_C2IMR1_IM25_Pos (25U) #define EXTI_C2IMR1_IM25_Pos (25U)
#define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */ #define EXTI_C2IMR1_IM25_Msk (0x1UL << EXTI_C2IMR1_IM25_Pos) /*!< 0x02000000 */
#define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */ #define EXTI_C2IMR1_IM25 EXTI_C2IMR1_IM25_Msk /*!< CPU2 Interrupt Mask on line 25 */
#define EXTI_C2IMR1_IM26_Pos (26U)
#define EXTI_C2IMR1_IM26_Msk (0x1UL << EXTI_C2IMR1_IM26_Pos) /*!< 0x04000000 */
#define EXTI_C2IMR1_IM26 EXTI_C2IMR1_IM26_Msk /*!< CPU2 Interrupt Mask on line 26 */
#define EXTI_C2IMR1_IM27_Pos (27U)
#define EXTI_C2IMR1_IM27_Msk (0x1UL << EXTI_C2IMR1_IM27_Pos) /*!< 0x08000000 */
#define EXTI_C2IMR1_IM27 EXTI_C2IMR1_IM27_Msk /*!< CPU2 Interrupt Mask on line 27 */
#define EXTI_C2IMR1_IM28_Pos (28U) #define EXTI_C2IMR1_IM28_Pos (28U)
#define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */ #define EXTI_C2IMR1_IM28_Msk (0x1UL << EXTI_C2IMR1_IM28_Pos) /*!< 0x10000000 */
#define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */ #define EXTI_C2IMR1_IM28 EXTI_C2IMR1_IM28_Msk /*!< CPU2 Interrupt Mask on line 28 */
@ -3732,18 +3708,9 @@ typedef struct
#define EXTI_C2IMR2_Pos (0U) #define EXTI_C2IMR2_Pos (0U)
#define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */ #define EXTI_C2IMR2_Msk (0x0001FFFFUL << EXTI_C2IMR2_Pos) /*!< 0x0001FFFF */
#define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */ #define EXTI_C2IMR2_IM EXTI_C2IMR2_Msk /*!< CPU2 Interrupt Mask */
#define EXTI_C2IMR2_IM32_Pos (0U)
#define EXTI_C2IMR2_IM32_Msk (0x1UL << EXTI_C2IMR2_IM32_Pos) /*!< 0x00000001 */
#define EXTI_C2IMR2_IM32 EXTI_C2IMR2_IM32_Msk /*!< CPU2 Interrupt Mask on line 32 */
#define EXTI_C2IMR2_IM33_Pos (1U) #define EXTI_C2IMR2_IM33_Pos (1U)
#define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */ #define EXTI_C2IMR2_IM33_Msk (0x1UL << EXTI_C2IMR2_IM33_Pos) /*!< 0x00000002 */
#define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */ #define EXTI_C2IMR2_IM33 EXTI_C2IMR2_IM33_Msk /*!< CPU2 Interrupt Mask on line 33 */
#define EXTI_C2IMR2_IM34_Pos (2U)
#define EXTI_C2IMR2_IM34_Msk (0x1UL << EXTI_C2IMR2_IM34_Pos) /*!< 0x00000004 */
#define EXTI_C2IMR2_IM34 EXTI_C2IMR2_IM34_Msk /*!< CPU2 Interrupt Mask on line 34 */
#define EXTI_C2IMR2_IM35_Pos (3U)
#define EXTI_C2IMR2_IM35_Msk (0x1UL << EXTI_C2IMR2_IM35_Pos) /*!< 0x00000008 */
#define EXTI_C2IMR2_IM35 EXTI_C2IMR2_IM35_Msk /*!< CPU2 Interrupt Mask on line 35 */
#define EXTI_C2IMR2_IM36_Pos (4U) #define EXTI_C2IMR2_IM36_Pos (4U)
#define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */ #define EXTI_C2IMR2_IM36_Msk (0x1UL << EXTI_C2IMR2_IM36_Pos) /*!< 0x00000010 */
#define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */ #define EXTI_C2IMR2_IM36 EXTI_C2IMR2_IM36_Msk /*!< CPU2 Interrupt Mask on line 36 */
@ -3777,9 +3744,6 @@ typedef struct
#define EXTI_C2IMR2_IM46_Pos (14U) #define EXTI_C2IMR2_IM46_Pos (14U)
#define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */ #define EXTI_C2IMR2_IM46_Msk (0x1UL << EXTI_C2IMR2_IM46_Pos) /*!< 0x00004000 */
#define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */ #define EXTI_C2IMR2_IM46 EXTI_C2IMR2_IM46_Msk /*!< CPU2 Interrupt Mask on line 46 */
#define EXTI_C2IMR2_IM47_Pos (15U)
#define EXTI_C2IMR2_IM47_Msk (0x1UL << EXTI_C2IMR2_IM47_Pos) /*!< 0x00008000 */
#define EXTI_C2IMR2_IM47 EXTI_C2IMR2_IM47_Msk /*!< CPU2 Interrupt Mask on line 47 */
#define EXTI_C2IMR2_IM48_Pos (16U) #define EXTI_C2IMR2_IM48_Pos (16U)
#define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */ #define EXTI_C2IMR2_IM48_Msk (0x1UL << EXTI_C2IMR2_IM48_Pos) /*!< 0x00010000 */
#define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */ #define EXTI_C2IMR2_IM48 EXTI_C2IMR2_IM48_Msk /*!< CPU2 Interrupt Mask on line 48 */
@ -3790,10 +3754,10 @@ typedef struct
#define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */ #define EXTI_C2EMR2_EM EXTI_C2EMR2_Msk /*!< CPU2 Interrupt Mask */
#define EXTI_C2EMR2_EM40_Pos (8U) #define EXTI_C2EMR2_EM40_Pos (8U)
#define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */ #define EXTI_C2EMR2_EM40_Msk (0x1UL << EXTI_C2EMR2_EM40_Pos) /*!< 0x00000100 */
#define EXTI_C2EMR2_EM40 EXTI_C2EMR1_EM40_Msk /*!< CPU2 Event Mask on line 40 */ #define EXTI_C2EMR2_EM40 EXTI_C2EMR2_EM40_Msk /*!< CPU2 Event Mask on line 40 */
#define EXTI_C2EMR2_EM41_Pos (9U) #define EXTI_C2EMR2_EM41_Pos (9U)
#define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR1_EM41_Pos) /*!< 0x00000200 */ #define EXTI_C2EMR2_EM41_Msk (0x1UL << EXTI_C2EMR2_EM41_Pos) /*!< 0x00000200 */
#define EXTI_C2EMR2_EM41 EXTI_C2EMR1_EM41_Msk /*!< CPU2 Event Mask on line 41 */ #define EXTI_C2EMR2_EM41 EXTI_C2EMR2_EM41_Msk /*!< CPU2 Event Mask on line 41 */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -4054,9 +4018,9 @@ typedef struct
#define FLASH_ACR_LATENCY_Pos (0U) #define FLASH_ACR_LATENCY_Pos (0U)
#define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */ #define FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000007 */
#define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */ #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Latency */
#define FLASH_ACR_LATENCY_0 (0x1U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */ #define FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000001 */
#define FLASH_ACR_LATENCY_1 (0x2U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */ #define FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000002 */
#define FLASH_ACR_LATENCY_2 (0x4U << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */ #define FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos) /*!< 0x00000004 */
#define FLASH_ACR_PRFTEN_Pos (8U) #define FLASH_ACR_PRFTEN_Pos (8U)
#define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */ #define FLASH_ACR_PRFTEN_Msk (0x1UL << FLASH_ACR_PRFTEN_Pos) /*!< 0x00000100 */
#define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */ #define FLASH_ACR_PRFTEN FLASH_ACR_PRFTEN_Msk /*!< Prefetch enable */
@ -4164,7 +4128,7 @@ typedef struct
#define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */ #define FLASH_CR_RDERRIE FLASH_CR_RDERRIE_Msk /*!< PCROP read error interrupt enable */
#define FLASH_CR_OBL_LAUNCH_Pos (27U) #define FLASH_CR_OBL_LAUNCH_Pos (27U)
#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ #define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option bute loading */ #define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk /*!< Force the option byte loading */
#define FLASH_CR_OPTLOCK_Pos (30U) #define FLASH_CR_OPTLOCK_Pos (30U)
#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ #define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */ #define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk /*!< Options lock */
@ -6491,7 +6455,7 @@ typedef struct
#define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */ #define PWR_SR2_PVDO PWR_SR2_PVDO_Msk /*!< Power voltage detector output */
#define PWR_SR2_PVMO_Pos (12U) #define PWR_SR2_PVMO_Pos (12U)
#define PWR_SR2_PVMO_Msk (0x5UL << PWR_SR2_PVMO_Pos) /*!< 0x0000F000 */ #define PWR_SR2_PVMO_Msk (0x5UL << PWR_SR2_PVMO_Pos) /*!< 0x00005000 */
#define PWR_SR2_PVMO PWR_SR2_PVMO_Msk /*!< Peripheral voltage monitor output for all power domains */ #define PWR_SR2_PVMO PWR_SR2_PVMO_Msk /*!< Peripheral voltage monitor output for all power domains */
#define PWR_SR2_PVMO1_Pos (12U) #define PWR_SR2_PVMO1_Pos (12U)
#define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */ #define PWR_SR2_PVMO1_Msk (0x1UL << PWR_SR2_PVMO1_Pos) /*!< 0x00001000 */
@ -6502,7 +6466,7 @@ typedef struct
/******************** Bit definition for PWR_SCR register ********************/ /******************** Bit definition for PWR_SCR register ********************/
#define PWR_SCR_CWUF_Pos (0U) #define PWR_SCR_CWUF_Pos (0U)
#define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x000000FF */ #define PWR_SCR_CWUF_Msk (0x1FUL << PWR_SCR_CWUF_Pos) /*!< 0x0000001F */
#define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */ #define PWR_SCR_CWUF PWR_SCR_CWUF_Msk /*!< Clear Wake-up Flags for all pins */
#define PWR_SCR_CWUF1_Pos (0U) #define PWR_SCR_CWUF1_Pos (0U)
#define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */ #define PWR_SCR_CWUF1_Msk (0x1UL << PWR_SCR_CWUF1_Pos) /*!< 0x00000001 */
@ -6573,7 +6537,6 @@ typedef struct
#define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */ #define PWR_CR5_SMPSEN_Msk (0x1UL << PWR_CR5_SMPSEN_Pos) /*!< 0x00008000 */
#define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */ #define PWR_CR5_SMPSEN PWR_CR5_SMPSEN_Msk /*!< Enable SMPS Step Down converter SMPS mode enable */
/******************** Bit definition for PWR_PUCRA register *****************/ /******************** Bit definition for PWR_PUCRA register *****************/
#define PWR_PUCRA_PA0_Pos (0U) #define PWR_PUCRA_PA0_Pos (0U)
#define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */ #define PWR_PUCRA_PA0_Msk (0x1UL << PWR_PUCRA_PA0_Pos) /*!< 0x00000001 */
@ -7071,7 +7034,6 @@ typedef struct
#define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */ #define PWR_C2CR3_EIWUL_Msk (0x1UL << PWR_C2CR3_EIWUL_Pos) /*!< 0x00008000 */
#define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */ #define PWR_C2CR3_EIWUL PWR_C2CR3_EIWUL_Msk /*!< Internal Wake-Up line interrupt for CPU2 */
/******************** Bit definition for PWR_EXTSCR register ********************/ /******************** Bit definition for PWR_EXTSCR register ********************/
#define PWR_EXTSCR_C1CSSF_Pos (0U) #define PWR_EXTSCR_C1CSSF_Pos (0U)
#define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */ #define PWR_EXTSCR_C1CSSF_Msk (0x1UL << PWR_EXTSCR_C1CSSF_Pos) /*!< 0x00000001 */
@ -7296,12 +7258,17 @@ typedef struct
#define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */ #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
#define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */ #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* Reset and Clock Control */ /* Reset and Clock Control */
/* */ /* */
/******************************************************************************/ /******************************************************************************/
/*
* @brief Specific device feature definitions
*/
#define RCC_SMPS_SUPPORT
#define RCC_MCO3_SUPPORT
#define RCC_LSCO3_SUPPORT
/******************** Bit definition for RCC_CR register *****************/ /******************** Bit definition for RCC_CR register *****************/
#define RCC_CR_MSION_Pos (0U) #define RCC_CR_MSION_Pos (0U)
@ -7369,6 +7336,7 @@ typedef struct
#define RCC_CR_PLLRDY_Pos (25U) #define RCC_CR_PLLRDY_Pos (25U)
#define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */ #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
#define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */ #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
#define RCC_CR_PLLSAI1ON_Pos (26U) #define RCC_CR_PLLSAI1ON_Pos (26U)
#define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */ #define RCC_CR_PLLSAI1ON_Msk (0x1UL << RCC_CR_PLLSAI1ON_Pos) /*!< 0x04000000 */
#define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */ #define RCC_CR_PLLSAI1ON RCC_CR_PLLSAI1ON_Msk /*!< SAI1 PLL enable */
@ -7844,9 +7812,9 @@ typedef struct
#define RCC_APB2RSTR_TIM17RST_Pos (18U) #define RCC_APB2RSTR_TIM17RST_Pos (18U)
#define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */ #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
#define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
#define RCC_APB2RSTR_SAI1RST_Pos (21U) #define RCC_APB2RSTR_SAI1RST_Pos (21U)
#define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */ #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00200000 */
#define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
/******************** Bit definition for RCC_APB3RSTR register **************/ /******************** Bit definition for RCC_APB3RSTR register **************/
#define RCC_APB3RSTR_RFRST_Pos (0U) #define RCC_APB3RSTR_RFRST_Pos (0U)
@ -7975,10 +7943,9 @@ typedef struct
#define RCC_APB2ENR_TIM17EN_Pos (18U) #define RCC_APB2ENR_TIM17EN_Pos (18U)
#define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */ #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
#define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
#define RCC_APB2ENR_SAI1EN_Pos (21U) #define RCC_APB2ENR_SAI1EN_Pos (21U)
#define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */ #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00200000 */
#define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
/******************** Bit definition for RCC_AHB1SMENR register ****************/ /******************** Bit definition for RCC_AHB1SMENR register ****************/
#define RCC_AHB1SMENR_DMA1SMEN_Pos (0U) #define RCC_AHB1SMENR_DMA1SMEN_Pos (0U)
@ -8022,9 +7989,9 @@ typedef struct
#define RCC_AHB2SMENR_ADCSMEN_Pos (13U) #define RCC_AHB2SMENR_ADCSMEN_Pos (13U)
#define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */ #define RCC_AHB2SMENR_ADCSMEN_Msk (0x1UL << RCC_AHB2SMENR_ADCSMEN_Pos) /*!< 0x00002000 */
#define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk #define RCC_AHB2SMENR_ADCSMEN RCC_AHB2SMENR_ADCSMEN_Msk
#define RCC_AHB2SMENR_AES1SMEN_Pos (16U) #define RCC_AHB2SMENR_AES1SMEN_Pos (16U)
#define RCC_AHB2SMENR_AES1SMEN_Msk (0x1UL << RCC_AHB2SMENR_AES1SMEN_Pos) /*!< 0x00010000 */ #define RCC_AHB2SMENR_AES1SMEN_Msk (0x1UL << RCC_AHB2SMENR_AES1SMEN_Pos) /*!< 0x00010000 */
#define RCC_AHB2SMENR_AES1SMEN RCC_AHB2SMENR_AES1SMEN_Msk #define RCC_AHB2SMENR_AES1SMEN RCC_AHB2SMENR_AES1SMEN_Msk
/******************** Bit definition for RCC_AHB3SMENR register ***************/ /******************** Bit definition for RCC_AHB3SMENR register ***************/
#define RCC_AHB3SMENR_QUADSPISMEN_Pos (8U) #define RCC_AHB3SMENR_QUADSPISMEN_Pos (8U)
@ -8548,7 +8515,7 @@ typedef struct
#define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk #define RCC_C2AHB3SMENR_SRAM2SMEN RCC_C2AHB3SMENR_SRAM2SMEN_Msk
#define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U) #define RCC_C2AHB3SMENR_FLASHSMEN_Pos (25U)
#define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */ #define RCC_C2AHB3SMENR_FLASHSMEN_Msk (0x1UL << RCC_C2AHB3SMENR_FLASHSMEN_Pos) /*!< 0x02000000 */
#define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk #define RCC_C2AHB3SMENR_FLASHSMEN RCC_C2AHB3SMENR_FLASHSMEN_Msk
/******************** Bit definition for RCC_C2APB1SMENR1 register **************/ /******************** Bit definition for RCC_C2APB1SMENR1 register **************/
#define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U) #define RCC_C2APB1SMENR1_TIM2SMEN_Pos (0U)
@ -9375,9 +9342,9 @@ typedef struct
#define SPI_CR1_BR_Pos (3U) #define SPI_CR1_BR_Pos (3U)
#define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */ #define SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos) /*!< 0x00000038 */
#define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */ #define SPI_CR1_BR SPI_CR1_BR_Msk /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CR1_BR_0 (0x1U << SPI_CR1_BR_Pos) /*!< 0x00000008 */ #define SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos) /*!< 0x00000008 */
#define SPI_CR1_BR_1 (0x2U << SPI_CR1_BR_Pos) /*!< 0x00000010 */ #define SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos) /*!< 0x00000010 */
#define SPI_CR1_BR_2 (0x4U << SPI_CR1_BR_Pos) /*!< 0x00000020 */ #define SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos) /*!< 0x00000020 */
#define SPI_CR1_SPE_Pos (6U) #define SPI_CR1_SPE_Pos (6U)
#define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */ #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000040 */
@ -9438,10 +9405,10 @@ typedef struct
#define SPI_CR2_DS_Pos (8U) #define SPI_CR2_DS_Pos (8U)
#define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */ #define SPI_CR2_DS_Msk (0xFUL << SPI_CR2_DS_Pos) /*!< 0x00000F00 */
#define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */ #define SPI_CR2_DS SPI_CR2_DS_Msk /*!< DS[3:0] Data Size */
#define SPI_CR2_DS_0 (0x1U << SPI_CR2_DS_Pos) /*!< 0x00000100 */ #define SPI_CR2_DS_0 (0x1UL << SPI_CR2_DS_Pos) /*!< 0x00000100 */
#define SPI_CR2_DS_1 (0x2U << SPI_CR2_DS_Pos) /*!< 0x00000200 */ #define SPI_CR2_DS_1 (0x2UL << SPI_CR2_DS_Pos) /*!< 0x00000200 */
#define SPI_CR2_DS_2 (0x4U << SPI_CR2_DS_Pos) /*!< 0x00000400 */ #define SPI_CR2_DS_2 (0x4UL << SPI_CR2_DS_Pos) /*!< 0x00000400 */
#define SPI_CR2_DS_3 (0x8U << SPI_CR2_DS_Pos) /*!< 0x00000800 */ #define SPI_CR2_DS_3 (0x8UL << SPI_CR2_DS_Pos) /*!< 0x00000800 */
#define SPI_CR2_FRXTH_Pos (12U) #define SPI_CR2_FRXTH_Pos (12U)
#define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */ #define SPI_CR2_FRXTH_Msk (0x1UL << SPI_CR2_FRXTH_Pos) /*!< 0x00001000 */
#define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */ #define SPI_CR2_FRXTH SPI_CR2_FRXTH_Msk /*!< FIFO reception Threshold */
@ -9477,13 +9444,13 @@ typedef struct
#define SPI_SR_FRLVL_Pos (9U) #define SPI_SR_FRLVL_Pos (9U)
#define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */ #define SPI_SR_FRLVL_Msk (0x3UL << SPI_SR_FRLVL_Pos) /*!< 0x00000600 */
#define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */ #define SPI_SR_FRLVL SPI_SR_FRLVL_Msk /*!< FIFO Reception Level */
#define SPI_SR_FRLVL_0 (0x1U << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */ #define SPI_SR_FRLVL_0 (0x1UL << SPI_SR_FRLVL_Pos) /*!< 0x00000200 */
#define SPI_SR_FRLVL_1 (0x2U << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */ #define SPI_SR_FRLVL_1 (0x2UL << SPI_SR_FRLVL_Pos) /*!< 0x00000400 */
#define SPI_SR_FTLVL_Pos (11U) #define SPI_SR_FTLVL_Pos (11U)
#define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */ #define SPI_SR_FTLVL_Msk (0x3UL << SPI_SR_FTLVL_Pos) /*!< 0x00001800 */
#define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */ #define SPI_SR_FTLVL SPI_SR_FTLVL_Msk /*!< FIFO Transmission Level */
#define SPI_SR_FTLVL_0 (0x1U << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */ #define SPI_SR_FTLVL_0 (0x1UL << SPI_SR_FTLVL_Pos) /*!< 0x00000800 */
#define SPI_SR_FTLVL_1 (0x2U << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */ #define SPI_SR_FTLVL_1 (0x2UL << SPI_SR_FTLVL_Pos) /*!< 0x00001000 */
/******************** Bit definition for SPI_DR register ********************/ /******************** Bit definition for SPI_DR register ********************/
#define SPI_DR_DR_Pos (0U) #define SPI_DR_DR_Pos (0U)
@ -9992,7 +9959,6 @@ typedef struct
#define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */ #define TSC_IOGXCR_CNT_Msk (0x3FFFUL << TSC_IOGXCR_CNT_Pos) /*!< 0x00003FFF */
#define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!< CNT[13:0] bits (Counter value) */ #define TSC_IOGXCR_CNT TSC_IOGXCR_CNT_Msk /*!< CNT[13:0] bits (Counter value) */
/******************************************************************************/ /******************************************************************************/
/* */ /* */
/* LCD Controller (LCD) */ /* LCD Controller (LCD) */
@ -13211,7 +13177,7 @@ typedef struct
#define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK) #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
/****************** Bit definition for USB_BTABLE register ******************/ /****************** Bit definition for USB_BTABLE register ******************/
#define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U) /*!< TODO !!!! To we need this define Buffer Table */ #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8U)
/******************************************************************************/ /******************************************************************************/
/* */ /* */
@ -13352,7 +13318,6 @@ typedef struct
/*********************** UART Instances : Smard card mode *********************/ /*********************** UART Instances : Smard card mode *********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1) #define IS_SMARTCARD_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
/*********************** UART Instances : Driver Enable ***********************/ /*********************** UART Instances : Driver Enable ***********************/
#define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \ #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1)|| \
((INSTANCE) == LPUART1)) ((INSTANCE) == LPUART1))
@ -13363,7 +13328,6 @@ typedef struct
/******************** LPUART Instance *****************************************/ /******************** LPUART Instance *****************************************/
#define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1) #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
/******************************* ADC Instances ********************************/ /******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1) #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
@ -13372,7 +13336,6 @@ typedef struct
/******************************* AES Instances ********************************/ /******************************* AES Instances ********************************/
#define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES1) || ((INSTANCE) == AES2)) #define IS_AES_ALL_INSTANCE(INSTANCE) (((INSTANCE) == AES1) || ((INSTANCE) == AES2))
/******************************** COMP Instances ******************************/ /******************************** COMP Instances ******************************/
#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \ #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
((INSTANCE) == COMP2)) ((INSTANCE) == COMP2))
@ -13673,9 +13636,6 @@ typedef struct
((INSTANCE) == TIM16) || \ ((INSTANCE) == TIM16) || \
((INSTANCE) == TIM17)) ((INSTANCE) == TIM17))
/****************** TIM Instances : supporting synchronization ****************/
#define IS_TIM_SYNCHRO_INSTANCE(INSTANCE) IS_TIM_MASTER_INSTANCE(INSTANCE)
/****************** TIM Instances : supporting ADC triggering through TRGO2 ***/ /****************** TIM Instances : supporting ADC triggering through TRGO2 ***/
#define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1) #define IS_TIM_TRGO2_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

9
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/stm32wbxx.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/stm32wbxx.h
View File

@ -62,14 +62,14 @@
In this case, these drivers will not be included and the application code will In this case, these drivers will not be included and the application code will
be based on direct access to peripherals registers be based on direct access to peripherals registers
*/ */
#define USE_HAL_DRIVER /*#define USE_HAL_DRIVER */
#endif /* USE_HAL_DRIVER */ #endif /* USE_HAL_DRIVER */
/** /**
* @brief CMSIS Device version number * @brief CMSIS Device version number
*/ */
#define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_CMSIS_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_CMSIS_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ #define __STM32WBxx_CMSIS_VERSION_SUB1 (0x03U) /*!< [23:16] sub1 version */
#define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_CMSIS_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\ #define __STM32WBxx_CMSIS_DEVICE_VERSION ((__STM32WBxx_CMSIS_VERSION_MAIN << 24)\
@ -84,13 +84,14 @@
/** @addtogroup Device_Included /** @addtogroup Device_Included
* @{ * @{
*/ */
#define STM32WB55xx // Added for MBED
#if defined(STM32WB55xx) #if defined(STM32WB55xx)
#include "stm32wb55xx.h" #include "stm32wb55xx.h"
#elif defined(STM32WB50xx)
#include "stm32wb50xx.h"
#else #else
#error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)" #error "Please select first the target STM32WBxx device used in your application, for instance xxx (in stm32wbxx.h file)"
#endif #endif
/** /**
* @} * @}
*/ */

2
targets/TARGET_STM/TARGET_STM32WB/TARGET_STM32WB55xG/device/system_stm32wbxx.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/CMSIS/system_stm32wbxx.h
View File

@ -64,7 +64,9 @@ extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */ extern const uint32_t MSIRangeTable[16]; /*!< MSI ranges table values */
#if defined(STM32WB55xx)
extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */ extern const uint32_t SmpsPrescalerTable[4][6]; /*!< SMPS factor ranges table values */
#endif
/** /**
* @} * @}
*/ */

343
targets/TARGET_STM/TARGET_STM32WB/device/stm32_hal_legacy.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/Legacy/stm32_hal_legacy.h
View File

@ -7,7 +7,7 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2018 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
@ -236,6 +236,15 @@
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
#if defined(STM32G4) || defined(STM32H7)
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
#endif
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32H7) || defined(STM32F4)
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
#endif
/** /**
* @} * @}
@ -297,8 +306,17 @@
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
#endif
#endif /* STM32L4 */ #endif /* STM32L4 */
#if defined(STM32G0)
#define DMA_REQUEST_DAC1_CHANNEL1 DMA_REQUEST_DAC1_CH1
#define DMA_REQUEST_DAC1_CHANNEL2 DMA_REQUEST_DAC1_CH2
#endif
#if defined(STM32H7) #if defined(STM32H7)
#define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1 #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
@ -356,6 +374,9 @@
#define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM2 DFSDM_FILTER_EXT_TRIG_LPTIM2_OUT
#define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT #define DFSDM_FILTER_EXT_TRIG_LPTIM3 DFSDM_FILTER_EXT_TRIG_LPTIM3_OUT
#define DAC_TRIGGER_LP1_OUT DAC_TRIGGER_LPTIM1_OUT
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
#endif /* STM32H7 */ #endif /* STM32H7 */
/** /**
@ -451,7 +472,9 @@
#define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2 #define FLASH_FLAG_SNECCE_BANK2RR FLASH_FLAG_SNECCERR_BANK2
#define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2 #define FLASH_FLAG_DBECCE_BANK2RR FLASH_FLAG_DBECCERR_BANK2
#define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2 #define FLASH_FLAG_STRBER_BANK2R FLASH_FLAG_STRBERR_BANK2
#endif #define FLASH_FLAG_WDW FLASH_FLAG_WBNE
#define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL
#endif /* STM32H7 */
/** /**
* @} * @}
@ -487,6 +510,13 @@
#define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 I2C_FASTMODEPLUS_I2C1
#define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 I2C_FASTMODEPLUS_I2C2
#define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3 #define HAL_SYSCFG_FASTMODEPLUS_I2C3 I2C_FASTMODEPLUS_I2C3
#if defined(STM32G4)
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOSwitchBooster
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOSwitchBooster
#define HAL_SYSCFG_EnableIOAnalogSwitchVDD HAL_SYSCFG_EnableIOSwitchVDD
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
#endif /* STM32G4 */
/** /**
* @} * @}
*/ */
@ -495,7 +525,7 @@
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{ * @{
*/ */
#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) #if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@ -548,18 +578,25 @@
#define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2 #define GPIO_AF9_SDIO2 GPIO_AF9_SDMMC2
#define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2 #define GPIO_AF10_SDIO2 GPIO_AF10_SDMMC2
#define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2 #define GPIO_AF11_SDIO2 GPIO_AF11_SDMMC2
#endif
#if defined (STM32H743xx) || defined (STM32H753xx) || defined (STM32H750xx) || defined (STM32H742xx) \
|| defined (STM32H745xx) || defined (STM32H755xx) || defined (STM32H747xx) || defined (STM32H757xx)
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
#endif /* STM32H7 */
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32H7) #if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7)
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32H7*/ #endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 || STM32H7*/
#if defined(STM32L1) #if defined(STM32L1)
#define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
@ -600,6 +637,185 @@
#define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER #define __HAL_HRTIM_GetClockPrescaler __HAL_HRTIM_GETCLOCKPRESCALER
#define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE
#define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE
#if defined(STM32G4)
#define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig
#define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable
#define HAL_HRTIM_ExternalEventCounterDisable HAL_HRTIM_ExtEventCounterDisable
#define HAL_HRTIM_ExternalEventCounterReset HAL_HRTIM_ExtEventCounterReset
#endif /* STM32G4 */
#if defined(STM32H7)
#define HRTIM_OUTPUTSET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTSET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTSET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTSET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTSET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTSET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTSET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTSET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTSET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTSET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMAEV1_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMAEV2_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMAEV3_TIMCCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMAEV4_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMAEV5_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMAEV6_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMAEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMAEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMAEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMBEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMBEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMBEV3_TIMCCMP3 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMBEV4_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMBEV5_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMBEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMBEV7_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMBEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMBEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMCEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMCEV2_TIMACMP2 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMCEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMCEV4_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMCEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMCEV6_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMCEV7_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMCEV8_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMCEV9_TIMFCMP2 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMDEV1_TIMACMP1 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMDEV2_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMDEV3_TIMBCMP2 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMDEV4_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMDEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMDEV6_TIMECMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMDEV7_TIMECMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMDEV8_TIMFCMP1 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMDEV9_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMEEV1_TIMACMP4 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMEEV2_TIMBCMP3 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMEEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMEEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMEEV5_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMEEV6_TIMDCMP1 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMEEV7_TIMDCMP2 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMEEV8_TIMFCMP3 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMEEV9_TIMFCMP4 HRTIM_OUTPUTSET_TIMEV_9
#define HRTIM_OUTPUTRESET_TIMFEV1_TIMACMP3 HRTIM_OUTPUTSET_TIMEV_1
#define HRTIM_OUTPUTRESET_TIMFEV2_TIMBCMP1 HRTIM_OUTPUTSET_TIMEV_2
#define HRTIM_OUTPUTRESET_TIMFEV3_TIMBCMP4 HRTIM_OUTPUTSET_TIMEV_3
#define HRTIM_OUTPUTRESET_TIMFEV4_TIMCCMP1 HRTIM_OUTPUTSET_TIMEV_4
#define HRTIM_OUTPUTRESET_TIMFEV5_TIMCCMP4 HRTIM_OUTPUTSET_TIMEV_5
#define HRTIM_OUTPUTRESET_TIMFEV6_TIMDCMP3 HRTIM_OUTPUTSET_TIMEV_6
#define HRTIM_OUTPUTRESET_TIMFEV7_TIMDCMP4 HRTIM_OUTPUTSET_TIMEV_7
#define HRTIM_OUTPUTRESET_TIMFEV8_TIMECMP2 HRTIM_OUTPUTSET_TIMEV_8
#define HRTIM_OUTPUTRESET_TIMFEV9_TIMECMP3 HRTIM_OUTPUTSET_TIMEV_9
#endif /* STM32H7 */
#if defined(STM32F3)
/** @brief Constants defining available sources associated to external events.
*/
#define HRTIM_EVENTSRC_1 (0x00000000U)
#define HRTIM_EVENTSRC_2 (HRTIM_EECR1_EE1SRC_0)
#define HRTIM_EVENTSRC_3 (HRTIM_EECR1_EE1SRC_1)
#define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0)
/** @brief Constants defining the events that can be selected to configure the
* set/reset crossbar of a timer output
*/
#define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1)
#define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2)
#define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3)
#define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4)
#define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5)
#define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6)
#define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7)
#define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8)
#define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9)
#define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1)
#define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2)
#define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3)
#define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4)
#define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5)
#define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6)
#define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7)
#define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8)
#define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9)
/** @brief Constants defining the event filtering applied to external events
* by a timer
*/
#define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0)
#define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1)
#define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0)
/** @brief Constants defining the DLL calibration periods (in micro seconds)
*/
#define HRTIM_CALIBRATIONRATE_7300 0x00000000U
#define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0)
#define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1)
#define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0)
#endif /* STM32F3 */
/** /**
* @} * @}
*/ */
@ -739,6 +955,12 @@
#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0 #define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1 #define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
#if defined(STM32L1) || defined(STM32L4) || defined(STM32H7)
#define HAL_OPAMP_MSP_INIT_CB_ID HAL_OPAMP_MSPINIT_CB_ID
#define HAL_OPAMP_MSP_DEINIT_CB_ID HAL_OPAMP_MSPDEINIT_CB_ID
#endif
/** /**
* @} * @}
*/ */
@ -754,7 +976,6 @@
#define I2S_FLAG_TXE I2S_FLAG_TXP #define I2S_FLAG_TXE I2S_FLAG_TXP
#define I2S_FLAG_RXNE I2S_FLAG_RXP #define I2S_FLAG_RXNE I2S_FLAG_RXP
#define I2S_FLAG_FRE I2S_FLAG_TIFRE
#endif #endif
#if defined(STM32F7) #if defined(STM32F7)
@ -825,6 +1046,16 @@
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
#if defined(STM32H7)
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
#endif /* STM32H7 */
/** /**
* @} * @}
*/ */
@ -972,6 +1203,24 @@
#define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE #define IS_TIM_HALL_INTERFACE_INSTANCE IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE
#endif #endif
#if defined(STM32H7)
#define TIM_TIM1_ETR_COMP1_OUT TIM_TIM1_ETR_COMP1
#define TIM_TIM1_ETR_COMP2_OUT TIM_TIM1_ETR_COMP2
#define TIM_TIM8_ETR_COMP1_OUT TIM_TIM8_ETR_COMP1
#define TIM_TIM8_ETR_COMP2_OUT TIM_TIM8_ETR_COMP2
#define TIM_TIM2_ETR_COMP1_OUT TIM_TIM2_ETR_COMP1
#define TIM_TIM2_ETR_COMP2_OUT TIM_TIM2_ETR_COMP2
#define TIM_TIM3_ETR_COMP1_OUT TIM_TIM3_ETR_COMP1
#define TIM_TIM1_TI1_COMP1_OUT TIM_TIM1_TI1_COMP1
#define TIM_TIM8_TI1_COMP2_OUT TIM_TIM8_TI1_COMP2
#define TIM_TIM2_TI4_COMP1_OUT TIM_TIM2_TI4_COMP1
#define TIM_TIM2_TI4_COMP2_OUT TIM_TIM2_TI4_COMP2
#define TIM_TIM2_TI4_COMP1COMP2_OUT TIM_TIM2_TI4_COMP1_COMP2
#define TIM_TIM3_TI1_COMP1_OUT TIM_TIM3_TI1_COMP1
#define TIM_TIM3_TI1_COMP2_OUT TIM_TIM3_TI1_COMP2
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
#endif
/** /**
* @} * @}
*/ */
@ -1222,6 +1471,13 @@
#endif #endif
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
#define HAL_DisableSRDomainDBGStandbyMode HAL_DisableDomain3DBGStandbyMode
#endif /* STM32H7A3xx || STM32H7B3xx || STM32H7B0xx || STM32H7A3xxQ || STM32H7B3xxQ || STM32H7B0xxQ */
/** /**
* @} * @}
*/ */
@ -1251,16 +1507,18 @@
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) #define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) #if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32G4)
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
#define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Receive_DMA HAL_I2C_Slave_Seq_Receive_DMA
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 */ #endif /* STM32H7 || STM32WB || STM32G0 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 */
#if defined(STM32F4) #if defined(STM32F4)
#define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT #define HAL_FMPI2C_Master_Sequential_Transmit_IT HAL_FMPI2C_Master_Seq_Transmit_IT
@ -1279,6 +1537,13 @@
/** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose /** @defgroup HAL_PWR_Aliased HAL PWR Aliased maintained for legacy purpose
* @{ * @{
*/ */
#if defined(STM32G0)
#define HAL_PWR_ConfigPVD HAL_PWREx_ConfigPVD
#define HAL_PWR_EnablePVD HAL_PWREx_EnablePVD
#define HAL_PWR_DisablePVD HAL_PWREx_DisablePVD
#define HAL_PWR_PVD_IRQHandler HAL_PWREx_PVD_IRQHandler
#endif
#define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD #define HAL_PWR_PVDConfig HAL_PWR_ConfigPVD
#define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg #define HAL_PWR_DisableBkUpReg HAL_PWREx_DisableBkUpReg
#define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown #define HAL_PWR_DisableFlashPowerDown HAL_PWREx_DisableFlashPowerDown
@ -1351,14 +1616,14 @@
#define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMAError TIM_DMAError
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F7) || defined(STM32F4) || defined(STM32L0) #if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
#define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent #define HAL_TIMEx_ConfigCommutationEvent HAL_TIMEx_ConfigCommutEvent
#define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT #define HAL_TIMEx_ConfigCommutationEvent_IT HAL_TIMEx_ConfigCommutEvent_IT
#define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA #define HAL_TIMEx_ConfigCommutationEvent_DMA HAL_TIMEx_ConfigCommutEvent_DMA
#endif /* STM32H7 || STM32G0 || STM32F7 || STM32F4 || STM32L0 */ #endif /* STM32H7 || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 */
/** /**
* @} * @}
*/ */
@ -2477,12 +2742,28 @@
#define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE #define __USB_OTG_FS_CLK_DISABLE __HAL_RCC_USB_OTG_FS_CLK_DISABLE
#define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE #define __USB_OTG_FS_CLK_ENABLE __HAL_RCC_USB_OTG_FS_CLK_ENABLE
#define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET #define __USB_RELEASE_RESET __HAL_RCC_USB_RELEASE_RESET
#if defined(STM32H7)
#define __HAL_RCC_WWDG_CLK_DISABLE __HAL_RCC_WWDG1_CLK_DISABLE
#define __HAL_RCC_WWDG_CLK_ENABLE __HAL_RCC_WWDG1_CLK_ENABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG1_CLK_SLEEP_DISABLE
#define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG1_CLK_SLEEP_ENABLE
#define __HAL_RCC_WWDG_FORCE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_RELEASE_RESET ((void)0U) /* Not available on the STM32H7*/
#define __HAL_RCC_WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG1_IS_CLK_ENABLED
#define __HAL_RCC_WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG1_IS_CLK_DISABLED
#endif
#define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE #define __WWDG_CLK_DISABLE __HAL_RCC_WWDG_CLK_DISABLE
#define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE #define __WWDG_CLK_ENABLE __HAL_RCC_WWDG_CLK_ENABLE
#define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE #define __WWDG_CLK_SLEEP_DISABLE __HAL_RCC_WWDG_CLK_SLEEP_DISABLE
#define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE #define __WWDG_CLK_SLEEP_ENABLE __HAL_RCC_WWDG_CLK_SLEEP_ENABLE
#define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET #define __WWDG_FORCE_RESET __HAL_RCC_WWDG_FORCE_RESET
#define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET #define __WWDG_RELEASE_RESET __HAL_RCC_WWDG_RELEASE_RESET
#define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE #define __TIM21_CLK_ENABLE __HAL_RCC_TIM21_CLK_ENABLE
#define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE #define __TIM21_CLK_DISABLE __HAL_RCC_TIM21_CLK_DISABLE
#define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET #define __TIM21_FORCE_RESET __HAL_RCC_TIM21_FORCE_RESET
@ -2815,6 +3096,15 @@
#define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED #define __WWDG_IS_CLK_ENABLED __HAL_RCC_WWDG_IS_CLK_ENABLED
#define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED #define __WWDG_IS_CLK_DISABLED __HAL_RCC_WWDG_IS_CLK_DISABLED
#if defined(STM32L1)
#define __HAL_RCC_CRYP_CLK_DISABLE __HAL_RCC_AES_CLK_DISABLE
#define __HAL_RCC_CRYP_CLK_ENABLE __HAL_RCC_AES_CLK_ENABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE __HAL_RCC_AES_CLK_SLEEP_DISABLE
#define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE __HAL_RCC_AES_CLK_SLEEP_ENABLE
#define __HAL_RCC_CRYP_FORCE_RESET __HAL_RCC_AES_FORCE_RESET
#define __HAL_RCC_CRYP_RELEASE_RESET __HAL_RCC_AES_RELEASE_RESET
#endif /* STM32L1 */
#if defined(STM32F4) #if defined(STM32F4)
#define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET #define __HAL_RCC_SDMMC1_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET #define __HAL_RCC_SDMMC1_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
@ -2929,8 +3219,9 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
#if defined(STM32L4) || defined(STM32WB) #if defined(STM32L4)
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
#elif defined(STM32WB) || defined(STM32G0) || defined(STM32G4)
#else #else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
#endif #endif
@ -3058,7 +3349,7 @@
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined STM32L4Q5xx #if defined (STM32G0) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined STM32G4
#else #else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
#endif #endif
@ -3174,7 +3465,7 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler #define SDIO_IRQHandler SDMMC1_IRQHandler
#endif #endif
#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) #if defined(STM32F7) || defined(STM32F4) || defined(STM32F2) || defined(STM32L4) || defined(STM32H7)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef #define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef #define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef #define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
@ -3421,13 +3712,23 @@
/** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose /** @defgroup HAL_HRTIM_Aliased_Functions HAL HRTIM Aliased Functions maintained for legacy purpose
* @{ * @{
*/ */
#if defined (STM32H7) || defined (STM32F3) #if defined (STM32H7) || defined (STM32G4) || defined (STM32F3)
#define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT #define HAL_HRTIM_WaveformCounterStart_IT HAL_HRTIM_WaveformCountStart_IT
#define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA #define HAL_HRTIM_WaveformCounterStart_DMA HAL_HRTIM_WaveformCountStart_DMA
#define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart #define HAL_HRTIM_WaveformCounterStart HAL_HRTIM_WaveformCountStart
#define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT #define HAL_HRTIM_WaveformCounterStop_IT HAL_HRTIM_WaveformCountStop_IT
#define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA #define HAL_HRTIM_WaveformCounterStop_DMA HAL_HRTIM_WaveformCountStop_DMA
#define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop #define HAL_HRTIM_WaveformCounterStop HAL_HRTIM_WaveformCountStop
#endif
/**
* @}
*/
/** @defgroup HAL_QSPI_Aliased_Macros HAL QSPI Aliased Macros maintained for legacy purpose
* @{
*/
#if defined (STM32L4)
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE HAL_QSPI_TIMEOUT_DEFAULT_VALUE
#endif #endif
/** /**
* @} * @}

7
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal.c
View File

@ -56,7 +56,7 @@
* @brief STM32WBxx HAL Driver version number * @brief STM32WBxx HAL Driver version number
*/ */
#define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define __STM32WBxx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32WBxx_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ #define __STM32WBxx_HAL_VERSION_SUB1 (0x04U) /*!< [23:16] sub1 version */
#define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ #define __STM32WBxx_HAL_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */
#define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define __STM32WBxx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\ #define __STM32WBxx_HAL_VERSION ((__STM32WBxx_HAL_VERSION_MAIN << 24U)\
@ -64,7 +64,9 @@
|(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\ |(__STM32WBxx_HAL_VERSION_SUB2 << 8U )\
|(__STM32WBxx_HAL_VERSION_RC)) |(__STM32WBxx_HAL_VERSION_RC))
#if defined(VREFBUF)
#define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */ #define VREFBUF_TIMEOUT_VALUE 10U /* 10 ms */
#endif
/** /**
* @} * @}
@ -575,6 +577,7 @@ void HAL_DBGMCU_DisableDBGStandbyMode(void)
(+) Enable/Disable the Voltage reference buffer (+) Enable/Disable the Voltage reference buffer
(+) Enable/Disable the I/O analog switch voltage booster (+) Enable/Disable the I/O analog switch voltage booster
(+) Enable/Disable the access for security IP (AES1, AES2, PKA, RNG) (+) Enable/Disable the access for security IP (AES1, AES2, PKA, RNG)
(+) Enable/Disable the access for security IP (AES2, PKA, RNG)
@endverbatim @endverbatim
* @{ * @{
@ -614,6 +617,7 @@ uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void)
return (LL_SYSCFG_IsEnabledSRAMFetch()); return (LL_SYSCFG_IsEnabledSRAMFetch());
} }
#if defined(VREFBUF)
/** /**
* @brief Configure the internal voltage reference buffer voltage scale. * @brief Configure the internal voltage reference buffer voltage scale.
* @param VoltageScaling specifies the output voltage to achieve * @param VoltageScaling specifies the output voltage to achieve
@ -698,6 +702,7 @@ void HAL_SYSCFG_DisableVREFBUF(void)
{ {
LL_VREFBUF_Disable(); LL_VREFBUF_Disable();
} }
#endif /* VREFBUF */
/** /**
* @brief Enable the I/O analog switch voltage booster * @brief Enable the I/O analog switch voltage booster

18
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal.h
View File

@ -65,7 +65,9 @@
#define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */ #define SYSCFG_BOOT_MAINFLASH LL_SYSCFG_REMAP_FLASH /*!< Main Flash memory mapped at 0x00000000 */
#define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */ #define SYSCFG_BOOT_SYSTEMFLASH LL_SYSCFG_REMAP_SYSTEMFLASH /*!< System Flash memory mapped at 0x00000000 */
#define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */ #define SYSCFG_BOOT_SRAM LL_SYSCFG_REMAP_SRAM /*!< SRAM1 mapped at 0x00000000 */
#if defined(LL_SYSCFG_REMAP_QUADSPI)
#define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */ #define SYSCFG_BOOT_QUADSPI LL_SYSCFG_REMAP_QUADSPI /*!< QUADSPI memory mapped at 0x00000000 */
#endif
/** /**
* @} * @}
*/ */
@ -215,7 +217,9 @@
/** @defgroup Secure_IP_Write_Access Secure IP Write Access /** @defgroup Secure_IP_Write_Access Secure IP Write Access
* @{ * @{
*/ */
#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
#define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */ #define HAL_SYSCFG_SECURE_ACCESS_AES1 LL_SYSCFG_SECURE_ACCESS_AES1 /*!< Enabling the security access of Advanced Encryption Standard 1 KEY[7:0] */
#endif
#define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */ #define HAL_SYSCFG_SECURE_ACCESS_AES2 LL_SYSCFG_SECURE_ACCESS_AES2 /*!< Enabling the security access of Advanced Encryption Standard 2 */
#define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */ #define HAL_SYSCFG_SECURE_ACCESS_PKA LL_SYSCFG_SECURE_ACCESS_PKA /*!< Enabling the security access of Public Key Accelerator */
#define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */ #define HAL_SYSCFG_SECURE_ACCESS_RNG LL_SYSCFG_SECURE_ACCESS_RNG /*!< Enabling the security access of Random Number Generator */
@ -382,9 +386,11 @@
*/ */
#define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM) #define __HAL_SYSCFG_REMAPMEMORY_SRAM() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_SRAM)
#if defined(LL_SYSCFG_REMAP_QUADSPI)
/** @brief QUADSPI mapped at 0x00000000. /** @brief QUADSPI mapped at 0x00000000.
*/ */
#define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI) #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() LL_SYSCFG_SetRemapMemory(LL_SYSCFG_REMAP_QUADSPI)
#endif
/** /**
* @brief Return the boot mode as configured by user. * @brief Return the boot mode as configured by user.
@ -393,7 +399,9 @@
* @arg @ref SYSCFG_BOOT_MAINFLASH * @arg @ref SYSCFG_BOOT_MAINFLASH
* @arg @ref SYSCFG_BOOT_SYSTEMFLASH * @arg @ref SYSCFG_BOOT_SYSTEMFLASH
* @arg @ref SYSCFG_BOOT_SRAM * @arg @ref SYSCFG_BOOT_SRAM
#if defined(LL_SYSCFG_REMAP_QUADSPI)
* @arg @ref SYSCFG_BOOT_QUADSPI * @arg @ref SYSCFG_BOOT_QUADSPI
#endif
*/ */
#define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory() #define __HAL_SYSCFG_GET_BOOT_MODE() LL_SYSCFG_GetRemapMemory()
@ -510,6 +518,7 @@
#define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU)) #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0U) && ((__PAGE__) <= 0xFFFFFFFFU))
#if defined(VREFBUF)
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \
((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1))
@ -517,16 +526,23 @@
((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE))
#define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= VREFBUF_CCR_TRIM))
#endif
#define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \
(((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9))
#if defined(LL_SYSCFG_SECURE_ACCESS_AES1)
#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \ #define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES1) == HAL_SYSCFG_SECURE_ACCESS_AES1) || \
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \ (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG)) (((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
#else
#define IS_SYSCFG_SECURITY_ACCESS(__VALUE__) ((((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_AES2) == HAL_SYSCFG_SECURE_ACCESS_AES2) || \
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_PKA) == HAL_SYSCFG_SECURE_ACCESS_PKA) || \
(((__VALUE__) & HAL_SYSCFG_SECURE_ACCESS_RNG) == HAL_SYSCFG_SECURE_ACCESS_RNG))
#endif
/** /**
* @} * @}
@ -628,11 +644,13 @@ void HAL_SYSCFG_SRAM2Erase(void);
void HAL_SYSCFG_DisableSRAMFetch(void); void HAL_SYSCFG_DisableSRAMFetch(void);
uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void); uint32_t HAL_SYSCFG_IsEnabledSRAMFetch(void);
#if defined(VREFBUF)
void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling);
void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode);
void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue);
HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void);
void HAL_SYSCFG_DisableVREFBUF(void); void HAL_SYSCFG_DisableVREFBUF(void);
#endif
void HAL_SYSCFG_EnableIOBooster(void); void HAL_SYSCFG_EnableIOBooster(void);
void HAL_SYSCFG_DisableIOBooster(void); void HAL_SYSCFG_DisableIOBooster(void);

1365
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_adc.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.c
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File diff suppressed because it is too large Load Diff

223
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_adc.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc.h
View File

@ -22,7 +22,7 @@
#define STM32WBxx_HAL_ADC_H #define STM32WBxx_HAL_ADC_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -44,7 +44,7 @@
* @{ * @{
*/ */
/** /**
* @brief ADC group regular oversampling structure definition * @brief ADC group regular oversampling structure definition
*/ */
typedef struct typedef struct
@ -66,7 +66,7 @@ typedef struct
(the oversampling buffer is zeroed during injection sequence). (the oversampling buffer is zeroed during injection sequence).
This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */
}ADC_OversamplingTypeDef; } ADC_OversamplingTypeDef;
/** /**
* @brief Structure definition of ADC instance and ADC group regular. * @brief Structure definition of ADC instance and ADC group regular.
@ -89,15 +89,19 @@ typedef struct
uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler.
This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE.
Note: The ADC clock configuration is common to all ADC instances. Note: The ADC clock configuration is common to all ADC instances.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, Note: ADC clock source and prescaler must be selected in function of system clock to not exceed ADC maximum frequency, depending on devices.
Example: STM32WB55xx ADC maximum frequency is 64MHz (corresponding to 4.27Msmp/s maximum)
Example: STM32WB50xx ADC maximum frequency is 32MHz (corresponding to 2.13Msmp/s maximum)
For ADC maximum frequency, refer to datasheet of the selected device.
Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits,
AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only
if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC
must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details.
Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level.
Note: This parameter can be modified only if all ADC instances are disabled. */ Note: This parameter can be modified only if all ADC instances are disabled. */
uint32_t Resolution; /*!< Configure the ADC resolution. uint32_t Resolution; /*!< Configure the ADC resolution.
This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */
uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left).
@ -134,7 +138,7 @@ typedef struct
uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer.
To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 16. This parameter must be a number between Min_Data = 1 and Max_Data = 16.
Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without
continuous mode or external trigger that could launch a conversion). */ continuous mode or external trigger that could launch a conversion). */
FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence
@ -151,7 +155,7 @@ typedef struct
If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead.
This parameter can be a value of @ref ADC_regular_external_trigger_source. This parameter can be a value of @ref ADC_regular_external_trigger_source.
Caution: external trigger source is common to all ADC instances. */ Caution: external trigger source is common to all ADC instances. */
uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start.
If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded.
This parameter can be a value of @ref ADC_regular_external_trigger_edge */ This parameter can be a value of @ref ADC_regular_external_trigger_edge */
@ -164,11 +168,11 @@ typedef struct
uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default).
This parameter applies to ADC group regular only. This parameter applies to ADC group regular only.
This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR.
Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear
end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function
HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear).
Note: Error reporting with respect to the conversion mode: Note: Error reporting with respect to the conversion mode:
- Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data
overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case.
- Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */
@ -179,7 +183,7 @@ typedef struct
ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */
}ADC_InitTypeDef; } ADC_InitTypeDef;
/** /**
* @brief Structure definition of ADC channel for regular group * @brief Structure definition of ADC channel for regular group
@ -232,12 +236,12 @@ typedef struct
uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data.
Offset value must be a positive number. Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF,
0x3FF, 0xFF or 0x3F respectively. 0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */ without continuous mode or external trigger that could launch a conversion). */
}ADC_ChannelConfTypeDef; } ADC_ChannelConfTypeDef;
/** /**
* @brief Structure definition of ADC analog watchdog * @brief Structure definition of ADC analog watchdog
@ -268,7 +272,7 @@ typedef struct
uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits
the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored.
Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are
impacted: the comparison of analog watchdog thresholds is done on impacted: the comparison of analog watchdog thresholds is done on
@ -284,7 +288,7 @@ typedef struct
impacted: the comparison of analog watchdog thresholds is done on impacted: the comparison of analog watchdog thresholds is done on
oversampling final computation (after ratio and shift application): oversampling final computation (after ratio and shift application):
ADC data register bitfield [15:4] (12 most significant bits). */ ADC data register bitfield [15:4] (12 most significant bits). */
}ADC_AnalogWDGConfTypeDef; } ADC_AnalogWDGConfTypeDef;
/** /**
* @brief ADC group injected contexts queue configuration * @brief ADC group injected contexts queue configuration
@ -292,12 +296,12 @@ typedef struct
*/ */
typedef struct typedef struct
{ {
uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each
HAL_ADCEx_InjectedConfigChannel() call to finally initialize HAL_ADCEx_InjectedConfigChannel() call to finally initialize
JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */
uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ uint32_t ChannelCount; /*!< Number of channels in the injected sequence */
}ADC_InjectionConfigTypeDef; } ADC_InjectionConfigTypeDef;
/** @defgroup ADC_States ADC States /** @defgroup ADC_States ADC States
* @{ * @{
@ -307,7 +311,7 @@ typedef struct
* @brief HAL ADC state machine: ADC states definition (bitfields) * @brief HAL ADC state machine: ADC states definition (bitfields)
* @note ADC state machine is managed by bitfields, state must be compared * @note ADC state machine is managed by bitfields, state must be compared
* with bit by bit. * with bit by bit.
* For example: * For example:
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
*/ */
@ -377,7 +381,7 @@ typedef struct
void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */
void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
}ADC_HandleTypeDef; } ADC_HandleTypeDef;
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/** /**
@ -752,7 +756,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @param __HANDLE__ ADC handle * @param __HANDLE__ ADC handle
* @retval None * @retval None
*/ */
#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
/** /**
* @brief Simultaneously clear and set specific bits of the handle State. * @brief Simultaneously clear and set specific bits of the handle State.
@ -766,7 +770,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** /**
* @brief Verify that a given value is aligned with the ADC resolution range. * @brief Verify that a given value is aligned with the ADC resolution range.
* @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits).
* @param __ADC_VALUE__ value checked against the resolution. * @param __ADC_VALUE__ value checked against the resolution.
* @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__)
*/ */
#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
@ -774,7 +778,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** /**
* @brief Verify the length of the scheduled regular conversions group. * @brief Verify the length of the scheduled regular conversions group.
* @param __LENGTH__ number of programmed conversions. * @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large)
*/ */
#define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL))) #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1UL)) && ((__LENGTH__) <= (16UL)))
@ -782,7 +786,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/** /**
* @brief Verify the number of scheduled regular conversions in discontinuous mode. * @brief Verify the number of scheduled regular conversions in discontinuous mode.
* @param NUMBER number of scheduled regular conversions in discontinuous mode. * @param NUMBER number of scheduled regular conversions in discontinuous mode.
* @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large) * @retval SET (NUMBER is within the maximum number of regular conversions in discontinuous mode) or RESET (NUMBER is null or too large)
*/ */
#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL))) #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1UL)) && ((NUMBER) <= (8UL)))
@ -807,7 +811,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \
((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) )
/** /**
* @brief Verify the ADC resolution setting. * @brief Verify the ADC resolution setting.
@ -818,18 +822,18 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
((__RESOLUTION__) == ADC_RESOLUTION_6B) ) ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
/** /**
* @brief Verify the ADC resolution setting when limited to 6 or 8 bits. * @brief Verify the ADC resolution setting when limited to 6 or 8 bits.
* @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits.
* @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid)
*/ */
#define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
((__RESOLUTION__) == ADC_RESOLUTION_6B) ) ((__RESOLUTION__) == ADC_RESOLUTION_6B) )
/** /**
* @brief Verify the ADC converted data alignment. * @brief Verify the ADC converted data alignment.
* @param __ALIGN__ programmed ADC converted data alignment. * @param __ALIGN__ programmed ADC converted data alignment.
* @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid)
*/ */
#define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
@ -939,7 +943,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
/* Minimum ADC Clock frequency is 0.14 MHz */ /* Minimum ADC Clock frequency is 0.14 MHz */
/* Maximum conversion time is */ /* Maximum conversion time is */
/* 653 / 0.14 MHz = 4.66 ms */ /* 653 / 0.14 MHz = 4.66 ms */
#define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */ #define ADC_STOP_CONVERSION_TIMEOUT ( 5UL) /*!< ADC stop time-out value */
/* Delay for temperature sensor stabilization time. */ /* Delay for temperature sensor stabilization time. */
/* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */
@ -969,10 +973,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
do{ \ do{ \
(__HANDLE__)->State = HAL_ADC_STATE_RESET; \ (__HANDLE__)->State = HAL_ADC_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0) } while(0)
#else #else
#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \
((__HANDLE__)->State = HAL_ADC_STATE_RESET) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
@ -993,7 +997,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval None * @retval None
*/ */
#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1014,7 +1018,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval None * @retval None
*/ */
#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
@ -1034,28 +1038,28 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog)
* @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog)
* @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source.
* @retval State of interruption (SET or RESET) * @retval State of interruption (SET or RESET)
*/ */
#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
(((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__))
/** /**
* @brief Check whether the specified ADC flag is set or not. * @brief Check whether the specified ADC flag is set or not.
* @param __HANDLE__ ADC handle * @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag * @param __FLAG__ ADC flag
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref ADC_FLAG_RDY ADC Ready flag * @arg @ref ADC_FLAG_RDY ADC Ready flag
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag * @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @retval State of flag (TRUE or FALSE). * @retval State of flag (TRUE or FALSE).
*/ */
#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \
@ -1066,17 +1070,17 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @param __HANDLE__ ADC handle * @param __HANDLE__ ADC handle
* @param __FLAG__ ADC flag * @param __FLAG__ ADC flag
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref ADC_FLAG_RDY ADC Ready flag * @arg @ref ADC_FLAG_RDY ADC Ready flag
* @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag
* @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag
* @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag
* @arg @ref ADC_FLAG_OVR ADC overrun flag * @arg @ref ADC_FLAG_OVR ADC overrun flag
* @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag
* @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag
* @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog)
* @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog)
* @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag.
* @retval None * @retval None
*/ */
/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */
@ -1129,7 +1133,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @retval Value between Min_Data=0 and Max_Data=18 * @retval Value between Min_Data=0 and Max_Data=18
*/ */
#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \
__LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__))
/** /**
* @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x
@ -1169,7 +1173,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL().
*/ */
#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \
__LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__))
/** /**
* @brief Helper macro to determine whether the selected channel * @brief Helper macro to determine whether the selected channel
@ -1218,7 +1222,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel.
*/ */
#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \
__LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__))
/** /**
* @brief Helper macro to convert a channel defined from parameter * @brief Helper macro to convert a channel defined from parameter
@ -1281,7 +1285,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @arg @ref ADC_CHANNEL_18 * @arg @ref ADC_CHANNEL_18
*/ */
#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \
__LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__))
/** /**
* @brief Helper macro to determine whether the internal channel * @brief Helper macro to determine whether the internal channel
@ -1305,7 +1309,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* Value "1" if the internal channel selected is available on the ADC instance selected. * Value "1" if the internal channel selected is available on the ADC instance selected.
*/ */
#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \
__LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__))
/** /**
* @brief Helper macro to select the ADC common instance * @brief Helper macro to select the ADC common instance
@ -1318,7 +1322,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @retval ADC common register instance * @retval ADC common register instance
*/ */
#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \
__LL_ADC_COMMON_INSTANCE((__ADCx__)) __LL_ADC_COMMON_INSTANCE((__ADCx__))
/** /**
* @brief Helper macro to check if all ADC instances sharing the same * @brief Helper macro to check if all ADC instances sharing the same
@ -1338,7 +1342,7 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* is enabled. * is enabled.
*/ */
#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \
__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__))
/** /**
* @brief Helper macro to define the ADC conversion data full-scale digital * @brief Helper macro to define the ADC conversion data full-scale digital
@ -1354,12 +1358,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @retval ADC conversion data full-scale digital value * @retval ADC conversion data full-scale digital value
*/ */
#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \
__LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__))
/** /**
* @brief Helper macro to convert the ADC conversion data from * @brief Helper macro to convert the ADC conversion data from
* a resolution to another resolution. * a resolution to another resolution.
* @param __DATA__ ADC conversion data to be converted * @param __DATA__ ADC conversion data to be converted
* @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref ADC_RESOLUTION_12B * @arg @ref ADC_RESOLUTION_12B
@ -1377,9 +1381,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\
__ADC_RESOLUTION_CURRENT__,\ __ADC_RESOLUTION_CURRENT__,\
__ADC_RESOLUTION_TARGET__) \ __ADC_RESOLUTION_TARGET__) \
__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__), \
(__ADC_RESOLUTION_CURRENT__),\ (__ADC_RESOLUTION_CURRENT__), \
(__ADC_RESOLUTION_TARGET__)) (__ADC_RESOLUTION_TARGET__))
/** /**
* @brief Helper macro to calculate the voltage (unit: mVolt) * @brief Helper macro to calculate the voltage (unit: mVolt)
@ -1400,9 +1404,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\
__ADC_DATA__,\ __ADC_DATA__,\
__ADC_RESOLUTION__) \ __ADC_RESOLUTION__) \
__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__), \
(__ADC_DATA__),\ (__ADC_DATA__), \
(__ADC_RESOLUTION__)) (__ADC_RESOLUTION__))
/** /**
* @brief Helper macro to calculate analog reference voltage (Vref+) * @brief Helper macro to calculate analog reference voltage (Vref+)
@ -1431,8 +1435,8 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
*/ */
#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\
__ADC_RESOLUTION__) \ __ADC_RESOLUTION__) \
__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__), \
(__ADC_RESOLUTION__)) (__ADC_RESOLUTION__))
/** /**
* @brief Helper macro to calculate the temperature (unit: degree Celsius) * @brief Helper macro to calculate the temperature (unit: degree Celsius)
@ -1482,9 +1486,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
#define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\ __TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \ __ADC_RESOLUTION__) \
__LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__), \
(__TEMPSENSOR_ADC_DATA__),\ (__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__)) (__ADC_RESOLUTION__))
/** /**
* @brief Helper macro to calculate the temperature (unit: degree Celsius) * @brief Helper macro to calculate the temperature (unit: degree Celsius)
@ -1536,12 +1540,12 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
__VREFANALOG_VOLTAGE__,\ __VREFANALOG_VOLTAGE__,\
__TEMPSENSOR_ADC_DATA__,\ __TEMPSENSOR_ADC_DATA__,\
__ADC_RESOLUTION__) \ __ADC_RESOLUTION__) \
__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__), \
(__TEMPSENSOR_TYP_CALX_V__),\ (__TEMPSENSOR_TYP_CALX_V__), \
(__TEMPSENSOR_CALX_TEMP__),\ (__TEMPSENSOR_CALX_TEMP__), \
(__VREFANALOG_VOLTAGE__),\ (__VREFANALOG_VOLTAGE__), \
(__TEMPSENSOR_ADC_DATA__),\ (__TEMPSENSOR_ADC_DATA__), \
(__ADC_RESOLUTION__)) (__ADC_RESOLUTION__))
/** /**
* @} * @}
@ -1564,14 +1568,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to
* @{ * @{
*/ */
/* Initialization and de-initialization functions ****************************/ /* Initialization and de-initialization functions ****************************/
HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc);
void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc);
#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/ /* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
pADC_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
/** /**
@ -1585,39 +1590,39 @@ HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_Ca
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout);
/* Non-blocking mode: Interruption */ /* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc);
/* Non-blocking mode: DMA */ /* Non-blocking mode: DMA */
HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length);
HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */ /* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}
*/ */
/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions
* @brief Peripheral Control functions * @brief Peripheral Control functions
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig);
HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig);
/** /**
* @} * @}
@ -1627,7 +1632,7 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_Ana
/** @addtogroup ADC_Exported_Functions_Group4 /** @addtogroup ADC_Exported_Functions_Group4
* @{ * @{
*/ */
uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc);
uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** /**
@ -1642,9 +1647,9 @@ uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
/** @addtogroup ADC_Private_Functions ADC Private Functions /** @addtogroup ADC_Private_Functions ADC Private Functions
* @{ * @{
*/ */
HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup);
HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc);
void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
void ADC_DMAError(DMA_HandleTypeDef *hdma); void ADC_DMAError(DMA_HandleTypeDef *hdma);

669
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_adc_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.c
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File diff suppressed because it is too large Load Diff

177
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_adc_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_adc_ex.h
View File

@ -22,7 +22,7 @@
#define STM32WBxx_HAL_ADC_EX_H #define STM32WBxx_HAL_ADC_EX_H
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -48,12 +48,12 @@ typedef struct
{ {
uint32_t Ratio; /*!< Configures the oversampling ratio. uint32_t Ratio; /*!< Configures the oversampling ratio.
This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */
uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler.
This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */
}ADC_InjOversamplingTypeDef; } ADC_InjOversamplingTypeDef;
/** /**
* @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected * @brief Structure definition of ADC group injected and ADC channel affected to ADC group injected
* @note Parameters of this structure are shared within 2 scopes: * @note Parameters of this structure are shared within 2 scopes:
* - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset * - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime , InjectedSingleDiff, InjectedOffsetNumber, InjectedOffset
@ -64,7 +64,7 @@ typedef struct
* - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff') * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'InjectedSingleDiff')
* - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group. * - For parameters 'InjectedDiscontinuousConvMode', 'QueueInjectedContext', 'InjecOversampling': ADC enabled without conversion on going on injected group.
* - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups. * - For parameters 'InjectedSamplingTime', 'InjectedOffset', 'InjectedOffsetNumber', 'AutoInjectedConv': ADC enabled without conversion on going on regular and injected groups.
* - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going * - For parameters 'InjectedChannel', 'InjectedRank', 'InjectedNbrOfConversion', 'ExternalTrigInjecConv', 'ExternalTrigInjecConvEdge': ADC enabled and while conversion on going
* on ADC groups regular and injected. * on ADC groups regular and injected.
* If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
* without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly). * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) on the fly).
@ -77,7 +77,7 @@ typedef struct
uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer. uint32_t InjectedRank; /*!< Specifies the rank in the ADC group injected sequencer.
This parameter must be a value of @ref ADC_INJ_SEQ_RANKS. This parameter must be a value of @ref ADC_INJ_SEQ_RANKS.
Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by
the new channel setting (or parameter number of conversions adjusted) */ the new channel setting (or parameter number of conversions adjusted) */
uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel. uint32_t InjectedSamplingTime; /*!< Sampling time value to be set for the selected channel.
@ -100,7 +100,7 @@ typedef struct
Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. Note: Refer to Reference Manual to ensure the selected channel is available in differential mode.
Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case
of another parameter update on the fly) */ of another parameter update on the fly) */
uint32_t InjectedOffsetNumber; /*!< Selects the offset number. uint32_t InjectedOffsetNumber; /*!< Selects the offset number.
@ -111,27 +111,27 @@ typedef struct
Offset value must be a positive number. Offset value must be a positive number.
Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number
between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively.
Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled
without continuous mode or external trigger that could launch a conversion). */ without continuous mode or external trigger that could launch a conversion). */
uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer. uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ranks that will be converted within the ADC group injected sequencer.
To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
This parameter must be a number between Min_Data = 1 and Max_Data = 4. This parameter must be a number between Min_Data = 1 and Max_Data = 4.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence FunctionalState InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of ADC group injected is performed in Complete-sequence/Discontinuous-sequence
(main sequence subdivided in successive parts). (main sequence subdivided in successive parts).
Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
Discontinuous mode can be enabled only if continuous mode is disabled. Discontinuous mode can be enabled only if continuous mode is disabled.
This parameter can be set to ENABLE or DISABLE. This parameter can be set to ENABLE or DISABLE.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank). Note: For injected group, discontinuous mode converts the sequence channel by channel (discontinuous length fixed to 1 rank).
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one FunctionalState AutoInjectedConv; /*!< Enables or disables the selected ADC group injected automatic conversion after regular one
This parameter can be set to ENABLE or DISABLE. This parameter can be set to ENABLE or DISABLE.
Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE) Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START) Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_INJECTED_SOFTWARE_START)
Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete. Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
@ -142,11 +142,11 @@ typedef struct
FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled. FunctionalState QueueInjectedContext; /*!< Specifies whether the context queue feature is enabled.
This parameter can be set to ENABLE or DISABLE. This parameter can be set to ENABLE or DISABLE.
If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a If context queue is enabled, injected sequencer&channels configurations are queued on up to 2 contexts. If a
new injected context is set when queue is full, error is triggered by interruption and through function new injected context is set when queue is full, error is triggered by interruption and through function
'HAL_ADCEx_InjectedQueueOverflowCallback'. 'HAL_ADCEx_InjectedQueueOverflowCallback'.
Caution: This feature request that the sequence is fully configured before injected conversion start. Caution: This feature request that the sequence is fully configured before injected conversion start.
Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter. Therefore, configure channels with as many calls to HAL_ADCEx_InjectedConfigChannel() as the 'InjectedNbrOfConversion' parameter.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. configure a channel on injected group can impact the configuration of other channels previously set.
Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */ Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). */
@ -159,7 +159,7 @@ typedef struct
uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group. uint32_t ExternalTrigInjecConvEdge; /*!< Selects the external trigger edge of injected group.
This parameter can be a value of @ref ADC_injected_external_trigger_edge. This parameter can be a value of @ref ADC_injected_external_trigger_edge.
If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded. If trigger source is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
configure a channel on injected group can impact the configuration of other channels previously set. */ configure a channel on injected group can impact the configuration of other channels previously set. */
FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled. FunctionalState InjecOversamplingMode; /*!< Specifies whether the oversampling feature is enabled or disabled.
@ -167,9 +167,9 @@ typedef struct
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters. ADC_InjOversamplingTypeDef InjecOversampling; /*!< Specifies the Oversampling parameters.
Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled. Caution: this setting overwrites the previous oversampling configuration if oversampling already enabled.
Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */
}ADC_InjectionConfTypeDef; } ADC_InjectionConfTypeDef;
/** /**
* @} * @}
@ -199,10 +199,10 @@ typedef struct
/** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected) /** @defgroup ADC_injected_external_trigger_edge ADC group injected trigger edge (when external trigger is selected)
* @{ * @{
*/ */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE (0x00000000UL) /*!< Injected conversions hardware trigger detection disabled */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING (ADC_JSQR_JEXTEN_0) /*!< Injected conversions hardware trigger detection on the rising edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING (ADC_JSQR_JEXTEN_1) /*!< Injected conversions hardware trigger detection on the falling edge */
#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */ #define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING (ADC_JSQR_JEXTEN) /*!< Injected conversions hardware trigger detection on both the rising and falling edges */
/** /**
* @} * @}
*/ */
@ -261,7 +261,7 @@ typedef struct
/** /**
* @} * @}
*/ */
/** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields /** @defgroup ADC_SMPR1_fields ADCx SMPR1 fields
* @{ * @{
*/ */
@ -273,7 +273,7 @@ typedef struct
* @} * @}
*/ */
/** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields /** @defgroup ADC_CFGR_fields_2 ADCx CFGR sub fields
* @{ * @{
*/ */
/* ADC_CFGR fields of parameters that can be updated when no conversion /* ADC_CFGR fields of parameters that can be updated when no conversion
@ -310,7 +310,7 @@ typedef struct
/** /**
* @brief Check whether or not ADC is independent. * @brief Check whether or not ADC is independent.
* @param __HANDLE__ ADC handle. * @param __HANDLE__ ADC handle.
* @note When multimode feature is not available, the macro always returns SET. * @note When multimode feature is not available, the macro always returns SET.
* @retval SET (ADC is independent) or RESET (ADC is not). * @retval SET (ADC is independent) or RESET (ADC is not).
*/ */
#define ADC_IS_INDEPENDENT(__HANDLE__) (SET) #define ADC_IS_INDEPENDENT(__HANDLE__) (SET)
@ -374,7 +374,7 @@ typedef struct
/** /**
* @brief Shift the offset with respect to the selected ADC resolution. * @brief Shift the offset with respect to the selected ADC resolution.
* @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0. * @note Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0.
* If resolution 12 bits, no shift. * If resolution 12 bits, no shift.
* If resolution 10 bits, shift of 2 ranks on the left. * If resolution 10 bits, shift of 2 ranks on the left.
@ -386,7 +386,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \ #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, __OFFSET__) \
((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) ((__OFFSET__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
/** /**
* @brief Shift the AWD1 threshold with respect to the selected ADC resolution. * @brief Shift the AWD1 threshold with respect to the selected ADC resolution.
@ -401,7 +401,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) ((__THRESHOLD__) << ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL))
/** /**
* @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution. * @brief Shift the AWD2 and AWD3 threshold with respect to the selected ADC resolution.
@ -416,8 +416,8 @@ typedef struct
*/ */
#define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \ #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, __THRESHOLD__) \
((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \ ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) != (ADC_CFGR_RES_1 | ADC_CFGR_RES_0)) ? \
((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \ ((__THRESHOLD__) >> ((4UL - ((((__HANDLE__)->Instance->CFGR & ADC_CFGR_RES) >> 3UL) * 2UL)) & 0x1FUL)) : \
((__THRESHOLD__) << 2UL) \ ((__THRESHOLD__) << 2UL) \
) )
/** /**
@ -455,7 +455,7 @@ typedef struct
/** /**
* @brief Verify the length of scheduled injected conversions group. * @brief Verify the length of scheduled injected conversions group.
* @param __LENGTH__ number of programmed conversions. * @param __LENGTH__ number of programmed conversions.
* @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large) * @retval SET (__LENGTH__ is within the maximum number of possible programmable injected conversions) or RESET (__LENGTH__ is null or too large)
*/ */
#define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U))) #define IS_ADC_INJECTED_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (4U)))
@ -471,7 +471,7 @@ typedef struct
/** /**
* @brief Verify the ADC channel setting. * @brief Verify the ADC channel setting.
* @param __HANDLE__ ADC handle. * @param __HANDLE__ ADC handle.
* @param __CHANNEL__ programmed ADC channel. * @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/ */
#define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \ #define IS_ADC_CHANNEL(__HANDLE__, __CHANNEL__) ((((__HANDLE__)->Instance) == ADC1) && \
@ -501,7 +501,7 @@ typedef struct
/** /**
* @brief Verify the ADC channel setting in differential mode. * @brief Verify the ADC channel setting in differential mode.
* @param __HANDLE__ ADC handle. * @param __HANDLE__ ADC handle.
* @param __CHANNEL__ programmed ADC channel. * @param __CHANNEL__ programmed ADC channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/ */
#define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \ #define IS_ADC_DIFF_CHANNEL(__HANDLE__, __CHANNEL__) (((__CHANNEL__) == ADC_CHANNEL_1) || \
@ -522,7 +522,7 @@ typedef struct
/** /**
* @brief Verify the ADC single-ended input or differential mode setting. * @brief Verify the ADC single-ended input or differential mode setting.
* @param __SING_DIFF__ programmed channel setting. * @param __SING_DIFF__ programmed channel setting.
* @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid) * @retval SET (__SING_DIFF__ is valid) or RESET (__SING_DIFF__ is invalid)
*/ */
#define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \ #define IS_ADC_SINGLE_DIFFERENTIAL(__SING_DIFF__) (((__SING_DIFF__) == ADC_SINGLE_ENDED) || \
@ -530,24 +530,24 @@ typedef struct
/** /**
* @brief Verify the ADC offset management setting. * @brief Verify the ADC offset management setting.
* @param __OFFSET_NUMBER__ ADC offset management. * @param __OFFSET_NUMBER__ ADC offset management.
* @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid) * @retval SET (__OFFSET_NUMBER__ is valid) or RESET (__OFFSET_NUMBER__ is invalid)
*/ */
#define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \ #define IS_ADC_OFFSET_NUMBER(__OFFSET_NUMBER__) (((__OFFSET_NUMBER__) == ADC_OFFSET_NONE) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_1) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_2) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \ ((__OFFSET_NUMBER__) == ADC_OFFSET_3) || \
((__OFFSET_NUMBER__) == ADC_OFFSET_4) ) ((__OFFSET_NUMBER__) == ADC_OFFSET_4) )
/** /**
* @brief Verify the ADC injected channel setting. * @brief Verify the ADC injected channel setting.
* @param __CHANNEL__ programmed ADC injected channel. * @param __CHANNEL__ programmed ADC injected channel.
* @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid)
*/ */
#define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \ #define IS_ADC_INJECTED_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_INJECTED_RANK_1) || \
((__CHANNEL__) == ADC_INJECTED_RANK_2) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_2) || \
((__CHANNEL__) == ADC_INJECTED_RANK_3) || \ ((__CHANNEL__) == ADC_INJECTED_RANK_3) || \
((__CHANNEL__) == ADC_INJECTED_RANK_4) ) ((__CHANNEL__) == ADC_INJECTED_RANK_4) )
/** /**
* @brief Verify the ADC injected conversions external trigger. * @brief Verify the ADC injected conversions external trigger.
@ -567,11 +567,11 @@ typedef struct
* @brief Verify the ADC edge trigger setting for injected group. * @brief Verify the ADC edge trigger setting for injected group.
* @param __EDGE__ programmed ADC edge trigger setting. * @param __EDGE__ programmed ADC edge trigger setting.
* @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid)
*/ */
#define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \ #define IS_ADC_EXTTRIGINJEC_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \ ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING) || \
((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) ) ((__EDGE__) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING) )
/** /**
* @brief Verify the ADC analog watchdog setting. * @brief Verify the ADC analog watchdog setting.
@ -580,7 +580,7 @@ typedef struct
*/ */
#define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \ #define IS_ADC_ANALOG_WATCHDOG_NUMBER(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_1) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \ ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_2) || \
((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) ) ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_3) )
/** /**
* @brief Verify the ADC analog watchdog mode setting. * @brief Verify the ADC analog watchdog mode setting.
@ -593,31 +593,31 @@ typedef struct
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \ ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) ) ((__WATCHDOG_MODE__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) )
/** /**
* @brief Verify the ADC conversion (regular or injected or both). * @brief Verify the ADC conversion (regular or injected or both).
* @param __CONVERSION__ ADC conversion group. * @param __CONVERSION__ ADC conversion group.
* @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid) * @retval SET (__CONVERSION__ is valid) or RESET (__CONVERSION__ is invalid)
*/ */
#define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \ #define IS_ADC_CONVERSION_GROUP(__CONVERSION__) (((__CONVERSION__) == ADC_REGULAR_GROUP) || \
((__CONVERSION__) == ADC_INJECTED_GROUP) || \ ((__CONVERSION__) == ADC_INJECTED_GROUP) || \
((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) ) ((__CONVERSION__) == ADC_REGULAR_INJECTED_GROUP) )
/** /**
* @brief Verify the ADC event type. * @brief Verify the ADC event type.
* @param __EVENT__ ADC event. * @param __EVENT__ ADC event.
* @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid) * @retval SET (__EVENT__ is valid) or RESET (__EVENT__ is invalid)
*/ */
#define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \ #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_EOSMP_EVENT) || \
((__EVENT__) == ADC_AWD_EVENT) || \ ((__EVENT__) == ADC_AWD_EVENT) || \
((__EVENT__) == ADC_AWD2_EVENT) || \ ((__EVENT__) == ADC_AWD2_EVENT) || \
((__EVENT__) == ADC_AWD3_EVENT) || \ ((__EVENT__) == ADC_AWD3_EVENT) || \
((__EVENT__) == ADC_OVR_EVENT) || \ ((__EVENT__) == ADC_OVR_EVENT) || \
((__EVENT__) == ADC_JQOVF_EVENT) ) ((__EVENT__) == ADC_JQOVF_EVENT) )
/** /**
* @brief Verify the ADC oversampling ratio. * @brief Verify the ADC oversampling ratio.
* @param __RATIO__ programmed ADC oversampling ratio. * @param __RATIO__ programmed ADC oversampling ratio.
* @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid)
*/ */
@ -631,7 +631,7 @@ typedef struct
((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 ))
/** /**
* @brief Verify the ADC oversampling shift. * @brief Verify the ADC oversampling shift.
* @param __SHIFT__ programmed ADC oversampling shift. * @param __SHIFT__ programmed ADC oversampling shift.
* @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid)
*/ */
@ -646,37 +646,37 @@ typedef struct
((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 ))
/** /**
* @brief Verify the ADC oversampling triggered mode. * @brief Verify the ADC oversampling triggered mode.
* @param __MODE__ programmed ADC oversampling triggered mode. * @param __MODE__ programmed ADC oversampling triggered mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/ */
#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ #define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \
((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) )
/** /**
* @brief Verify the ADC oversampling regular conversion resumed or continued mode. * @brief Verify the ADC oversampling regular conversion resumed or continued mode.
* @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode. * @param __MODE__ programmed ADC oversampling regular conversion resumed or continued mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/ */
#define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \ #define IS_ADC_REGOVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_REGOVERSAMPLING_CONTINUED_MODE) || \
((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) ) ((__MODE__) == ADC_REGOVERSAMPLING_RESUMED_MODE) )
/** /**
* @brief Verify the DFSDM mode configuration. * @brief Verify the DFSDM mode configuration.
* @param __HANDLE__ ADC handle. * @param __HANDLE__ ADC handle.
* @note When DMSDFM configuration is not supported, the macro systematically reports SET. For * @note When DMSDFM configuration is not supported, the macro systematically reports SET. For
* this reason, the input parameter is the ADC handle and not the configuration parameter * this reason, the input parameter is the ADC handle and not the configuration parameter
* directly. * directly.
* @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid) * @retval SET (DFSDM mode configuration is valid) or RESET (DFSDM mode configuration is invalid)
*/ */
#define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET) #define IS_ADC_DFSDMCFG_MODE(__HANDLE__) (SET)
/** /**
* @brief Return the DFSDM configuration mode. * @brief Return the DFSDM configuration mode.
* @param __HANDLE__ ADC handle. * @param __HANDLE__ ADC handle.
* @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled). * @note When DMSDFM configuration is not supported, the macro systematically reports 0x0 (i.e disabled).
* For this reason, the input parameter is the ADC handle and not the configuration parameter * For this reason, the input parameter is the ADC handle and not the configuration parameter
* directly. * directly.
* @retval DFSDM configuration mode * @retval DFSDM configuration mode
*/ */
#define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL) #define ADC_CFGR_DFSDM(__HANDLE__) (0x0UL)
@ -697,33 +697,34 @@ typedef struct
/* IO operation functions *****************************************************/ /* IO operation functions *****************************************************/
/* ADC calibration */ /* ADC calibration */
HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t SingleDiff); HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff); uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff);
HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff, uint32_t CalibrationFactor); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t SingleDiff,
uint32_t CalibrationFactor);
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout);
/* Non-blocking mode: Interruption */ /* Non-blocking mode: Interruption */
HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc);
/* ADC retrieve conversion value intended to be used with polling or interruption */ /* ADC retrieve conversion value intended to be used with polling or interruption */
uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank); uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef *hadc, uint32_t InjectedRank);
/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc);
void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef* hadc); void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc);
/* ADC group regular conversions stop */ /* ADC group regular conversions stop */
HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}
*/ */
@ -732,11 +733,11 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc);
* @{ * @{
*/ */
/* Peripheral Control functions ***********************************************/ /* Peripheral Control functions ***********************************************/
HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected); HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef *hadc,ADC_InjectionConfTypeDef* sConfigInjected);
HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_EnableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_DisableInjectedQueue(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc);
HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef* hadc); HAL_StatusTypeDef HAL_ADCEx_EnterADCDeepPowerDownMode(ADC_HandleTypeDef *hadc);
/** /**
* @} * @}

208
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_comp.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_comp.c
View File

@ -3,14 +3,14 @@
* @file stm32wbxx_hal_comp.c * @file stm32wbxx_hal_comp.c
* @author MCD Application Team * @author MCD Application Team
* @brief COMP HAL module driver. * @brief COMP HAL module driver.
* This file provides firmware functions to manage the following * This file provides firmware functions to manage the following
* functionalities of the COMP peripheral: * functionalities of the COMP peripheral:
* + Initialization and de-initialization functions * + Initialization and de-initialization functions
* + Start/Stop operation functions in polling mode * + Start/Stop operation functions in polling mode
* + Start/Stop operation functions in interrupt mode (through EXTI interrupt) * + Start/Stop operation functions in interrupt mode (through EXTI interrupt)
* + Peripheral control functions * + Peripheral control functions
* + Peripheral state functions * + Peripheral state functions
* *
@verbatim @verbatim
================================================================================ ================================================================================
##### COMP Peripheral features ##### ##### COMP Peripheral features #####
@ -22,18 +22,18 @@
(#) Comparators input minus (inverting input) and input plus (non inverting input) (#) Comparators input minus (inverting input) and input plus (non inverting input)
can be set to internal references or to GPIO pins can be set to internal references or to GPIO pins
(refer to GPIO list in reference manual). (refer to GPIO list in reference manual).
(#) Comparators output level is available using HAL_COMP_GetOutputLevel() (#) Comparators output level is available using HAL_COMP_GetOutputLevel()
and can be redirected to other peripherals: GPIO pins (in mode and can be redirected to other peripherals: GPIO pins (in mode
alternate functions for comparator), timers. alternate functions for comparator), timers.
(refer to GPIO list in reference manual). (refer to GPIO list in reference manual).
(#) The comparators have interrupt capability through the EXTI controller (#) The comparators have interrupt capability through the EXTI controller
with wake-up from sleep and stop modes. with wake-up from sleep and stop modes.
(#) Pairs of comparators instances can be combined in window mode (#) Pairs of comparators instances can be combined in window mode
(2 consecutive instances odd and even COMP<x> and COMP<x+1>). (2 consecutive instances odd and even COMP<x> and COMP<x+1>).
From the corresponding IRQ handler, the right interrupt source can be retrieved From the corresponding IRQ handler, the right interrupt source can be retrieved
using macro __HAL_COMP_COMPx_EXTI_GET_FLAG(). using macro __HAL_COMP_COMPx_EXTI_GET_FLAG().
@ -42,18 +42,18 @@
[..] [..]
This driver provides functions to configure and program the comparator instances This driver provides functions to configure and program the comparator instances
of STM32WBxx devices. of STM32WBxx devices.
To use the comparator, perform the following steps: To use the comparator, perform the following steps:
(#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit(): (#) Initialize the COMP low level resources by implementing the HAL_COMP_MspInit():
(++) Configure the GPIO connected to comparator inputs plus and minus in analog mode (++) Configure the GPIO connected to comparator inputs plus and minus in analog mode
using HAL_GPIO_Init(). using HAL_GPIO_Init().
(++) If needed, configure the GPIO connected to comparator output in alternate function mode (++) If needed, configure the GPIO connected to comparator output in alternate function mode
using HAL_GPIO_Init(). using HAL_GPIO_Init().
(++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and (++) If required enable the COMP interrupt by configuring and enabling EXTI line in Interrupt mode and
selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator selecting the desired sensitivity level using HAL_GPIO_Init() function. After that enable the comparator
interrupt vector using HAL_NVIC_EnableIRQ() function. interrupt vector using HAL_NVIC_EnableIRQ() function.
(#) Configure the comparator using HAL_COMP_Init() function: (#) Configure the comparator using HAL_COMP_Init() function:
(++) Select the input minus (inverting input) (++) Select the input minus (inverting input)
(++) Select the input plus (non-inverting input) (++) Select the input plus (non-inverting input)
@ -62,29 +62,29 @@
(++) Select the output polarity (++) Select the output polarity
(++) Select the power mode (++) Select the power mode
(++) Select the window mode (++) Select the window mode
-@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE() -@@- HAL_COMP_Init() calls internally __HAL_RCC_SYSCFG_CLK_ENABLE()
to enable internal control clock of the comparators. to enable internal control clock of the comparators.
However, this is a legacy strategy. In future STM32 families, However, this is a legacy strategy. In future STM32 families,
COMP clock enable must be implemented by user in "HAL_COMP_MspInit()". COMP clock enable must be implemented by user in "HAL_COMP_MspInit()".
Therefore, for compatibility anticipation, it is recommended to Therefore, for compatibility anticipation, it is recommended to
implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()". implement __HAL_RCC_SYSCFG_CLK_ENABLE() in "HAL_COMP_MspInit()".
(#) Reconfiguration on-the-fly of comparator can be done by calling again (#) Reconfiguration on-the-fly of comparator can be done by calling again
function HAL_COMP_Init() with new input structure parameters values. function HAL_COMP_Init() with new input structure parameters values.
(#) Enable the comparator using HAL_COMP_Start() function. (#) Enable the comparator using HAL_COMP_Start() function.
(#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions (#) Use HAL_COMP_TriggerCallback() or HAL_COMP_GetOutputLevel() functions
to manage comparator outputs (events and output level). to manage comparator outputs (events and output level).
(#) Disable the comparator using HAL_COMP_Stop() function. (#) Disable the comparator using HAL_COMP_Stop() function.
(#) De-initialize the comparator using HAL_COMP_DeInit() function. (#) De-initialize the comparator using HAL_COMP_DeInit() function.
(#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function. (#) For safety purpose, comparator configuration can be locked using HAL_COMP_Lock() function.
The only way to unlock the comparator is a device hardware reset. The only way to unlock the comparator is a device hardware reset.
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..] [..]
@ -141,7 +141,7 @@
When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or When the compilation flag USE_HAL_COMP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
@ -168,7 +168,7 @@
#ifdef HAL_COMP_MODULE_ENABLED #ifdef HAL_COMP_MODULE_ENABLED
#if defined (COMP1) || defined (COMP2)
/** @defgroup COMP COMP /** @defgroup COMP COMP
* @brief COMP HAL module driver * @brief COMP HAL module driver
@ -209,14 +209,14 @@
* @{ * @{
*/ */
/** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions /** @defgroup COMP_Exported_Functions_Group1 Initialization/de-initialization functions
* @brief Initialization and de-initialization functions. * @brief Initialization and de-initialization functions.
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Initialization and de-initialization functions ##### ##### Initialization and de-initialization functions #####
=============================================================================== ===============================================================================
[..] This section provides functions to initialize and de-initialize comparators [..] This section provides functions to initialize and de-initialize comparators
@endverbatim @endverbatim
* @{ * @{
@ -237,7 +237,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */ uint32_t comp_voltage_scaler_initialized; /* Value "0" if comparator voltage scaler is not initialized */
__IO uint32_t wait_loop_index = 0UL; __IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */ /* Check the COMP handle allocation and lock status */
if(hcomp == NULL) if(hcomp == NULL)
{ {
@ -256,19 +256,19 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol)); assert_param(IS_COMP_OUTPUTPOL(hcomp->Init.OutputPol));
assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode)); assert_param(IS_COMP_POWERMODE(hcomp->Init.Mode));
assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis)); assert_param(IS_COMP_HYSTERESIS(hcomp->Init.Hysteresis));
assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce)); assert_param(IS_COMP_BLANKINGSRC_INSTANCE(hcomp->Instance, hcomp->Init.BlankingSrce));
assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode)); assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode)); assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
if(hcomp->State == HAL_COMP_STATE_RESET) if(hcomp->State == HAL_COMP_STATE_RESET)
{ {
/* Allocate lock resource and initialize it */ /* Allocate lock resource and initialize it */
hcomp->Lock = HAL_UNLOCKED; hcomp->Lock = HAL_UNLOCKED;
/* Set COMP error code to none */ /* Set COMP error code to none */
COMP_CLEAR_ERRORCODE(hcomp); COMP_CLEAR_ERRORCODE(hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Init the COMP Callback settings */ /* Init the COMP Callback settings */
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
@ -277,7 +277,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ {
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
} }
/* Init the low level hardware */ /* Init the low level hardware */
/* Note: Internal control clock of the comparators must */ /* Note: Internal control clock of the comparators must */
/* be enabled in "HAL_COMP_MspInit()" */ /* be enabled in "HAL_COMP_MspInit()" */
@ -291,10 +291,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
HAL_COMP_MspInit(hcomp); HAL_COMP_MspInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
} }
/* Memorize voltage scaler state before initialization */ /* Memorize voltage scaler state before initialization */
comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN); comp_voltage_scaler_initialized = READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN);
/* Set COMP parameters */ /* Set COMP parameters */
tmp_csr = ( hcomp->Init.InputMinus tmp_csr = ( hcomp->Init.InputMinus
| hcomp->Init.InputPlus | hcomp->Init.InputPlus
@ -303,7 +303,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
| hcomp->Init.OutputPol | hcomp->Init.OutputPol
| hcomp->Init.Mode | hcomp->Init.Mode
); );
/* Set parameters in COMP register */ /* Set parameters in COMP register */
/* Note: Update all bits except read-only, lock and enable bits */ /* Note: Update all bits except read-only, lock and enable bits */
MODIFY_REG(hcomp->Instance->CSR, MODIFY_REG(hcomp->Instance->CSR,
@ -312,7 +312,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL, COMP_CSR_BLANKING | COMP_CSR_BRGEN | COMP_CSR_SCALEN | COMP_CSR_INMESEL,
tmp_csr tmp_csr
); );
/* Set window mode */ /* Set window mode */
/* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */ /* Note: Window mode bit is located into 1 out of the 2 pairs of COMP */
/* instances. Therefore, this function can update another COMP */ /* instances. Therefore, this function can update another COMP */
@ -325,7 +325,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ {
CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE); CLEAR_BIT(COMP12_COMMON->CSR, COMP_CSR_WINMODE);
} }
/* Delay for COMP scaler bridge voltage stabilization */ /* Delay for COMP scaler bridge voltage stabilization */
/* Apply the delay if voltage scaler bridge is required and not already enabled */ /* Apply the delay if voltage scaler bridge is required and not already enabled */
if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) && if ((READ_BIT(hcomp->Instance->CSR, COMP_CSR_SCALEN) != 0UL) &&
@ -341,10 +341,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
wait_loop_index--; wait_loop_index--;
} }
} }
/* Get the EXTI line corresponding to the selected COMP instance */ /* Get the EXTI line corresponding to the selected COMP instance */
exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Manage EXTI settings */ /* Manage EXTI settings */
if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL) if((hcomp->Init.TriggerMode & (COMP_EXTI_IT | COMP_EXTI_EVENT)) != 0UL)
{ {
@ -357,7 +357,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ {
LL_EXTI_DisableRisingTrig_0_31(exti_line); LL_EXTI_DisableRisingTrig_0_31(exti_line);
} }
/* Configure EXTI falling edge */ /* Configure EXTI falling edge */
if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL) if((hcomp->Init.TriggerMode & COMP_EXTI_FALLING) != 0UL)
{ {
@ -367,10 +367,10 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ {
LL_EXTI_DisableFallingTrig_0_31(exti_line); LL_EXTI_DisableFallingTrig_0_31(exti_line);
} }
/* Clear COMP EXTI pending bit (if any) */ /* Clear COMP EXTI pending bit (if any) */
LL_EXTI_ClearFlag_0_31(exti_line); LL_EXTI_ClearFlag_0_31(exti_line);
/* Configure EXTI event mode */ /* Configure EXTI event mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL) if((hcomp->Init.TriggerMode & COMP_EXTI_EVENT) != 0UL)
{ {
@ -380,7 +380,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ {
LL_EXTI_DisableEvent_0_31(exti_line); LL_EXTI_DisableEvent_0_31(exti_line);
} }
/* Configure EXTI interrupt mode */ /* Configure EXTI interrupt mode */
if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL) if((hcomp->Init.TriggerMode & COMP_EXTI_IT) != 0UL)
{ {
@ -395,11 +395,11 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
{ {
/* Disable EXTI event mode */ /* Disable EXTI event mode */
LL_EXTI_DisableEvent_0_31(exti_line); LL_EXTI_DisableEvent_0_31(exti_line);
/* Disable EXTI interrupt mode */ /* Disable EXTI interrupt mode */
LL_EXTI_DisableIT_0_31(exti_line); LL_EXTI_DisableIT_0_31(exti_line);
} }
/* Set HAL COMP handle state */ /* Set HAL COMP handle state */
/* Note: Transition from state reset to state ready, */ /* Note: Transition from state reset to state ready, */
/* otherwise (coming from state ready or busy) no state update. */ /* otherwise (coming from state ready or busy) no state update. */
@ -408,7 +408,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
hcomp->State = HAL_COMP_STATE_READY; hcomp->State = HAL_COMP_STATE_READY;
} }
} }
return status; return status;
} }
@ -422,7 +422,7 @@ HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */ /* Check the COMP handle allocation and lock status */
if(hcomp == NULL) if(hcomp == NULL)
{ {
@ -436,30 +436,30 @@ HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
{ {
/* Check the parameter */ /* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Set COMP_CSR register to reset value */ /* Set COMP_CSR register to reset value */
WRITE_REG(hcomp->Instance->CSR, 0x00000000UL); WRITE_REG(hcomp->Instance->CSR, 0x00000000UL);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
if (hcomp->MspDeInitCallback == NULL) if (hcomp->MspDeInitCallback == NULL)
{ {
hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */ hcomp->MspDeInitCallback = HAL_COMP_MspDeInit; /* Legacy weak MspDeInit */
} }
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */ /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
hcomp->MspDeInitCallback(hcomp); hcomp->MspDeInitCallback(hcomp);
#else #else
/* DeInit the low level hardware: GPIO, RCC clock, NVIC */ /* DeInit the low level hardware: GPIO, RCC clock, NVIC */
HAL_COMP_MspDeInit(hcomp); HAL_COMP_MspDeInit(hcomp);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/* Set HAL COMP handle state */ /* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_RESET; hcomp->State = HAL_COMP_STATE_RESET;
/* Release Lock */ /* Release Lock */
__HAL_UNLOCK(hcomp); __HAL_UNLOCK(hcomp);
} }
return status; return status;
} }
@ -472,7 +472,7 @@ __weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hcomp); UNUSED(hcomp);
/* NOTE : This function should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_MspInit could be implemented in the user file the HAL_COMP_MspInit could be implemented in the user file
*/ */
@ -487,7 +487,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hcomp); UNUSED(hcomp);
/* NOTE : This function should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_MspDeInit could be implemented in the user file the HAL_COMP_MspDeInit could be implemented in the user file
*/ */
@ -510,7 +510,7 @@ __weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback) HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
if (pCallback == NULL) if (pCallback == NULL)
{ {
/* Update the error code */ /* Update the error code */
@ -518,7 +518,7 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
return HAL_ERROR; return HAL_ERROR;
} }
if (HAL_COMP_STATE_READY == hcomp->State) if (HAL_COMP_STATE_READY == hcomp->State)
{ {
switch (CallbackID) switch (CallbackID)
@ -526,19 +526,19 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
case HAL_COMP_TRIGGER_CB_ID : case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = pCallback; hcomp->TriggerCallback = pCallback;
break; break;
case HAL_COMP_MSPINIT_CB_ID : case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback; hcomp->MspInitCallback = pCallback;
break; break;
case HAL_COMP_MSPDEINIT_CB_ID : case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback; hcomp->MspDeInitCallback = pCallback;
break; break;
default : default :
/* Update the error code */ /* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
break; break;
@ -551,15 +551,15 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
case HAL_COMP_MSPINIT_CB_ID : case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = pCallback; hcomp->MspInitCallback = pCallback;
break; break;
case HAL_COMP_MSPDEINIT_CB_ID : case HAL_COMP_MSPDEINIT_CB_ID :
hcomp->MspDeInitCallback = pCallback; hcomp->MspDeInitCallback = pCallback;
break; break;
default : default :
/* Update the error code */ /* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
break; break;
@ -569,11 +569,11 @@ HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_
{ {
/* Update the error code */ /* Update the error code */
hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK; hcomp->ErrorCode |= HAL_COMP_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
} }
return status; return status;
} }
@ -600,7 +600,7 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM
case HAL_COMP_TRIGGER_CB_ID : case HAL_COMP_TRIGGER_CB_ID :
hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */ hcomp->TriggerCallback = HAL_COMP_TriggerCallback; /* Legacy weak callback */
break; break;
case HAL_COMP_MSPINIT_CB_ID : case HAL_COMP_MSPINIT_CB_ID :
hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */ hcomp->MspInitCallback = HAL_COMP_MspInit; /* Legacy weak MspInit */
break; break;
@ -657,13 +657,13 @@ HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COM
* @} * @}
*/ */
/** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions /** @defgroup COMP_Exported_Functions_Group2 Start-Stop operation functions
* @brief Start-Stop operation functions. * @brief Start-Stop operation functions.
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### IO operation functions ##### ##### IO operation functions #####
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Start a comparator instance. (+) Start a comparator instance.
(+) Stop a comparator instance. (+) Stop a comparator instance.
@ -681,7 +681,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{ {
__IO uint32_t wait_loop_index = 0UL; __IO uint32_t wait_loop_index = 0UL;
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */ /* Check the COMP handle allocation and lock status */
if(hcomp == NULL) if(hcomp == NULL)
{ {
@ -700,10 +700,10 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
{ {
/* Enable the selected comparator */ /* Enable the selected comparator */
SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN); SET_BIT(hcomp->Instance->CSR, COMP_CSR_EN);
/* Set HAL COMP handle state */ /* Set HAL COMP handle state */
hcomp->State = HAL_COMP_STATE_BUSY; hcomp->State = HAL_COMP_STATE_BUSY;
/* Delay for COMP startup time */ /* Delay for COMP startup time */
/* Wait loop initialization and execution */ /* Wait loop initialization and execution */
/* Note: Variable divided by 2 to compensate partially */ /* Note: Variable divided by 2 to compensate partially */
@ -732,7 +732,7 @@ HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */ /* Check the COMP handle allocation and lock status */
if(hcomp == NULL) if(hcomp == NULL)
{ {
@ -746,7 +746,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
{ {
/* Check the parameter */ /* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */ /* Check compliant states: HAL_COMP_STATE_READY or HAL_COMP_STATE_BUSY */
/* (all states except HAL_COMP_STATE_RESET and except locked status. */ /* (all states except HAL_COMP_STATE_RESET and except locked status. */
if(hcomp->State != HAL_COMP_STATE_RESET) if(hcomp->State != HAL_COMP_STATE_RESET)
@ -762,7 +762,7 @@ HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
status = HAL_ERROR; status = HAL_ERROR;
} }
} }
return status; return status;
} }
@ -775,7 +775,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
{ {
/* Get the EXTI line corresponding to the selected COMP instance */ /* Get the EXTI line corresponding to the selected COMP instance */
uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance); uint32_t exti_line = COMP_GET_EXTI_LINE(hcomp->Instance);
/* Check COMP EXTI flag */ /* Check COMP EXTI flag */
if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL) if(LL_EXTI_IsActiveFlag_0_31(exti_line) != 0UL)
{ {
@ -796,7 +796,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
/* Clear COMP EXTI line pending bit */ /* Clear COMP EXTI line pending bit */
LL_EXTI_ClearFlag_0_31(exti_line); LL_EXTI_ClearFlag_0_31(exti_line);
} }
/* COMP trigger user callback */ /* COMP trigger user callback */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
hcomp->TriggerCallback(hcomp); hcomp->TriggerCallback(hcomp);
@ -810,15 +810,15 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
* @} * @}
*/ */
/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions /** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
* @brief Management functions. * @brief Management functions.
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Peripheral Control functions ##### ##### Peripheral Control functions #####
=============================================================================== ===============================================================================
[..] [..]
This subsection provides a set of functions allowing to control the comparators. This subsection provides a set of functions allowing to control the comparators.
@endverbatim @endverbatim
* @{ * @{
@ -835,7 +835,7 @@ void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp) HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
/* Check the COMP handle allocation and lock status */ /* Check the COMP handle allocation and lock status */
if(hcomp == NULL) if(hcomp == NULL)
{ {
@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
{ {
/* Check the parameter */ /* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
/* Set HAL COMP handle state */ /* Set HAL COMP handle state */
switch(hcomp->State) switch(hcomp->State)
{ {
@ -864,18 +864,18 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
break; break;
} }
} }
if(status == HAL_OK) if(status == HAL_OK)
{ {
/* Set the lock bit corresponding to selected comparator */ /* Set the lock bit corresponding to selected comparator */
__HAL_COMP_LOCK(hcomp); __HAL_COMP_LOCK(hcomp);
} }
return status; return status;
} }
/** /**
* @brief Return the output level (high or low) of the selected comparator. * @brief Return the output level (high or low) of the selected comparator.
* The output level depends on the selected polarity. * The output level depends on the selected polarity.
* If the polarity is not inverted: * If the polarity is not inverted:
* - Comparator output is low when the input plus is at a lower * - Comparator output is low when the input plus is at a lower
@ -888,16 +888,16 @@ HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
* - Comparator output is low when the input plus is at a higher * - Comparator output is low when the input plus is at a higher
* voltage than the input minus * voltage than the input minus
* @param hcomp COMP handle * @param hcomp COMP handle
* @retval Returns the selected comparator output level: * @retval Returns the selected comparator output level:
* @arg COMP_OUTPUT_LEVEL_LOW * @arg COMP_OUTPUT_LEVEL_LOW
* @arg COMP_OUTPUT_LEVEL_HIGH * @arg COMP_OUTPUT_LEVEL_HIGH
* *
*/ */
uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp) uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
{ {
/* Check the parameter */ /* Check the parameter */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE) return (uint32_t)(READ_BIT(hcomp->Instance->CSR, COMP_CSR_VALUE)
>> COMP_OUTPUT_LEVEL_BITOFFSET_POS); >> COMP_OUTPUT_LEVEL_BITOFFSET_POS);
} }
@ -911,7 +911,7 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
{ {
/* Prevent unused argument(s) compilation warning */ /* Prevent unused argument(s) compilation warning */
UNUSED(hcomp); UNUSED(hcomp);
/* NOTE : This function should not be modified, when the callback is needed, /* NOTE : This function should not be modified, when the callback is needed,
the HAL_COMP_TriggerCallback should be implemented in the user file the HAL_COMP_TriggerCallback should be implemented in the user file
*/ */
@ -922,13 +922,13 @@ __weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
* @} * @}
*/ */
/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions /** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions
* @brief Peripheral State functions. * @brief Peripheral State functions.
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Peripheral State functions ##### ##### Peripheral State functions #####
=============================================================================== ===============================================================================
[..] [..]
This subsection permit to get in run-time the status of the peripheral. This subsection permit to get in run-time the status of the peripheral.
@ -965,7 +965,7 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance)); assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
return hcomp->ErrorCode; return hcomp->ErrorCode;
} }
@ -981,7 +981,7 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp)
* @} * @}
*/ */
#endif /* COMP1 || COMP2 */
#endif /* HAL_COMP_MODULE_ENABLED */ #endif /* HAL_COMP_MODULE_ENABLED */

39
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_comp.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_comp.h
View File

@ -32,19 +32,19 @@ extern "C" {
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{
*/ */
#if defined (COMP1) || defined (COMP2)
/** @addtogroup COMP /** @addtogroup COMP
* @{ * @{
*/ */
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/
/** @defgroup COMP_Exported_Types COMP Exported Types /** @defgroup COMP_Exported_Types COMP Exported Types
* @{ * @{
*/ */
/** /**
* @brief COMP Init structure definition * @brief COMP Init structure definition
*/ */
typedef struct typedef struct
{ {
@ -77,7 +77,7 @@ typedef struct
uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI). uint32_t TriggerMode; /*!< Set the comparator output triggering External Interrupt Line (EXTI).
This parameter can be a value of @ref COMP_EXTI_TriggerMode */ This parameter can be a value of @ref COMP_EXTI_TriggerMode */
}COMP_InitTypeDef; } COMP_InitTypeDef;
/** /**
* @brief HAL COMP state machine: HAL COMP states definition * @brief HAL COMP state machine: HAL COMP states definition
@ -91,9 +91,9 @@ typedef enum
HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */ HAL_COMP_STATE_READY_LOCKED = (HAL_COMP_STATE_READY | COMP_STATE_BITFIELD_LOCK), /*!< COMP initialized but configuration is locked */
HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */ HAL_COMP_STATE_BUSY = 0x02U, /*!< COMP is running */
HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */ HAL_COMP_STATE_BUSY_LOCKED = (HAL_COMP_STATE_BUSY | COMP_STATE_BITFIELD_LOCK) /*!< COMP is running and configuration is locked */
}HAL_COMP_StateTypeDef; } HAL_COMP_StateTypeDef;
/** /**
* @brief COMP Handle Structure definition * @brief COMP Handle Structure definition
*/ */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
@ -282,10 +282,10 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @retval None * @retval None
*/ */
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \ #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) do{ \
(__HANDLE__)->State = HAL_COMP_STATE_RESET; \ (__HANDLE__)->State = HAL_COMP_STATE_RESET; \
(__HANDLE__)->MspInitCallback = NULL; \ (__HANDLE__)->MspInitCallback = NULL; \
(__HANDLE__)->MspDeInitCallback = NULL; \ (__HANDLE__)->MspDeInitCallback = NULL; \
} while(0) } while(0)
#else #else
#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET) #define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
@ -296,7 +296,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __HANDLE__ COMP handle * @param __HANDLE__ COMP handle
* @retval None * @retval None
*/ */
#define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE) #define COMP_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_COMP_ERROR_NONE)
/** /**
* @brief Enable the specified comparator. * @brief Enable the specified comparator.
@ -374,7 +374,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/** /**
* @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @brief Disable the COMP1 EXTI line rising & falling edge trigger.
* @retval None * @retval None
*/ */
#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ #define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \
LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \
LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \
@ -550,7 +550,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @{ * @{
*/ */
/** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators /** @defgroup COMP_GET_EXTI_LINE COMP private macros to get EXTI line associated with comparators
* @{ * @{
*/ */
/** /**
@ -558,8 +558,8 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
* @param __INSTANCE__ specifies the COMP instance. * @param __INSTANCE__ specifies the COMP instance.
* @retval value of @ref COMP_ExtiLine * @retval value of @ref COMP_ExtiLine
*/ */
#define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \ #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 \
: COMP_EXTI_LINE_COMP2) : COMP_EXTI_LINE_COMP2)
/** /**
* @} * @}
*/ */
@ -643,13 +643,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer
/* Initialization and de-initialization functions **********************************/ /* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp); HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp); void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
#if (USE_HAL_COMP_REGISTER_CALLBACKS == 1) #if (USE_HAL_COMP_REGISTER_CALLBACKS == 1)
/* Callbacks Register/UnRegister functions ***********************************/ /* Callbacks Register/UnRegister functions ***********************************/
HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID, pCOMP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_COMP_RegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID,
pCOMP_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_COMP_UnRegisterCallback(COMP_HandleTypeDef *hcomp, HAL_COMP_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_COMP_REGISTER_CALLBACKS */ #endif /* USE_HAL_COMP_REGISTER_CALLBACKS */
/** /**
@ -696,7 +697,7 @@ uint32_t HAL_COMP_GetError(COMP_HandleTypeDef *hcomp);
/** /**
* @} * @}
*/ */
#endif /* COMP1 || COMP2 */
/** /**
* @} * @}
*/ */

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_cortex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.c
View File

1
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_cortex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cortex.h
View File

@ -27,7 +27,6 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal_def.h" #include "stm32wbxx_hal_def.h"
#include "stm32wb55xx.h"
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_crc.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_crc.c
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_crc.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_crc.h
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_crc_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_crc_ex.c
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_crc_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_crc_ex.h
View File

380
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_cryp.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp.c
View File

@ -155,83 +155,24 @@
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
(#) structure of message construction in GCM is defined as below : (#) structure of message construction in GCM is defined as below :
(##) 16 bytes Initial Counter Block (ICB)composed of IV and counter (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
ICB
+-------------------------------------------------------+
| Initialization vector (IV) | Counter |
|----------------|----------------|-----------|---------|
127 95 63 31 0
Bit Number Register Contents
---------- --------------- -----------
127 ...96 CRYP_IV1R[31:0] ICB[127:96]
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
(##) The authenticated header A (also knows as Additional Authentication Data AAD) (##) The authenticated header A (also knows as Additional Authentication Data AAD)
this part of the message is only authenticated, not encrypted. this part of the message is only authenticated, not encrypted.
(##) The plaintext message P is both authenticated and encrypted as ciphertext. (##) The plaintext message P is both authenticated and encrypted as ciphertext.
GCM standard specifies that ciphertext has same bit length as the plaintext. GCM standard specifies that ciphertext has same bit length as the plaintext.
(##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
(on 64 bits) (on 64 bits)
GCM last block definition
+-------------------------------------------------------------------+ [..] A more detailed description of the GCM message structure is available below.
| Bit[0] | Bit[32] | Bit[64] | Bit[96] |
|-----------|--------------------|-----------|----------------------|
| 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
|-----------|--------------------|-----------|----------------------|
[..] This section describe The AES Counter with Cipher Block Chaining-Message [..] This section describe The AES Counter with Cipher Block Chaining-Message
Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral: Authentication Code (CCM) supported by both CRYP1 and TinyAES peripheral:
(#) Specific parameters for CCM : (#) Specific parameters for CCM :
(##) B0 block : According to NIST Special Publication 800-38C, (##) B0 block : follows NIST Special Publication 800-38C,
The first block B0 is formatted as follows, where l(m) is encoded in (##) B1 block (header)
most-significant-byte first order:
Octet Number Contents
------------ ---------
0 Flags
1 ... 15-q Nonce N
16-q ... 15 Q
the Flags field is formatted as follows:
Bit Number Contents
---------- ----------------------
7 Reserved (always zero)
6 Adata
5 ... 3 (t-2)/2
2 ... 0 [q-1]3
- Q: a bit string representation of the octet length of P (plaintext)
- q The octet length of the binary representation of the octet length of the payload
- A nonce (N), n The octet length of the where n+q=15.
- Flags: most significant octet containing four flags for control information,
- t The octet length of the MAC.
(##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
the associated data length expressed in bytes (a) defined as below:
- If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
- If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
- If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
(##) CTRx block : control blocks (##) CTRx block : control blocks
- Generation of CTR1 from first block B0 information :
equal to B0 with first 5 bits zeroed and most significant bits storing octet
length of P also zeroed, then incremented by one
Bit Number Register Contents [..] A detailed description of the CCM message structure is available below.
---------- --------------- -----------
127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
bit 0 that is set to 1
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] B0[63:32]
31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
- Generation of CTR0: same as CTR1 with bit[0] set to zero.
(#) Four phases are performed in CCM for CRYP1 peripheral: (#) Four phases are performed in CCM for CRYP1 peripheral:
(##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing (##) Init phase: peripheral prepares the GCM hash subkey (H) and do the IV processing
@ -248,13 +189,15 @@
(##) Final phase: peripheral generates the authenticated tag (T) using the last block of data. (##) Final phase: peripheral generates the authenticated tag (T) using the last block of data.
*** Callback registration *** *** Callback registration ***
============================================= =============================
[..]
The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback() Use Functions @ref HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
to register an interrupt callback. to register an interrupt callback.
[..]
Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks: Function @ref HAL_CRYP_RegisterCallback() allows to register following callbacks:
(+) InCpltCallback : Input FIFO transfer completed callback. (+) InCpltCallback : Input FIFO transfer completed callback.
(+) OutCpltCallback : Output FIFO transfer completed callback. (+) OutCpltCallback : Output FIFO transfer completed callback.
@ -264,6 +207,7 @@
This function takes as parameters the HAL peripheral handle, the Callback ID This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
[..]
Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default Use function @ref HAL_CRYP_UnRegisterCallback() to reset a callback to the default
weak function. weak function.
@ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle, @ref HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@ -275,6 +219,7 @@
(+) MspInitCallback : CRYP MspInit. (+) MspInitCallback : CRYP MspInit.
(+) MspDeInitCallback : CRYP MspDeInit. (+) MspDeInitCallback : CRYP MspDeInit.
[..]
By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET By default, after the @ref HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
all callbacks are set to the corresponding weak functions : all callbacks are set to the corresponding weak functions :
examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback(). examples @ref HAL_CRYP_InCpltCallback() , @ref HAL_CRYP_OutCpltCallback().
@ -284,6 +229,7 @@
if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit() if not, MspInit or MspDeInit are not null, the @ref HAL_CRYP_Init() / @ref HAL_CRYP_DeInit()
keep and use the user MspInit/MspDeInit functions (registered beforehand) keep and use the user MspInit/MspDeInit functions (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only. Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
Exception done MspInit/MspDeInit callbacks that can be registered/unregistered Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state, in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
@ -292,14 +238,16 @@
using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit() using @ref HAL_CRYP_RegisterCallback() before calling @ref HAL_CRYP_DeInit()
or @ref HAL_CRYP_Init() function. or @ref HAL_CRYP_Init() function.
[..]
When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
*** Suspend/Resume feature *** *** Suspend/Resume feature ***
============================================= ==============================
[..]
The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1 The compilation define USE_HAL_CRYP_SUSPEND_RESUME when set to 1
allows the user to resort to the suspend/resume feature. allows the user to resort to the suspend/resume feature.
A low priority block processing can be suspended to process a high priority block A low priority block processing can be suspended to process a high priority block
@ -974,11 +922,15 @@ void HAL_CRYP_ProcessSuspend(CRYP_HandleTypeDef *hcryp)
*/ */
HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp) HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
{ {
HAL_CRYP_STATETypeDef state;
/* Request suspension */ /* Request suspension */
HAL_CRYP_ProcessSuspend(hcryp); HAL_CRYP_ProcessSuspend(hcryp);
while ((HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_SUSPENDED) && \ do
(HAL_CRYP_GetState(hcryp) != HAL_CRYP_STATE_READY)); {
state = HAL_CRYP_GetState(hcryp);
} while ((state != HAL_CRYP_STATE_SUSPENDED) && (state != HAL_CRYP_STATE_READY));
if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY) if (HAL_CRYP_GetState(hcryp) == HAL_CRYP_STATE_READY)
{ {
@ -1012,7 +964,8 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
hcryp->CrypOutCount_saved = hcryp->CrypOutCount; hcryp->CrypOutCount_saved = hcryp->CrypOutCount;
hcryp->Phase_saved = hcryp->Phase; hcryp->Phase_saved = hcryp->Phase;
hcryp->State_saved = hcryp->State; hcryp->State_saved = hcryp->State;
hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? hcryp->Size /4 : hcryp->Size); hcryp->Size_saved = ( (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD) ? (hcryp->Size /4U) : hcryp->Size);
hcryp->SizesSum_saved = hcryp->SizesSum;
hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation; hcryp->AutoKeyDerivation_saved = hcryp->AutoKeyDerivation;
hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount; hcryp->CrypHeaderCount_saved = hcryp->CrypHeaderCount;
hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE; hcryp->SuspendRequest = HAL_CRYP_SUSPEND_NONE;
@ -1042,6 +995,12 @@ HAL_StatusTypeDef HAL_CRYP_Suspend(CRYP_HandleTypeDef *hcryp)
*/ */
HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp) HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
{ {
/* Check the CRYP handle allocation */
if (hcryp == NULL)
{
return HAL_ERROR;
}
if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED) if (hcryp->State_saved != HAL_CRYP_STATE_SUSPENDED)
{ {
/* CRYP was not suspended */ /* CRYP was not suspended */
@ -1068,16 +1027,14 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
hcryp->Init.pInitVect = hcryp->IV_saved; hcryp->Init.pInitVect = hcryp->IV_saved;
} }
__HAL_CRYP_DISABLE(hcryp); __HAL_CRYP_DISABLE(hcryp);
if (HAL_CRYP_Init(hcryp) != HAL_OK) (void) HAL_CRYP_Init(hcryp);
{
return HAL_ERROR;
}
} }
else /* Authentication algorithms case */ else /* Authentication algorithms case */
{ {
/* Restore low-priority block CRYP handle parameters */ /* Restore low-priority block CRYP handle parameters */
hcryp->Phase = hcryp->Phase_saved; hcryp->Phase = hcryp->Phase_saved;
hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved; hcryp->CrypHeaderCount = hcryp->CrypHeaderCount_saved;
hcryp->SizesSum = hcryp->SizesSum_saved;
/* Disable AES and write-back SUSPxR registers */; /* Disable AES and write-back SUSPxR registers */;
__HAL_CRYP_DISABLE(hcryp); __HAL_CRYP_DISABLE(hcryp);
@ -1087,8 +1044,6 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
hcryp->Instance->CR = hcryp->CR_saved; hcryp->Instance->CR = hcryp->CR_saved;
CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize); CRYP_Write_KeyRegisters(hcryp, hcryp->Key_saved, hcryp->Init.KeySize);
CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved); CRYP_Write_IVRegisters(hcryp, hcryp->IV_saved);
__HAL_CRYP_ENABLE_IT(hcryp,CRYP_IT_CCFIE | CRYP_IT_ERRIE);
__HAL_CRYP_ENABLE(hcryp);
/* At the same time, set handle state back to READY to be able to resume the AES calculations /* At the same time, set handle state back to READY to be able to resume the AES calculations
without the processing APIs returning HAL_BUSY when called. */ without the processing APIs returning HAL_BUSY when called. */
@ -1150,6 +1105,81 @@ HAL_StatusTypeDef HAL_CRYP_Resume(CRYP_HandleTypeDef *hcryp)
* @{ * @{
*/ */
/* GCM message structure additional details
ICB
+-------------------------------------------------------+
| Initialization vector (IV) | Counter |
|----------------|----------------|-----------|---------|
127 95 63 31 0
Bit Number Register Contents
---------- --------------- -----------
127 ...96 CRYP_IV1R[31:0] ICB[127:96]
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
GCM last block definition
+-------------------------------------------------------------------+
| Bit[0] | Bit[32] | Bit[64] | Bit[96] |
|-----------|--------------------|-----------|----------------------|
| 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
|-----------|--------------------|-----------|----------------------|
*/
/* CCM message blocks description
(##) B0 block : According to NIST Special Publication 800-38C,
The first block B0 is formatted as follows, where l(m) is encoded in
most-significant-byte first order:
Octet Number Contents
------------ ---------
0 Flags
1 ... 15-q Nonce N
16-q ... 15 Q
the Flags field is formatted as follows:
Bit Number Contents
---------- ----------------------
7 Reserved (always zero)
6 Adata
5 ... 3 (t-2)/2
2 ... 0 [q-1]3
- Q: a bit string representation of the octet length of P (plaintext)
- q The octet length of the binary representation of the octet length of the payload
- A nonce (N), n The octet length of the where n+q=15.
- Flags: most significant octet containing four flags for control information,
- t The octet length of the MAC.
(##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
the associated data length expressed in bytes (a) defined as below:
- If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
- If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
- If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
(##) CTRx block : control blocks
- Generation of CTR1 from first block B0 information :
equal to B0 with first 5 bits zeroed and most significant bits storing octet
length of P also zeroed, then incremented by one
Bit Number Register Contents
---------- --------------- -----------
127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
bit 0 that is set to 1
95 ...64 CRYP_IV1L[31:0] B0[95:64]
63 ... 32 CRYP_IV0R[31:0] B0[63:32]
31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
- Generation of CTR0: same as CTR1 with bit[0] set to zero.
*/
/** /**
* @brief Encryption mode. * @brief Encryption mode.
* @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains
@ -1164,6 +1194,12 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
{ {
uint32_t algo; uint32_t algo;
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif
if (hcryp->State == HAL_CRYP_STATE_READY) if (hcryp->State == HAL_CRYP_STATE_READY)
{ {
@ -1258,6 +1294,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, u
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
uint32_t algo; uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif
if (hcryp->State == HAL_CRYP_STATE_READY) if (hcryp->State == HAL_CRYP_STATE_READY)
{ {
@ -1351,6 +1393,12 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
uint32_t algo; uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif
if (hcryp->State == HAL_CRYP_STATE_READY) if (hcryp->State == HAL_CRYP_STATE_READY)
{ {
@ -1367,8 +1415,8 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
hcryp->ResumingFlag = 0U; hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{ {
hcryp->CrypInCount = hcryp->CrypInCount_saved; hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
hcryp->CrypOutCount = hcryp->CrypOutCount_saved; hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
} }
else else
{ {
@ -1455,6 +1503,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
uint32_t algo; uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif
if (hcryp->State == HAL_CRYP_STATE_READY) if (hcryp->State == HAL_CRYP_STATE_READY)
{ {
@ -1471,8 +1525,8 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input
hcryp->ResumingFlag = 0U; hcryp->ResumingFlag = 0U;
if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED) if (hcryp->Phase != CRYP_PHASE_HEADER_SUSPENDED)
{ {
hcryp->CrypInCount = hcryp->CrypInCount_saved; hcryp->CrypInCount = (uint16_t) hcryp->CrypInCount_saved;
hcryp->CrypOutCount = hcryp->CrypOutCount_saved; hcryp->CrypOutCount = (uint16_t) hcryp->CrypOutCount_saved;
} }
else else
{ {
@ -1559,6 +1613,12 @@ HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
uint32_t algo; uint32_t algo;
uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif
if (hcryp->State == HAL_CRYP_STATE_READY) if (hcryp->State == HAL_CRYP_STATE_READY)
{ {
@ -1679,6 +1739,12 @@ HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Inpu
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
uint32_t algo; uint32_t algo;
#ifdef USE_FULL_ASSERT
uint32_t algo_assert = (hcryp->Instance->CR) & AES_CR_CHMOD;
/* Check input buffer size */
assert_param(IS_CRYP_BUFFERSIZE(algo_assert, hcryp->Init.DataWidthUnit, Size));
#endif
if (hcryp->State == HAL_CRYP_STATE_READY) if (hcryp->State == HAL_CRYP_STATE_READY)
{ {
@ -4999,7 +5065,7 @@ static void CRYP_Read_SuspendRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Outp
__IO uint32_t count = 0U; __IO uint32_t count = 0U;
/* In case of GCM payload phase encryption, check that suspension can be carried out */ /* In case of GCM payload phase encryption, check that suspension can be carried out */
if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0)) if (READ_BIT(hcryp->Instance->CR, (AES_CR_CHMOD|AES_CR_GCMPH|AES_CR_MODE)) == (CRYP_AES_GCM_GMAC|AES_CR_GCMPH_1|0x0U))
{ {
/* Wait for BUSY flag to be cleared */ /* Wait for BUSY flag to be cleared */
@ -5137,21 +5203,21 @@ static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input,
if (KeySize == CRYP_KEYSIZE_256B) if (KeySize == CRYP_KEYSIZE_256B)
{ {
hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR7 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR6 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR5 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR4 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
} }
hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR3 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR2 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR1 = *(uint32_t*)(keyaddr);
keyaddr+=4; keyaddr+=4U;
hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr); hcryp->Instance->KEYR0 = *(uint32_t*)(keyaddr);
} }
@ -5163,9 +5229,19 @@ static void CRYP_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint32_t* Input,
*/ */
static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp) static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
{ {
uint32_t loopcounter = 0U; uint32_t loopcounter;
uint32_t lastwordsize =0; uint16_t lastwordsize;
uint32_t npblb = 0U ; uint16_t npblb;
uint32_t cr_temp;
__HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR | CRYP_CCF_CLEAR);
/* Enable computation complete flag and error interrupts */
__HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
/* Enable the CRYP peripheral */
__HAL_CRYP_ENABLE(hcryp);
/* Case of header phase resumption =================================================*/ /* Case of header phase resumption =================================================*/
if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) if (hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED)
@ -5176,7 +5252,7 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
/* Select header phase */ /* Select header phase */
CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER); CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
if (((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount) >= 4U)) if ((((hcryp->Init.HeaderSize) - (hcryp->CrypHeaderCount)) >= 4U))
{ {
/* Write the input block in the IN FIFO */ /* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount ); hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount );
@ -5205,73 +5281,77 @@ static void CRYP_PhaseProcessingResume(CRYP_HandleTypeDef *hcryp)
} }
} }
/* Case of payload phase resumption =================================================*/ /* Case of payload phase resumption =================================================*/
else if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED) else
{ {
if (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)
/* Set the phase */
hcryp->Phase = CRYP_PHASE_PROCESS;
/* Select payload phase once the header phase is performed */
MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
if ((hcryp->Size/4) - (hcryp->CrypInCount) >= 4U)
{ {
/* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
{
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
}
else /* Last block of payload < 128bit*/
{
/* Compute the number of padding bytes in last block of payload */
npblb = ((hcryp->Size/16U)+1U)*16U- (hcryp->Size);
if((((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
(((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, npblb<< 20U);
}
/* Number of valid words (lastwordsize) in last block */ /* Set the phase */
if (npblb % 4U ==0U) hcryp->Phase = CRYP_PHASE_PROCESS;
{
lastwordsize = (16U-npblb)/4U;
}
else
{
lastwordsize = (16U-npblb)/4U +1U;
}
/* Last block optionally pad the data with zeros*/ /* Select payload phase once the header phase is performed */
for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++) MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
/* Set to 0 the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, 0U);
if (((hcryp->Size/4U) - (hcryp->CrypInCount)) >= 4U)
{ {
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount ); /* Write the input block in the IN FIFO */
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++; hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
if((hcryp->CrypInCount == hcryp->Size) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC))
{
/* Call output transfer complete callback */
#if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
/*Call registered Input complete callback*/
hcryp->InCpltCallback(hcryp);
#else
/*Call legacy weak Input complete callback*/
HAL_CRYP_InCpltCallback(hcryp);
#endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
}
} }
while(loopcounter < 4U ) else /* Last block of payload < 128bit*/
{ {
/* pad the data with zeros to have a complete block */ /* Compute the number of padding bytes in last block of payload */
hcryp->Instance->DINR = 0x0U; npblb = (((hcryp->Size/16U)+1U)*16U) - (hcryp->Size);
loopcounter++; cr_temp = hcryp->Instance->CR;
if((((cr_temp & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT) && (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)) ||
(((cr_temp& AES_CR_MODE) == CRYP_OPERATINGMODE_DECRYPT) && (hcryp->Init.Algorithm == CRYP_AES_CCM)))
{
/* Specify the number of non-valid bytes using NPBLB register*/
MODIFY_REG(hcryp->Instance->CR, AES_CR_NPBLB, ((uint32_t)npblb)<< 20U);
}
/* Number of valid words (lastwordsize) in last block */
if ((npblb % 4U) ==0U)
{
lastwordsize = (16U-npblb)/4U;
}
else
{
lastwordsize = ((16U-npblb)/4U) +1U;
}
/* Last block optionally pad the data with zeros*/
for(loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
{
hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount );
hcryp->CrypInCount++;
}
while(loopcounter < 4U )
{
/* pad the data with zeros to have a complete block */
hcryp->Instance->DINR = 0x0U;
loopcounter++;
}
} }
} }
} }

10
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_cryp.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp.h
View File

@ -182,10 +182,12 @@ typedef struct
uint32_t Key_saved[8]; /*!< copy of key registers */ uint32_t Key_saved[8]; /*!< copy of key registers */
uint32_t Size_saved; /*!< copy of input buffer size */ uint16_t Size_saved; /*!< copy of input buffer size */
uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */ uint16_t CrypHeaderCount_saved; /*!< copy of CRYP header data counter when processing is suspended */
uint32_t SizesSum_saved; /*!< copy of SizesSum when processing is suspended */
uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */ uint32_t ResumingFlag; /*!< resumption flag to bypass steps already carried out */
FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */ FunctionalState AutoKeyDerivation_saved; /*!< copy of CRYP handle auto key derivation parameter */
@ -565,6 +567,12 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp);
#define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \ #define IS_CRYP_INIT(CONFIG)(((CONFIG) == CRYP_KEYIVCONFIG_ALWAYS) || \
((CONFIG) == CRYP_KEYIVCONFIG_ONCE)) ((CONFIG) == CRYP_KEYIVCONFIG_ONCE))
#define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \
(((((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || ((ALGO) == CRYP_AES_CTR)) && \
((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \
(((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \
(((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM)))
/** /**
* @} * @}
*/ */

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_cryp_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp_ex.c
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_cryp_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_cryp_ex.h
View File

2
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_def.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_def.h
View File

@ -28,7 +28,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx.h" #include "stm32wbxx.h"
#include "stm32_hal_legacy.h" /* Aliases file for old names compatibility */ #include "Legacy/stm32_hal_legacy.h" /* Aliases file for old names compatibility */
#include <stddef.h> #include <stddef.h>
/* Exported types ------------------------------------------------------------*/ /* Exported types ------------------------------------------------------------*/

64
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_dma.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.c
View File

@ -18,17 +18,15 @@
necessary). Please refer to the Reference manual for connection between peripherals necessary). Please refer to the Reference manual for connection between peripherals
and DMA requests. and DMA requests.
__HAL_RCC_DMAMUX1_CLK_ENABLE
(#) For a given Channel, program the required configuration through the following parameters: (#) For a given Channel, program the required configuration through the following parameters:
Channel request, Transfer Direction, Source and Destination data formats, Channel request, Transfer Direction, Source and Destination data formats,
Circular or Normal mode, Channel Priority level, Source and Destination Increment mode Circular or Normal mode, Channel Priority level, Source and Destination Increment mode
using HAL_DMA_Init() function. using HAL_DMA_Init() function.
Prior to HAL_DMA_Init the CLK shall be enabled for both DMA & DMAMUX Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX
thanks to: thanks to:
DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ;
DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE();
(#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error
detection. detection.
@ -36,6 +34,7 @@
(#) Use HAL_DMA_Abort() function to abort the current transfer (#) Use HAL_DMA_Abort() function to abort the current transfer
-@- In Memory-to-Memory transfer mode, Circular mode is not allowed. -@- In Memory-to-Memory transfer mode, Circular mode is not allowed.
*** Polling mode IO operation *** *** Polling mode IO operation ***
================================= =================================
[..] [..]
@ -54,13 +53,12 @@
In this case the DMA interrupt is configured In this case the DMA interrupt is configured
(+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
(+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can
add his own function by customization of function pointer XferCpltCallback and add his own function to register callbacks with HAL_DMA_RegisterCallback().
XferErrorCallback (i.e. a member of DMA handle structure).
*** DMA HAL driver macros list *** *** DMA HAL driver macros list ***
============================================= =============================================
[..] [..]
Below the list of most used macros in DMA HAL driver. Below the list of macros in DMA HAL driver.
(+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
(+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
@ -68,7 +66,7 @@
(+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
(+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
(+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
(+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt is enabled or not.
[..] [..]
(@) You can refer to the DMA HAL driver header file for more useful macros (@) You can refer to the DMA HAL driver header file for more useful macros
@ -172,19 +170,25 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request));
#if defined(DMA2)
/* Compute the channel index */ /* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
{ {
/* DMA1 */ /* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1; hdma->DmaBaseAddress = DMA1;
} }
else else
{ {
/* DMA2 */ /* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA2; hdma->DmaBaseAddress = DMA2;
} }
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
#endif
/* Change DMA peripheral state */ /* Change DMA peripheral state */
hdma->State = HAL_DMA_STATE_BUSY; hdma->State = HAL_DMA_STATE_BUSY;
@ -263,6 +267,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
*/ */
HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
{ {
/* Check the DMA handle allocation */ /* Check the DMA handle allocation */
if (NULL == hdma) if (NULL == hdma)
{ {
@ -275,19 +280,25 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
/* Disable the selected DMA Channelx */ /* Disable the selected DMA Channelx */
__HAL_DMA_DISABLE(hdma); __HAL_DMA_DISABLE(hdma);
#if defined(DMA2)
/* Compute the channel index */ /* Compute the channel index */
if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1))
{ {
/* DMA1 */ /* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1; hdma->DmaBaseAddress = DMA1;
} }
else else
{ {
/* DMA2 */ /* DMA2 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA2; hdma->DmaBaseAddress = DMA2;
} }
#else
/* DMA1 */
hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U;
hdma->DmaBaseAddress = DMA1;
#endif
/* Reset DMA Channel control register */ /* Reset DMA Channel control register */
hdma->Instance->CCR = 0U; hdma->Instance->CCR = 0U;
@ -645,9 +656,9 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_Level
/* Get tick */ /* Get tick */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
while (0U == (hdma->DmaBaseAddress->ISR & temp)) while((hdma->DmaBaseAddress->ISR & temp) == 0U)
{ {
if ((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU))))) if((hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1CU))) != 0U)
{ {
/* When a DMA transfer error occurs */ /* When a DMA transfer error occurs */
/* A hardware clear of its EN bits is performed */ /* A hardware clear of its EN bits is performed */
@ -753,7 +764,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
__HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
} }
/* Clear the half transfer complete flag */ /* Clear the half transfer complete flag */
hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU)); hdma->DmaBaseAddress->IFCR = (DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU));
/* DMA peripheral state is not updated in Half Transfer */ /* DMA peripheral state is not updated in Half Transfer */
/* but in Transfer Complete case */ /* but in Transfer Complete case */
@ -766,7 +777,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
} }
/* Transfer Complete Interrupt management ***********************************/ /* Transfer Complete Interrupt management ***********************************/
else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) else if (((flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU))) != 0U) && ((source_it & DMA_IT_TC) != 0U))
{ {
if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
{ {
@ -956,7 +967,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
*/ */
/** /**
* @brief Return the DMA hande state. * @brief Return the DMA handle state.
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Channel. * the configuration information for the specified DMA Channel.
* @retval HAL state * @retval HAL state
@ -1016,7 +1027,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel data length */ /* Configure DMA Channel data length */
hdma->Instance->CNDTR = DataLength; hdma->Instance->CNDTR = DataLength;
/* Peripheral to Memory */ /* Memory to Peripheral */
if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{ {
/* Configure DMA Channel destination address */ /* Configure DMA Channel destination address */
@ -1025,7 +1036,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
hdma->Instance->CMAR = SrcAddress; hdma->Instance->CMAR = SrcAddress;
} }
/* Memory to Peripheral */ /* Peripheral to Memory */
else else
{ {
/* Configure DMA Channel source address */ /* Configure DMA Channel source address */
@ -1037,9 +1048,9 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
} }
/** /**
* @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on channel number
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Channel.
* @retval None * @retval None
*/ */
static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
@ -1047,6 +1058,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
uint32_t channel_number; uint32_t channel_number;
/* check if instance is not outside the DMA channel range */ /* check if instance is not outside the DMA channel range */
#if defined(DMA2)
if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1)
{ {
/* DMA1 */ /* DMA1 */
@ -1057,6 +1069,10 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
/* DMA2 */ /* DMA2 */
hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U));
} }
#else
/* DMA1 */
hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U));
#endif
channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U;
hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus;
hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU);
@ -1065,7 +1081,7 @@ static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma)
/** /**
* @brief Updates the DMA handle with the DMAMUX request generator params * @brief Updates the DMA handle with the DMAMUX request generator params
* @param hdma Pointer to a DMA_HandleTypeDef structure that contains * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream. * the configuration information for the specified DMA Channel.
* @retval None * @retval None
*/ */
@ -1078,7 +1094,7 @@ static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma)
hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus;
/* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/
hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U);
} }

66
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_dma.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma.h
View File

@ -204,8 +204,10 @@ typedef struct __DMA_HandleTypeDef
#define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */ #define DMA_REQUEST_LPUART1_RX LL_DMAMUX_REQ_LPUART1_RX /*!< DMAMUX LP_UART1_RX request */
#define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */ #define DMA_REQUEST_LPUART1_TX LL_DMAMUX_REQ_LPUART1_TX /*!< DMAMUX LP_UART1_RX request */
#if defined (SAI1)
#define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */ #define DMA_REQUEST_SAI1_A LL_DMAMUX_REQ_SAI1_A /*!< DMAMUX SAI1 A request */
#define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */ #define DMA_REQUEST_SAI1_B LL_DMAMUX_REQ_SAI1_B /*!< DMAMUX SAI1 B request */
#endif /* SAI1 */
#define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */ #define DMA_REQUEST_QUADSPI LL_DMAMUX_REQ_QUADSPI /*!< DMAMUX QUADSPI request */
@ -361,7 +363,7 @@ typedef struct __DMA_HandleTypeDef
* @{ * @{
*/ */
/** @brief Reset DMA handle state /** @brief Reset DMA handle state.
* @param __HANDLE__ DMA handle * @param __HANDLE__ DMA handle
* @retval None * @retval None
*/ */
@ -385,11 +387,12 @@ typedef struct __DMA_HandleTypeDef
/* Interrupt & Flag management */ /* Interrupt & Flag management */
/** /**
* @brief Returns the current DMA Channel transfer complete flag. * @brief Return the current DMA Channel transfer complete flag.
* @param __HANDLE__ DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index. * @retval The specified transfer complete flag index.
*/ */
#if defined(DMA2)
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
@ -404,12 +407,23 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7) DMA_FLAG_TC7)
#else
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
DMA_FLAG_TC7)
#endif
/** /**
* @brief Returns the current DMA Channel half transfer complete flag. * @brief Return the current DMA Channel half transfer complete flag.
* @param __HANDLE__ DMA handle * @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index. * @retval The specified half transfer complete flag index.
*/ */
#if defined(DMA2)
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
@ -424,12 +438,23 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7) DMA_FLAG_HT7)
#else
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
DMA_FLAG_HT7)
#endif
/** /**
* @brief Returns the current DMA Channel transfer error flag. * @brief Return the current DMA Channel transfer error flag.
* @param __HANDLE__ DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#if defined(DMA2)
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
@ -444,12 +469,23 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7) DMA_FLAG_TE7)
#else
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
DMA_FLAG_TE7)
#endif
/** /**
* @brief Returns the current DMA Channel Global interrupt flag. * @brief Return the current DMA Channel Global interrupt flag.
* @param __HANDLE__ DMA handle * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index. * @retval The specified transfer error flag index.
*/ */
#if defined(DMA2)
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\
@ -464,6 +500,16 @@ typedef struct __DMA_HandleTypeDef
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7) DMA_ISR_GIF7)
#else
#define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\
((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\
DMA_ISR_GIF7)
#endif
/** /**
* @brief Get the DMA Channel pending flags. * @brief Get the DMA Channel pending flags.
@ -477,8 +523,12 @@ typedef struct __DMA_HandleTypeDef
* Where x can be from 1 to 7 to select the DMA Channel x flag. * Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval The state of FLAG (SET or RESET). * @retval The state of FLAG (SET or RESET).
*/ */
#if defined(DMA2)
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__)))
#else
#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (DMA1->ISR & (__FLAG__))
#endif
/** /**
* @brief Clear the DMA Channel pending flags. * @brief Clear the DMA Channel pending flags.
@ -492,8 +542,12 @@ typedef struct __DMA_HandleTypeDef
* Where x can be from 1 to 7 to select the DMA Channel x flag. * Where x can be from 1 to 7 to select the DMA Channel x flag.
* @retval None * @retval None
*/ */
#if defined(DMA2)
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \
(DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__)))
#else
#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
#endif
/** /**
* @brief Enable the specified DMA Channel interrupts. * @brief Enable the specified DMA Channel interrupts.
@ -532,7 +586,7 @@ typedef struct __DMA_HandleTypeDef
#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__)))
/** /**
* @brief Returns the number of remaining data units in the current DMA Channel transfer. * @brief Return the number of remaining data units in the current DMA Channel transfer.
* @param __HANDLE__ DMA handle * @param __HANDLE__ DMA handle
* @retval The number of remaining data units in the current DMA Channel transfer. * @retval The number of remaining data units in the current DMA Channel transfer.
*/ */

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_dma_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.c
View File

@ -76,8 +76,8 @@
=============================================================================== ===============================================================================
[..] This section provides functions allowing to: [..] This section provides functions allowing to:
(+) Configure the DMA_MUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function. (+) Configure the DMAMUX Synchronization Block using HAL_DMAEx_ConfigMuxSync function.
(+) Configure the DMA_MUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function. (+) Configure the DMAMUX Request Generator Block using HAL_DMAEx_ConfigMuxRequestGenerator function.
Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used Functions HAL_DMAEx_EnableMuxRequestGenerator and HAL_DMAEx_DisableMuxRequestGenerator can then be used
to respectively enable/disable the request generator. to respectively enable/disable the request generator.

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_dma_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_dma_ex.h
View File

8
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_exti.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.c
View File

@ -25,11 +25,9 @@
(++) Falling (++) Falling
(++) Both of them (++) Both of them
(+) When set in interrupt mode, configurable Exti lines have two diffenrents (+) When set in interrupt mode, configurable Exti lines have one
interrupt pending registers which allow to distinguish which transition interrupt pending register:
occurs: (++) Trigger request occurred
(++) Rising edge pending interrupt
(++) Falling
(+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can (+) Exti lines 0 to 15 are linked to gpio pin number 0 to 15. Gpio port can
be selected throught multiplexer. be selected throught multiplexer.

14
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_exti.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_exti.h
View File

@ -128,7 +128,11 @@ typedef struct
#define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u) #define EXTI_LINE_40 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x08u)
#define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u) #define EXTI_LINE_41 (EXTI_CONFIG | EXTI_EVENT | EXTI_REG2 | 0x09u)
#define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au) #define EXTI_LINE_42 (EXTI_DIRECT | EXTI_REG2 | 0x0Au)
#if defined (STM32WB55xx)
#define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu) #define EXTI_LINE_43 (EXTI_DIRECT | EXTI_REG2 | 0x0Bu)
#else
#define EXTI_LINE_43 (EXTI_RESERVED | EXTI_REG2 | 0x0Bu)
#endif
#define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu) #define EXTI_LINE_44 (EXTI_DIRECT | EXTI_REG2 | 0x0Cu)
#define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du) #define EXTI_LINE_45 (EXTI_DIRECT | EXTI_REG2 | 0x0Du)
#define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu) #define EXTI_LINE_46 (EXTI_DIRECT | EXTI_REG2 | 0x0Eu)
@ -166,7 +170,9 @@ typedef struct
#define EXTI_GPIOA 0x00000000u #define EXTI_GPIOA 0x00000000u
#define EXTI_GPIOB 0x00000001u #define EXTI_GPIOB 0x00000001u
#define EXTI_GPIOC 0x00000002u #define EXTI_GPIOC 0x00000002u
#if defined (STM32WB55xx)
#define EXTI_GPIOD 0x00000003u #define EXTI_GPIOD 0x00000003u
#endif
#define EXTI_GPIOE 0x00000004u #define EXTI_GPIOE 0x00000004u
#define EXTI_GPIOH 0x00000007u #define EXTI_GPIOH 0x00000007u
/** /**
@ -255,12 +261,20 @@ typedef struct
#define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u) #define IS_EXTI_CONFIG_LINE(__LINE__) (((__LINE__) & EXTI_CONFIG) != 0x00u)
#if defined (STM32WB55xx)
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \ #define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \ ((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \ ((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOD) || \ ((__PORT__) == EXTI_GPIOD) || \
((__PORT__) == EXTI_GPIOE) || \ ((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH)) ((__PORT__) == EXTI_GPIOH))
#else
#define IS_EXTI_GPIO_PORT(__PORT__) (((__PORT__) == EXTI_GPIOA) || \
((__PORT__) == EXTI_GPIOB) || \
((__PORT__) == EXTI_GPIOC) || \
((__PORT__) == EXTI_GPIOE) || \
((__PORT__) == EXTI_GPIOH))
#endif
#define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u) #define IS_EXTI_GPIO_PIN(__PIN__) ((__PIN__) < 16u)

148
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_flash.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.c
View File

@ -269,7 +269,7 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
pFlash.Address = Address; pFlash.Address = Address;
/* Enable End of Operation and Error interrupts */ /* Enable End of Operation and Error interrupts */
__HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR | FLASH_IT_ECCC); __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP | FLASH_IT_OPERR);
if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD) if (TypeProgram == FLASH_TYPEPROGRAM_DOUBLEWORD)
{ {
@ -299,51 +299,31 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, u
*/ */
void HAL_FLASH_IRQHandler(void) void HAL_FLASH_IRQHandler(void)
{ {
uint32_t clearbit; uint32_t param = 0xFFFFFFFFU;
uint32_t param;
uint32_t error; uint32_t error;
/* save flash errors. Only ECC detection can be checked here as ECCC /* Check FLASH operation error flags */
generates NMI */ error = (FLASH->SR & FLASH_FLAG_SR_ERRORS);
error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
error |= (FLASH->ECCR & FLASH_FLAG_ECCC); /* Clear Current operation */
CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
/* A] Set parameter for user or error callbacks */ /* A] Set parameter for user or error callbacks */
/* check operation was a program or erase */ /* check operation was a program or erase */
if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0U) if ((pFlash.ProcedureOnGoing & (FLASH_TYPEPROGRAM_DOUBLEWORD | FLASH_TYPEPROGRAM_FAST)) != 0U)
{ {
/* return adress being programmed */ /* return adress being programmed */
param = pFlash.Address; param = pFlash.Address;
/* set operation bit to clear */
clearbit = pFlash.ProcedureOnGoing;
} }
else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U) else if ((pFlash.ProcedureOnGoing & (FLASH_TYPEERASE_MASSERASE | FLASH_TYPEERASE_PAGES)) != 0U)
{ {
/* return page number being erased (0 for mass erase) */ /* return page number being erased (0 for mass erase) */
param = pFlash.Page; param = pFlash.Page;
if (pFlash.ProcedureOnGoing != FLASH_TYPEERASE_PAGES)
{
/* set operation bit to clear */
clearbit = pFlash.ProcedureOnGoing;
}
else
{
clearbit = 0U;
}
} }
else else
{ {
param = 0U; /* No Procedure on-going */
clearbit = 0U; /* Nothing to do, but check error if any */
}
/* clear operation bit if needed */
if (clearbit != 0U)
{
CLEAR_BIT(FLASH->CR, clearbit);
} }
/* B] Check errors */ /* B] Check errors */
@ -353,8 +333,7 @@ void HAL_FLASH_IRQHandler(void)
pFlash.ErrorCode |= error; pFlash.ErrorCode |= error;
/* clear error flags */ /* clear error flags */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_SR_ERROR); __HAL_FLASH_CLEAR_FLAG(error);
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ECCC);
/*Stop the procedure ongoing*/ /*Stop the procedure ongoing*/
pFlash.ProcedureOnGoing = FLASH_TYPENONE; pFlash.ProcedureOnGoing = FLASH_TYPENONE;
@ -384,17 +363,12 @@ void HAL_FLASH_IRQHandler(void)
else else
{ {
/* No more pages to erase: stop erase pages procedure */ /* No more pages to erase: stop erase pages procedure */
/* Reset Address and stop Erase pages procedure */
CLEAR_BIT(FLASH->CR, pFlash.ProcedureOnGoing);
pFlash.Page = 0xFFFFFFFFU;
param = pFlash.Page;
pFlash.ProcedureOnGoing = FLASH_TYPENONE; pFlash.ProcedureOnGoing = FLASH_TYPENONE;
} }
} }
else else
{ {
/*Stop the ongoing procedure */ /*Stop the ongoing procedure */
param = 0xFFFFFFFFU;
pFlash.ProcedureOnGoing = FLASH_TYPENONE; pFlash.ProcedureOnGoing = FLASH_TYPENONE;
} }
@ -497,22 +471,16 @@ HAL_StatusTypeDef HAL_FLASH_Unlock(void)
*/ */
HAL_StatusTypeDef HAL_FLASH_Lock(void) HAL_StatusTypeDef HAL_FLASH_Lock(void)
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status = HAL_OK;
/* Verify that next operation can be proceed */ /* Set the LOCK Bit to lock the FLASH Registers access */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
if (status == HAL_OK) /* verify Flash is locked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U)
{ {
/* Set the LOCK Bit to lock the FLASH Registers access */ status = HAL_ERROR;
/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
SET_BIT(FLASH->CR, FLASH_CR_LOCK);
/* verify Flash is locked */
if (READ_BIT(FLASH->CR, FLASH_CR_LOCK) == 0U)
{
status = HAL_ERROR;
}
} }
return status; return status;
@ -549,22 +517,16 @@ HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
*/ */
HAL_StatusTypeDef HAL_FLASH_OB_Lock(void) HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
{ {
HAL_StatusTypeDef status; HAL_StatusTypeDef status = HAL_OK;
/* Verify that next operation can be proceed */ /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); /* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
if (status == HAL_OK) /* verify option bytes are lock */
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U)
{ {
/* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */ status = HAL_ERROR;
/* @Note The lock and unlock procedure is done only using CR registers even from CPU2 */
SET_BIT(FLASH->CR, FLASH_CR_OPTLOCK);
/* verify option bytes are lock */
if (READ_BIT(FLASH->CR, FLASH_CR_OPTLOCK) == 0U)
{
status = HAL_ERROR;
}
} }
return status; return status;
@ -576,21 +538,13 @@ HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
*/ */
HAL_StatusTypeDef HAL_FLASH_OB_Launch(void) HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
{ {
HAL_StatusTypeDef status; /* Set the bit to force the option byte reloading */
/* The OB launch is done from the same register either from CPU1 or CPU2 */
/* Verify that next operation can be proceed */ SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
if (status == HAL_OK)
{
/* Set the bit to force the option byte reloading */
/* The OB launch is done from the same register either from CPU1 or CPU2 */
SET_BIT(FLASH->CR, FLASH_CR_OBL_LAUNCH);
}
/* We should not reach here : Option byte launch generates Option byte reset /* We should not reach here : Option byte launch generates Option byte reset
so return error */ so return error */
return status; return HAL_ERROR;
} }
/** /**
@ -625,7 +579,6 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
* @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error * @arg @ref HAL_FLASH_ERROR_FAST FLASH Fast programming error
* @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP) * @arg @ref HAL_FLASH_ERROR_RD FLASH Read Protection error (PCROP)
* @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error * @arg @ref HAL_FLASH_ERROR_OPTV FLASH Option validity error
* @arg @ref HAL_FLASH_ERROR_ECCD FLASH two ECC errors have been detected
*/ */
uint32_t HAL_FLASH_GetError(void) uint32_t HAL_FLASH_GetError(void)
{ {
@ -661,30 +614,45 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
flag will be set */ flag will be set */
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY)) while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY))
{ {
if (Timeout != HAL_MAX_DELAY) if ((HAL_GetTick() - tickstart) >= Timeout)
{ {
if ((HAL_GetTick() - tickstart) >= Timeout) return HAL_TIMEOUT;
{
return HAL_TIMEOUT;
}
} }
} }
/* check flash errors. Only ECC correction can be checked here as ECCD /* Check FLASH operation error flags */
generates NMI */ error = FLASH->SR;
error = (FLASH->SR & FLASH_FLAG_SR_ERROR);
/* Check FLASH End of Operation flag */
if ((error & FLASH_FLAG_EOP) != 0U)
{
/* Clear FLASH End of Operation pending bit */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
}
/* Now update error variable to only error value */
error &= FLASH_FLAG_SR_ERRORS;
/* clear error flags */
__HAL_FLASH_CLEAR_FLAG(error);
if (error != 0U) if (error != 0U)
{ {
/*Save the error code*/ /*Save the error code*/
pFlash.ErrorCode |= error; pFlash.ErrorCode = error;
/* clear error flags */
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_SR_ERROR);
__HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_ECCC);
return HAL_ERROR; return HAL_ERROR;
} }
/* Wait for control register to be written */
while (__HAL_FLASH_GET_FLAG(FLASH_FLAG_CFGBSY))
{
if ((HAL_GetTick() - tickstart) >= Timeout)
{
return HAL_TIMEOUT;
}
}
return HAL_OK; return HAL_OK;
} }
@ -700,14 +668,14 @@ static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
SET_BIT(FLASH->CR, FLASH_CR_PG); SET_BIT(FLASH->CR, FLASH_CR_PG);
/* Program first word */ /* Program first word */
*(__IO uint32_t *)Address = (uint32_t)Data; *(uint32_t *)Address = (uint32_t)Data;
/* Barrier to ensure programming is performed in 2 steps, in right order /* Barrier to ensure programming is performed in 2 steps, in right order
(independently of compiler optimization behavior) */ (independently of compiler optimization behavior) */
__ISB(); __ISB();
/* Program second word */ /* Program second word */
*(__IO uint32_t *)((uint32_t)(Address + 4U)) = (uint32_t)(Data >> 32U); *(uint32_t *)(Address + 4U) = (uint32_t)(Data >> 32U);
} }
/** /**

325
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_flash.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash.h
View File

@ -49,9 +49,9 @@ typedef struct
uint32_t TypeErase; /*!< Mass erase or page erase. uint32_t TypeErase; /*!< Mass erase or page erase.
This parameter can be a value of @ref FLASH_TYPE_ERASE */ This parameter can be a value of @ref FLASH_TYPE_ERASE */
uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled uint32_t Page; /*!< Initial Flash page to erase when page erase is enabled
This parameter must be a value between 0 and (max number of pages - 1) */ This parameter must be a value between 0 and (FLASH_PAGE_NB - 1) */
uint32_t NbPages; /*!< Number of pages to be erased. uint32_t NbPages; /*!< Number of pages to be erased.
This parameter must be a value between 1 and (max number of pages - value of initial page)*/ This parameter must be a value between 1 and (FLASH_PAGE_NB - value of initial page)*/
} FLASH_EraseInitTypeDef; } FLASH_EraseInitTypeDef;
/** /**
@ -92,22 +92,23 @@ typedef struct
to protect. Make sure this parameter is multiple of PCROP granularity */ to protect. Make sure this parameter is multiple of PCROP granularity */
uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block uint32_t PCROP1BEndAddr; /*!< PCROP Zone B End address (used for OPTIONBYTE_PCROP). It represents first address of end block
to protect. Make sure this parameter is multiple of PCROP granularity */ to protect. Make sure this parameter is multiple of PCROP granularity */
uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SFSA). uint32_t SecureFlashStartAddr; /*!< Secure Flash start address (used for OPTIONBYTE_SECURE_MODE).
This parameter must be a value between begin and end of bank This parameter must be a value between begin and end of Flash bank
=> Contains the start address of the first 4K page of the secure Flash area */ => Contains the start address of the first 4kB page of the secure Flash area */
uint32_t SecureRAM2aStartAddr; /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SBRSA). uint32_t SecureRAM2aStartAddr; /*!< Secure Backup RAM2a start address (used for OPTIONBYTE_SECURE_MODE).
This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */ This parameter can be a value of @ref FLASH_SRAM2A_ADDRESS_RANGE */
uint32_t SecureRAM2bStartAddr; /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SNBRSB) uint32_t SecureRAM2bStartAddr; /*!< Secure non-Backup RAM2b start address (used for OPTIONBYTE_SECURE_MODE)
This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */ This parameter can be a value of @ref FLASH_SRAM2B_ADDRESS_RANGE */
uint32_t SecureMode; /*!< Secure mode activated or desactivated. uint32_t SecureMode; /*!< Secure mode activated or desactivated.
This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */ This parameter can be a value of @ref FLASH_OB_SECURITY_MODE */
uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT). uint32_t C2BootRegion; /*!< CPU2 Secure Boot memory region(used for OPTIONBYTE_C2_BOOT_VECT).
This parameter can be a value of @ref FLASH_OB_C2_BOOT_REGION */ This parameter can be a value of @ref C2_FLASH_OB_BOOT_REGION */
uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT). uint32_t C2SecureBootVectAddr; /*!< CPU2 Secure Boot reset vector (used for OPTIONBYTE_C2_BOOT_VECT).
This parameter contains the CPU2 boot reset start address within This parameter contains the CPU2 boot reset start address within
the selected memory region. Make sure this parameter is word aligned. */ the selected memory region. Make sure this parameter is word aligned. */
uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR). uint32_t IPCCdataBufAddr; /*!< IPCC mailbox data buffer base address (used for OPTIONBYTE_IPCC_BUF_ADDR).
This parameter contains the IPCC mailbox data buffer start address area in SRAM2 */ This parameter contains the IPCC mailbox data buffer start address area in SRAM2.
Make sure this parameter is double-word aligned. */
} FLASH_OBProgramInitTypeDef; } FLASH_OBProgramInitTypeDef;
/** /**
@ -149,10 +150,10 @@ typedef struct
/** @defgroup FLASH_LATENCY FLASH Latency /** @defgroup FLASH_LATENCY FLASH Latency
* @{ * @{
*/ */
#define FLASH_LATENCY_0 (FLASH_ACR_LATENCY_0WS) /*!< FLASH Zero wait state */ #define FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
#define FLASH_LATENCY_1 (FLASH_ACR_LATENCY_1WS) /*!< FLASH One wait state */ #define FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
#define FLASH_LATENCY_2 (FLASH_ACR_LATENCY_2WS) /*!< FLASH Two wait states */ #define FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
#define FLASH_LATENCY_3 (FLASH_ACR_LATENCY_3WS) /*!< FLASH Three wait states */ #define FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
/** /**
* @} * @}
*/ */
@ -178,12 +179,14 @@ typedef struct
#define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */ #define FLASH_FLAG_ECCC FLASH_ECCR_ECCC /*!< FLASH ECC correction */
#define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */ #define FLASH_FLAG_ECCD FLASH_ECCR_ECCD /*!< FLASH ECC detection */
#define FLASH_FLAG_SR_ERROR (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \ #define FLASH_FLAG_SR_ERRORS (FLASH_FLAG_OPERR | FLASH_FLAG_PROGERR | FLASH_FLAG_WRPERR | \
FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \ FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | FLASH_FLAG_PGSERR | \
FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \ FLASH_FLAG_MISERR | FLASH_FLAG_FASTERR | FLASH_FLAG_RDERR | \
FLASH_FLAG_OPTVERR) /*!< All SR error flags */ FLASH_FLAG_OPTVERR) /*!< All SR error flags */
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERROR | FLASH_FLAG_ECCC | FLASH_FLAG_ECCD) #define FLASH_FLAG_ECCR_ERRORS (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)
#define FLASH_FLAG_ALL_ERRORS (FLASH_FLAG_SR_ERRORS | FLASH_FLAG_ECCR_ERRORS)
/** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition /** @defgroup FLASH_INTERRUPT_DEFINITION FLASH Interrupts Definition
* @brief FLASH Interrupt definition * @brief FLASH Interrupt definition
@ -211,7 +214,6 @@ typedef struct
#define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR #define HAL_FLASH_ERROR_FAST FLASH_FLAG_FASTERR
#define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR #define HAL_FLASH_ERROR_RD FLASH_FLAG_RDERR
#define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR #define HAL_FLASH_ERROR_OPTV FLASH_FLAG_OPTVERR
#define HAL_FLASH_ERROR_ECCD FLASH_FLAG_ECCD
/** /**
* @} * @}
*/ */
@ -275,20 +277,20 @@ typedef struct
/** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type /** @defgroup FLASH_OB_USER_TYPE FLASH Option Bytes User Type
* @{ * @{
*/ */
#define OB_USER_BOR_LEV (FLASH_OPTR_BOR_LEV) /*!< BOR reset Level */ #define OB_USER_BOR_LEV FLASH_OPTR_BOR_LEV /*!< BOR reset Level */
#define OB_USER_nRST_STOP (FLASH_OPTR_nRST_STOP) /*!< Reset generated when entering the stop mode */ #define OB_USER_nRST_STOP FLASH_OPTR_nRST_STOP /*!< Reset generated when entering the stop mode */
#define OB_USER_nRST_STDBY (FLASH_OPTR_nRST_STDBY) /*!< Reset generated when entering the standby mode */ #define OB_USER_nRST_STDBY FLASH_OPTR_nRST_STDBY /*!< Reset generated when entering the standby mode */
#define OB_USER_nRST_SHDW (FLASH_OPTR_nRST_SHDW) /*!< Reset generated when entering the shutdown mode */ #define OB_USER_nRST_SHDW FLASH_OPTR_nRST_SHDW /*!< Reset generated when entering the shutdown mode */
#define OB_USER_IWDG_SW (FLASH_OPTR_IWDG_SW) /*!< Independent watchdog selection */ #define OB_USER_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Independent watchdog selection */
#define OB_USER_IWDG_STOP (FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter freeze in stop mode */ #define OB_USER_IWDG_STOP FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter freeze in stop mode */
#define OB_USER_IWDG_STDBY (FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter freeze in standby mode */ #define OB_USER_IWDG_STDBY FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter freeze in standby mode */
#define OB_USER_WWDG_SW (FLASH_OPTR_WWDG_SW) /*!< Window watchdog selection */ #define OB_USER_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Window watchdog selection */
#define OB_USER_nBOOT1 (FLASH_OPTR_nBOOT1) /*!< Boot configuration */ #define OB_USER_nBOOT1 FLASH_OPTR_nBOOT1 /*!< Boot configuration */
#define OB_USER_SRAM2PE (FLASH_OPTR_SRAM2PE) /*!< SRAM2 parity check enable */ #define OB_USER_SRAM2PE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check enable */
#define OB_USER_SRAM2RST (FLASH_OPTR_SRAM2RST) /*!< SRAM2 erase when system reset */ #define OB_USER_SRAM2RST FLASH_OPTR_SRAM2RST /*!< SRAM2 erase when system reset */
#define OB_USER_nSWBOOT0 (FLASH_OPTR_nSWBOOT0) /*!< Software BOOT0 */ #define OB_USER_nSWBOOT0 FLASH_OPTR_nSWBOOT0 /*!< Software BOOT0 */
#define OB_USER_nBOOT0 (FLASH_OPTR_nBOOT0) /*!< nBOOT0 option bit */ #define OB_USER_nBOOT0 FLASH_OPTR_nBOOT0 /*!< nBOOT0 option bit */
#define OB_USER_AGC_TRIM (FLASH_OPTR_AGC_TRIM) /*!< Automatic Gain Control Trimming */ #define OB_USER_AGC_TRIM FLASH_OPTR_AGC_TRIM /*!< Automatic Gain Control Trimming */
#define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \ #define OB_USER_ALL (OB_USER_BOR_LEV | OB_USER_nRST_STOP | OB_USER_nRST_STDBY | \
OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \ OB_USER_nRST_SHDW | OB_USER_IWDG_SW | OB_USER_IWDG_STOP | \
OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \ OB_USER_IWDG_STDBY | OB_USER_WWDG_SW | OB_USER_nBOOT1 | \
@ -303,10 +305,10 @@ typedef struct
* @{ * @{
*/ */
#define OB_AGC_TRIM_0 0x00000000U /*!< Automatic Gain Control Trimming Value 0 */ #define OB_AGC_TRIM_0 0x00000000U /*!< Automatic Gain Control Trimming Value 0 */
#define OB_AGC_TRIM_1 (FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 1 */ #define OB_AGC_TRIM_1 FLASH_OPTR_AGC_TRIM_0 /*!< Automatic Gain Control Trimming Value 1 */
#define OB_AGC_TRIM_2 (FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 2 */ #define OB_AGC_TRIM_2 FLASH_OPTR_AGC_TRIM_1 /*!< Automatic Gain Control Trimming Value 2 */
#define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 3 */ #define OB_AGC_TRIM_3 (FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 3 */
#define OB_AGC_TRIM_4 (FLASH_OPTR_AGC_TRIM_2) /*!< Automatic Gain Control Trimming Value 4 */ #define OB_AGC_TRIM_4 FLASH_OPTR_AGC_TRIM_2 /*!< Automatic Gain Control Trimming Value 4 */
#define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 5 */ #define OB_AGC_TRIM_5 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 5 */
#define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 6 */ #define OB_AGC_TRIM_6 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1) /*!< Automatic Gain Control Trimming Value 6 */
#define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 7 */ #define OB_AGC_TRIM_7 (FLASH_OPTR_AGC_TRIM_2 | FLASH_OPTR_AGC_TRIM_1 | FLASH_OPTR_AGC_TRIM_0) /*!< Automatic Gain Control Trimming Value 7 */
@ -318,10 +320,10 @@ typedef struct
* @{ * @{
*/ */
#define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */ #define OB_BOR_LEVEL_0 0x00000000U /*!< Reset level threshold is around 1.7V */
#define OB_BOR_LEVEL_1 (FLASH_OPTR_BOR_LEV_0) /*!< Reset level threshold is around 2.0V */ #define OB_BOR_LEVEL_1 FLASH_OPTR_BOR_LEV_0 /*!< Reset level threshold is around 2.0V */
#define OB_BOR_LEVEL_2 (FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.2V */ #define OB_BOR_LEVEL_2 FLASH_OPTR_BOR_LEV_1 /*!< Reset level threshold is around 2.2V */
#define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */ #define OB_BOR_LEVEL_3 (FLASH_OPTR_BOR_LEV_0 | FLASH_OPTR_BOR_LEV_1) /*!< Reset level threshold is around 2.5V */
#define OB_BOR_LEVEL_4 (FLASH_OPTR_BOR_LEV_2) /*!< Reset level threshold is around 2.8V */ #define OB_BOR_LEVEL_4 FLASH_OPTR_BOR_LEV_2 /*!< Reset level threshold is around 2.8V */
/** /**
* @} * @}
*/ */
@ -329,8 +331,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop /** @defgroup FLASH_OB_USER_nRST_STOP FLASH Option Bytes User Reset On Stop
* @{ * @{
*/ */
#define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */ #define OB_STOP_RST 0x00000000U /*!< Reset generated when entering the stop mode */
#define OB_STOP_NORST (FLASH_OPTR_nRST_STOP) /*!< No reset generated when entering the stop mode */ #define OB_STOP_NORST FLASH_OPTR_nRST_STOP /*!< No reset generated when entering the stop mode */
/** /**
* @} * @}
*/ */
@ -338,8 +340,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby /** @defgroup FLASH_OB_USER_nRST_STANDBY FLASH Option Bytes User Reset On Standby
* @{ * @{
*/ */
#define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */ #define OB_STANDBY_RST 0x00000000U /*!< Reset generated when entering the standby mode */
#define OB_STANDBY_NORST (FLASH_OPTR_nRST_STDBY) /*!< No reset generated when entering the standby mode */ #define OB_STANDBY_NORST FLASH_OPTR_nRST_STDBY /*!< No reset generated when entering the standby mode */
/** /**
* @} * @}
*/ */
@ -347,8 +349,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown /** @defgroup FLASH_OB_USER_nRST_SHUTDOWN FLASH Option Bytes User Reset On Shutdown
* @{ * @{
*/ */
#define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */ #define OB_SHUTDOWN_RST 0x00000000U /*!< Reset generated when entering the shutdown mode */
#define OB_SHUTDOWN_NORST (FLASH_OPTR_nRST_SHDW) /*!< No reset generated when entering the shutdown mode */ #define OB_SHUTDOWN_NORST FLASH_OPTR_nRST_SHDW /*!< No reset generated when entering the shutdown mode */
/** /**
* @} * @}
*/ */
@ -356,8 +358,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type /** @defgroup FLASH_OB_USER_IWDG_SW FLASH Option Bytes User IWDG Type
* @{ * @{
*/ */
#define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */ #define OB_IWDG_HW 0x00000000U /*!< Hardware independent watchdog */
#define OB_IWDG_SW (FLASH_OPTR_IWDG_SW) /*!< Software independent watchdog */ #define OB_IWDG_SW FLASH_OPTR_IWDG_SW /*!< Software independent watchdog */
/** /**
* @} * @}
*/ */
@ -365,8 +367,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop /** @defgroup FLASH_OB_USER_IWDG_STOP FLASH Option Bytes User IWDG Mode On Stop
* @{ * @{
*/ */
#define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */ #define OB_IWDG_STOP_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Stop mode */
#define OB_IWDG_STOP_RUN (FLASH_OPTR_IWDG_STOP) /*!< Independent watchdog counter is running in Stop mode */ #define OB_IWDG_STOP_RUN FLASH_OPTR_IWDG_STOP /*!< Independent watchdog counter is running in Stop mode */
/** /**
* @} * @}
*/ */
@ -374,8 +376,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby /** @defgroup FLASH_OB_USER_IWDG_STANDBY FLASH Option Bytes User IWDG Mode On Standby
* @{ * @{
*/ */
#define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */ #define OB_IWDG_STDBY_FREEZE 0x00000000U /*!< Independent watchdog counter is frozen in Standby mode */
#define OB_IWDG_STDBY_RUN (FLASH_OPTR_IWDG_STDBY) /*!< Independent watchdog counter is running in Standby mode */ #define OB_IWDG_STDBY_RUN FLASH_OPTR_IWDG_STDBY /*!< Independent watchdog counter is running in Standby mode */
/** /**
* @} * @}
*/ */
@ -383,8 +385,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type /** @defgroup FLASH_OB_USER_WWDG_SW FLASH Option Bytes User WWDG Type
* @{ * @{
*/ */
#define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */ #define OB_WWDG_HW 0x00000000U /*!< Hardware window watchdog */
#define OB_WWDG_SW (FLASH_OPTR_WWDG_SW) /*!< Software window watchdog */ #define OB_WWDG_SW FLASH_OPTR_WWDG_SW /*!< Software window watchdog */
/** /**
* @} * @}
*/ */
@ -392,8 +394,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check /** @defgroup FLASH_OB_USER_SRAM2PE FLASH Option Bytes SRAM2 parity check
* @{ * @{
*/ */
#define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */ #define OB_SRAM2_PARITY_ENABLE 0x00000000U /*!< SRAM2 parity check enable */
#define OB_SRAM2_PARITY_DISABLE (FLASH_OPTR_SRAM2PE) /*!< SRAM2 parity check disable */ #define OB_SRAM2_PARITY_DISABLE FLASH_OPTR_SRAM2PE /*!< SRAM2 parity check disable */
/** /**
* @} * @}
*/ */
@ -401,8 +403,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset /** @defgroup FLASH_OB_USER_SRAM2RST FLASH Option Bytes SRAM2 erase when system reset
* @{ * @{
*/ */
#define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset */ #define OB_SRAM2_RST_ERASE 0x00000000U /*!< SRAM2 erased when a system reset */
#define OB_SRAM2_RST_NOT_ERASE (FLASH_OPTR_SRAM2RST) /*!< SRAM2 is not erased when a system reset */ #define OB_SRAM2_RST_NOT_ERASE FLASH_OPTR_SRAM2RST /*!< SRAM2 is not erased when a system reset */
/** /**
* @} * @}
*/ */
@ -410,8 +412,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type /** @defgroup FLASH_OB_USER_nBOOT1 FLASH Option Bytes User BOOT1 Type
* @{ * @{
*/ */
#define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */ #define OB_BOOT1_SRAM 0x00000000U /*!< Embedded SRAM is selected as boot space (if BOOT0=1) */
#define OB_BOOT1_SYSTEM (FLASH_OPTR_nBOOT1) /*!< System memory is selected as boot space (if BOOT0=1) */ #define OB_BOOT1_SYSTEM FLASH_OPTR_nBOOT1 /*!< System memory is selected as boot space (if BOOT0=1) */
/** /**
* @} * @}
*/ */
@ -419,8 +421,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0 /** @defgroup FLASH_OB_USER_nSWBOOT0 FLASH Option Bytes User Software BOOT0
* @{ * @{
*/ */
#define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */ #define OB_BOOT0_FROM_OB 0x00000000U /*!< BOOT0 taken from the option bit nBOOT0 */
#define OB_BOOT0_FROM_PIN (FLASH_OPTR_nSWBOOT0) /*!< BOOT0 taken from PH3/BOOT0 pin */ #define OB_BOOT0_FROM_PIN FLASH_OPTR_nSWBOOT0 /*!< BOOT0 taken from PH3/BOOT0 pin */
/** /**
* @} * @}
*/ */
@ -428,8 +430,8 @@ typedef struct
/** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit /** @defgroup FLASH_OB_USER_nBOOT0 FLASH Option Bytes User nBOOT0 option bit
* @{ * @{
*/ */
#define OB_BOOT0_RESET 0x0000000U /*!< nBOOT0 = 0 */ #define OB_BOOT0_RESET 0x00000000U /*!< nBOOT0 = 0 */
#define OB_BOOT0_SET (FLASH_OPTR_nBOOT0) /*!< nBOOT0 = 1 */ #define OB_BOOT0_SET FLASH_OPTR_nBOOT0 /*!< nBOOT0 = 1 */
/** /**
* @} * @}
*/ */
@ -446,10 +448,10 @@ typedef struct
/** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type /** @defgroup FLASH_OB_PCROP_RDP FLASH Option Bytes PCROP On RDP Level Type
* @{ * @{
*/ */
#define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level #define OB_PCROP_RDP_NOT_ERASE 0x00000000U /*!< PCROP area is not erased when the RDP level
is decreased from Level 1 to Level 0 */ is decreased from Level 1 to Level 0 */
#define OB_PCROP_RDP_ERASE (FLASH_PCROP1AER_PCROP_RDP) /*!< PCROP area is erased when the RDP level is #define OB_PCROP_RDP_ERASE FLASH_PCROP1AER_PCROP_RDP /*!< PCROP area is erased when the RDP level is
decreased from Level 1 to Level 0 (full mass erase) */ decreased from Level 1 to Level 0 (full mass erase) */
/** /**
* @} * @}
*/ */
@ -457,17 +459,17 @@ typedef struct
/** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode /** @defgroup FLASH_OB_SECURITY_MODE Option Bytes FLASH Secure mode
* @{ * @{
*/ */
#define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U /*!< Unsecure mode: Security disabled */ #define SYSTEM_NOT_IN_SECURE_MODE 0x00000000U /*!< Unsecure mode: Security disabled */
#define SYSTEM_IN_SECURE_MODE (FLASH_OPTR_ESE) /*!< Secure mode : Security enabled */ #define SYSTEM_IN_SECURE_MODE FLASH_OPTR_ESE /*!< Secure mode : Security enabled */
/** /**
* @} * @}
*/ */
/** @defgroup FLASH_OB_C2_BOOT_REGION CPU2 Option Bytes Reset Boot Vector /** @defgroup C2_FLASH_OB_BOOT_REGION CPU2 Option Bytes Reset Boot Vector
* @{ * @{
*/ */
#define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from Sram */ #define OB_C2_BOOT_FROM_SRAM 0x00000000U /*!< CPU2 boot from Sram */
#define OB_C2_BOOT_FROM_FLASH (FLASH_SRRVR_C2OPT) /*!< CPU2 boot from Flash */ #define OB_C2_BOOT_FROM_FLASH FLASH_SRRVR_C2OPT /*!< CPU2 boot from Flash */
/** /**
* @} * @}
*/ */
@ -479,39 +481,39 @@ typedef struct
* @{ * @{
*/ */
#define SRAM2A_START_SECURE_ADDR_0 0x20030000U /* When in secure mode 0x20030000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_0 (SRAM2A_BASE + 0x0000U) /* When in secure mode (SRAM2A_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_1 0x20030400U /* When in secure mode 0x20030400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_1 (SRAM2A_BASE + 0x0400U) /* When in secure mode (SRAM2A_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_2 0x20030800U /* When in secure mode 0x20030800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_2 (SRAM2A_BASE + 0x0800U) /* When in secure mode (SRAM2A_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_3 0x20030C00U /* When in secure mode 0x20030C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_3 (SRAM2A_BASE + 0x0C00U) /* When in secure mode (SRAM2A_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_4 0x20031000U /* When in secure mode 0x20031000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_4 (SRAM2A_BASE + 0x1000U) /* When in secure mode (SRAM2A_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_5 0x20031400U /* When in secure mode 0x20031400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_5 (SRAM2A_BASE + 0x1400U) /* When in secure mode (SRAM2A_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_6 0x20031800U /* When in secure mode 0x20031800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_6 (SRAM2A_BASE + 0x1800U) /* When in secure mode (SRAM2A_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_7 0x20031C00U /* When in secure mode 0x20031C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_7 (SRAM2A_BASE + 0x1C00U) /* When in secure mode (SRAM2A_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_8 0x20032000U /* When in secure mode 0x20032000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_8 (SRAM2A_BASE + 0x2000U) /* When in secure mode (SRAM2A_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_9 0x20032400U /* When in secure mode 0x20032400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_9 (SRAM2A_BASE + 0x2400U) /* When in secure mode (SRAM2A_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_10 0x20032800U /* When in secure mode 0x20032800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_10 (SRAM2A_BASE + 0x2800U) /* When in secure mode (SRAM2A_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_11 0x20032C00U /* When in secure mode 0x20032C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_11 (SRAM2A_BASE + 0x2C00U) /* When in secure mode (SRAM2A_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_12 0x20033000U /* When in secure mode 0x20033000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_12 (SRAM2A_BASE + 0x3000U) /* When in secure mode (SRAM2A_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_13 0x20033400U /* When in secure mode 0x20033400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_13 (SRAM2A_BASE + 0x3400U) /* When in secure mode (SRAM2A_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_14 0x20033800U /* When in secure mode 0x20033800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_14 (SRAM2A_BASE + 0x3800U) /* When in secure mode (SRAM2A_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_15 0x20033C00U /* When in secure mode 0x20033C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_15 (SRAM2A_BASE + 0x3C00U) /* When in secure mode (SRAM2A_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_16 0x20034000U /* When in secure mode 0x20034000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_16 (SRAM2A_BASE + 0x4000U) /* When in secure mode (SRAM2A_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_17 0x20034400U /* When in secure mode 0x20034400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_17 (SRAM2A_BASE + 0x4400U) /* When in secure mode (SRAM2A_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_18 0x20034800U /* When in secure mode 0x20034800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_18 (SRAM2A_BASE + 0x4800U) /* When in secure mode (SRAM2A_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_19 0x20034C00U /* When in secure mode 0x20034C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_19 (SRAM2A_BASE + 0x4C00U) /* When in secure mode (SRAM2A_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_20 0x20035000U /* When in secure mode 0x20035000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_20 (SRAM2A_BASE + 0x5000U) /* When in secure mode (SRAM2A_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_21 0x20035400U /* When in secure mode 0x20035400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_21 (SRAM2A_BASE + 0x5400U) /* When in secure mode (SRAM2A_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_22 0x20035800U /* When in secure mode 0x20035800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_22 (SRAM2A_BASE + 0x5800U) /* When in secure mode (SRAM2A_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_23 0x20035C00U /* When in secure mode 0x20035C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_23 (SRAM2A_BASE + 0x5C00U) /* When in secure mode (SRAM2A_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_24 0x20036000U /* When in secure mode 0x20036000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_24 (SRAM2A_BASE + 0x6000U) /* When in secure mode (SRAM2A_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_25 0x20036400U /* When in secure mode 0x20036400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_25 (SRAM2A_BASE + 0x6400U) /* When in secure mode (SRAM2A_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_26 0x20036800U /* When in secure mode 0x20036800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_26 (SRAM2A_BASE + 0x6800U) /* When in secure mode (SRAM2A_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_27 0x20036C00U /* When in secure mode 0x20036C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_27 (SRAM2A_BASE + 0x6C00U) /* When in secure mode (SRAM2A_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_28 0x20037000U /* When in secure mode 0x20037000 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_28 (SRAM2A_BASE + 0x7000U) /* When in secure mode (SRAM2A_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_29 0x20037400U /* When in secure mode 0x20037400 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_29 (SRAM2A_BASE + 0x7400U) /* When in secure mode (SRAM2A_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_30 0x20037800U /* When in secure mode 0x20037800 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_30 (SRAM2A_BASE + 0x7800U) /* When in secure mode (SRAM2A_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_START_SECURE_ADDR_31 0x20037C00U /* When in secure mode 0x20037C00 - 0x20037FFF is accessible only by M0 Plus */ #define SRAM2A_START_SECURE_ADDR_31 (SRAM2A_BASE + 0x7C00U) /* When in secure mode (SRAM2A_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2A_FULL_UNSECURE 0x20040000U /* The RAM2A is accessible to M0 Plus and M4 */ #define SRAM2A_FULL_UNSECURE (SRAM2A_BASE + 0x8000U) /* The RAM2A is accessible to M0 Plus and M4 */
/** /**
* @} * @}
@ -521,39 +523,39 @@ typedef struct
* @{ * @{
*/ */
#define SRAM2B_START_SECURE_ADDR_0 0x20038000U /* When in secure mode 0x20038000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_0 (SRAM2B_BASE + 0x0000U) /* When in secure mode (SRAM2B_BASE + 0x0000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_1 0x20038400U /* When in secure mode 0x20038400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_1 (SRAM2B_BASE + 0x0400U) /* When in secure mode (SRAM2B_BASE + 0x0400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_2 0x20038800U /* When in secure mode 0x20038800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_2 (SRAM2B_BASE + 0x0800U) /* When in secure mode (SRAM2B_BASE + 0x0800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_3 0x20038C00U /* When in secure mode 0x20038C00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_3 (SRAM2B_BASE + 0x0C00U) /* When in secure mode (SRAM2B_BASE + 0x0C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_4 0x20039000U /* When in secure mode 0x20039000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_4 (SRAM2B_BASE + 0x1000U) /* When in secure mode (SRAM2B_BASE + 0x1000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_5 0x20039400U /* When in secure mode 0x20039400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_5 (SRAM2B_BASE + 0x1400U) /* When in secure mode (SRAM2B_BASE + 0x1400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_6 0x20039800U /* When in secure mode 0x20039800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_6 (SRAM2B_BASE + 0x1800U) /* When in secure mode (SRAM2B_BASE + 0x1800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_7 0x20039C00U /* When in secure mode 0x20039C00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_7 (SRAM2B_BASE + 0x1C00U) /* When in secure mode (SRAM2B_BASE + 0x1C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_8 0x2003A000U /* When in secure mode 0x2003A000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_8 (SRAM2B_BASE + 0x2000U) /* When in secure mode (SRAM2B_BASE + 0x2000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_9 0x2003A400U /* When in secure mode 0x2003A400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_9 (SRAM2B_BASE + 0x2400U) /* When in secure mode (SRAM2B_BASE + 0x2400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_10 0x2003A800U /* When in secure mode 0x2003A800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_10 (SRAM2B_BASE + 0x2800U) /* When in secure mode (SRAM2B_BASE + 0x2800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_11 0x2003AC00U /* When in secure mode 0x2003AC00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_11 (SRAM2B_BASE + 0x2C00U) /* When in secure mode (SRAM2B_BASE + 0x2C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_12 0x2003B000U /* When in secure mode 0x2003B000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_12 (SRAM2B_BASE + 0x3000U) /* When in secure mode (SRAM2B_BASE + 0x3000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_13 0x2003B400U /* When in secure mode 0x2003B400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_13 (SRAM2B_BASE + 0x3400U) /* When in secure mode (SRAM2B_BASE + 0x3400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_14 0x2003B800U /* When in secure mode 0x2003B800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_14 (SRAM2B_BASE + 0x3800U) /* When in secure mode (SRAM2B_BASE + 0x3800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_15 0x2003BC00U /* When in secure mode 0x2003BC00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_15 (SRAM2B_BASE + 0x3C00U) /* When in secure mode (SRAM2B_BASE + 0x3C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_16 0x2003C000U /* When in secure mode 0x2003C000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_16 (SRAM2B_BASE + 0x4000U) /* When in secure mode (SRAM2B_BASE + 0x4000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_17 0x2003C400U /* When in secure mode 0x2003C400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_17 (SRAM2B_BASE + 0x4400U) /* When in secure mode (SRAM2B_BASE + 0x4400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_18 0x2003C800U /* When in secure mode 0x2003C800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_18 (SRAM2B_BASE + 0x4800U) /* When in secure mode (SRAM2B_BASE + 0x4800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_19 0x2003CC00U /* When in secure mode 0x2003CC00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_19 (SRAM2B_BASE + 0x4C00U) /* When in secure mode (SRAM2B_BASE + 0x4C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_20 0x2003D000U /* When in secure mode 0x2003D000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_20 (SRAM2B_BASE + 0x5000U) /* When in secure mode (SRAM2B_BASE + 0x5000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_21 0x2003D400U /* When in secure mode 0x2003D400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_21 (SRAM2B_BASE + 0x5400U) /* When in secure mode (SRAM2B_BASE + 0x5400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_22 0x2003D800U /* When in secure mode 0x2003D800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_22 (SRAM2B_BASE + 0x5800U) /* When in secure mode (SRAM2B_BASE + 0x5800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_23 0x2003DC00U /* When in secure mode 0x2003DC00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_23 (SRAM2B_BASE + 0x5C00U) /* When in secure mode (SRAM2B_BASE + 0x5C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_24 0x2003E000U /* When in secure mode 0x2003E000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_24 (SRAM2B_BASE + 0x6000U) /* When in secure mode (SRAM2B_BASE + 0x6000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_25 0x2003E400U /* When in secure mode 0x2003E400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_25 (SRAM2B_BASE + 0x6400U) /* When in secure mode (SRAM2B_BASE + 0x6400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_26 0x2003E800U /* When in secure mode 0x2003E800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_26 (SRAM2B_BASE + 0x6800U) /* When in secure mode (SRAM2B_BASE + 0x6800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_27 0x2003EC00U /* When in secure mode 0x2003EC00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_27 (SRAM2B_BASE + 0x6C00U) /* When in secure mode (SRAM2B_BASE + 0x6C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_28 0x2003F000U /* When in secure mode 0x2003F000 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_28 (SRAM2B_BASE + 0x7000U) /* When in secure mode (SRAM2B_BASE + 0x7000) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_29 0x2003F400U /* When in secure mode 0x2003F400 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_29 (SRAM2B_BASE + 0x7400U) /* When in secure mode (SRAM2B_BASE + 0x7400) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_30 0x2003F800U /* When in secure mode 0x2003F800 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_30 (SRAM2B_BASE + 0x7800U) /* When in secure mode (SRAM2B_BASE + 0x7800) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_START_SECURE_ADDR_31 0x2003FC00U /* When in secure mode 0x2003FC00 - 0x2003FFFF is accessible only by M0 Plus */ #define SRAM2B_START_SECURE_ADDR_31 (SRAM2B_BASE + 0x7C00U) /* When in secure mode (SRAM2B_BASE + 0x7C00) -> SRAM2B_END_ADDR is accessible only by M0 Plus */
#define SRAM2B_FULL_UNSECURE 0x2003FF00U /* The RAM2B is accessible to M0 Plus and M4 */ #define SRAM2B_FULL_UNSECURE (SRAM2B_BASE + 0x8000U) /* The RAM2B is accessible to M0 Plus and M4 */
/** /**
* @} * @}
@ -706,7 +708,7 @@ typedef struct
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
* @retval The new state of FLASH_FLAG (SET or RESET). * @retval The new state of FLASH_FLAG (SET or RESET).
*/ */
#define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) ? \ #define __HAL_FLASH_GET_FLAG(__FLAG__) ((((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) ? \
(READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \ (READ_BIT(FLASH->ECCR, (__FLAG__)) == (__FLAG__)) : \
(READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__))) (READ_BIT(FLASH->SR, (__FLAG__)) == (__FLAG__)))
/** /**
@ -726,11 +728,13 @@ typedef struct
* @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag * @arg @ref FLASH_FLAG_OPTVERR FLASH Option validity error flag
* @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected * @arg @ref FLASH_FLAG_ECCC FLASH one ECC error has been detected and corrected
* @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected * @arg @ref FLASH_FLAG_ECCD FLASH two ECC errors have been detected
* @arg @ref FLASH_FLAG_SR_ERRORS FLASH All SR errors flags
* @arg @ref FLASH_FLAG_ECCR_ERRORS FLASH All ECCR errors flags
* @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags * @arg @ref FLASH_FLAG_ALL_ERRORS FLASH All errors flags
* @retval None * @retval None
*/ */
#define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ #define __HAL_FLASH_CLEAR_FLAG(__FLAG__) do { if(((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS)) != 0U) { SET_BIT(FLASH->ECCR, ((__FLAG__) & (FLASH_FLAG_ECCR_ERRORS))); }\
if(((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCC | FLASH_FLAG_ECCD))); }\ if(((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS)) != 0U) { WRITE_REG(FLASH->SR, ((__FLAG__) & ~(FLASH_FLAG_ECCR_ERRORS))); }\
} while(0) } while(0)
/** /**
* @} * @}
@ -807,27 +811,26 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
/** @defgroup FLASH_Private_Constants FLASH Private Constants /** @defgroup FLASH_Private_Constants FLASH Private Constants
* @{ * @{
*/ */
#define FLASH_SIZE (((uint32_t)(*((uint16_t *)FLASHSIZE_BASE)) & (0x07FFUL)) << 10U) #define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
#define FLASH_END_ADDR (FLASH_BASE + FLASH_SIZE - 1U)
#define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */ #define FLASH_BANK_SIZE FLASH_SIZE /*!< FLASH Bank Size */
#define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4KBytes */ #define FLASH_PAGE_SIZE 0x00001000U /*!< FLASH Page Size, 4 KBytes */
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */ #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE)
#define FLASH_TIMEOUT_VALUE 1000U /*!< FLASH Execution Timeout, 1 s */
#define FLASH_WRP_GRANULARITY 0x00001000U /*!< FLASH Write Protection Granularity, 4KBytes */ #define FLASH_PCROP_GRANULARITY_OFFSET 11U /*!< FLASH Code Readout Protection granularity offset */
#define FLASH_PCROP_GRANULARITY 0x00000800U /*!< FLASH Code Readout Protection Granularity, 2KBytes */ #define FLASH_PCROP_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< FLASH Code Readout Protection granularity, 2 KBytes */
#define FLASH_SECURE_PAGE_GRANULARITY 0x00001000U /*!< FLASH Code Readout Protection Granularity, 4KBytes */
#define FLASH_TYPENONE 0x00000000u /*!< No Programming Procedure On Going */ #define FLASH_TYPENONE 0x00000000U /*!< No Programmation Procedure On Going */
/** /**
* @} * @}
*/ */
/** @defgroup SRAM_MEMORY_SIZE SRAM memory size /** @defgroup SRAM_MEMORY_SIZE SRAM memory size
* @{ * @{
*/ */
#define SRAM_SECURE_PAGE_GRANULARITY 0x00000400U /*!< Secure SRAM2A and SRAM2B Protection Granularity, 1KBytes */ #define SRAM_SECURE_PAGE_GRANULARITY_OFFSET 10U /*!< Secure SRAM2A and SRAM2B Protection granularity offset */
#define SRAM_SECURE_PAGE_GRANULARITY (1UL << FLASH_PCROP_GRANULARITY_OFFSET) /*!< Secure SRAM2A and SRAM2B Protection granularity, 1KBytes */
/** /**
* @} * @}
*/ */
@ -844,11 +847,11 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) #define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL))
#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) ((IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__)) || (IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))) #define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__))
#define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) <= 0xFFU) #define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB)
#define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & ~0x7U) == (__VALUE__)) #define IS_ADDR_ALIGNED_64BITS(__VALUE__) (((__VALUE__) & 0x7U) == (0x00UL))
#define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \ #define IS_FLASH_TYPEERASE(__VALUE__) (((__VALUE__) == FLASH_TYPEERASE_PAGES) || \
((__VALUE__) == FLASH_TYPEERASE_MASSERASE)) ((__VALUE__) == FLASH_TYPEERASE_MASSERASE))
@ -856,13 +859,6 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \ #define IS_FLASH_TYPEPROGRAM(__VALUE__) (((__VALUE__) == FLASH_TYPEPROGRAM_DOUBLEWORD) || \
((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) ((__VALUE__) == FLASH_TYPEPROGRAM_FAST))
#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \
(((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \
(((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \
(((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U))))
#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__))) #define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~(uint32_t)0xFFFU) == (__VALUE__)))
#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) #define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) #define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__)))
@ -908,10 +904,17 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout);
#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) #define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U)
#define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) #define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__))
#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) ((((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1U))) || \
(((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE - 1U))) || \
(((__VALUE__) >= SRAM2A_BASE) && ((__VALUE__) <= (SRAM2A_BASE + SRAM2A_SIZE - 1U))) || \
(((__VALUE__) >= SRAM2B_BASE) && ((__VALUE__) <= (SRAM2B_BASE + SRAM2B_SIZE - 1U))))
#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM))
#define IS_OB_SECURE_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_SECURE_CONFIG_MEMORY | OB_SECURE_CONFIG_BOOT_RESET)) == 0U)
#define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ #define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \
((__VALUE__) == FLASH_LATENCY_1) || \ ((__VALUE__) == FLASH_LATENCY_1) || \
((__VALUE__) == FLASH_LATENCY_2) || \ ((__VALUE__) == FLASH_LATENCY_2) || \

241
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_flash_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.c
View File

@ -57,9 +57,9 @@
(++) Suspend or Allow new program or erase operation request using HAL_FLASHEx_SuspendOperation() and (++) Suspend or Allow new program or erase operation request using HAL_FLASHEx_SuspendOperation() and
HAL_FLASHEx_AllowOperation() functions HAL_FLASHEx_AllowOperation() functions
(#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck. (#) Check is flash content is empty or not using HAL_FLASHEx_FlashEmptyCheck().
and modify this setting (for flash loader purpose e.g.) using and modify this setting (for flash loader purpose e.g.) using
HAL_FLASHEx_ForceFlashEmpty. HAL_FLASHEx_ForceFlashEmpty().
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
@ -103,7 +103,8 @@ static void FLASH_AcknowledgePageErase(void);
static void FLASH_FlushCaches(void); static void FLASH_FlushCaches(void);
static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset); static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32_t WRDPEndOffset);
static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel); static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t RDPLevel);
static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr, uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr); static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr);
static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr);
static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr); static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr);
static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam); static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam);
static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset); static void FLASH_OB_GetWRP(uint32_t WRPArea, uint32_t *WRPStartOffset, uint32_t *WRDPEndOffset);
@ -174,6 +175,8 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t
/* Wait for last operation to be completed */ /* Wait for last operation to be completed */
status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE); status = FLASH_WaitForLastOperation(FLASH_TIMEOUT_VALUE);
/* If operation is completed or interrupted, no need to clear the Mass Erase Bit */
} }
else else
{ {
@ -284,9 +287,7 @@ HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
*/ */
HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit) HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
{ {
uint32_t optrRDPLevel; uint32_t optr;
uint32_t optrUserType;
uint32_t optrUserConfig;
HAL_StatusTypeDef status; HAL_StatusTypeDef status;
/* Check the parameters */ /* Check the parameters */
@ -304,35 +305,31 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset); FLASH_OB_WRPConfig(pOBInit->WRPArea, pOBInit->WRPStartOffset, pOBInit->WRPEndOffset);
} }
/* Option register (either RDP or USER)*/ /* Option register */
if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) != 0U) if ((pOBInit->OptionType & (OPTIONBYTE_RDP | OPTIONBYTE_USER)) == (OPTIONBYTE_RDP | OPTIONBYTE_USER))
{ {
if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
{
/* Modify RDP */
optrRDPLevel = pOBInit->RDPLevel;
}
else
{
/* Do not modify RDP */
optrRDPLevel = FLASH_OB_GetRDP();
}
if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
{
/* Modify User Data */
optrUserType = pOBInit->UserType;
optrUserConfig = pOBInit->UserConfig;
}
else
{
/* Do not modifiy User Data */
optrUserType = FLASH_OB_GetUser();
optrUserConfig = FLASH_OB_GetUser();
}
/* Fully modify OPTR register with RDP & user datas */ /* Fully modify OPTR register with RDP & user datas */
FLASH_OB_OptrConfig(optrUserType, optrUserConfig, optrRDPLevel); FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, pOBInit->RDPLevel);
}
else if ((pOBInit->OptionType & OPTIONBYTE_RDP) != 0U)
{
/* Only modify RDP so get current user data */
optr = FLASH_OB_GetUser();
/* Remove BOR LEVEL User Type*/
optr &= ~OB_USER_BOR_LEV;
FLASH_OB_OptrConfig(optr, optr, pOBInit->RDPLevel);
}
else if ((pOBInit->OptionType & OPTIONBYTE_USER) != 0U)
{
/* Only modify user so get current RDP level */
optr = FLASH_OB_GetRDP();
FLASH_OB_OptrConfig(pOBInit->UserType, pOBInit->UserConfig, optr);
}
else
{
/* Do Nothing */
} }
/* PCROP Configuration */ /* PCROP Configuration */
@ -341,10 +338,16 @@ HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig)); assert_param(IS_OB_PCROP_CONFIG(pOBInit->PCROPConfig));
if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) != 0U) if ((pOBInit->PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0U)
{ {
/* Configure the Zone 1A, 1B Proprietary code readout protection */ /* Configure the Zone 1A Proprietary code readout protection */
FLASH_OB_PCROPConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr, pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr); FLASH_OB_PCROP1AConfig(pOBInit->PCROPConfig, pOBInit->PCROP1AStartAddr, pOBInit->PCROP1AEndAddr);
}
if ((pOBInit->PCROPConfig & OB_PCROP_ZONE_B) != 0U)
{
/* Configure the Zone 1B Proprietary code readout protection */
FLASH_OB_PCROP1BConfig(pOBInit->PCROP1BStartAddr, pOBInit->PCROP1BEndAddr);
} }
} }
@ -387,8 +390,11 @@ void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
{ {
pOBInit->OptionType = OPTIONBYTE_ALL; pOBInit->OptionType = OPTIONBYTE_ALL;
/* Get write protection on the selected area */ if ((pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAA) || (pOBInit->WRPArea == OB_WRPAREA_BANK1_AREAB))
FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset)); {
/* Get write protection on the selected area */
FLASH_OB_GetWRP(pOBInit->WRPArea, &(pOBInit->WRPStartOffset), &(pOBInit->WRPEndOffset));
}
/* Get Read protection level */ /* Get Read protection level */
pOBInit->RDPLevel = FLASH_OB_GetRDP(); pOBInit->RDPLevel = FLASH_OB_GetRDP();
@ -513,10 +519,8 @@ uint32_t HAL_FLASHEx_IsOperationSuspended(void)
*/ */
static void FLASH_MassErase(void) static void FLASH_MassErase(void)
{ {
/* Set the Mass Erase Bit */ /* Set the Mass Erase Bit and start bit */
SET_BIT(FLASH->CR, FLASH_CR_MER); SET_BIT(FLASH->CR, (FLASH_CR_MER | FLASH_CR_STRT));
/* Proceed to erase all sectors */
SET_BIT(FLASH->CR, FLASH_CR_STRT);
} }
/** /**
@ -531,8 +535,7 @@ void FLASH_PageErase(uint32_t Page)
assert_param(IS_FLASH_PAGE(Page)); assert_param(IS_FLASH_PAGE(Page));
/* Proceed to erase the page */ /* Proceed to erase the page */
MODIFY_REG(FLASH->CR, (FLASH_CR_PNB | FLASH_CR_PER), ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER)); MODIFY_REG(FLASH->CR, FLASH_CR_PNB, ((Page << FLASH_CR_PNB_Pos) | FLASH_CR_PER | FLASH_CR_STRT));
SET_BIT(FLASH->CR, FLASH_CR_STRT);
} }
/** /**
@ -617,7 +620,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
} }
/** /**
* @brief Set user & RDP configiuration * @brief Set user & RDP configuration
* @note !!! Warning : When enabling OB_RDP level 2 it's no more possible * @note !!! Warning : When enabling OB_RDP level 2 it's no more possible
* to go back to level 1 or 0 !!! * to go back to level 1 or 0 !!!
* @param UserType The FLASH User Option Bytes to be modified * @param UserType The FLASH User Option Bytes to be modified
@ -630,7 +633,7 @@ static void FLASH_OB_WRPConfig(uint32_t WRPArea, uint32_t WRPStartOffset, uint32
* @param UserConfig The FLASH User Option Bytes values. * @param UserConfig The FLASH User Option Bytes values.
* This parameter can be a combination of all the following values: * This parameter can be a combination of all the following values:
* @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4 * @arg @ref OB_BOR_LEVEL_0 or @ref OB_BOR_LEVEL_1 or ... or @ref OB_BOR_LEVEL_4
* @arg @ref OB_STOP_RST or @ref OB_STOP_RST * @arg @ref OB_STOP_RST or @ref OB_STOP_NORST
* @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST * @arg @ref OB_STANDBY_RST or @ref OB_STANDBY_NORST
* @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST * @arg @ref OB_SHUTDOWN_RST or @ref OB_SHUTDOWN_NORST
* @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW * @arg @ref OB_IWDG_SW or @ref OB_IWDG_HW
@ -666,7 +669,7 @@ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t
} }
/** /**
* @brief Configure the Zone 1A, 1B Proprietary code readout protection of the desired addresses, * @brief Configure the Zone 1A Proprietary code readout protection of the desired addresses,
* and erase configuration on RDP regression. * and erase configuration on RDP regression.
* @note To configure the PCROP options, the option lock bit OPTLOCK must be * @note To configure the PCROP options, the option lock bit OPTLOCK must be
* cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
@ -678,13 +681,9 @@ static void FLASH_OB_OptrConfig(uint32_t UserType, uint32_t UserConfig, uint32_t
* This parameter can be an address between begin and end of the flash * This parameter can be an address between begin and end of the flash
* @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection * @param PCROP1AEndAddr Specifies the Zone 1A end address of the Proprietary code readout protection
* This parameter can be an address between PCROP1AStartAddr and end of the flash * This parameter can be an address between PCROP1AStartAddr and end of the flash
* @param PCROP1BStartAddr Specifies the Zone 1B Start address of the Proprietary code readout protection
* This parameter can be an address between begin and end of the flash
* @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection
* This parameter can be an address between PCROP1BStartAddr and end of the flash
* @retval None * @retval None
*/ */
static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr, uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr) static void FLASH_OB_PCROP1AConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr, uint32_t PCROP1AEndAddr)
{ {
uint32_t startoffset; uint32_t startoffset;
uint32_t endoffset; uint32_t endoffset;
@ -692,55 +691,67 @@ static void FLASH_OB_PCROPConfig(uint32_t PCROPConfig, uint32_t PCROP1AStartAddr
/* Check the parameters */ /* Check the parameters */
assert_param(IS_OB_PCROP_CONFIG(PCROPConfig)); assert_param(IS_OB_PCROP_CONFIG(PCROPConfig));
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr));
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr));
if ((PCROPConfig & OB_PCROP_ZONE_B) == OB_PCROP_ZONE_B) /* get pcrop 1A end register */
pcrop1aend = FLASH->PCROP1AER;
/* Configure the Proprietary code readout protection offset */
if ((PCROPConfig & OB_PCROP_ZONE_A) != 0U)
{ {
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr));
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr));
/* Compute offset depending on pcrop granularity */ /* Compute offset depending on pcrop granularity */
startoffset = ((PCROP1BStartAddr - FLASH_BASE) / FLASH_PCROP_GRANULARITY); /* 2K pages */ startoffset = ((PCROP1AStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
endoffset = ((PCROP1BEndAddr - FLASH_BASE) / FLASH_PCROP_GRANULARITY); /* 2K pages */ endoffset = ((PCROP1AEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
/* Configure the Proprietary code readout protection start address */ /* Set Zone A start offset */
MODIFY_REG(FLASH->PCROP1BSR, FLASH_PCROP1BSR_PCROP1B_STRT, startoffset); WRITE_REG(FLASH->PCROP1ASR, startoffset);
/* Configure the Proprietary code readout protection end address */ /* Set Zone A end offset */
MODIFY_REG(FLASH->PCROP1BER, FLASH_PCROP1BER_PCROP1B_END, endoffset); pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END;
pcrop1aend |= endoffset;
} }
if ((PCROPConfig & (OB_PCROP_ZONE_A | OB_PCROP_RDP_ERASE)) != 0U) /* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */
if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0U)
{ {
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AStartAddr)); pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP;
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1AEndAddr));
/* get pcrop 1A end register */
pcrop1aend = FLASH->PCROP1AER;
/* Configure the Proprietary code readout protection offset */
if ((PCROPConfig & OB_PCROP_ZONE_A) != 0U)
{
/* Compute offset depending on pcrop granularity */
startoffset = ((PCROP1AStartAddr - FLASH_BASE) / FLASH_PCROP_GRANULARITY); /* 2K pages */
endoffset = ((PCROP1AEndAddr - FLASH_BASE) / FLASH_PCROP_GRANULARITY); /* 2K pages */
/* Set Zone A start offset */
MODIFY_REG(FLASH->PCROP1ASR, FLASH_PCROP1ASR_PCROP1A_STRT, startoffset);
/* Set Zone A end offset */
pcrop1aend &= ~FLASH_PCROP1AER_PCROP1A_END;
pcrop1aend |= endoffset;
}
/* Set RDP erase protection if needed. This bit is only set & will be reset by mass erase */
if ((PCROPConfig & OB_PCROP_RDP_ERASE) != 0U)
{
pcrop1aend |= FLASH_PCROP1AER_PCROP_RDP;
}
/* set 1A End register */
MODIFY_REG(FLASH->PCROP1AER, FLASH_PCROP1AER_PCROP1A_END, pcrop1aend);
} }
/* set 1A End register */
WRITE_REG(FLASH->PCROP1AER, pcrop1aend);
}
/**
* @brief Configure the Zone 1B Proprietary code readout protection of the desired addresses.
* @note To configure the PCROP options, the option lock bit OPTLOCK must be
* cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
* @note To validate the PCROP options, the option bytes must be reloaded
* through the call of the @ref HAL_FLASH_OB_Launch() function.
* @param PCROP1BStartAddr Specifies the Zone 1BStart address of the Proprietary code readout protection
* This parameter can be an address between begin and end of the flash
* @param PCROP1BEndAddr Specifies the Zone 1B end address of the Proprietary code readout protection
* This parameter can be an address between PCROP1BStartAddr and end of the flash
* @retval None
*/
static void FLASH_OB_PCROP1BConfig(uint32_t PCROP1BStartAddr, uint32_t PCROP1BEndAddr)
{
uint32_t startoffset;
uint32_t endoffset;
/* Check the parameters */
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BStartAddr));
assert_param(IS_FLASH_MAIN_MEM_ADDRESS(PCROP1BEndAddr));
/* Compute offset depending on pcrop granularity */
startoffset = ((PCROP1BStartAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
endoffset = ((PCROP1BEndAddr - FLASH_BASE) >> FLASH_PCROP_GRANULARITY_OFFSET); /* 2K pages */
/* Configure the Proprietary code readout protection start address */
WRITE_REG(FLASH->PCROP1BSR, startoffset);
/* Configure the Proprietary code readout protection end address */
WRITE_REG(FLASH->PCROP1BER, endoffset);
} }
/** /**
@ -758,12 +769,12 @@ static void FLASH_OB_IPCCBufferAddrConfig(uint32_t IPCCDataBufAddr)
assert_param(IS_OB_IPCC_BUF_ADDR(IPCCDataBufAddr)); assert_param(IS_OB_IPCC_BUF_ADDR(IPCCDataBufAddr));
/* Configure the option bytes register */ /* Configure the option bytes register */
MODIFY_REG(FLASH->IPCCBR, FLASH_IPCCBR_IPCCDBA, (uint32_t)((IPCCDataBufAddr - SRAM2A_BASE) >> 4)); WRITE_REG(FLASH->IPCCBR, (uint32_t)((IPCCDataBufAddr - SRAM2A_BASE) >> 4));
} }
/** /**
* @brief Configure the secure start address of the different memories (FLASH and SRAM2) * @brief Configure the secure start address of the different memories (FLASH and SRAM2),
* , the secure mode and the CPU2 Secure Boot reset vector * the secure mode and the CPU2 Secure Boot reset vector
* @note To configure the PCROP options, the option lock bit OPTLOCK must be * @note To configure the PCROP options, the option lock bit OPTLOCK must be
* cleared with the call of the @ref HAL_FLASH_OB_Unlock() function. * cleared with the call of the @ref HAL_FLASH_OB_Unlock() function.
* @param pOBParam Pointer to an @ref FLASH_OBProgramInitTypeDef structure that * @param pOBParam Pointer to an @ref FLASH_OBProgramInitTypeDef structure that
@ -783,14 +794,14 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam)
assert_param(IS_OB_SECURE_MODE(pOBParam->SecureMode)); assert_param(IS_OB_SECURE_MODE(pOBParam->SecureMode));
/* Configure SFR register content with start PAGE index to secure */ /* Configure SFR register content with start PAGE index to secure */
MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (uint32_t)((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE)); MODIFY_REG(sfr_reg_val, FLASH_SFR_SFSA, (((pOBParam->SecureFlashStartAddr - FLASH_BASE) / FLASH_PAGE_SIZE) << FLASH_SFR_SFSA_Pos));
/* Configure SRRVR register */ /* Configure SRRVR register */
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \ MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRSA | FLASH_SRRVR_SNBRSA), \
(((uint32_t)(((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) / SRAM_SECURE_PAGE_GRANULARITY) << FLASH_SRRVR_SBRSA_Pos)) | \ (((((pOBParam->SecureRAM2aStartAddr - SRAM2A_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SBRSA_Pos)) | \
((uint32_t)(((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) / SRAM_SECURE_PAGE_GRANULARITY) << FLASH_SRRVR_SNBRSA_Pos)))); ((((pOBParam->SecureRAM2bStartAddr - SRAM2B_BASE) >> SRAM_SECURE_PAGE_GRANULARITY_OFFSET) << FLASH_SRRVR_SNBRSA_Pos))));
/* If Secure mode is requested, clear the corresponding bit */ /* If Full System Secure mode is requested, clear all the corresponding bit */
/* Else set the corresponding bit */ /* Else set the corresponding bit */
if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE) if (pOBParam->SecureMode == SYSTEM_IN_SECURE_MODE)
{ {
@ -817,11 +828,11 @@ static void FLASH_OB_SecureConfig(FLASH_OBProgramInitTypeDef *pOBParam)
/* Set the boot vector */ /* Set the boot vector */
if (pOBParam->C2BootRegion == OB_C2_BOOT_FROM_FLASH) if (pOBParam->C2BootRegion == OB_C2_BOOT_FROM_FLASH)
{ {
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (uint32_t)((uint32_t)((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion)); MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - FLASH_BASE) >> 2) | pOBParam->C2BootRegion));
} }
else else
{ {
MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (uint32_t)((uint32_t)((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion)); MODIFY_REG(srrvr_reg_val, (FLASH_SRRVR_SBRV | FLASH_SRRVR_C2OPT), (((pOBParam->C2SecureBootVectAddr - SRAM1_BASE) >> 2) | pOBParam->C2BootRegion));
} }
} }
@ -902,8 +913,7 @@ static uint32_t FLASH_OB_GetRDP(void)
static uint32_t FLASH_OB_GetUser(void) static uint32_t FLASH_OB_GetUser(void)
{ {
uint32_t user_config = (READ_REG(FLASH->OPTR) & OB_USER_ALL); uint32_t user_config = (READ_REG(FLASH->OPTR) & OB_USER_ALL);
CLEAR_BIT(user_config, FLASH_OPTR_RDP); CLEAR_BIT(user_config, (FLASH_OPTR_RDP | FLASH_OPTR_ESE));
CLEAR_BIT(user_config, FLASH_OPTR_ESE);
return user_config; return user_config;
} }
@ -926,16 +936,16 @@ static void FLASH_OB_GetPCROP(uint32_t *PCROPConfig, uint32_t *PCROP1AStartAddr,
uint32_t pcrop; uint32_t pcrop;
pcrop = (READ_BIT(FLASH->PCROP1BSR, FLASH_PCROP1BSR_PCROP1B_STRT)); pcrop = (READ_BIT(FLASH->PCROP1BSR, FLASH_PCROP1BSR_PCROP1B_STRT));
*PCROP1BStartAddr = ((pcrop * FLASH_PCROP_GRANULARITY) + FLASH_BASE); *PCROP1BStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
pcrop = (READ_BIT(FLASH->PCROP1BER, FLASH_PCROP1BER_PCROP1B_END)); pcrop = (READ_BIT(FLASH->PCROP1BER, FLASH_PCROP1BER_PCROP1B_END));
*PCROP1BEndAddr = ((pcrop * FLASH_PCROP_GRANULARITY) + FLASH_BASE); *PCROP1BEndAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
pcrop = (READ_BIT(FLASH->PCROP1ASR, FLASH_PCROP1ASR_PCROP1A_STRT)); pcrop = (READ_BIT(FLASH->PCROP1ASR, FLASH_PCROP1ASR_PCROP1A_STRT));
*PCROP1AStartAddr = ((pcrop * FLASH_PCROP_GRANULARITY) + FLASH_BASE); *PCROP1AStartAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
pcrop = (READ_BIT(FLASH->PCROP1AER, FLASH_PCROP1AER_PCROP1A_END)); pcrop = (READ_BIT(FLASH->PCROP1AER, FLASH_PCROP1AER_PCROP1A_END));
*PCROP1AEndAddr = ((pcrop * FLASH_PCROP_GRANULARITY) + FLASH_BASE); *PCROP1AEndAddr = ((pcrop << FLASH_PCROP_GRANULARITY_OFFSET) + FLASH_BASE);
*PCROPConfig = (READ_REG(FLASH->PCROP1AER) & FLASH_PCROP1AER_PCROP_RDP); *PCROPConfig = (READ_REG(FLASH->PCROP1AER) & FLASH_PCROP1AER_PCROP_RDP);
} }
@ -962,18 +972,25 @@ static uint32_t FLASH_OB_GetIPCCBufferAddr(void)
*/ */
static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode) static void FLASH_OB_GetSecureMemoryConfig(uint32_t *SecureFlashStartAddr, uint32_t *SecureRAM2aStartAddr, uint32_t *SecureRAM2bStartAddr, uint32_t *SecureMode)
{ {
uint32_t user_config = (READ_BIT(FLASH->SFR, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos); uint32_t sfr_reg_val = READ_REG(FLASH->SFR);
uint32_t srrvr_reg_val = READ_REG(FLASH->SRRVR);
/* Get Secure Flash start address */
uint32_t user_config = (READ_BIT(sfr_reg_val, FLASH_SFR_SFSA) >> FLASH_SFR_SFSA_Pos);
*SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE); *SecureFlashStartAddr = ((user_config * FLASH_PAGE_SIZE) + FLASH_BASE);
user_config = (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos); /* Get Secure SRAM2a start address */
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SBRSA) >> FLASH_SRRVR_SBRSA_Pos);
*SecureRAM2aStartAddr = ((user_config * SRAM_SECURE_PAGE_GRANULARITY) + SRAM2A_BASE); *SecureRAM2aStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2A_BASE);
user_config = (READ_BIT(FLASH->SRRVR, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos); /* Get Secure SRAM2b start address */
user_config = (READ_BIT(srrvr_reg_val, FLASH_SRRVR_SNBRSA) >> FLASH_SRRVR_SNBRSA_Pos);
*SecureRAM2bStartAddr = ((user_config * SRAM_SECURE_PAGE_GRANULARITY) + SRAM2B_BASE); *SecureRAM2bStartAddr = ((user_config << SRAM_SECURE_PAGE_GRANULARITY_OFFSET) + SRAM2B_BASE);
/* Get Secure Area mode */
*SecureMode = (READ_BIT(FLASH->OPTR, FLASH_OPTR_ESE)); *SecureMode = (READ_BIT(FLASH->OPTR, FLASH_OPTR_ESE));
} }

6
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_flash_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_flash_ex.h
View File

@ -41,11 +41,11 @@ extern "C" {
/** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants /** @defgroup FLASHEx_Exported_Constants FLASH Exported Constants
* @{ * @{
*/ */
/** @defgroup FLASHEx_Empty_Check FLASHEx Empty Check /** @defgroup FLASHEx_EMPTY_CHECK FLASHEx Empty Check
* @{ * @{
*/ */
#define FLASH_PROG_NOT_EMPTY 0x00000000u /*!< 1st location in Flash is programmed */ #define FLASH_PROG_NOT_EMPTY 0x00000000U /*!< 1st location in Flash is programmed */
#define FLASH_PROG_EMPTY FLASH_ACR_EMPTY /*!< 1st location in Flash is empty */ #define FLASH_PROG_EMPTY FLASH_ACR_EMPTY /*!< 1st location in Flash is empty */
/** /**
* @} * @}
*/ */

9
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_gpio.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.c
View File

@ -431,13 +431,13 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_GPIO_PIN(GPIO_Pin)); assert_param(IS_GPIO_PIN(GPIO_Pin));
if ((GPIOx->ODR & GPIO_Pin) == GPIO_Pin) if ((GPIOx->ODR & GPIO_Pin) != 0x00u)
{ {
GPIOx->BSRR = (uint32_t)GPIO_Pin << GPIO_NUMBER; GPIOx->BRR = (uint32_t)GPIO_Pin;
} }
else else
{ {
GPIOx->BSRR = GPIO_Pin; GPIOx->BSRR = (uint32_t)GPIO_Pin;
} }
} }
@ -468,9 +468,10 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
GPIOx->LCKR = GPIO_Pin; GPIOx->LCKR = GPIO_Pin;
/* Set LCKx bit(s): LCKK='1' + LCK[15-0] */ /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
GPIOx->LCKR = tmp; GPIOx->LCKR = tmp;
/* Read LCKK bit*/ /* Read LCKK register. This read is mandatory to complete key lock sequence */
tmp = GPIOx->LCKR; tmp = GPIOx->LCKR;
/* read again in order to confirm lock is active */
if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u) if ((GPIOx->LCKR & GPIO_LCKR_LCKK) != 0x00u)
{ {
return HAL_OK; return HAL_OK;

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_gpio.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio.h
View File

@ -213,8 +213,8 @@ typedef enum
*/ */
#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET)) #define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
#define IS_GPIO_PIN(__PIN__) ((((__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\ #define IS_GPIO_PIN(__PIN__) ((((uint32_t)(__PIN__) & GPIO_PIN_MASK) != 0x00u) &&\
(((__PIN__) & ~GPIO_PIN_MASK) == 0x00u)) (((uint32_t)(__PIN__) & ~GPIO_PIN_MASK) == 0x00u))
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\ #define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\ ((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\

16
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_gpio_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_gpio_ex.h
View File

@ -53,7 +53,9 @@
* *
*/ */
/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 | #if defined (STM32WB55xx) || defined (STM32WB50xx)
/* | AF0 | AF1 | AF2 | AF3 | AF4 | AF5 | AF6 | AF7 |
*_____________________________________________________________________________________________ *_____________________________________________________________________________________________
* |SYS_AF |TIM |TIM |SPI/SAI/TI|I2C | I2C | RF | USART | * |SYS_AF |TIM |TIM |SPI/SAI/TI|I2C | I2C | RF | USART |
*_____________________________________________________________________________________________ *_____________________________________________________________________________________________
@ -358,6 +360,9 @@
#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f) #define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x0f)
#endif
/** /**
* @} * @}
@ -375,13 +380,18 @@
/** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index /** @defgroup GPIOEx_Get_Port_Index GPIOEx Get Port Index
* @{ * @{
*/ */
#if defined (STM32WB55xx)
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\ #define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
((__GPIOx__) == (GPIOB))? 1uL :\ ((__GPIOx__) == (GPIOB))? 1uL :\
((__GPIOx__) == (GPIOC))? 2uL :\ ((__GPIOx__) == (GPIOC))? 2uL :\
((__GPIOx__) == (GPIOD))? 3uL :\ ((__GPIOx__) == (GPIOD))? 3uL :\
((__GPIOx__) == (GPIOE))? 4uL : 7uL) ((__GPIOx__) == (GPIOE))? 4uL : 7uL)
#else
#define GPIO_GET_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0uL :\
((__GPIOx__) == (GPIOB))? 1uL :\
((__GPIOx__) == (GPIOC))? 2uL :\
((__GPIOx__) == (GPIOE))? 4uL : 7uL)
#endif
/** /**
* @} * @}
*/ */

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_hsem.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.c
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_hsem.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_hsem.h
View File

45
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_i2c.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.c
View File

@ -223,12 +223,12 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1 The compilation flag USE_HAL_I2C_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback() Use Functions @ref HAL_I2C_RegisterCallback() or @ref HAL_I2C_RegisterAddrCallback()
to register an interrupt callback. to register an interrupt callback.
[..]
Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks: Function @ref HAL_I2C_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer.
@ -243,9 +243,9 @@
(+) MspDeInitCallback : callback for Msp DeInit. (+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback(). For specific callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_RegisterAddrCallback().
[..]
Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default Use function @ref HAL_I2C_UnRegisterCallback to reset a callback to the default
weak function. weak function.
@ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle, @ref HAL_I2C_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ -262,9 +262,9 @@
(+) AbortCpltCallback : callback for abort completion process. (+) AbortCpltCallback : callback for abort completion process.
(+) MspInitCallback : callback for Msp Init. (+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit. (+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback(). For callback AddrCallback use dedicated register callbacks : @ref HAL_I2C_UnRegisterAddrCallback().
[..]
By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET By default, after the @ref HAL_I2C_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions: all callbacks are set to the corresponding weak functions:
examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback(). examples @ref HAL_I2C_MasterTxCpltCallback(), @ref HAL_I2C_MasterRxCpltCallback().
@ -273,7 +273,7 @@
these callbacks are null (not registered beforehand). these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit() If MspInit or MspDeInit are not null, the @ref HAL_I2C_Init()/ @ref HAL_I2C_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@ -281,7 +281,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit() using @ref HAL_I2C_RegisterCallback() before calling @ref HAL_I2C_DeInit()
or @ref HAL_I2C_Init() function. or @ref HAL_I2C_Init() function.
[..]
When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or When the compilation flag USE_HAL_I2C_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@ -4737,6 +4737,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Process locked */ /* Process locked */
__HAL_LOCK(hi2c); __HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{ {
/* Check that I2C transfer finished */ /* Check that I2C transfer finished */
@ -4788,9 +4795,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
{ {
if (hi2c->XferCount > 0U) if (hi2c->XferCount > 0U)
{ {
/* Remove RXNE flag on temporary variable as read done */
tmpITFlags &= ~I2C_FLAG_RXNE;
/* Read data from RXDR */ /* Read data from RXDR */
*hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR; *hi2c->pBuffPtr = (uint8_t)hi2c->Instance->RXDR;
@ -4844,13 +4848,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
/* Nothing to do */ /* Nothing to do */
} }
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, tmpITFlags);
}
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hi2c); __HAL_UNLOCK(hi2c);
@ -5008,6 +5005,13 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
/* Process locked */ /* Process locked */
__HAL_LOCK(hi2c); __HAL_LOCK(hi2c);
/* Check if STOPF is set */
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET)) if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
{ {
/* Check that I2C transfer finished */ /* Check that I2C transfer finished */
@ -5092,11 +5096,6 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
{ {
I2C_ITAddrCplt(hi2c, ITFlags); I2C_ITAddrCplt(hi2c, ITFlags);
} }
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_STOPF) != RESET) && (I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
}
else else
{ {
/* Nothing to do */ /* Nothing to do */

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_i2c.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c.h
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_i2c_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.c
View File

8
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_i2c_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_i2c_ex.h
View File

@ -55,12 +55,17 @@ extern "C" {
/** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus /** @defgroup I2CEx_FastModePlus I2C Extended Fast Mode Plus
* @{ * @{
*/ */
#define I2C_FMP_NOT_SUPPORTED 0xAAAA0000U /*!< Fast Mode Plus not supported */
#define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */ #define I2C_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
#define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */ #define I2C_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
#define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */ #define I2C_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
#define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */ #define I2C_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
#define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */ #define I2C_FASTMODEPLUS_I2C1 SYSCFG_CFGR1_I2C1_FMP /*!< Enable Fast Mode Plus on I2C1 pins */
#if defined(SYSCFG_CFGR1_I2C3_FMP)
#define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */ #define I2C_FASTMODEPLUS_I2C3 SYSCFG_CFGR1_I2C3_FMP /*!< Enable Fast Mode Plus on I2C3 pins */
#else
#define I2C_FASTMODEPLUS_I2C3 (uint32_t)(0x00000400U | I2C_FMP_NOT_SUPPORTED) /*!< Fast Mode Plus I2C3 not supported */
#endif
/** /**
* @} * @}
*/ */
@ -113,6 +118,9 @@ void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
(((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_PB9)) == I2C_FASTMODEPLUS_PB9) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \ (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C1)) == I2C_FASTMODEPLUS_I2C1) || \
(((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3)) (((__CONFIG__) & (I2C_FASTMODEPLUS_I2C3)) == I2C_FASTMODEPLUS_I2C3))
/** /**
* @} * @}
*/ */

7
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_ipcc.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_ipcc.c
View File

@ -41,11 +41,11 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
@ -55,6 +55,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal.h" #include "stm32wbxx_hal.h"
#if defined(IPCC)
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{
*/ */
@ -742,5 +743,5 @@ void IPCC_Reset_Register(IPCC_CommonTypeDef *Instance)
/** /**
* @} * @}
*/ */
#endif /* IPCC */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

6
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_ipcc.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_ipcc.h
View File

@ -6,11 +6,11 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
@ -28,6 +28,7 @@ extern "C" {
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal_def.h" #include "stm32wbxx_hal_def.h"
#if defined(IPCC)
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{
@ -253,6 +254,7 @@ void HAL_IPCC_RxCallback(IPCC_HandleTypeDef *hipcc, uint32_t ChannelIndex, IPCC_
/** /**
* @} * @}
*/ */
#endif /* IPCC */
#ifdef __cplusplus #ifdef __cplusplus
} }

51
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_irda.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_irda.c
View File

@ -782,10 +782,13 @@ HAL_StatusTypeDef HAL_IRDA_UnRegisterCallback(IRDA_HandleTypeDef *hirda, HAL_IRD
/** /**
* @brief Send an amount of data in blocking mode. * @brief Send an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module. * the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer. * @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data to be sent. * @param Size Amount of data elements (u8 or u16) to be sent.
* @param Timeout Specify timeout value. * @param Timeout Specify timeout value.
* @retval HAL status * @retval HAL status
*/ */
@ -868,10 +871,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, u
/** /**
* @brief Receive an amount of data in blocking mode. * @brief Receive an amount of data in blocking mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module. * the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer. * @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data to be received. * @param Size Amount of data elements (u8 or u16) to be received.
* @param Timeout Specify timeout value. * @param Timeout Specify timeout value.
* @retval HAL status * @retval HAL status
*/ */
@ -956,10 +962,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, ui
/** /**
* @brief Send an amount of data in interrupt mode. * @brief Send an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module. * the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer. * @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data to be sent. * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -998,10 +1007,13 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData
/** /**
* @brief Receive an amount of data in interrupt mode. * @brief Receive an amount of data in interrupt mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module. * the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer. * @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data to be received. * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1047,10 +1059,13 @@ HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData,
/** /**
* @brief Send an amount of data in DMA mode. * @brief Send an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the sent data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module. * the configuration information for the specified IRDA module.
* @param pData pointer to data buffer. * @param pData pointer to data buffer (u8 or u16 data elements).
* @param Size amount of data to be sent. * @param Size Amount of data elements (u8 or u16) to be sent.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -1122,12 +1137,15 @@ HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pDat
/** /**
* @brief Receive an amount of data in DMA mode. * @brief Receive an amount of data in DMA mode.
* @note When UART parity is not enabled (PCE = 0), and Word Length is configured to 9 bits (M1-M0 = 01),
* the received data is handled as a set of u16. In this case, Size must reflect the number
* of u16 available through pData.
* @note When the IRDA parity is enabled (PCE = 1), the received data contains * @note When the IRDA parity is enabled (PCE = 1), the received data contains
* the parity bit (MSB position). * the parity bit (MSB position).
* @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module. * the configuration information for the specified IRDA module.
* @param pData Pointer to data buffer. * @param pData Pointer to data buffer (u8 or u16 data elements).
* @param Size Amount of data to be received. * @param Size Amount of data elements (u8 or u16) to be received.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size) HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@ -2213,6 +2231,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
IRDA_ClockSourceTypeDef clocksource; IRDA_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK; HAL_StatusTypeDef ret = HAL_OK;
const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; const uint16_t IRDAPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the communication parameters */ /* Check the communication parameters */
assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate)); assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));
@ -2241,7 +2260,7 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler); MODIFY_REG(hirda->Instance->PRESC, USART_PRESC_PRESCALER, hirda->Init.ClockPrescaler);
/*-------------------------- USART GTPR Configuration ----------------------*/ /*-------------------------- USART GTPR Configuration ----------------------*/
MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler); MODIFY_REG(hirda->Instance->GTPR, (uint16_t)USART_GTPR_PSC, (uint16_t)hirda->Init.Prescaler);
/*-------------------------- USART BRR Configuration -----------------------*/ /*-------------------------- USART BRR Configuration -----------------------*/
IRDA_GETCLOCKSOURCE(hirda, clocksource); IRDA_GETCLOCKSOURCE(hirda, clocksource);
@ -2249,13 +2268,15 @@ static HAL_StatusTypeDef IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
switch (clocksource) switch (clocksource)
{ {
case IRDA_CLOCKSOURCE_PCLK2: case IRDA_CLOCKSOURCE_PCLK2:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break; break;
case IRDA_CLOCKSOURCE_HSI: case IRDA_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HSI_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break; break;
case IRDA_CLOCKSOURCE_SYSCLK: case IRDA_CLOCKSOURCE_SYSCLK:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(HAL_RCC_GetSysClockFreq(), hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); pclk = HAL_RCC_GetSysClockFreq();
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16(pclk, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));
break; break;
case IRDA_CLOCKSOURCE_LSE: case IRDA_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler)); tmpreg = (uint16_t)(IRDA_DIV_SAMPLING16((uint32_t)LSE_VALUE, hirda->Init.BaudRate, hirda->Init.ClockPrescaler));

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_irda.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_irda.h
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_irda_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_irda_ex.h
View File

24
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_iwdg.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_iwdg.c
View File

@ -36,7 +36,7 @@
(+) Debug mode : When the microcontroller enters debug mode (core halted), (+) Debug mode : When the microcontroller enters debug mode (core halted),
the IWDG counter either continues to work normally or stops, depending the IWDG counter either continues to work normally or stops, depending
on DBG_IWDG_STOP configuration bit in DBG module, accessible through on DBG_IWDG_STOP configuration bit in DBG module, accessible through
__HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros __HAL_DBGMCU_FREEZE_IWDG() and __HAL_DBGMCU_UNFREEZE_IWDG() macros.
[..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s [..] Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx The IWDG timeout may vary due to LSI frequency dispersion. STM32WBxx
@ -48,19 +48,19 @@
============================================================================== ==============================================================================
[..] [..]
(#) Use IWDG using HAL_IWDG_Init() function to : (#) Use IWDG using HAL_IWDG_Init() function to :
(+) Enable instance by writing Start keyword in IWDG_KEY register. LSI (++) Enable instance by writing Start keyword in IWDG_KEY register. LSI
clock is forced ON and IWDG counter starts downcounting. clock is forced ON and IWDG counter starts counting down.
(+) Enable write access to configuration register: IWDG_PR, IWDG_RLR & (++) Enable write access to configuration registers:
IWDG_WINR. IWDG_PR, IWDG_RLR and IWDG_WINR.
(+) Configure the IWDG prescaler and counter reload value. This reload (++) Configure the IWDG prescaler and counter reload value. This reload
value will be loaded in the IWDG counter each time the watchdog is value will be loaded in the IWDG counter each time the watchdog is
reloaded, then the IWDG will start counting down from this value. reloaded, then the IWDG will start counting down from this value.
(+) wait for status flags to be reset (++) Wait for status flags to be reset.
(+) Depending on window parameter: (++) Depending on window parameter:
(++) If Window Init parameter is same as Window register value, (+++) If Window Init parameter is same as Window register value,
nothing more is done but reload counter value in order to exit nothing more is done but reload counter value in order to exit
function withy exact time base. function with exact time base.
(++) Else modify Window register. This will automatically reload (+++) Else modify Window register. This will automatically reload
watchdog counter. watchdog counter.
(#) Then the application program must refresh the IWDG counter at regular (#) Then the application program must refresh the IWDG counter at regular
@ -167,7 +167,7 @@ HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload)); assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window)); assert_param(IS_IWDG_WINDOW(hiwdg->Init.Window));
/* Enable IWDG. LSI is turned on automaticaly */ /* Enable IWDG. LSI is turned on automatically */
__HAL_IWDG_START(hiwdg); __HAL_IWDG_START(hiwdg);
/* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing /* Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers by writing

3
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_iwdg.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_iwdg.h
View File

@ -119,7 +119,7 @@ typedef struct
/** /**
* @brief Reload IWDG counter with value defined in the reload register * @brief Reload IWDG counter with value defined in the reload register
* (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). * (write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers disabled).
* @param __HANDLE__ IWDG handle * @param __HANDLE__ IWDG handle
* @retval None * @retval None
*/ */
@ -219,6 +219,7 @@ HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
*/ */
#define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN) #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
/** /**
* @} * @}
*/ */

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_lcd.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_lcd.c
View File

@ -89,6 +89,8 @@
#ifdef HAL_LCD_MODULE_ENABLED #ifdef HAL_LCD_MODULE_ENABLED
#if defined (LCD)
/** @defgroup LCD LCD /** @defgroup LCD LCD
* @brief LCD HAL module driver * @brief LCD HAL module driver
* @{ * @{
@ -597,6 +599,8 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
* @} * @}
*/ */
#endif /* LCD */
#endif /* HAL_LCD_MODULE_ENABLED */ #endif /* HAL_LCD_MODULE_ENABLED */
/** /**

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_lcd.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_lcd.h
View File

@ -33,6 +33,8 @@ extern "C" {
* @{ * @{
*/ */
#if defined (LCD)
/** @addtogroup LCD /** @addtogroup LCD
* @{ * @{
*/ */
@ -755,6 +757,8 @@ HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
* @} * @}
*/ */
#endif /* LCD */
/** /**
* @} * @}
*/ */

489
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_lptim.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.c
View File

@ -92,19 +92,19 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1 The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback. Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
@ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle, @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function. the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the
default weak function. default weak function.
@ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle, @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
[..]
These functions allow to register/unregister following callbacks: These functions allow to register/unregister following callbacks:
(+) MspInitCallback : LPTIM Base Msp Init Callback. (+) MspInitCallback : LPTIM Base Msp Init Callback.
@ -117,15 +117,18 @@
(+) DirectionUpCallback : Up-counting direction change Callback. (+) DirectionUpCallback : Up-counting direction change Callback.
(+) DirectionDownCallback : Down-counting direction change Callback. (+) DirectionDownCallback : Down-counting direction change Callback.
[..]
By default, after the Init and when the state is HAL_LPTIM_STATE_RESET By default, after the Init and when the state is HAL_LPTIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions: all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback(). examples @ref HAL_LPTIM_TriggerCallback(), @ref HAL_LPTIM_CompareMatchCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init/DeInit only when these callbacks are null functionalities in the Init/DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only. Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state,
@ -133,13 +136,14 @@
In that case first register the MspInit/MspDeInit user callbacks In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function. using @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@endverbatim @endverbatim
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
@ -148,7 +152,8 @@
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* ****************************************************************************** *
******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
@ -170,12 +175,20 @@
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/ /* Private macro -------------------------------------------------------------*/
/** @addtogroup LPTIM_Private_Constants
* @{
*/
#define TIMEOUT 1000UL /* Timeout is 1s */ #define TIMEOUT 1000UL /* Timeout is 1s */
/**
* @}
*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim); static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag);
/* Exported functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/
@ -347,6 +360,11 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
/* Disable the LPTIM Peripheral Clock */ /* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
if (hlptim->MspDeInitCallback == NULL) if (hlptim->MspDeInitCallback == NULL)
{ {
@ -455,12 +473,30 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start(LPTIM_HandleTypeDef *hlptim, uint32_t Peri
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */ /* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */ /* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse); __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -487,6 +523,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/ /* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY; hlptim->State = HAL_LPTIM_STATE_READY;
@ -516,6 +557,41 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
/* Reset WAVE bit to set PWM mode */ /* Reset WAVE bit to set PWM mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */ /* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -538,12 +614,6 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t P
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -570,6 +640,11 @@ HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */ /* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -621,12 +696,30 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */ /* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */ /* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse); __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in single (one shot) mode */ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim); __HAL_LPTIM_START_SINGLE(hlptim);
@ -653,6 +746,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/ /* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY; hlptim->State = HAL_LPTIM_STATE_READY;
@ -682,6 +780,41 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
/* Reset WAVE bit to set one pulse mode */ /* Reset WAVE bit to set one pulse mode */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE; hlptim->Instance->CFGR &= ~LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */ /* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -704,12 +837,6 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Start_IT(LPTIM_HandleTypeDef *hlptim, uint3
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Start timer in single (one shot) mode */ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim); __HAL_LPTIM_START_SINGLE(hlptim);
@ -736,6 +863,11 @@ HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */ /* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -787,12 +919,30 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */ /* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */ /* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse); __HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in single (one shot) mode */ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim); __HAL_LPTIM_START_SINGLE(hlptim);
@ -819,6 +969,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/ /* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY; hlptim->State = HAL_LPTIM_STATE_READY;
@ -848,6 +1003,41 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set WAVE bit to enable the set once mode */ /* Set WAVE bit to enable the set once mode */
hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE; hlptim->Instance->CFGR |= LPTIM_CFGR_WAVE;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */ /* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -870,12 +1060,6 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the pulse value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Pulse);
/* Start timer in single (one shot) mode */ /* Start timer in single (one shot) mode */
__HAL_LPTIM_START_SINGLE(hlptim); __HAL_LPTIM_START_SINGLE(hlptim);
@ -902,6 +1086,11 @@ HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */ /* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -967,9 +1156,18 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */ /* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -996,6 +1194,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset ENC bit to disable the encoder interface */ /* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@ -1043,6 +1246,29 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set ENC bit to enable the encoder interface */ /* Set ENC bit to enable the encoder interface */
hlptim->Instance->CFGR |= LPTIM_CFGR_ENC; hlptim->Instance->CFGR |= LPTIM_CFGR_ENC;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable "switch to down direction" interrupt */ /* Enable "switch to down direction" interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN); __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_DOWN);
@ -1052,9 +1278,6 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1081,6 +1304,11 @@ HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset ENC bit to disable the encoder interface */ /* Reset ENC bit to disable the encoder interface */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC; hlptim->Instance->CFGR &= ~LPTIM_CFGR_ENC;
@ -1124,12 +1352,30 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */ /* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the Timeout value in the compare register */ /* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout); __HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1156,6 +1402,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset TIMOUT bit to enable the timeout function */ /* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@ -1190,18 +1441,47 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Set TIMOUT bit to enable the timeout function */ /* Set TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT; hlptim->Instance->CFGR |= LPTIM_CFGR_TIMOUT;
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
/* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Compare match interrupt */ /* Enable Compare match interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM); __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_CMPM);
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Load the Timeout value in the compare register */
__HAL_LPTIM_COMPARE_SET(hlptim, Timeout);
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1228,6 +1508,11 @@ HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Reset TIMOUT bit to enable the timeout function */ /* Reset TIMOUT bit to enable the timeout function */
hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT; hlptim->Instance->CFGR &= ~LPTIM_CFGR_TIMOUT;
@ -1269,9 +1554,18 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start(LPTIM_HandleTypeDef *hlptim, uint32_t
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */ /* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period); __HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1298,6 +1592,11 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Change the TIM state*/ /* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY; hlptim->State = HAL_LPTIM_STATE_READY;
@ -1330,6 +1629,29 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC; hlptim->Instance->CFGR &= ~LPTIM_CFGR_PRESC;
} }
/* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim);
/* Clear flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Enable Autoreload write complete interrupt */ /* Enable Autoreload write complete interrupt */
__HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_ENABLE_IT(hlptim, LPTIM_IT_ARROK);
@ -1339,9 +1661,6 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32
/* Enable the Peripheral */ /* Enable the Peripheral */
__HAL_LPTIM_ENABLE(hlptim); __HAL_LPTIM_ENABLE(hlptim);
/* Load the period value in the autoreload register */
__HAL_LPTIM_AUTORELOAD_SET(hlptim, Period);
/* Start timer in continuous mode */ /* Start timer in continuous mode */
__HAL_LPTIM_START_CONTINUOUS(hlptim); __HAL_LPTIM_START_CONTINUOUS(hlptim);
@ -1368,12 +1687,16 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
/* Disable the Peripheral */ /* Disable the Peripheral */
__HAL_LPTIM_DISABLE(hlptim); __HAL_LPTIM_DISABLE(hlptim);
if (HAL_LPTIM_GetState(hlptim) == HAL_LPTIM_STATE_TIMEOUT)
{
return HAL_TIMEOUT;
}
/* Disable Autoreload write complete interrupt */ /* Disable Autoreload write complete interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK); __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARROK);
/* Disable Autoreload match interrupt */ /* Disable Autoreload match interrupt */
__HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM); __HAL_LPTIM_DISABLE_IT(hlptim, LPTIM_IT_ARRM);
/* Change the TIM state*/ /* Change the TIM state*/
hlptim->State = HAL_LPTIM_STATE_READY; hlptim->State = HAL_LPTIM_STATE_READY;
@ -1970,16 +2293,40 @@ static void LPTIM_ResetCallback(LPTIM_HandleTypeDef *lptim)
} }
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @brief LPTimer Wait for flag set
* @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module.
* @param flag The lptim flag
* @retval HAL status
*/
static HAL_StatusTypeDef LPTIM_WaitForFlag(LPTIM_HandleTypeDef *hlptim, uint32_t flag)
{
HAL_StatusTypeDef result = HAL_OK;
uint32_t count = TIMEOUT * (SystemCoreClock / 20UL / 1000UL);
do
{
count--;
if (count == 0UL)
{
result = HAL_TIMEOUT;
}
}
while((!(__HAL_LPTIM_GET_FLAG((hlptim), (flag)))) && (count != 0UL));
return result;
}
/** /**
* @brief Disable LPTIM HW instance. * @brief Disable LPTIM HW instance.
* @param lptim pointer to a LPTIM_HandleTypeDef structure that contains * @param hlptim pointer to a LPTIM_HandleTypeDef structure that contains
* the configuration information for LPTIM module. * the configuration information for LPTIM module.
* @note The following sequence is required to solve LPTIM disable HW limitation. * @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain * Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section. * stuck in LPTIM interrupt when entering Stop mode" section.
* @retval None * @retval None
*/ */
void LPTIM_Disable(LPTIM_HandleTypeDef *lptim) void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim)
{ {
uint32_t tmpclksource = 0; uint32_t tmpclksource = 0;
uint32_t tmpIER; uint32_t tmpIER;
@ -1992,7 +2339,7 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
/*********** Save LPTIM Config ***********/ /*********** Save LPTIM Config ***********/
/* Save LPTIM source clock */ /* Save LPTIM source clock */
switch ((uint32_t)lptim->Instance) switch ((uint32_t)hlptim->Instance)
{ {
case LPTIM1_BASE: case LPTIM1_BASE:
tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE(); tmpclksource = __HAL_RCC_GET_LPTIM1_SOURCE();
@ -2007,14 +2354,14 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
} }
/* Save LPTIM configuration registers */ /* Save LPTIM configuration registers */
tmpIER = lptim->Instance->IER; tmpIER = hlptim->Instance->IER;
tmpCFGR = lptim->Instance->CFGR; tmpCFGR = hlptim->Instance->CFGR;
tmpCMP = lptim->Instance->CMP; tmpCMP = hlptim->Instance->CMP;
tmpARR = lptim->Instance->ARR; tmpARR = hlptim->Instance->ARR;
tmpOR = lptim->Instance->OR; tmpOR = hlptim->Instance->OR;
/*********** Reset LPTIM ***********/ /*********** Reset LPTIM ***********/
switch ((uint32_t)lptim->Instance) switch ((uint32_t)hlptim->Instance)
{ {
case LPTIM1_BASE: case LPTIM1_BASE:
__HAL_RCC_LPTIM1_FORCE_RESET(); __HAL_RCC_LPTIM1_FORCE_RESET();
@ -2031,13 +2378,10 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
} }
/*********** Restore LPTIM Config ***********/ /*********** Restore LPTIM Config ***********/
uint32_t Ref_Time;
uint32_t Time_Elapsed;
if ((tmpCMP != 0UL) || (tmpARR != 0UL)) if ((tmpCMP != 0UL) || (tmpARR != 0UL))
{ {
/* Force LPTIM source kernel clock from APB */ /* Force LPTIM source kernel clock from APB */
switch ((uint32_t)lptim->Instance) switch ((uint32_t)hlptim->Instance)
{ {
case LPTIM1_BASE: case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1); __HAL_RCC_LPTIM1_CONFIG(RCC_LPTIM1CLKSOURCE_PCLK1);
@ -2054,35 +2398,34 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
if (tmpCMP != 0UL) if (tmpCMP != 0UL)
{ {
/* Restore CMP register (LPTIM should be enabled first) */ /* Restore CMP register (LPTIM should be enabled first) */
lptim->Instance->CR |= LPTIM_CR_ENABLE; hlptim->Instance->CR |= LPTIM_CR_ENABLE;
lptim->Instance->CMP = tmpCMP; hlptim->Instance->CMP = tmpCMP;
/* Polling on CMP write ok status after above restore operation */
Ref_Time = HAL_GetTick();
do
{
Time_Elapsed = HAL_GetTick() - Ref_Time;
} while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_CMPOK))) && (Time_Elapsed <= TIMEOUT));
__HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_CMPOK); /* Wait for the completion of the write operation to the LPTIM_CMP register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_CMPOK) == HAL_TIMEOUT)
{
hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
}
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
} }
if (tmpARR != 0UL) if (tmpARR != 0UL)
{ {
/* Restore ARR register (LPTIM should be enabled first) */ /* Restore ARR register (LPTIM should be enabled first) */
lptim->Instance->CR |= LPTIM_CR_ENABLE; hlptim->Instance->CR |= LPTIM_CR_ENABLE;
lptim->Instance->ARR = tmpARR; hlptim->Instance->ARR = tmpARR;
/* Polling on ARR write ok status after above restore operation */
Ref_Time = HAL_GetTick();
do
{
Time_Elapsed = HAL_GetTick() - Ref_Time;
} while ((!(__HAL_LPTIM_GET_FLAG(lptim, LPTIM_FLAG_ARROK))) && (Time_Elapsed <= TIMEOUT));
__HAL_LPTIM_CLEAR_FLAG(lptim, LPTIM_FLAG_ARROK); /* Wait for the completion of the write operation to the LPTIM_ARR register */
if (LPTIM_WaitForFlag(hlptim, LPTIM_FLAG_ARROK) == HAL_TIMEOUT)
{
hlptim->State = HAL_LPTIM_STATE_TIMEOUT;
}
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
} }
/* Restore LPTIM source kernel clock */ /* Restore LPTIM source kernel clock */
switch ((uint32_t)lptim->Instance) switch ((uint32_t)hlptim->Instance)
{ {
case LPTIM1_BASE: case LPTIM1_BASE:
__HAL_RCC_LPTIM1_CONFIG(tmpclksource); __HAL_RCC_LPTIM1_CONFIG(tmpclksource);
@ -2098,10 +2441,10 @@ void LPTIM_Disable(LPTIM_HandleTypeDef *lptim)
} }
/* Restore configuration registers (LPTIM should be disabled first) */ /* Restore configuration registers (LPTIM should be disabled first) */
lptim->Instance->CR &= ~(LPTIM_CR_ENABLE); hlptim->Instance->CR &= ~(LPTIM_CR_ENABLE);
lptim->Instance->IER = tmpIER; hlptim->Instance->IER = tmpIER;
lptim->Instance->CFGR = tmpCFGR; hlptim->Instance->CFGR = tmpCFGR;
lptim->Instance->OR = tmpOR; hlptim->Instance->OR = tmpOR;
__enable_irq(); __enable_irq();
} }

95
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_lptim.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_lptim.h
View File

@ -42,6 +42,8 @@ extern "C" {
/** @defgroup LPTIM_Exported_Types LPTIM Exported Types /** @defgroup LPTIM_Exported_Types LPTIM Exported Types
* @{ * @{
*/ */
#define LPTIM_EXTI_LINE_LPTIM1 EXTI_IMR1_IM29 /*!< External interrupt line 29 Connected to the LPTIM1 EXTI Line */
#define LPTIM_EXTI_LINE_LPTIM2 EXTI_IMR1_IM30 /*!< External interrupt line 30 Connected to the LPTIM2 EXTI Line */
/** /**
* @brief LPTIM Clock configuration definition * @brief LPTIM Clock configuration definition
@ -397,6 +399,8 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @note The following sequence is required to solve LPTIM disable HW limitation. * @note The following sequence is required to solve LPTIM disable HW limitation.
* Please check Errata Sheet ES0335 for more details under "MCU may remain * Please check Errata Sheet ES0335 for more details under "MCU may remain
* stuck in LPTIM interrupt when entering Stop mode" section. * stuck in LPTIM interrupt when entering Stop mode" section.
* @note Please call @ref HAL_LPTIM_GetState() after a call to __HAL_LPTIM_DISABLE to
* check for TIMEOUT.
* @retval None * @retval None
*/ */
#define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__) #define __HAL_LPTIM_DISABLE(__HANDLE__) LPTIM_Disable(__HANDLE__)
@ -433,6 +437,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle * @param __HANDLE__ LPTIM handle
* @param __VALUE__ Autoreload value * @param __VALUE__ Autoreload value
* @retval None * @retval None
* @note The ARR register can only be modified when the LPTIM instance is enabled.
*/ */
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__)) #define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
@ -441,6 +446,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @param __HANDLE__ LPTIM handle * @param __HANDLE__ LPTIM handle
* @param __VALUE__ Compare value * @param __VALUE__ Compare value
* @retval None * @retval None
* @note The CMP register can only be modified when the LPTIM instance is enabled.
*/ */
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__)) #define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
@ -489,6 +495,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None. * @retval None.
* @note The LPTIM interrupts can only be enabled when the LPTIM instance is disabled.
*/ */
#define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__)) #define __HAL_LPTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
@ -505,6 +512,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @arg LPTIM_IT_ARRM : Autoreload match Interrupt. * @arg LPTIM_IT_ARRM : Autoreload match Interrupt.
* @arg LPTIM_IT_CMPM : Compare match Interrupt. * @arg LPTIM_IT_CMPM : Compare match Interrupt.
* @retval None. * @retval None.
* @note The LPTIM interrupts can only be disabled when the LPTIM instance is disabled.
*/ */
#define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__))) #define __HAL_LPTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
@ -525,6 +533,56 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/**
* @brief Enable the LPTIM1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM1)
/**
* @brief Disable the LPTIM1 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
/**
* @brief Enable the LPTIM1 EXTI line in event mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM1_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM1)
/**
* @brief Disable the LPTIM1 EXTI line in event mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM1_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM1))
/**
* @brief Enable the LPTIM2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_IT() (EXTI->IMR1 |= LPTIM_EXTI_LINE_LPTIM2)
/**
* @brief Disable the LPTIM2 EXTI line in interrupt mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
/**
* @brief Enable the LPTIM2 EXTI line in event mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM2_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= LPTIM_EXTI_LINE_LPTIM2)
/**
* @brief Disable the LPTIM2 EXTI line in event mode.
* @retval None
*/
#define __HAL_LPTIM_LPTIM2_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(LPTIM_EXTI_LINE_LPTIM2))
/** /**
* @} * @}
*/ */
@ -534,6 +592,10 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin
* @{ * @{
*/ */
/** @addtogroup LPTIM_Exported_Functions_Group1
* @brief Initialization and Configuration functions.
* @{
*/
/* Initialization/de-initialization functions ********************************/ /* Initialization/de-initialization functions ********************************/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
@ -541,7 +603,14 @@ HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim);
/* MSP functions *************************************************************/ /* MSP functions *************************************************************/
void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group2
* @brief Start-Stop operation functions.
* @{
*/
/* Start/Stop operation functions *********************************************/ /* Start/Stop operation functions *********************************************/
/* ################################# PWM Mode ################################*/ /* ################################# PWM Mode ################################*/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
@ -590,12 +659,26 @@ HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim);
/* Non-Blocking mode: Interrupt */ /* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period); HAL_StatusTypeDef HAL_LPTIM_Counter_Start_IT(LPTIM_HandleTypeDef *hlptim, uint32_t Period);
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim); HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group3
* @brief Read operation functions.
* @{
*/
/* Reading operation functions ************************************************/ /* Reading operation functions ************************************************/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim);
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim); uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** @addtogroup LPTIM_Exported_Functions_Group4
* @brief LPTIM IRQ handler and callback functions.
* @{
*/
/* LPTIM IRQ functions *******************************************************/ /* LPTIM IRQ functions *******************************************************/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim); void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim);
@ -613,9 +696,19 @@ void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
/**
* @}
*/
/** @addtogroup LPTIM_Group5
* @brief Peripheral State functions.
* @{
*/
/* Peripheral State functions ************************************************/ /* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/**
* @}
*/
/** /**
* @} * @}
@ -737,7 +830,7 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
/** @defgroup LPTIM_Private_Functions LPTIM Private Functions /** @defgroup LPTIM_Private_Functions LPTIM Private Functions
* @{ * @{
*/ */
void LPTIM_Disable(LPTIM_HandleTypeDef *lptim); void LPTIM_Disable(LPTIM_HandleTypeDef *hlptim);
/** /**
* @} * @}
*/ */

22
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pcd.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd.c
View File

@ -1714,7 +1714,10 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
{ {
/* Get SETUP Packet*/ /* Get SETUP Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count);
USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup,
ep->pmaadress, (uint16_t)ep->xfer_count);
/* SETUP bit kept frozen while CTR_RX = 1*/ /* SETUP bit kept frozen while CTR_RX = 1*/
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
@ -1729,21 +1732,24 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
else if ((wEPVal & USB_EP_CTR_RX) != 0U) else if ((wEPVal & USB_EP_CTR_RX) != 0U)
{ {
PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
/* Get Control Data OUT Packet*/ /* Get Control Data OUT Packet*/
ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
if (ep->xfer_count != 0U) if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U))
{ {
USB_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, (uint16_t)ep->xfer_count); USB_ReadPMA(hpcd->Instance, ep->xfer_buff,
ep->xfer_buff += ep->xfer_count; ep->pmaadress, (uint16_t)ep->xfer_count);
}
/* Process Control Data OUT Packet*/ ep->xfer_buff += ep->xfer_count;
/* Process Control Data OUT Packet*/
#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U)
hpcd->DataOutStageCallback(hpcd, 0U); hpcd->DataOutStageCallback(hpcd, 0U);
#else #else
HAL_PCD_DataOutStageCallback(hpcd, 0U); HAL_PCD_DataOutStageCallback(hpcd, 0U);
#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */
}
PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);

2
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pcd.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd.h
View File

@ -155,7 +155,7 @@ typedef struct
/** @defgroup PCD_Speed PCD Speed /** @defgroup PCD_Speed PCD Speed
* @{ * @{
*/ */
#define PCD_SPEED_FULL 2U #define PCD_SPEED_FULL USBD_FS_SPEED
/** /**
* @} * @}
*/ */

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pcd_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd_ex.c
View File

@ -125,6 +125,9 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
USB_TypeDef *USBx = hpcd->Instance; USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 1U; hpcd->battery_charging_active = 1U;
/* Enable BCD feature */
USBx->BCDR |= USB_BCDR_BCDEN;
/* Enable DCD : Data Contact Detect */ /* Enable DCD : Data Contact Detect */
USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_PDEN);
USBx->BCDR &= ~(USB_BCDR_SDEN); USBx->BCDR &= ~(USB_BCDR_SDEN);
@ -143,6 +146,7 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
USB_TypeDef *USBx = hpcd->Instance; USB_TypeDef *USBx = hpcd->Instance;
hpcd->battery_charging_active = 0U; hpcd->battery_charging_active = 0U;
/* Disable BCD feature */
USBx->BCDR &= ~(USB_BCDR_BCDEN); USBx->BCDR &= ~(USB_BCDR_BCDEN);
return HAL_OK; return HAL_OK;

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pcd_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pcd_ex.h
View File

185
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pka.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pka.c
View File

@ -80,6 +80,7 @@
(++) HAL_PKA_ECCMulFastMode_IT(). (++) HAL_PKA_ECCMulFastMode_IT().
(++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation. (++) HAL_PKA_ECCMul_GetResult() to retrieve the result of the operation.
*** Low level operation *** *** Low level operation ***
================================= =================================
[..] [..]
@ -142,8 +143,6 @@
(++) HAL_PKA_MontgomeryParam(). (++) HAL_PKA_MontgomeryParam().
(++) HAL_PKA_MontgomeryParam_IT(). (++) HAL_PKA_MontgomeryParam_IT().
(++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation. (++) HAL_PKA_MontgomeryParam_GetResult() to retrieve the result of the operation.
(+) You can save computation time by storing this parameter for a later usage.
Use it again with HAL_PKA_MontgomeryParam_Set();
*** Polling mode operation *** *** Polling mode operation ***
=================================== ===================================
@ -263,11 +262,15 @@
* @{ * @{
*/ */
#define PKA_RAM_SIZE 894U #define PKA_RAM_SIZE 894U
/* Private macro -------------------------------------------------------------*/
#define __PKA_RAM_PARAM_END(TAB,INDEX) do{ \
TAB[INDEX] = 0UL; \
} while(0)
/** /**
* @} * @}
*/ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/ /* Private function prototypes -----------------------------------------------*/
/** @defgroup PKA_Private_Functions PKA Private Functions /** @defgroup PKA_Private_Functions PKA Private Functions
@ -320,9 +323,7 @@ void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *p
(+) User must implement HAL_PKA_MspInit() function in which he configures (+) User must implement HAL_PKA_MspInit() function in which he configures
all related peripherals resources (CLOCK, IT and NVIC ). all related peripherals resources (CLOCK, IT and NVIC ).
(+) Call the function HAL_PKA_Init() to configure the selected device with (+) Call the function HAL_PKA_Init() to configure the device.
the selected configuration:
(++) Security level
(+) Call the function HAL_PKA_DeInit() to restore the default configuration (+) Call the function HAL_PKA_DeInit() to restore the default configuration
of the selected PKAx peripheral. of the selected PKAx peripheral.
@ -689,6 +690,7 @@ HAL_StatusTypeDef HAL_PKA_UnRegisterCallback(PKA_HandleTypeDef *hpka, HAL_PKA_Ca
(++) HAL_PKA_ECCMulFastMode() (++) HAL_PKA_ECCMulFastMode()
(++) HAL_PKA_ECCMul_GetResult(); (++) HAL_PKA_ECCMul_GetResult();
(++) HAL_PKA_Add() (++) HAL_PKA_Add()
(++) HAL_PKA_Sub() (++) HAL_PKA_Sub()
(++) HAL_PKA_Cmp() (++) HAL_PKA_Cmp()
@ -807,6 +809,7 @@ HAL_StatusTypeDef HAL_PKA_ModExpFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ModExpF
return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE); return PKA_Process_IT(hpka, PKA_MODE_MODULAR_EXP_FAST_MODE);
} }
/** /**
* @brief Retrieve operation result. * @brief Retrieve operation result.
* @param hpka PKA handle * @param hpka PKA handle
@ -859,7 +862,7 @@ HAL_StatusTypeDef HAL_PKA_ECDSASign_IT(PKA_HandleTypeDef *hpka, PKA_ECDSASignInT
* @brief Retrieve operation result. * @brief Retrieve operation result.
* @param hpka PKA handle * @param hpka PKA handle
* @param out Output information * @param out Output information
* @param outExt Additionnal Output information (facultative) * @param outExt Additional Output information (facultative)
*/ */
void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt) void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDef *out, PKA_ECDSASignOutExtParamTypeDef *outExt)
{ {
@ -873,7 +876,7 @@ void HAL_PKA_ECDSASign_GetResult(PKA_HandleTypeDef *hpka, PKA_ECDSASignOutTypeDe
PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size); PKA_Memcpy_u32_to_u8(out->SSign, &hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_SIGNATURE_S], size);
} }
/* If user requires the additionnal information */ /* If user requires the additional information */
if (outExt != NULL) if (outExt != NULL)
{ {
/* Move the result to appropriate location (indicated in outExt parameter) */ /* Move the result to appropriate location (indicated in outExt parameter) */
@ -1009,8 +1012,9 @@ HAL_StatusTypeDef HAL_PKA_PointCheck_IT(PKA_HandleTypeDef *hpka, PKA_PointCheckI
*/ */
uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka) uint32_t HAL_PKA_PointCheck_IsOnCurve(PKA_HandleTypeDef const *const hpka)
{ {
#define PKA_POINT_IS_ON_CURVE 0UL
/* Invert the value of the PKA RAM containig the result of the operation */ /* Invert the value of the PKA RAM containig the result of the operation */
return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == 0UL) ? 1UL : 0UL; return (hpka->Instance->RAM[PKA_POINT_CHECK_OUT_ERROR] == PKA_POINT_IS_ON_CURVE) ? 1UL : 0UL;
} }
/** /**
@ -1043,7 +1047,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMul_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef
/* Start the operation */ /* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL); return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL);
} }
/** /**
* @brief ECC scalar multiplication in blocking mode. * @brief ECC scalar multiplication in blocking mode.
* @param hpka PKA handle * @param hpka PKA handle
@ -1074,7 +1077,6 @@ HAL_StatusTypeDef HAL_PKA_ECCMulFastMode_IT(PKA_HandleTypeDef *hpka, PKA_ECCMulF
/* Start the operation */ /* Start the operation */
return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL_FAST_MODE); return PKA_Process_IT(hpka, PKA_MODE_ECC_MUL_FAST_MODE);
} }
/** /**
* @brief Retrieve operation result. * @brief Retrieve operation result.
* @param hpka PKA handle * @param hpka PKA handle
@ -1469,6 +1471,7 @@ HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_Montgo
return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM); return PKA_Process_IT(hpka, PKA_MODE_MONTGOMERY_PARAM);
} }
/** /**
* @brief Retrieve operation result. * @brief Retrieve operation result.
* @param hpka PKA handle * @param hpka PKA handle
@ -1568,7 +1571,6 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka)
hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION; hpka->ErrorCode |= HAL_PKA_ERROR_OPERATION;
} }
} }
/* Trigger the error callback if an error is present */ /* Trigger the error callback if an error is present */
if (hpka->ErrorCode != HAL_PKA_ERROR_NONE) if (hpka->ErrorCode != HAL_PKA_ERROR_NONE)
{ {
@ -1738,8 +1740,9 @@ uint32_t PKA_CheckError(PKA_HandleTypeDef *hpka, uint32_t mode)
/* Check the operation success in case of ECDSA signature */ /* Check the operation success in case of ECDSA signature */
if (mode == PKA_MODE_ECDSA_SIGNATURE) if (mode == PKA_MODE_ECDSA_SIGNATURE)
{ {
/* If error output result is different from 0, ecsa sign operation need to be repeated */ #define EDCSA_SIGN_NOERROR 0UL
if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != 0UL) /* If error output result is different from no error, ecsa sign operation need to be repeated */
if (hpka->Instance->RAM[PKA_ECDSA_SIGN_OUT_ERROR] != EDCSA_SIGN_NOERROR)
{ {
err |= HAL_PKA_ERROR_OPERATION; err |= HAL_PKA_ERROR_OPERATION;
} }
@ -1767,7 +1770,46 @@ uint32_t PKA_GetOptBitSize_u8(uint32_t byteNumber, uint8_t msb)
{ {
uint32_t position; uint32_t position;
#if defined(CORE_CM0PLUS)
if (msb > 0x7FU)
{
position = 8UL;
}
else if (msb > 0x3FU)
{
position = 7UL;
}
else if (msb > 0x1FU)
{
position = 6UL;
}
else if (msb > 0x0FU)
{
position = 5UL;
}
else if (msb > 0x07U)
{
position = 4UL;
}
else if (msb > 0x03U)
{
position = 3UL;
}
else if (msb > 0x01U)
{
position = 2UL;
}
else if (msb > 0x00U)
{
position = 1UL;
}
else
{
position = 0UL;
}
#else
position = 32UL - __CLZ(msb); position = 32UL - __CLZ(msb);
#endif
return (((byteNumber - 1UL) * 8UL) + position); return (((byteNumber - 1UL) * 8UL) + position);
} }
@ -2026,15 +2068,15 @@ void PKA_ModExp_Set(PKA_HandleTypeDef *hpka, PKA_ModExpInTypeDef *in)
/* Move the input parameters pOp1 to PKA RAM */ /* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
/* Move the exponent to PKA RAM */ /* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
/* Move the modulus to PKA RAM */ /* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
} }
/** /**
@ -2052,21 +2094,22 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef
/* Move the input parameters pOp1 to PKA RAM */ /* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL));
/* Move the exponent to PKA RAM */ /* Move the exponent to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL));
/* Move the modulus to PKA RAM */ /* Move the modulus to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL));
/* Move the Montgomery parameter to PKA RAM */ /* Move the Montgomery parameter to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->expSize / 4UL); PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->expSize / 4UL);
hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->expSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->expSize / 4UL));
} }
/** /**
* @brief Set input parameters. * @brief Set input parameters.
* @param hpka PKA handle * @param hpka PKA handle
@ -2085,35 +2128,35 @@ void PKA_ECDSASign_Set(PKA_HandleTypeDef *hpka, PKA_ECDSASignInTypeDef *in)
/* Move the input parameters coefficient |a| to PKA RAM */ /* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF], in->coef, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */ /* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF], in->modulus, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters integer k to PKA RAM */ /* Move the input parameters integer k to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K], in->integer, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_K + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate x to PKA RAM */ /* Move the input parameters base point G coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate y to PKA RAM */ /* Move the input parameters base point G coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters hash of message z to PKA RAM */ /* Move the input parameters hash of message z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E], in->hash, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters private key d to PKA RAM */ /* Move the input parameters private key d to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D], in->privateKey, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_PRIVATE_KEY_D + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters prime order n to PKA RAM */ /* Move the input parameters prime order n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_SIGN_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
} }
/** /**
@ -2134,43 +2177,43 @@ void PKA_ECDSAVerif_Set(PKA_HandleTypeDef *hpka, PKA_ECDSAVerifInTypeDef *in)
/* Move the input parameters coefficient |a| to PKA RAM */ /* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF], in->coef, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */ /* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF], in->modulus, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate x to PKA RAM */ /* Move the input parameters base point G coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X], in->basePointX, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters base point G coordinate y to PKA RAM */ /* Move the input parameters base point G coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y], in->basePointY, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X], in->pPubKeyCurvePtX, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */ /* Move the input parameters public-key curve point Q coordinate xQ to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y], in->pPubKeyCurvePtY, in->modulusSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_PUBLIC_KEY_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters signature part r to PKA RAM */ /* Move the input parameters signature part r to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R], in->RSign, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_R + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters signature part s to PKA RAM */ /* Move the input parameters signature part s to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S], in->SSign, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_SIGNATURE_S + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters hash of message z to PKA RAM */ /* Move the input parameters hash of message z to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E], in->hash, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_HASH_E + ((in->primeOrderSize + 3UL) / 4UL));
/* Move the input parameters curve prime order n to PKA RAM */ /* Move the input parameters curve prime order n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N], in->primeOrder, in->primeOrderSize);
hpka->Instance->RAM[PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECDSA_VERIF_IN_ORDER_N + ((in->primeOrderSize + 3UL) / 4UL));
} }
/** /**
@ -2185,27 +2228,27 @@ void PKA_RSACRTExp_Set(PKA_HandleTypeDef *hpka, PKA_RSACRTExpInTypeDef *in)
/* Move the input parameters operand dP to PKA RAM */ /* Move the input parameters operand dP to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT], in->pOpDp, in->size / 2UL);
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DP_CRT + (in->size / 8UL));
/* Move the input parameters operand dQ to PKA RAM */ /* Move the input parameters operand dQ to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT], in->pOpDq, in->size / 2UL);
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_DQ_CRT + (in->size / 8UL));
/* Move the input parameters operand qinv to PKA RAM */ /* Move the input parameters operand qinv to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT], in->pOpQinv, in->size / 2UL);
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_QINV_CRT + (in->size / 8UL));
/* Move the input parameters prime p to PKA RAM */ /* Move the input parameters prime p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P], in->pPrimeP, in->size / 2UL);
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_P + (in->size / 8UL));
/* Move the input parameters prime q to PKA RAM */ /* Move the input parameters prime q to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q], in->pPrimeQ, in->size / 2UL);
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_PRIME_Q + (in->size / 8UL));
/* Move the input parameters operand A to PKA RAM */ /* Move the input parameters operand A to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE], in->popA, in->size);
hpka->Instance->RAM[PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_RSA_CRT_EXP_IN_EXPONENT_BASE + (in->size / 4UL));
} }
/** /**
@ -2223,23 +2266,23 @@ void PKA_PointCheck_Set(PKA_HandleTypeDef *hpka, PKA_PointCheckInTypeDef *in)
/* Move the input parameters coefficient |a| to PKA RAM */ /* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF], in->coefA, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters coefficient b to PKA RAM */ /* Move the input parameters coefficient b to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF], in->coefB, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_B_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */ /* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF], in->modulus, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate x to PKA RAM */ /* Move the input parameters Point P coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate y to PKA RAM */ /* Move the input parameters Point P coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
} }
/** /**
@ -2260,25 +2303,28 @@ void PKA_ECCMul_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulInTypeDef *in)
/* Move the input parameters coefficient |a| to PKA RAM */ /* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */ /* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters scalar multiplier k to PKA RAM */ /* Move the input parameters scalar multiplier k to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate x to PKA RAM */ /* Move the input parameters Point P coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate y to PKA RAM */ /* Move the input parameters Point P coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
} }
/** /**
* @brief Set input parameters. * @brief Set input parameters.
* @param hpka PKA handle * @param hpka PKA handle
@ -2297,29 +2343,28 @@ void PKA_ECCMulFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ECCMulFastModeInTypeDef
/* Move the input parameters coefficient |a| to PKA RAM */ /* Move the input parameters coefficient |a| to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF], in->coefA, in->modulusSize);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_A_COEFF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters modulus value p to PKA RAM */ /* Move the input parameters modulus value p to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF], in->modulus, in->modulusSize);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MOD_GF + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters scalar multiplier k to PKA RAM */ /* Move the input parameters scalar multiplier k to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K], in->scalarMul, in->scalarMulSize);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_K + ((in->scalarMulSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate x to PKA RAM */ /* Move the input parameters Point P coordinate x to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X], in->pointX, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_X + ((in->modulusSize + 3UL) / 4UL));
/* Move the input parameters Point P coordinate y to PKA RAM */ /* Move the input parameters Point P coordinate y to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y], in->pointY, in->modulusSize);
hpka->Instance->RAM[PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_POINT_CHECK_IN_INITIAL_POINT_Y + ((in->modulusSize + 3UL) / 4UL));
/* Move the Montgomery parameter to PKA RAM */ /* Move the Montgomery parameter to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, (in->modulusSize + 3UL) / 4UL); PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, (in->modulusSize + 3UL) / 4UL);
hpka->Instance->RAM[PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ECC_SCALAR_MUL_IN_MONTGOMERY_PARAM + ((in->modulusSize + 3UL) / 4UL));
} }
/** /**
* @brief Set input parameters. * @brief Set input parameters.
* @param hpka PKA handle * @param hpka PKA handle
@ -2332,11 +2377,11 @@ void PKA_ModInv_Set(PKA_HandleTypeDef *hpka, PKA_ModInvInTypeDef *in)
/* Move the input parameters operand A to PKA RAM */ /* Move the input parameters operand A to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size); PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1], in->pOp1, in->size);
hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP1 + in->size] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP1 + in->size);
/* Move the input parameters modulus value n to PKA RAM */ /* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD], in->pMod, in->size * 4UL);
hpka->Instance->RAM[PKA_MODULAR_INV_IN_OP2_MOD + in->size] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_INV_IN_OP2_MOD + in->size);
} }
/** /**
@ -2354,11 +2399,11 @@ void PKA_ModRed_Set(PKA_HandleTypeDef *hpka, PKA_ModRedInTypeDef *in)
/* Move the input parameters operand A to PKA RAM */ /* Move the input parameters operand A to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize); PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND], in->pOp1, in->OpSize);
hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_OPERAND + in->OpSize);
/* Move the input parameters modulus value n to PKA RAM */ /* Move the input parameters modulus value n to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS], in->pMod, in->modSize);
hpka->Instance->RAM[PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_REDUC_IN_MODULUS + (in->modSize / 4UL));
} }
/** /**
@ -2376,7 +2421,7 @@ void PKA_MontgomeryParam_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const
/* Move the input parameters pOp1 to PKA RAM */ /* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS], pOp1, size);
hpka->Instance->RAM[PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL)] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MONTGOMERY_PARAM_IN_MODULUS + ((size + 3UL) / 4UL));
} }
} }
@ -2397,21 +2442,21 @@ void PKA_ARI_Set(PKA_HandleTypeDef *hpka, const uint32_t size, const uint32_t *p
{ {
/* Move the input parameters pOp1 to PKA RAM */ /* Move the input parameters pOp1 to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size); PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1], pOp1, size);
hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP1 + size);
} }
if (pOp2 != NULL) if (pOp2 != NULL)
{ {
/* Move the input parameters pOp2 to PKA RAM */ /* Move the input parameters pOp2 to PKA RAM */
PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size); PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2], pOp2, size);
hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP2 + size);
} }
if (pOp3 != NULL) if (pOp3 != NULL)
{ {
/* Move the input parameters pOp3 to PKA RAM */ /* Move the input parameters pOp3 to PKA RAM */
PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL); PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3], pOp3, size * 4UL);
hpka->Instance->RAM[PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size] = 0UL; __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_ARITHMETIC_ALL_OPS_IN_OP3 + size);
} }
} }

9
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pka.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pka.h
View File

@ -99,7 +99,11 @@ typedef enum
* @brief PKA handle Structure definition * @brief PKA handle Structure definition
* @{ * @{
*/ */
#if (USE_HAL_PKA_REGISTER_CALLBACKS == 1)
typedef struct __PKA_HandleTypeDef typedef struct __PKA_HandleTypeDef
#else
typedef struct
#endif /* USE_HAL_PKA_REGISTER_CALLBACKS */
{ {
PKA_TypeDef *Instance; /*!< Register base address */ PKA_TypeDef *Instance; /*!< Register base address */
__IO HAL_PKA_StateTypeDef State; /*!< PKA state */ __IO HAL_PKA_StateTypeDef State; /*!< PKA state */
@ -220,6 +224,7 @@ typedef struct
uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */ uint8_t *ptY; /*!< Pointer to point P coordinate yP (Array of modulusSize elements) */
} PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef; } PKA_ECDSASignOutExtParamTypeDef, PKA_ECCMulOutTypeDef;
typedef struct typedef struct
{ {
uint32_t expSize; /*!< Number of element in pExp array */ uint32_t expSize; /*!< Number of element in pExp array */
@ -229,6 +234,7 @@ typedef struct
const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */ const uint8_t *pMod; /*!< Pointer to modulus (Array of OpSize elements) */
} PKA_ModExpInTypeDef; } PKA_ModExpInTypeDef;
typedef struct typedef struct
{ {
uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */ uint32_t expSize; /*!< Number of element in pExp and pMontgomeryParam arrays */
@ -320,6 +326,7 @@ typedef struct
#define PKA_IT_PROCEND PKA_CR_PROCENDIE #define PKA_IT_PROCEND PKA_CR_PROCENDIE
#define PKA_IT_ADDRERR PKA_CR_ADDRERRIE #define PKA_IT_ADDRERR PKA_CR_ADDRERRIE
#define PKA_IT_RAMERR PKA_CR_RAMERRIE #define PKA_IT_RAMERR PKA_CR_RAMERRIE
/** /**
* @} * @}
*/ */
@ -330,6 +337,7 @@ typedef struct
#define PKA_FLAG_PROCEND PKA_SR_PROCENDF #define PKA_FLAG_PROCEND PKA_SR_PROCENDF
#define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF #define PKA_FLAG_ADDRERR PKA_SR_ADDRERRF
#define PKA_FLAG_RAMERR PKA_SR_RAMERRF #define PKA_FLAG_RAMERR PKA_SR_RAMERRF
/** /**
* @} * @}
*/ */
@ -516,6 +524,7 @@ HAL_StatusTypeDef HAL_PKA_MontgomeryParam(PKA_HandleTypeDef *hpka, PKA_Montgomer
HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in); HAL_StatusTypeDef HAL_PKA_MontgomeryParam_IT(PKA_HandleTypeDef *hpka, PKA_MontgomeryParamInTypeDef *in);
void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes); void HAL_PKA_MontgomeryParam_GetResult(PKA_HandleTypeDef *hpka, uint32_t *pRes);
HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka); HAL_StatusTypeDef HAL_PKA_Abort(PKA_HandleTypeDef *hpka);
void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka); void HAL_PKA_RAMReset(PKA_HandleTypeDef *hpka);
void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka); void HAL_PKA_OperationCpltCallback(PKA_HandleTypeDef *hpka);

6
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pwr.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.c
View File

@ -114,8 +114,10 @@ void HAL_PWR_DeInit(void)
LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE); LL_PWR_WriteReg(PDCRB, PWR_PDCRB_RESET_VALUE);
LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE); LL_PWR_WriteReg(PUCRC, PWR_PUCRC_RESET_VALUE);
LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE); LL_PWR_WriteReg(PDCRC, PWR_PDCRC_RESET_VALUE);
#if defined(GPIOD)
LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE); LL_PWR_WriteReg(PUCRD, PWR_PUCRD_RESET_VALUE);
LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE); LL_PWR_WriteReg(PDCRD, PWR_PDCRD_RESET_VALUE);
#endif
LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE); LL_PWR_WriteReg(PUCRE, PWR_PUCRE_RESET_VALUE);
LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE); LL_PWR_WriteReg(PDCRE, PWR_PDCRE_RESET_VALUE);
LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE); LL_PWR_WriteReg(PUCRH, PWR_PUCRH_RESET_VALUE);
@ -131,8 +133,10 @@ void HAL_PWR_DeInit(void)
| LL_PWR_SCR_CCRPEF | LL_PWR_SCR_CCRPEF
| LL_PWR_SCR_C802WUF | LL_PWR_SCR_C802WUF
| LL_PWR_SCR_CBLEWUF | LL_PWR_SCR_CBLEWUF
#if defined(PWR_CR5_SMPSEN)
| LL_PWR_SCR_CBORHF | LL_PWR_SCR_CBORHF
| LL_PWR_SCR_CSMPSFBF | LL_PWR_SCR_CSMPSFBF
#endif
| LL_PWR_SCR_CWUF | LL_PWR_SCR_CWUF
); );
@ -556,6 +560,8 @@ void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
* startup delay is incurred when waking up. * startup delay is incurred when waking up.
* By keeping the internal regulator ON during Stop mode (Stop 0), the consumption * By keeping the internal regulator ON during Stop mode (Stop 0), the consumption
* is higher although the startup time is reduced. * is higher although the startup time is reduced.
* @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
* the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
* @note According to system power policy, system entering in Stop mode * @note According to system power policy, system entering in Stop mode
* is depending on other CPU power mode. * is depending on other CPU power mode.
* @param Regulator Specifies the regulator state in Stop mode. * @param Regulator Specifies the regulator state in Stop mode.

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pwr.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr.h
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63
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pwr_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.c
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@ -79,6 +79,7 @@
*/ */
#if defined(PWR_CR1_VOS)
/** /**
* @brief Return Voltage Scaling Range. * @brief Return Voltage Scaling Range.
* @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2) * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2)
@ -145,7 +146,8 @@ HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling)
} }
return HAL_OK; return HAL_OK;
} }
#endif
/****************************************************************************/ /****************************************************************************/
@ -179,7 +181,7 @@ void HAL_PWREx_DisableBatteryCharging(void)
} }
/****************************************************************************/ /****************************************************************************/
#if defined(PWR_CR2_PVME1)
/** /**
* @brief Enable VDDUSB supply. * @brief Enable VDDUSB supply.
* @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present.
@ -198,6 +200,7 @@ void HAL_PWREx_DisableVddUSB(void)
{ {
CLEAR_BIT(PWR->CR2, PWR_CR2_USV); CLEAR_BIT(PWR->CR2, PWR_CR2_USV);
} }
#endif
/****************************************************************************/ /****************************************************************************/
@ -219,7 +222,7 @@ void HAL_PWREx_DisableInternalWakeUpLine(void)
CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL); CLEAR_BIT(PWR->CR3, PWR_CR3_EIWUL);
} }
#if defined(PWR_CR5_SMPSEN)
/** /**
* @brief Enable BORH and SMPS step down converter forced in bypass mode * @brief Enable BORH and SMPS step down converter forced in bypass mode
* interrupt for CPU1 * interrupt for CPU1
@ -239,7 +242,7 @@ void HAL_PWREx_DisableBORH_SMPSBypassIT(void)
{ {
CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB); CLEAR_BIT(PWR->CR3, PWR_CR3_EBORHSMPSFB);
} }
#endif
/** /**
* @brief Enable RF Phase interrupt. * @brief Enable RF Phase interrupt.
@ -358,11 +361,13 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber)
case PWR_GPIO_C: case PWR_GPIO_C:
SET_BIT(PWR->PUCRC, GPIONumber); SET_BIT(PWR->PUCRC, GPIONumber);
CLEAR_BIT(PWR->PDCRC, GPIONumber); CLEAR_BIT(PWR->PDCRC, GPIONumber);
break; break;
#if defined(GPIOD)
case PWR_GPIO_D: case PWR_GPIO_D:
SET_BIT(PWR->PUCRD, GPIONumber); SET_BIT(PWR->PUCRD, GPIONumber);
CLEAR_BIT(PWR->PDCRD, GPIONumber); CLEAR_BIT(PWR->PDCRD, GPIONumber);
break; break;
#endif
case PWR_GPIO_E: case PWR_GPIO_E:
SET_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); SET_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
@ -411,10 +416,12 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber
break; break;
case PWR_GPIO_C: case PWR_GPIO_C:
CLEAR_BIT(PWR->PUCRC, GPIONumber); CLEAR_BIT(PWR->PUCRC, GPIONumber);
break; break;
#if defined(GPIOD)
case PWR_GPIO_D: case PWR_GPIO_D:
CLEAR_BIT(PWR->PUCRD, GPIONumber); CLEAR_BIT(PWR->PUCRD, GPIONumber);
break; break;
#endif
case PWR_GPIO_E: case PWR_GPIO_E:
CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
break; break;
@ -472,11 +479,13 @@ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumbe
case PWR_GPIO_C: case PWR_GPIO_C:
SET_BIT(PWR->PDCRC, GPIONumber); SET_BIT(PWR->PDCRC, GPIONumber);
CLEAR_BIT(PWR->PUCRC, GPIONumber); CLEAR_BIT(PWR->PUCRC, GPIONumber);
break; break;
#if defined(GPIOD)
case PWR_GPIO_D: case PWR_GPIO_D:
SET_BIT(PWR->PDCRD, GPIONumber); SET_BIT(PWR->PDCRD, GPIONumber);
CLEAR_BIT(PWR->PUCRD, GPIONumber); CLEAR_BIT(PWR->PUCRD, GPIONumber);
break; break;
#endif
case PWR_GPIO_E: case PWR_GPIO_E:
SET_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); SET_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); CLEAR_BIT(PWR->PUCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
@ -526,9 +535,11 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb
case PWR_GPIO_C: case PWR_GPIO_C:
CLEAR_BIT(PWR->PDCRC, GPIONumber); CLEAR_BIT(PWR->PDCRC, GPIONumber);
break; break;
#if defined(GPIOD)
case PWR_GPIO_D: case PWR_GPIO_D:
CLEAR_BIT(PWR->PDCRD, GPIONumber); CLEAR_BIT(PWR->PDCRD, GPIONumber);
break; break;
#endif
case PWR_GPIO_E: case PWR_GPIO_E:
CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS)); CLEAR_BIT(PWR->PDCRE, (GPIONumber & PWR_PORTE_AVAILABLE_PINS));
break; break;
@ -571,6 +582,7 @@ void HAL_PWREx_DisablePullUpPullDownConfig(void)
/****************************************************************************/ /****************************************************************************/
#if defined(PWR_CR5_SMPSEN)
/** /**
* @brief Set BOR configuration * @brief Set BOR configuration
* @param BORConfiguration This parameter can be one of the following values: * @param BORConfiguration This parameter can be one of the following values:
@ -592,6 +604,7 @@ uint32_t HAL_PWREx_GetBORConfig(void)
{ {
return LL_PWR_GetBORConfig(); return LL_PWR_GetBORConfig();
} }
#endif
/****************************************************************************/ /****************************************************************************/
/** /**
@ -690,6 +703,7 @@ void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode)
} }
/****************************************************************************/ /****************************************************************************/
#if defined(PWR_CR2_PVME1)
/** /**
* @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V.
* @retval None * @retval None
@ -707,6 +721,8 @@ void HAL_PWREx_DisablePVM1(void)
{ {
CLEAR_BIT(PWR->CR2, PWR_PVM_1); CLEAR_BIT(PWR->CR2, PWR_PVM_1);
} }
#endif
/** /**
* @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V.
* @retval None * @retval None
@ -753,6 +769,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
configure the corresponding EXTI line accordingly. */ configure the corresponding EXTI line accordingly. */
switch (sConfigPVM->PVMType) switch (sConfigPVM->PVMType)
{ {
#if defined(PWR_CR2_PVME1)
case PWR_PVM_1: case PWR_PVM_1:
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
__HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); __HAL_PWR_PVM1_EXTI_DISABLE_EVENT();
@ -782,7 +799,8 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
{ {
__HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE();
} }
break; break;
#endif
case PWR_PVM_3: case PWR_PVM_3:
/* Clear any previous config. Keep it clear if no event or IT mode is selected */ /* Clear any previous config. Keep it clear if no event or IT mode is selected */
@ -824,6 +842,7 @@ HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM)
return status; return status;
} }
#if defined(PWR_CR5_SMPSEN)
/** /**
* @brief Configure the SMPS step down converter. * @brief Configure the SMPS step down converter.
* @note SMPS output voltage is calibrated in production, * @note SMPS output voltage is calibrated in production,
@ -867,13 +886,13 @@ HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS)
OutputVoltageLevelTrimmed = 0; OutputVoltageLevelTrimmed = 0;
status = HAL_ERROR; status = HAL_ERROR;
} }
else if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
{
OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS;
status = HAL_ERROR;
}
else else
{ {
if(OutputVoltageLevelTrimmed > (int32_t)PWR_CR5_SMPSVOS)
{
OutputVoltageLevelTrimmed = (int32_t)PWR_CR5_SMPSVOS;
status = HAL_ERROR;
}
} }
/* Update register */ /* Update register */
@ -923,6 +942,7 @@ uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void)
{ {
return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF))); return (uint32_t)(READ_BIT(PWR->SR2, (PWR_SR2_SMPSF | PWR_SR2_SMPSBF)));
} }
#endif
/****************************************************************************/ /****************************************************************************/
@ -1069,6 +1089,8 @@ HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void)
* is set; the MSI oscillator is selected if STOPWUCK is cleared. * is set; the MSI oscillator is selected if STOPWUCK is cleared.
* @note By keeping the internal regulator ON during Stop 0 mode, the consumption * @note By keeping the internal regulator ON during Stop 0 mode, the consumption
* is higher although the startup time is reduced. * is higher although the startup time is reduced.
* @note Case of Stop0 mode with SMPS: Before entering Stop 0 mode with SMPS Step Down converter enabled,
* the HSI16 must be kept on by enabling HSI kernel clock (set HSIKERON register bit).
* @note According to system power policy, system entering in Stop mode * @note According to system power policy, system entering in Stop mode
* is depending on other CPU power mode. * is depending on other CPU power mode.
* @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
@ -1177,6 +1199,15 @@ void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry)
* @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event,
* the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register
* is set; the MSI oscillator is selected if STOPWUCK is cleared. * is set; the MSI oscillator is selected if STOPWUCK is cleared.
* @note Case of Stop2 mode and debugger probe attached: a workaround should be applied.
* Issue specified in "ES0394 - STM32WB55Cx/Rx/Vx device errata":
* 2.2.9 Incomplete Stop 2 mode entry after a wakeup from debug upon EXTI line 48 event
* "With the JTAG debugger enabled on GPIO pins and after a wakeup from debug triggered by an event on EXTI
* line 48 (CDBGPWRUPREQ), the device may enter in a state in which attempts to enter Stop 2 mode are not fully
* effective ..."
* Workaround implementation example using LL driver:
* LL_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
* LL_C2_EXTI_DisableIT_32_63(LL_EXTI_LINE_48);
* @note According to system power policy, system entering in Stop mode * @note According to system power policy, system entering in Stop mode
* is depending on other CPU power mode. * is depending on other CPU power mode.
* @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction.
@ -1270,7 +1301,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
__HAL_PWR_PVD_EXTI_CLEAR_FLAG(); __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
} }
#if defined(PWR_CR2_PVME1)
/* Next, successively check PVMx exti flags */ /* Next, successively check PVMx exti flags */
if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U) if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != 0U)
{ {
@ -1280,6 +1311,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
/* Clear PVM1 exti pending bit */ /* Clear PVM1 exti pending bit */
__HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); __HAL_PWR_PVM1_EXTI_CLEAR_FLAG();
} }
#endif
if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U) if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != 0U)
{ {
@ -1291,7 +1323,7 @@ void HAL_PWREx_PVD_PVM_IRQHandler(void)
} }
} }
#if defined(PWR_CR2_PVME1)
/** /**
* @brief PWR PVM1 interrupt callback * @brief PWR PVM1 interrupt callback
* @retval None * @retval None
@ -1302,6 +1334,7 @@ __weak void HAL_PWREx_PVM1Callback(void)
HAL_PWREx_PVM1Callback() API can be implemented in the user file HAL_PWREx_PVM1Callback() API can be implemented in the user file
*/ */
} }
#endif
/** /**
* @brief PWR PVM3 interrupt callback * @brief PWR PVM3 interrupt callback

121
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_pwr_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_pwr_ex.h
View File

@ -61,6 +61,7 @@ typedef struct
This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */ This parameter can be a value of @ref PWREx_WakeUpTarget_Definition */
}PWR_PVMTypeDef; }PWR_PVMTypeDef;
#if defined(PWR_CR5_SMPSEN)
/** /**
* @brief PWR SMPS step down configuration structure definition * @brief PWR SMPS step down configuration structure definition
*/ */
@ -72,6 +73,7 @@ typedef struct
uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level. uint32_t OutputVoltage; /*!< SMPS step down converter output voltage scaling voltage level.
This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */ This parameter can be a value of @ref PWREx_SMPS_OUTPUT_VOLTAGE_LEVEL */
}PWR_SMPSTypeDef; }PWR_SMPSTypeDef;
#endif
/** /**
* @} * @}
@ -96,26 +98,44 @@ typedef struct
* @{ * @{
*/ */
#define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN1_HIGH PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#if defined(PWR_CR3_EWUP2)
#define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN2_HIGH PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#endif
#if defined(PWR_CR3_EWUP3)
#define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ #define PWR_WAKEUP_PIN3_HIGH PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#endif
#define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #define PWR_WAKEUP_PIN4_HIGH PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#if defined(PWR_CR3_EWUP5)
#define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ #define PWR_WAKEUP_PIN5_HIGH PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#endif
#define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */ #define PWR_WAKEUP_PIN1_LOW ((PWR_CR4_WP1<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP1) /*!< Wakeup pin 1 (with low level polarity) */
#if defined(PWR_CR3_EWUP2)
#define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */ #define PWR_WAKEUP_PIN2_LOW ((PWR_CR4_WP2<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP2) /*!< Wakeup pin 2 (with low level polarity) */
#endif
#if defined(PWR_CR3_EWUP3)
#define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */ #define PWR_WAKEUP_PIN3_LOW ((PWR_CR4_WP3<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP3) /*!< Wakeup pin 3 (with low level polarity) */
#endif
#define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */ #define PWR_WAKEUP_PIN4_LOW ((PWR_CR4_WP4<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP4) /*!< Wakeup pin 4 (with low level polarity) */
#if defined(PWR_CR3_EWUP5)
#define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */ #define PWR_WAKEUP_PIN5_LOW ((PWR_CR4_WP5<<PWR_WUP_POLARITY_SHIFT) | PWR_CR3_EWUP5) /*!< Wakeup pin 5 (with low level polarity) */
#endif
/** /**
* @} * @}
*/ */
/* Literals kept for legacy purpose */ /* Literals kept for legacy purpose */
#define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */ #define PWR_WAKEUP_PIN1 PWR_CR3_EWUP1 /*!< Wakeup pin 1 (with high level polarity) */
#if defined(PWR_CR3_EWUP2)
#define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */ #define PWR_WAKEUP_PIN2 PWR_CR3_EWUP2 /*!< Wakeup pin 2 (with high level polarity) */
#endif
#if defined(PWR_CR3_EWUP3)
#define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */ #define PWR_WAKEUP_PIN3 PWR_CR3_EWUP3 /*!< Wakeup pin 3 (with high level polarity) */
#endif
#define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */ #define PWR_WAKEUP_PIN4 PWR_CR3_EWUP4 /*!< Wakeup pin 4 (with high level polarity) */
#if defined(PWR_CR3_EWUP5)
#define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */ #define PWR_WAKEUP_PIN5 PWR_CR3_EWUP5 /*!< Wakeup pin 5 (with high level polarity) */
#endif
/** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration /** @defgroup PWREx_PIN_Polarity PWREx Pin Polarity configuration
* @{ * @{
@ -129,7 +149,9 @@ typedef struct
/** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type /** @defgroup PWREx_PVM_Type Peripheral Voltage Monitoring type
* @{ * @{
*/ */
#if defined(PWR_CR2_PVME1)
#define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */ #define PWR_PVM_1 PWR_CR2_PVME1 /*!< Peripheral Voltage Monitoring 1 enable: VDDUSB versus 1.2 V (applicable when USB feature is supported) */
#endif
#define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */ #define PWR_PVM_3 PWR_CR2_PVME3 /*!< Peripheral Voltage Monitoring 3 enable: VDDA versus 1.62 V */
/** /**
* @} * @}
@ -163,8 +185,12 @@ typedef struct
/** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale /** @defgroup PWREx_Regulator_Voltage_Scale PWR Regulator voltage scale
* @{ * @{
*/ */
#if defined(PWR_CR1_VOS)
#define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */ #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR1_VOS_0 /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
#define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */ #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR1_VOS_1 /*!< Regulator voltage output range 2 mode, typical output voltage at 1.0 V, system frequency up to 16 MHz */
#else
#define PWR_REGULATOR_VOLTAGE_SCALE1 (0x00000200UL) /*!< Regulator voltage output range 1 mode, typical output voltage at 1.2 V, system frequency up to 64 MHz */
#endif
/** /**
* @} * @}
*/ */
@ -191,20 +217,20 @@ typedef struct
/** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode /** @defgroup PWREx_GPIO_Bit_Number GPIO bit number for I/O setting in standby/shutdown mode
* @{ * @{
*/ */
#define PWR_GPIO_BIT_0 PWR_PUCRC_PC0 /*!< GPIO port I/O pin 0 */ #define PWR_GPIO_BIT_0 PWR_PUCRA_PA0 /*!< GPIO port I/O pin 0 */
#define PWR_GPIO_BIT_1 PWR_PUCRC_PC1 /*!< GPIO port I/O pin 1 */ #define PWR_GPIO_BIT_1 PWR_PUCRA_PA1 /*!< GPIO port I/O pin 1 */
#define PWR_GPIO_BIT_2 PWR_PUCRC_PC2 /*!< GPIO port I/O pin 2 */ #define PWR_GPIO_BIT_2 PWR_PUCRA_PA2 /*!< GPIO port I/O pin 2 */
#define PWR_GPIO_BIT_3 PWR_PUCRC_PC3 /*!< GPIO port I/O pin 3 */ #define PWR_GPIO_BIT_3 PWR_PUCRA_PA3 /*!< GPIO port I/O pin 3 */
#define PWR_GPIO_BIT_4 PWR_PUCRC_PC4 /*!< GPIO port I/O pin 4 */ #define PWR_GPIO_BIT_4 PWR_PUCRA_PA4 /*!< GPIO port I/O pin 4 */
#define PWR_GPIO_BIT_5 PWR_PUCRC_PC5 /*!< GPIO port I/O pin 5 */ #define PWR_GPIO_BIT_5 PWR_PUCRA_PA5 /*!< GPIO port I/O pin 5 */
#define PWR_GPIO_BIT_6 PWR_PUCRC_PC6 /*!< GPIO port I/O pin 6 */ #define PWR_GPIO_BIT_6 PWR_PUCRA_PA6 /*!< GPIO port I/O pin 6 */
#define PWR_GPIO_BIT_7 PWR_PUCRC_PC7 /*!< GPIO port I/O pin 7 */ #define PWR_GPIO_BIT_7 PWR_PUCRA_PA7 /*!< GPIO port I/O pin 7 */
#define PWR_GPIO_BIT_8 PWR_PUCRC_PC8 /*!< GPIO port I/O pin 8 */ #define PWR_GPIO_BIT_8 PWR_PUCRA_PA8 /*!< GPIO port I/O pin 8 */
#define PWR_GPIO_BIT_9 PWR_PUCRC_PC9 /*!< GPIO port I/O pin 9 */ #define PWR_GPIO_BIT_9 PWR_PUCRA_PA9 /*!< GPIO port I/O pin 9 */
#define PWR_GPIO_BIT_10 PWR_PUCRC_PC10 /*!< GPIO port I/O pin 10 */ #define PWR_GPIO_BIT_10 PWR_PUCRA_PA10 /*!< GPIO port I/O pin 10 */
#define PWR_GPIO_BIT_11 PWR_PUCRC_PC11 /*!< GPIO port I/O pin 11 */ #define PWR_GPIO_BIT_11 PWR_PUCRA_PA11 /*!< GPIO port I/O pin 11 */
#define PWR_GPIO_BIT_12 PWR_PUCRC_PC12 /*!< GPIO port I/O pin 12 */ #define PWR_GPIO_BIT_12 PWR_PUCRA_PA12 /*!< GPIO port I/O pin 12 */
#define PWR_GPIO_BIT_13 PWR_PUCRC_PC13 /*!< GPIO port I/O pin 14 */ #define PWR_GPIO_BIT_13 PWR_PUCRA_PA13 /*!< GPIO port I/O pin 14 */
#define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */ #define PWR_GPIO_BIT_14 PWR_PDCRC_PC14 /*!< GPIO port I/O pin 14 */
#define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */ #define PWR_GPIO_BIT_15 PWR_PUCRC_PC15 /*!< GPIO port I/O pin 15 */
/** /**
@ -217,13 +243,16 @@ typedef struct
#define PWR_GPIO_A 0x00000000U /*!< GPIO port A */ #define PWR_GPIO_A 0x00000000U /*!< GPIO port A */
#define PWR_GPIO_B 0x00000001U /*!< GPIO port B */ #define PWR_GPIO_B 0x00000001U /*!< GPIO port B */
#define PWR_GPIO_C 0x00000002U /*!< GPIO port C */ #define PWR_GPIO_C 0x00000002U /*!< GPIO port C */
#if defined(GPIOD)
#define PWR_GPIO_D 0x00000003U /*!< GPIO port D */ #define PWR_GPIO_D 0x00000003U /*!< GPIO port D */
#endif
#define PWR_GPIO_E 0x00000004U /*!< GPIO port E */ #define PWR_GPIO_E 0x00000004U /*!< GPIO port E */
#define PWR_GPIO_H 0x00000007U /*!< GPIO port H */ #define PWR_GPIO_H 0x00000007U /*!< GPIO port H */
/** /**
* @} * @}
*/ */
#if defined(PWR_CR5_SMPSEN)
/** @defgroup PWREx_BOR_CONFIGURATION BOR configuration /** @defgroup PWREx_BOR_CONFIGURATION BOR configuration
* @{ * @{
*/ */
@ -286,6 +315,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif
/** @defgroup PWREx_Flag PWR Status Flags /** @defgroup PWREx_Flag PWR Status Flags
* Elements values convention: 0000 0000 0XXY YYYYb * Elements values convention: 0000 0000 0XXY YYYYb
@ -300,15 +330,22 @@ typedef struct
*/ */
/*--------------------------------SR1-------------------------------*/ /*--------------------------------SR1-------------------------------*/
#define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */ #define PWR_FLAG_WUF1 (0x0020U) /*!< Wakeup event on wakeup pin 1 */
#if defined(PWR_CR3_EWUP2)
#define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */ #define PWR_FLAG_WUF2 (0x0021U) /*!< Wakeup event on wakeup pin 2 */
#endif
#if defined(PWR_CR3_EWUP3)
#define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */ #define PWR_FLAG_WUF3 (0x0022U) /*!< Wakeup event on wakeup pin 3 */
#endif
#define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */ #define PWR_FLAG_WUF4 (0x0023U) /*!< Wakeup event on wakeup pin 4 */
#if defined(PWR_CR3_EWUP5)
#define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */ #define PWR_FLAG_WUF5 (0x0024U) /*!< Wakeup event on wakeup pin 5 */
#endif
#define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */ #define PWR_FLAG_WU PWR_SR1_WUF /*!< Encompass wakeup event on all wakeup pins */
#define PWR_FLAG_BHWF (0x0028U) /*!< BLE_Host WakeUp Flag */ #if defined(PWR_CR5_SMPSEN)
#define PWR_FLAG_FRCBYPI (0x0029U) /*!< SMPS Forced in Bypass Interrupt Flag */ #define PWR_FLAG_FRCBYPI (0x0027U) /*!< SMPS Forced in Bypass Interrupt Flag */
#endif
#define PWR_FLAG_BHWF (0x0029U) /*!< BLE_Host WakeUp Flag */
#define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */ #define PWR_FLAG_RFPHASEI (0x002BU) /*!< Radio Phase Interrupt Flag */
#define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */ #define PWR_FLAG_BLEACTI (0x002CU) /*!< BLE Activity Interrupt Flag */
#define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */ #define PWR_FLAG_802ACTI (0x002DU) /*!< 802.15.4 Activity Interrupt Flag */
@ -316,13 +353,17 @@ typedef struct
#define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */ #define PWR_FLAG_WUFI (0x002FU) /*!< Wakeup on internal wakeup line */
/*--------------------------------SR2-------------------------------*/ /*--------------------------------SR2-------------------------------*/
#if defined(PWR_CR5_SMPSEN)
#define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */ #define PWR_FLAG_SMPSRDYF (0x0040U) /*!< SMPS Ready Flag */
#define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */ #define PWR_FLAG_SMPSBYPF (0x0041U) /*!< SMPS Bypass Flag */
#endif
#define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */ #define PWR_FLAG_REGLPS (0x0048U) /*!< Low-power regulator start flag */
#define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */ #define PWR_FLAG_REGLPF (0x0049U) /*!< Low-power regulator flag */
#if defined(PWR_CR1_VOS)
#define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */ #define PWR_FLAG_VOSF (0x004AU) /*!< Voltage scaling flag */
#endif
#define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */ #define PWR_FLAG_PVDO (0x004BU) /*!< Power Voltage Detector output flag */
#define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */ #define PWR_FLAG_PVMO1 (0x004CU) /*!< Power Voltage Monitoring 1 output flag */
@ -373,7 +414,9 @@ typedef struct
/** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines /** @defgroup PWREx_PVM_EXTI_LINE PWR PVM external interrupts lines
* @{ * @{
*/ */
#if defined(PWR_CR2_PVME1)
#define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */ #define PWR_EXTI_LINE_PVM1 (LL_EXTI_LINE_31) /*!< External interrupt line 31 Connected to PVM1 */
#endif
#define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */ #define PWR_EXTI_LINE_PVM3 (LL_EXTI_LINE_33) /*!< External interrupt line 33 Connected to PVM3 */
/** /**
* @} * @}
@ -402,6 +445,7 @@ typedef struct
* @{ * @{
*/ */
#if defined(PWR_CR2_PVME1)
/** /**
* @brief Enable the PVM1 Extended Interrupt C1 Line. * @brief Enable the PVM1 Extended Interrupt C1 Line.
* @retval None * @retval None
@ -521,6 +565,7 @@ typedef struct
*/ */
#define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1) #define __HAL_PWR_PVM1_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_0_31(PWR_EXTI_LINE_PVM1)
#endif
/** /**
* @brief Enable the PVM3 Extended Interrupt C1 Line. * @brief Enable the PVM3 Extended Interrupt C1 Line.
@ -641,7 +686,7 @@ typedef struct
*/ */
#define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3) #define __HAL_PWR_PVM3_EXTI_CLEAR_FLAG() LL_EXTI_ClearFlag_32_63(PWR_EXTI_LINE_PVM3)
#if defined(PWR_CR1_VOS)
/** /**
* @brief Configure the main internal regulator output voltage. * @brief Configure the main internal regulator output voltage.
* @param __REGULATOR__ specifies the regulator output voltage to achieve * @param __REGULATOR__ specifies the regulator output voltage to achieve
@ -665,6 +710,7 @@ typedef struct
tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \ tmpreg = READ_BIT(PWR->CR1, PWR_CR1_VOS); \
UNUSED(tmpreg); \ UNUSED(tmpreg); \
} while(0) } while(0)
#endif
/** /**
* @brief Wakeup BLE controller from its sleep mode * @brief Wakeup BLE controller from its sleep mode
@ -690,7 +736,7 @@ typedef struct
/** @addtogroup PWREx_Private_Macros PWR Extended Private Macros /** @addtogroup PWREx_Private_Macros PWR Extended Private Macros
* @{ * @{
*/ */
#if defined(PWR_CR3_EWUP2)
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \ #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN2_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN2_HIGH) || \
((PIN) == PWR_WAKEUP_PIN3_HIGH) || \ ((PIN) == PWR_WAKEUP_PIN3_HIGH) || \
@ -701,13 +747,22 @@ typedef struct
((PIN) == PWR_WAKEUP_PIN3_LOW) || \ ((PIN) == PWR_WAKEUP_PIN3_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW) || \ ((PIN) == PWR_WAKEUP_PIN4_LOW) || \
((PIN) == PWR_WAKEUP_PIN5_LOW)) ((PIN) == PWR_WAKEUP_PIN5_LOW))
#else
#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1_HIGH) || \
((PIN) == PWR_WAKEUP_PIN4_HIGH) || \
((PIN) == PWR_WAKEUP_PIN1_LOW) || \
((PIN) == PWR_WAKEUP_PIN4_LOW))
#endif
#define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \ #define IS_PWR_WAKEUP_PIN_POLARITY(POLARITY) (((POLARITY) == PWR_PIN_POLARITY_HIGH) || \
((POLARITY) == PWR_PIN_POLARITY_LOW)) ((POLARITY) == PWR_PIN_POLARITY_LOW))
#if defined(PWR_CR2_PVME1)
#define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\ #define IS_PWR_PVM_TYPE(TYPE) (((TYPE) == PWR_PVM_1) ||\
((TYPE) == PWR_PVM_3)) ((TYPE) == PWR_PVM_3))
#else
#define IS_PWR_PVM_TYPE(TYPE) ((TYPE) == PWR_PVM_3)
#endif
#define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\ #define IS_PWR_PVM_MODE(MODE) (((MODE) == PWR_PVM_MODE_NORMAL) ||\
((MODE) == PWR_PVM_MODE_IT_RISING) ||\ ((MODE) == PWR_PVM_MODE_IT_RISING) ||\
@ -720,9 +775,10 @@ typedef struct
#define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \ #define IS_PWR_FLASH_POWERDOWN(__MODE__) ((((__MODE__) & (PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) != 0x00u) && \
(((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u)) (((__MODE__) & ~(PWR_FLASHPD_LPRUN | PWR_FLASHPD_LPSLEEP)) == 0x00u))
#if defined(PWR_CR1_VOS)
#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2)) ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2))
#endif
#define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\ #define IS_PWR_BATTERY_RESISTOR_SELECT(RESISTOR) (((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_5) ||\
((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5)) ((RESISTOR) == PWR_BATTERY_CHARGING_RESISTOR_1_5))
@ -732,14 +788,23 @@ typedef struct
#define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00) #define IS_PWR_GPIO_BIT_NUMBER(BIT_NUMBER) (((BIT_NUMBER) & GPIO_PIN_MASK) != (uint32_t)0x00)
#if defined(GPIOD)
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\ #define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\ ((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\ ((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_D) ||\ ((GPIO) == PWR_GPIO_D) ||\
((GPIO) == PWR_GPIO_E) ||\ ((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_H)) ((GPIO) == PWR_GPIO_H))
#else
#define IS_PWR_GPIO(GPIO) (((GPIO) == PWR_GPIO_A) ||\
((GPIO) == PWR_GPIO_B) ||\
((GPIO) == PWR_GPIO_C) ||\
((GPIO) == PWR_GPIO_E) ||\
((GPIO) == PWR_GPIO_H))
#endif
#if defined(PWR_CR5_SMPSEN)
#define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\ #define IS_PWR_SMPS_MODE(SMPS_MODE) (((SMPS_MODE) == PWR_SMPS_BYPASS) ||\
((SMPS_MODE) == PWR_SMPS_STEP_DOWN)) ((SMPS_MODE) == PWR_SMPS_STEP_DOWN))
@ -767,6 +832,7 @@ typedef struct
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V80) ||\
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\ ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V85) ||\
((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90)) ((SMPS_OUTPUT_VOLTAGE) == PWR_SMPS_OUTPUT_VOLTAGE_1V90))
#endif
#define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2)) #define IS_PWR_CORE(CPU) (((CPU) == PWR_CORE_CPU1) || ((CPU) == PWR_CORE_CPU2))
@ -785,7 +851,6 @@ typedef struct
* @{ * @{
*/ */
/* Peripheral Control functions **********************************************/ /* Peripheral Control functions **********************************************/
uint32_t HAL_PWREx_GetVoltageRange(void); uint32_t HAL_PWREx_GetVoltageRange(void);
HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling); HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling);
@ -799,8 +864,10 @@ void HAL_PWREx_DisableVddUSB(void);
void HAL_PWREx_EnableInternalWakeUpLine(void); void HAL_PWREx_EnableInternalWakeUpLine(void);
void HAL_PWREx_DisableInternalWakeUpLine(void); void HAL_PWREx_DisableInternalWakeUpLine(void);
#if defined(PWR_CR5_SMPSEN)
void HAL_PWREx_EnableBORH_SMPSBypassIT(void); void HAL_PWREx_EnableBORH_SMPSBypassIT(void);
void HAL_PWREx_DisableBORH_SMPSBypassIT(void); void HAL_PWREx_DisableBORH_SMPSBypassIT(void);
#endif
void HAL_PWREx_EnableRFPhaseIT(void); void HAL_PWREx_EnableRFPhaseIT(void);
void HAL_PWREx_DisableRFPhaseIT(void); void HAL_PWREx_DisableRFPhaseIT(void);
void HAL_PWREx_EnableBLEActivityIT(void); void HAL_PWREx_EnableBLEActivityIT(void);
@ -820,8 +887,10 @@ HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumb
void HAL_PWREx_EnablePullUpPullDownConfig(void); void HAL_PWREx_EnablePullUpPullDownConfig(void);
void HAL_PWREx_DisablePullUpPullDownConfig(void); void HAL_PWREx_DisablePullUpPullDownConfig(void);
#if defined(PWR_CR5_SMPSEN)
void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration); void HAL_PWREx_SetBORConfig(uint32_t BORConfiguration);
uint32_t HAL_PWREx_GetBORConfig(void); uint32_t HAL_PWREx_GetBORConfig(void);
#endif
void HAL_PWREx_EnableSRAMRetention(void); void HAL_PWREx_EnableSRAMRetention(void);
void HAL_PWREx_DisableSRAMRetention(void); void HAL_PWREx_DisableSRAMRetention(void);
@ -829,17 +898,21 @@ void HAL_PWREx_DisableSRAMRetention(void);
void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode); void HAL_PWREx_EnableFlashPowerDown(uint32_t PowerMode);
void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode); void HAL_PWREx_DisableFlashPowerDown(uint32_t PowerMode);
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_EnablePVM1(void); void HAL_PWREx_EnablePVM1(void);
void HAL_PWREx_DisablePVM1(void); void HAL_PWREx_DisablePVM1(void);
#endif
void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_EnablePVM3(void);
void HAL_PWREx_DisablePVM3(void); void HAL_PWREx_DisablePVM3(void);
HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM);
#if defined(PWR_CR5_SMPSEN)
HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS); HAL_StatusTypeDef HAL_PWREx_ConfigSMPS(PWR_SMPSTypeDef *sConfigSMPS);
void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode);
uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void); uint32_t HAL_PWREx_SMPS_GetEffectiveMode(void);
#endif
/* WakeUp pins configuration functions ****************************************/ /* WakeUp pins configuration functions ****************************************/
void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget); void HAL_PWREx_EnableWakeUpPin(uint32_t WakeUpPinPolarity, uint32_t wakeupTarget);
@ -857,7 +930,9 @@ void HAL_PWREx_EnterSHUTDOWNMode(void);
void HAL_PWREx_PVD_PVM_IRQHandler(void); void HAL_PWREx_PVD_PVM_IRQHandler(void);
#if defined(PWR_CR2_PVME1)
void HAL_PWREx_PVM1Callback(void); void HAL_PWREx_PVM1Callback(void);
#endif
void HAL_PWREx_PVM3Callback(void); void HAL_PWREx_PVM3Callback(void);
/** /**

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_qspi.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_qspi.c
View File

@ -208,7 +208,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal.h" #include "stm32wbxx_hal.h"
#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) #if defined(QUADSPI)
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{
@ -340,7 +340,7 @@ HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
#endif #endif
/* Configure the default timeout for the QSPI memory access */ /* Configure the default timeout for the QSPI memory access */
HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE); HAL_QSPI_SetTimeout(hqspi, HAL_QSPI_TIMEOUT_DEFAULT_VALUE);
} }
/* Configure QSPI FIFO Threshold */ /* Configure QSPI FIFO Threshold */

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_qspi.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_qspi.h
View File

@ -27,7 +27,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal_def.h" #include "stm32wbxx_hal_def.h"
#if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) #if defined(QUADSPI)
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{
@ -408,7 +408,7 @@ typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi);
* @brief QSPI Timeout definition * @brief QSPI Timeout definition
* @{ * @{
*/ */
#define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ #define HAL_QSPI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */
/** /**
* @} * @}
*/ */

140
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rcc.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.c
View File

@ -10,6 +10,7 @@
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### RCC specific features ##### ##### RCC specific features #####
============================================================================== ==============================================================================
[..] [..]
@ -18,8 +19,8 @@
and I-Cache are disabled, and all peripherals are off except internal and I-Cache are disabled, and all peripherals are off except internal
SRAM, Flash and JTAG. SRAM, Flash and JTAG.
(+) There is no prescaler on High speed (AHBs) and Low speed (APBs) busses: (+) There is no prescaler on High speed (AHBs) and Low speed (APBs) buses:
all peripherals mapped on these busses are running at MSI speed. all peripherals mapped on these buses are running at MSI speed.
(+) The clock for all peripherals is switched off, except the SRAM and FLASH. (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in analog mode, except the JTAG pins which (+) All GPIOs are in analog mode, except the JTAG pins which
are assigned to be used for debug purpose. are assigned to be used for debug purpose.
@ -29,7 +30,7 @@
(+) Configure the clock source to be used to drive the System clock (+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance) (if the application needs higher frequency/performance)
(+) Configure the System clock frequency and Flash settings (+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers (+) Configure the AHB and APB buses prescalers
(+) Enable the clock for the peripheral(s) to be used (+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not (+) Configure the clock source(s) for peripherals which clocks are not
derived from the System clock (SAI1, RTC, ADC, USB/RNG, USART1, LPUART1, LPTIMx, I2Cx, SMPS) derived from the System clock (SAI1, RTC, ADC, USB/RNG, USART1, LPUART1, LPTIMx, I2Cx, SMPS)
@ -38,11 +39,11 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
@ -145,7 +146,7 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t
=============================================================================== ===============================================================================
[..] [..]
This section provides functions allowing to configure the internal and external oscillators This section provides functions allowing to configure the internal and external oscillators
(HSE, HSI, LSE, MSI, LSI1, LSI2, PLL, CSS and MCO) and the System busses clocks (SYSCLK, HCLK1, HCLK2, HCLK4, PCLK1 (HSE, HSI, LSE, MSI, LSI1, LSI2, PLL, CSS and MCO) and the System buses clocks (SYSCLK, HCLK1, HCLK2, HCLK4, PCLK1
and PCLK2). and PCLK2).
[..] Internal/external clock and PLL configuration [..] Internal/external clock and PLL configuration
@ -196,14 +197,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t
(+) MCO (microcontroller clock output): used to output MSI, LSI1, LSI2, HSI, LSE, HSE (before and (+) MCO (microcontroller clock output): used to output MSI, LSI1, LSI2, HSI, LSE, HSE (before and
after stabilization), SYSCLK, HSI48 or main PLL clock (through a configurable prescaler) on PA8, PB6 & PA15 pins. after stabilization), SYSCLK, HSI48 or main PLL clock (through a configurable prescaler) on PA8, PB6 & PA15 pins.
[..] System, AHB and APB busses clocks configuration [..] System, AHB and APB buses clocks configuration
(+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI, (+) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
HSE and main PLL. HSE and main PLL.
The AHB clock (HCLK1) is derived from System clock through configurable The AHB clock (HCLK1) is derived from System clock through configurable
prescaler and used to clock the CPU, memory and peripherals mapped prescaler and used to clock the CPU, memory and peripherals mapped
on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
from AHB clock through configurable prescalers and used to clock from AHB clock through configurable prescalers and used to clock
the peripherals mapped on these busses. You can use the peripherals mapped on these buses. You can use
"@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks. "@ref HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
The AHB4 clock (HCLK4) is derived from System clock through configurable The AHB4 clock (HCLK4) is derived from System clock through configurable
prescaler and used to clock the FLASH prescaler and used to clock the FLASH
@ -308,13 +309,17 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
} }
/* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, PLLSAI11ON, HSEPRE bits */ /* Reset HSION, HSIKERON, HSIASFS, HSEON, PLLON, PLLSAI11ON, HSEPRE bits */
#if defined(SAI1)
CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON | RCC_CR_PLLSAI1ON); CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON | RCC_CR_PLLSAI1ON);
#else
CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSIKERON | RCC_CR_HSIASFS | RCC_CR_HSEON | RCC_CR_HSEPRE | RCC_CR_PLLON);
#endif
/* Reset HSEBYP bit once HSE is OFF */ /* Reset HSEBYP bit once HSE is OFF */
LL_RCC_HSE_DisableBypass(); LL_RCC_HSE_DisableBypass();
/* Get Start Tick*/ /* Get Start Tick*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
/* Wait till PLL is ready */ /* Wait till PLL is ready */
while (LL_RCC_PLL_IsReady() != 0U) while (LL_RCC_PLL_IsReady() != 0U)
@ -328,7 +333,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
/* once PLL is OFF, reset PLLCFGR register to default value */ /* once PLL is OFF, reset PLLCFGR register to default value */
WRITE_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLN_0); WRITE_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLN_0);
#if defined(SAI1)
/* Get Start Tick*/ /* Get Start Tick*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
@ -342,6 +347,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
} }
/* once PLLSAI1 is OFF, reset PLLSAI1CFGR register to default value */ /* once PLLSAI1 is OFF, reset PLLSAI1CFGR register to default value */
WRITE_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR_0 | RCC_PLLSAI1CFGR_PLLQ_0 | RCC_PLLSAI1CFGR_PLLP_1 | RCC_PLLSAI1CFGR_PLLN_0); WRITE_REG(RCC->PLLSAI1CFGR, RCC_PLLSAI1CFGR_PLLR_0 | RCC_PLLSAI1CFGR_PLLQ_0 | RCC_PLLSAI1CFGR_PLLP_1 | RCC_PLLSAI1CFGR_PLLN_0);
#endif
/* Disable all interrupts */ /* Disable all interrupts */
CLEAR_REG(RCC->CIER); CLEAR_REG(RCC->CIER);
@ -356,7 +362,7 @@ HAL_StatusTypeDef HAL_RCC_DeInit(void)
SystemCoreClock = MSI_VALUE; SystemCoreClock = MSI_VALUE;
/* Adapt Systick interrupt period */ /* Adapt Systick interrupt period */
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) if (HAL_InitTick(uwTickPrio) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -379,7 +385,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
uint32_t tickstart; uint32_t tickstart;
/* Check Null pointer */ /* Check Null pointer */
if(RCC_OscInitStruct == NULL) if (RCC_OscInitStruct == NULL)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -440,8 +446,8 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
} }
/* Update the SystemCoreClock global variable */ /* Update the SystemCoreClock global variable */
SystemCoreClockUpdate(); SystemCoreClockUpdate();
if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) if (HAL_InitTick(uwTickPrio) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -480,7 +486,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Get timeout */ /* Get timeout */
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
/* Wait till MSI is ready */ /* Wait till MSI is disabled */
while (LL_RCC_MSI_IsReady() != 0U) while (LL_RCC_MSI_IsReady() != 0U)
{ {
if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE)
@ -630,16 +636,16 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* 1. Check LSI1 state and enable if required */ /* 1. Check LSI1 state and enable if required */
if (LL_RCC_LSI1_IsReady() == 0U) if (LL_RCC_LSI1_IsReady() == 0U)
{ {
/* This is required to enable LSI1 before enabling LSI2 */ /* This is required to enable LSI1 before enabling LSI2 */
__HAL_RCC_LSI1_ENABLE(); __HAL_RCC_LSI1_ENABLE();
/* Get Start Tick*/ /* Get Start Tick*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
/* Wait till LSI1 is ready */ /* Wait till LSI1 is ready */
while(LL_RCC_LSI1_IsReady() == 0U) while (LL_RCC_LSI1_IsReady() == 0U)
{ {
if((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE) if ((HAL_GetTick() - tickstart) > LSI1_TIMEOUT_VALUE)
{ {
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
@ -918,8 +924,11 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/* Disable all PLL outputs to save power */ /* Disable all PLL outputs to save power */
MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE); MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSOURCE_NONE);
#if defined(SAI1) && defined(USB)
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_USBCLK | RCC_PLL_SAI1CLK); __HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK | RCC_PLL_USBCLK | RCC_PLL_SAI1CLK);
#else
__HAL_RCC_PLLCLKOUT_DISABLE(RCC_PLL_SYSCLK);
#endif
/* Get Start Tick*/ /* Get Start Tick*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
@ -936,18 +945,26 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
} }
else else
{ {
/* Do not return HAL_ERROR if request repeats the current configuration */ /* Check if there is a request to disable the PLL used as System clock source */
uint32_t pllcfgr = RCC->PLLCFGR; if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF)
if((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
{ {
return HAL_ERROR; return HAL_ERROR;
} }
else
{
/* Do not return HAL_ERROR if request repeats the current configuration */
uint32_t pllcfgr = RCC->PLLCFGR;
if ((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) ||
((READ_BIT(pllcfgr, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos) != RCC_OscInitStruct->PLL.PLLN) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLP) != RCC_OscInitStruct->PLL.PLLP) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLQ) != RCC_OscInitStruct->PLL.PLLQ) ||
(READ_BIT(pllcfgr, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR))
{
return HAL_ERROR;
}
}
} }
} }
return HAL_OK; return HAL_OK;
@ -955,7 +972,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
/** /**
* @brief Initialize the CPU, AHB and APB busses clocks according to the specified * @brief Initialize the CPU, AHB and APB buses clocks according to the specified
* parameters in the RCC_ClkInitStruct. * parameters in the RCC_ClkInitStruct.
* @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that * @param RCC_ClkInitStruct pointer to a @ref RCC_ClkInitTypeDef structure that
* contains the configuration information for the RCC peripheral. * contains the configuration information for the RCC peripheral.
@ -995,7 +1012,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
uint32_t tickstart; uint32_t tickstart;
/* Check Null pointer */ /* Check Null pointer */
if(RCC_ClkInitStruct == NULL) if (RCC_ClkInitStruct == NULL)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -1196,7 +1213,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui
/* Update the SystemCoreClock global variable */ /* Update the SystemCoreClock global variable */
SystemCoreClockUpdate(); SystemCoreClockUpdate();
/* Configure the source of time base considering new system clocks settings*/ /* Configure the source of time base considering new system clocks settings*/
return HAL_InitTick (HAL_GetTickPrio()); return HAL_InitTick(HAL_GetTickPrio());
} }
/** /**
@ -1265,7 +1282,7 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
/* RCC_MCO1 */ /* RCC_MCO1 */
if(RCC_MCOx == RCC_MCO1) if (RCC_MCOx == RCC_MCO1)
{ {
/* MCO1 Clock Enable */ /* MCO1 Clock Enable */
__MCO1_CLK_ENABLE(); __MCO1_CLK_ENABLE();
@ -1295,8 +1312,8 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct); HAL_GPIO_Init(MCO3_GPIO_PORT, &GPIO_InitStruct);
} }
/* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */ /* Mask MCOSEL[] and MCOPRE[] bits then set MCO clock source and prescaler */
LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv); LL_RCC_ConfigMCO(RCC_MCOSource, RCC_MCODiv);
} }
/** /**
@ -1335,7 +1352,7 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
uint32_t pllsource; uint32_t pllsource;
uint32_t sysclockfreq, pllinputfreq; uint32_t sysclockfreq, pllinputfreq;
const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE(); const uint32_t temp_sysclksrc = __HAL_RCC_GET_SYSCLK_SOURCE();
if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI) if (temp_sysclksrc == RCC_SYSCLKSOURCE_STATUS_MSI)
{ {
/* Retrieve MSI frequency range in HZ*/ /* Retrieve MSI frequency range in HZ*/
@ -1351,13 +1368,13 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
{ {
/* HSE used as system clock source */ /* HSE used as system clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U) if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
{ {
sysclockfreq = HSE_VALUE / 2U; sysclockfreq = HSE_VALUE / 2U;
} }
else else
{ {
sysclockfreq = HSE_VALUE; sysclockfreq = HSE_VALUE;
} }
} }
else else
{ {
@ -1369,14 +1386,14 @@ uint32_t HAL_RCC_GetSysClockFreq(void)
pllinputfreq = HSI_VALUE; pllinputfreq = HSI_VALUE;
break; break;
case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U) if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
{ {
pllinputfreq = HSE_VALUE / 2U; pllinputfreq = HSE_VALUE / 2U;
} }
else else
{ {
pllinputfreq = HSE_VALUE; pllinputfreq = HSE_VALUE;
} }
break; break;
case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */
default: default:
@ -1662,9 +1679,9 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
/* Check the parameters */ /* Check the parameters */
assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range)); assert_param(IS_RCC_MSI_CLOCK_RANGE(MSI_Range));
/* MSI frequency range in Hz */ /* MSI frequency range in Hz */
if(MSI_Range > RCC_MSIRANGE_11) if (MSI_Range > RCC_MSIRANGE_11)
{ {
msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11); msifreq = __LL_RCC_CALC_MSI_FREQ(RCC_MSIRANGE_11);
} }
@ -1672,10 +1689,14 @@ static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range)
{ {
msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range); msifreq = __LL_RCC_CALC_MSI_FREQ(MSI_Range);
} }
flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler()); flash_clksrcfreq = __LL_RCC_CALC_HCLK4_FREQ(msifreq, LL_RCC_GetAHB4Prescaler());
#if defined(PWR_CR1_VOS)
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange());
#else
return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), PWR_REGULATOR_VOLTAGE_SCALE1);
#endif
} }
@ -1689,13 +1710,16 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t
{ {
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */ /* Flash Clock source (HCLK4) range in MHz with a VCORE is range1 */
const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL}; const uint32_t FLASH_CLK_SRC_RANGE_VOS1[] = {18UL, 36UL, 54UL, 64UL};
#if defined(PWR_CR1_VOS)
/* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */ /* Flash Clock source (HCLK4) range in MHz with a VCORE is range2 */
const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL}; const uint32_t FLASH_CLK_SRC_RANGE_VOS2[] = {6UL, 12UL, 16UL};
#endif
/* Flash Latency range */ /* Flash Latency range */
const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3}; const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2, FLASH_LATENCY_3};
uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */
uint32_t tickstart; uint32_t tickstart;
#if defined(PWR_CR1_VOS)
if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1)
{ {
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
@ -1718,6 +1742,16 @@ static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t
} }
} }
} }
#else
for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++)
{
if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index])
{
latency = FLASH_LATENCY_RANGE[index];
break;
}
}
#endif
__HAL_FLASH_SET_LATENCY(latency); __HAL_FLASH_SET_LATENCY(latency);

453
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rcc.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc.h
View File

File diff suppressed because it is too large Load Diff

355
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rcc_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.c
View File

@ -12,11 +12,11 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
@ -71,17 +71,20 @@
/** @defgroup RCCEx_Private_Functions RCCEx Private Functions /** @defgroup RCCEx_Private_Functions RCCEx Private Functions
* @{ * @{
*/ */
#if defined(SAI1)
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1); static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNP(RCC_PLLSAI1InitTypeDef *PLLSAI1);
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1); static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNQ(RCC_PLLSAI1InitTypeDef *PLLSAI1);
static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1); static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1);
#endif
static uint32_t RCC_PLL_GetFreqDomain_P(void); static uint32_t RCC_PLL_GetFreqDomain_P(void);
static uint32_t RCC_PLL_GetFreqDomain_Q(void); static uint32_t RCC_PLL_GetFreqDomain_Q(void);
#if defined(SAI1)
static uint32_t RCC_PLLSAI1_GetFreqDomain_R(void); static uint32_t RCC_PLLSAI1_GetFreqDomain_R(void);
static uint32_t RCC_PLLSAI1_GetFreqDomain_P(void); static uint32_t RCC_PLLSAI1_GetFreqDomain_P(void);
static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void); static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void);
#endif
/** /**
* @} * @}
@ -151,6 +154,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Check the parameters */ /* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
#if defined(SAI1)
/*-------------------------- SAI1 clock source configuration ---------------------*/ /*-------------------------- SAI1 clock source configuration ---------------------*/
if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1)) if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1))
{ {
@ -197,23 +201,24 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret; status = ret;
} }
} }
#endif
/*-------------------------- RTC clock source configuration ----------------------*/ /*-------------------------- RTC clock source configuration ----------------------*/
if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC)
{ {
uint32_t rtcclocksource = LL_RCC_GetRTCClockSource(); uint32_t rtcclocksource = LL_RCC_GetRTCClockSource();
/* Check for RTC Parameters used to output RTCCLK */ /* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
/* Configure the clock source only if a different source is expected */ /* Configure the clock source only if a different source is expected */
if(rtcclocksource != PeriphClkInit->RTCClockSelection) if (rtcclocksource != PeriphClkInit->RTCClockSelection)
{ {
/* Enable write access to Backup domain */ /* Enable write access to Backup domain */
HAL_PWR_EnableBkUpAccess(); HAL_PWR_EnableBkUpAccess();
/* If a clock source is not yet selected */ /* If a clock source is not yet selected */
if(rtcclocksource == RCC_RTCCLKSOURCE_NONE) if (rtcclocksource == RCC_RTCCLKSOURCE_NONE)
{ {
/* Directly set the configuration of the clock source selection */ /* Directly set the configuration of the clock source selection */
LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection); LL_RCC_SetRTCClockSource(PeriphClkInit->RTCClockSelection);
@ -222,23 +227,23 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
{ {
/* Store the content of BDCR register before the reset of Backup Domain */ /* Store the content of BDCR register before the reset of Backup Domain */
uint32_t bdcr = LL_RCC_ReadReg(BDCR); uint32_t bdcr = LL_RCC_ReadReg(BDCR);
/* RTC Clock selection can be changed only if the Backup Domain is reset */ /* RTC Clock selection can be changed only if the Backup Domain is reset */
LL_RCC_ForceBackupDomainReset(); LL_RCC_ForceBackupDomainReset();
LL_RCC_ReleaseBackupDomainReset(); LL_RCC_ReleaseBackupDomainReset();
/* Set the value of the clock source selection */ /* Set the value of the clock source selection */
MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection); MODIFY_REG(bdcr, RCC_BDCR_RTCSEL, PeriphClkInit->RTCClockSelection);
/* Restore the content of BDCR register */ /* Restore the content of BDCR register */
LL_RCC_WriteReg(BDCR, bdcr); LL_RCC_WriteReg(BDCR, bdcr);
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if (LL_RCC_LSE_IsEnabled() == 1U) if (LL_RCC_LSE_IsEnabled() == 1U)
{ {
/* Get Start Tick*/ /* Get Start Tick*/
tickstart = HAL_GetTick(); tickstart = HAL_GetTick();
/* Wait till LSE is ready */ /* Wait till LSE is ready */
while (LL_RCC_LSE_IsReady() != 1U) while (LL_RCC_LSE_IsReady() != 1U)
{ {
@ -272,7 +277,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection);
} }
#if defined(LPUART1)
/*-------------------------- LPUART1 clock source configuration ------------------*/ /*-------------------------- LPUART1 clock source configuration ------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1)
{ {
@ -282,6 +287,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the LPUAR1 clock source */ /* Configure the LPUAR1 clock source */
__HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection);
} }
#endif
/*-------------------------- LPTIM1 clock source configuration -------------------*/ /*-------------------------- LPTIM1 clock source configuration -------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1))
@ -307,6 +313,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
__HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection);
} }
#if defined(I2C3)
/*-------------------------- I2C3 clock source configuration ---------------------*/ /*-------------------------- I2C3 clock source configuration ---------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3)
{ {
@ -316,9 +323,9 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the I2C3 clock source */ /* Configure the I2C3 clock source */
__HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection);
} }
#endif
/*-------------------------- USB clock source configuration ----------------------*/ /*-------------------------- USB clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB)) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USB) == (RCC_PERIPHCLK_USB))
{ {
assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection)); assert_param(IS_RCC_USBCLKSOURCE(PeriphClkInit->UsbClockSelection));
@ -329,7 +336,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Enable PLLQ output */ /* Enable PLLQ output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK); __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_USBCLK);
} }
#if defined(SAI1)
if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1) if (PeriphClkInit->UsbClockSelection == RCC_USBCLKSOURCE_PLLSAI1)
{ {
/* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */ /* PLLSAI1 parameters N & Q configuration and clock output (PLLSAI1ClockOut) */
@ -341,14 +349,23 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret; status = ret;
} }
} }
#endif
} }
/*-------------------------- RNG clock source configuration ----------------------*/ /*-------------------------- RNG clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG))
{ {
/* Check the parameters */
assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection));
/* Configure the RNG clock source */
__HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection);
if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL)
{
/* Enable PLLQ output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK);
}
} }
/*-------------------------- ADC clock source configuration ----------------------*/ /*-------------------------- ADC clock source configuration ----------------------*/
@ -365,7 +382,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Enable RCC_PLL_RNGCLK output */ /* Enable RCC_PLL_RNGCLK output */
__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK);
} }
#if defined(SAI1)
if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1) if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLLSAI1)
{ {
/* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */ /* PLLSAI1 parameters N & R configuration and clock output (PLLSAI1ClockOut) */
@ -377,6 +395,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
status = ret; status = ret;
} }
} }
#endif
} }
/*-------------------------- RFWKP clock source configuration ----------------------*/ /*-------------------------- RFWKP clock source configuration ----------------------*/
@ -390,6 +409,7 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
} }
#if defined(RCC_SMPS_SUPPORT)
/*-------------------------- SMPS clock source configuration ----------------------*/ /*-------------------------- SMPS clock source configuration ----------------------*/
if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS) if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)
{ {
@ -402,8 +422,8 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
/* Configure the SMPS interface clock source */ /* Configure the SMPS interface clock source */
__HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection); __HAL_RCC_SMPS_CONFIG(PeriphClkInit->SmpsClockSelection);
} }
#endif
return status; return status;
} }
@ -420,28 +440,52 @@ HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClk
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{ {
/* Set all possible values for the extended clock type parameter------------*/ /* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C3 | \
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_USB | \
RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP | \
RCC_PERIPHCLK_SMPS;
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LPTIM2 | \
RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_ADC | \
RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_RFWAKEUP;
#if defined(LPUART1)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LPUART1;
#endif
#if defined(I2C3)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_I2C3;
#endif
#if defined(SAI1)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SAI1;
#endif
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_USB;
#if defined(RCC_SMPS_SUPPORT)
PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_SMPS;
#endif
#if defined(SAI1)
/* Get the PLLSAI1 Clock configuration -----------------------------------------------*/ /* Get the PLLSAI1 Clock configuration -----------------------------------------------*/
PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN(); PeriphClkInit->PLLSAI1.PLLN = LL_RCC_PLLSAI1_GetN();
PeriphClkInit->PLLSAI1.PLLP = LL_RCC_PLLSAI1_GetP(); PeriphClkInit->PLLSAI1.PLLP = LL_RCC_PLLSAI1_GetP();
PeriphClkInit->PLLSAI1.PLLR = LL_RCC_PLLSAI1_GetR(); PeriphClkInit->PLLSAI1.PLLR = LL_RCC_PLLSAI1_GetR();
PeriphClkInit->PLLSAI1.PLLQ = LL_RCC_PLLSAI1_GetQ(); PeriphClkInit->PLLSAI1.PLLQ = LL_RCC_PLLSAI1_GetQ();
#endif
/* Get the USART1 clock source ---------------------------------------------*/ /* Get the USART1 clock source ---------------------------------------------*/
PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE(); PeriphClkInit->Usart1ClockSelection = __HAL_RCC_GET_USART1_SOURCE();
#if defined(LPUART1)
/* Get the LPUART1 clock source --------------------------------------------*/ /* Get the LPUART1 clock source --------------------------------------------*/
PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE(); PeriphClkInit->Lpuart1ClockSelection = __HAL_RCC_GET_LPUART1_SOURCE();
#endif
/* Get the I2C1 clock source -----------------------------------------------*/ /* Get the I2C1 clock source -----------------------------------------------*/
PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE(); PeriphClkInit->I2c1ClockSelection = __HAL_RCC_GET_I2C1_SOURCE();
#if defined(I2C3)
/* Get the I2C3 clock source -----------------------------------------------*/ /* Get the I2C3 clock source -----------------------------------------------*/
PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE(); PeriphClkInit->I2c3ClockSelection = __HAL_RCC_GET_I2C3_SOURCE();
#endif
/* Get the LPTIM1 clock source ---------------------------------------------*/ /* Get the LPTIM1 clock source ---------------------------------------------*/
PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE(); PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
@ -449,8 +493,10 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Get the LPTIM2 clock source ---------------------------------------------*/ /* Get the LPTIM2 clock source ---------------------------------------------*/
PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE(); PeriphClkInit->Lptim2ClockSelection = __HAL_RCC_GET_LPTIM2_SOURCE();
#if defined(SAI1)
/* Get the SAI1 clock source -----------------------------------------------*/ /* Get the SAI1 clock source -----------------------------------------------*/
PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE(); PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
#endif
/* Get the RTC clock source ------------------------------------------------*/ /* Get the RTC clock source ------------------------------------------------*/
PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE(); PeriphClkInit->RTCClockSelection = __HAL_RCC_GET_RTC_SOURCE();
@ -459,7 +505,7 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE(); PeriphClkInit->UsbClockSelection = __HAL_RCC_GET_USB_SOURCE();
/* Get the RNG clock source ------------------------------------------------*/ /* Get the RNG clock source ------------------------------------------------*/
PeriphClkInit->RngClockSelection = __HAL_RCC_GET_RNG_SOURCE(); PeriphClkInit->RngClockSelection = HAL_RCCEx_GetRngCLKSource();
/* Get the ADC clock source ------------------------------------------------*/ /* Get the ADC clock source ------------------------------------------------*/
PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE(); PeriphClkInit->AdcClockSelection = __HAL_RCC_GET_ADC_SOURCE();
@ -467,11 +513,13 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
/* Get the RFWKP clock source ----------------------------------------------*/ /* Get the RFWKP clock source ----------------------------------------------*/
PeriphClkInit->RFWakeUpClockSelection = __HAL_RCC_GET_RFWAKEUP_SOURCE(); PeriphClkInit->RFWakeUpClockSelection = __HAL_RCC_GET_RFWAKEUP_SOURCE();
#if defined(RCC_SMPS_SUPPORT)
/* Get the SMPS clock division factor --------------------------------------*/ /* Get the SMPS clock division factor --------------------------------------*/
PeriphClkInit->SmpsDivSelection = __HAL_RCC_GET_SMPS_DIV(); PeriphClkInit->SmpsDivSelection = __HAL_RCC_GET_SMPS_DIV();
/* Get the SMPS clock source -----------------------------------------------*/ /* Get the SMPS clock source -----------------------------------------------*/
PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE(); PeriphClkInit->SmpsClockSelection = __HAL_RCC_GET_SMPS_SOURCE();
#endif
} }
/** /**
@ -498,16 +546,19 @@ void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk) uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
{ {
uint32_t frequency; uint32_t frequency;
#if defined(RCC_SMPS_SUPPORT)
uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos); uint32_t smps_prescaler_index = ((LL_RCC_GetSMPSPrescaler()) >> RCC_SMPSCR_SMPSDIV_Pos);
#endif
/* Check the parameters */ /* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClk)); assert_param(IS_RCC_PERIPHCLOCK(PeriphClk));
if(PeriphClk == RCC_PERIPHCLK_RTC) if (PeriphClk == RCC_PERIPHCLK_RTC)
{ {
uint32_t rtcClockSource = LL_RCC_GetRTCClockSource(); uint32_t rtcClockSource = LL_RCC_GetRTCClockSource();
if(rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */ if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSE) /* LSE clock used as RTC clock source */
{ {
if (LL_RCC_LSE_IsReady() == 1U) if (LL_RCC_LSE_IsReady() == 1U)
{ {
@ -518,7 +569,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else if(rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */ else if (rtcClockSource == LL_RCC_RTC_CLKSOURCE_LSI) /* LSI clock used as RTC clock source */
{ {
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
@ -540,6 +591,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0; frequency = 0;
} }
} }
#if defined(SAI1)
else if (PeriphClk == RCC_PERIPHCLK_SAI1) else if (PeriphClk == RCC_PERIPHCLK_SAI1)
{ {
switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)) switch (LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE))
@ -565,7 +617,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
break; break;
case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */ case LL_RCC_SAI1_CLKSOURCE_PLL: /* PLL clock used as SAI1 clock source */
if (LL_RCC_PLL_IsReady() == 1U) if (LL_RCC_PLL_IsReady() == 1U)
{ {
@ -582,11 +634,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break; break;
} }
} }
else if(PeriphClk == RCC_PERIPHCLK_RNG) #endif
else if (PeriphClk == RCC_PERIPHCLK_RNG)
{ {
uint32_t rngClockSource = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE); uint32_t rngClockSource = HAL_RCCEx_GetRngCLKSource();
if(rngClockSource == LL_RCC_RNG_CLKSOURCE_LSI) /* LSI clock used as RNG clock source */ if (rngClockSource == RCC_RNGCLKSOURCE_LSI) /* LSI clock used as RNG clock source */
{ {
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
@ -599,7 +652,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else if(rngClockSource == LL_RCC_RNG_CLKSOURCE_LSE) /* LSE clock used as RNG clock source */ else if (rngClockSource == RCC_RNGCLKSOURCE_LSE) /* LSE clock used as RNG clock source */
{ {
if (LL_RCC_LSE_IsReady() == 1U) if (LL_RCC_LSE_IsReady() == 1U)
{ {
@ -610,61 +663,45 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else /* CLK48 clock used as RNG clock source */ else if (rngClockSource == RCC_RNGCLKSOURCE_PLL) /* PLL clock divided by 3 used as RNG clock source */
{ {
switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)) if (LL_RCC_PLL_IsReady() == 1U)
{ {
case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ frequency = (RCC_PLL_GetFreqDomain_Q() / 3U);
if (LL_RCC_PLLSAI1_IsReady() == 1U) }
{ else
frequency = RCC_PLLSAI1_GetFreqDomain_Q(); {
} frequency = 0U;
else }
{ }
frequency = 0U; else if (rngClockSource == RCC_RNGCLKSOURCE_MSI) /* MSI clock divided by 3 used as RNG clock source */
} {
break; if (LL_RCC_MSI_IsReady() == 1U)
{
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ frequency = (__LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()) / 3U);
if (LL_RCC_PLL_IsReady() == 1U) }
{ else
frequency = RCC_PLL_GetFreqDomain_Q(); {
} frequency = 0U;
else }
{ }
frequency = 0U; else /* HSI48 clock divided by 3 used as RNG clock source */
} {
break; if (LL_RCC_HSI48_IsReady() == 1U)
{
case LL_RCC_USB_CLKSOURCE_MSI: /* MSI clock used as USB clock source */ frequency = HSI48_VALUE / 3U;
if (LL_RCC_MSI_IsReady() == 1U) }
{ else
frequency = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); {
} frequency = 0U;
else
{
frequency = 0U;
}
break;
default: /* HSI48 clock used as USB clock source */
if (LL_RCC_HSI48_IsReady() == 1U)
{
frequency = HSI48_VALUE;
}
else
{
frequency = 0U;
}
break;
} }
frequency = frequency / 3U;
} }
} }
else if (PeriphClk == RCC_PERIPHCLK_USB) else if (PeriphClk == RCC_PERIPHCLK_USB)
{ {
switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE)) switch (LL_RCC_GetUSBClockSource(LL_RCC_USB_CLKSOURCE))
{ {
#if defined(SAI1)
case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */ case LL_RCC_USB_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as USB clock source */
if (LL_RCC_PLLSAI1_IsReady() == 1U) if (LL_RCC_PLLSAI1_IsReady() == 1U)
{ {
@ -675,7 +712,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
break; break;
#endif
case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */ case LL_RCC_USB_CLKSOURCE_PLL: /* PLL clock used as USB clock source */
if (LL_RCC_PLL_IsReady() == 1U) if (LL_RCC_PLL_IsReady() == 1U)
{ {
@ -697,7 +734,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
break; break;
default: /* HSI48 clock used as USB clock source */ default: /* HSI48 clock used as USB clock source */
if (LL_RCC_HSI48_IsReady() == 1U) if (LL_RCC_HSI48_IsReady() == 1U)
{ {
@ -710,6 +747,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break; break;
} }
} }
else if (PeriphClk == RCC_PERIPHCLK_USART1) else if (PeriphClk == RCC_PERIPHCLK_USART1)
{ {
switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)) switch (LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE))
@ -746,6 +784,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break; break;
} }
} }
#if defined(LPUART1)
else if (PeriphClk == RCC_PERIPHCLK_LPUART1) else if (PeriphClk == RCC_PERIPHCLK_LPUART1)
{ {
switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)) switch (LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE))
@ -782,10 +821,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break; break;
} }
} }
#endif
else if (PeriphClk == RCC_PERIPHCLK_ADC) else if (PeriphClk == RCC_PERIPHCLK_ADC)
{ {
switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE)) switch (LL_RCC_GetADCClockSource(LL_RCC_ADC_CLKSOURCE))
{ {
#if defined(SAI1)
case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */ case LL_RCC_ADC_CLKSOURCE_PLLSAI1: /* PLLSAI1 clock used as ADC clock source */
if (LL_RCC_PLLSAI1_IsReady() == 1U) if (LL_RCC_PLLSAI1_IsReady() == 1U)
{ {
@ -796,7 +837,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
break; break;
#endif
case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */ case LL_RCC_ADC_CLKSOURCE_SYSCLK: /* SYSCLK clock used as ADC clock source */
frequency = HAL_RCC_GetSysClockFreq(); frequency = HAL_RCC_GetSysClockFreq();
break; break;
@ -811,7 +852,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
break; break;
default: /* No clock used as ADC clock source */ default: /* No clock used as ADC clock source */
frequency = 0; frequency = 0;
break; break;
@ -842,6 +883,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break; break;
} }
} }
#if defined(I2C3)
else if (PeriphClk == RCC_PERIPHCLK_I2C3) else if (PeriphClk == RCC_PERIPHCLK_I2C3)
{ {
switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)) switch (LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE))
@ -867,11 +909,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
break; break;
} }
} }
#endif
else if (PeriphClk == RCC_PERIPHCLK_LPTIM1) else if (PeriphClk == RCC_PERIPHCLK_LPTIM1)
{ {
uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE); uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM1_CLKSOURCE);
if(lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */ if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSI) /* LPTIM1 Clock is LSI Osc. */
{ {
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
@ -884,7 +927,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else if( lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */ else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_HSI) /* LPTIM1 Clock is HSI Osc. */
{ {
if (LL_RCC_HSI_IsReady() == 1U) if (LL_RCC_HSI_IsReady() == 1U)
{ {
@ -895,7 +938,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else if(lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */ else if (lptimClockSource == LL_RCC_LPTIM1_CLKSOURCE_LSE) /* LPTIM1 Clock is LSE Osc. */
{ {
if (LL_RCC_LSE_IsReady() == 1U) if (LL_RCC_LSE_IsReady() == 1U)
{ {
@ -914,8 +957,8 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
else if (PeriphClk == RCC_PERIPHCLK_LPTIM2) else if (PeriphClk == RCC_PERIPHCLK_LPTIM2)
{ {
uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE); uint32_t lptimClockSource = LL_RCC_GetLPTIMClockSource(LL_RCC_LPTIM2_CLKSOURCE);
if( lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */ if (lptimClockSource == LL_RCC_LPTIM2_CLKSOURCE_LSI) /* LPTIM2 Clock is LSI Osc. */
{ {
const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady(); const uint32_t temp_lsi1ready = LL_RCC_LSI1_IsReady();
const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady(); const uint32_t temp_lsi2ready = LL_RCC_LSI2_IsReady();
@ -958,7 +1001,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
else if (PeriphClk == RCC_PERIPHCLK_RFWAKEUP) else if (PeriphClk == RCC_PERIPHCLK_RFWAKEUP)
{ {
uint32_t rfwkpClockSource = LL_RCC_GetRFWKPClockSource(); uint32_t rfwkpClockSource = LL_RCC_GetRFWKPClockSource();
if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSE) /* LSE clock used as RF Wakeup clock source */ if (rfwkpClockSource == LL_RCC_RFWKP_CLKSOURCE_LSE) /* LSE clock used as RF Wakeup clock source */
{ {
if (LL_RCC_LSE_IsReady() == 1U) if (LL_RCC_LSE_IsReady() == 1U)
@ -992,11 +1035,12 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0; frequency = 0;
} }
} }
#if defined(RCC_SMPS_SUPPORT)
else if (PeriphClk == RCC_PERIPHCLK_SMPS) else if (PeriphClk == RCC_PERIPHCLK_SMPS)
{ {
uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource(); uint32_t smpsClockSource = LL_RCC_GetSMPSClockSource();
if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */ if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSI) /* SMPS Clock source is HSI Osc. */
{ {
if (LL_RCC_HSI_IsReady() == 1U) if (LL_RCC_HSI_IsReady() == 1U)
{ {
@ -1008,7 +1052,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */ else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_HSE) /* SMPS Clock source is HSE Osc. */
{ {
if (LL_RCC_HSE_IsReady() == 1U) if (LL_RCC_HSE_IsReady() == 1U)
{ {
@ -1020,7 +1064,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
else if(smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */ else if (smpsClockSource == LL_RCC_SMPS_CLKSOURCE_STATUS_MSI) /* SMPS Clock source is MSI Osc. */
{ {
switch (LL_RCC_MSI_GetRange()) switch (LL_RCC_MSI_GetRange())
{ {
@ -1047,6 +1091,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
frequency = 0U; frequency = 0U;
} }
} }
#endif
else else
{ {
frequency = 0U; frequency = 0U;
@ -1054,6 +1099,30 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
return (frequency); return (frequency);
} }
/**
* @brief Return the RNG clock source
* @retval The RNG clock source can be one of the following values:
* @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock
*/
uint32_t HAL_RCCEx_GetRngCLKSource(void)
{
uint32_t rng_clock_source = LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE);
uint32_t clk48_clock_source;
/* RNG clock source originates from 48 MHz RC oscillator */
if (rng_clock_source == RCC_RNGCLKSOURCE_CLK48)
{
clk48_clock_source = LL_RCC_GetCLK48ClockSource(LL_RCC_CLK48_CLKSOURCE);
rng_clock_source = (CLK48_MASK | clk48_clock_source);
}
return rng_clock_source;
}
/** /**
* @} * @}
*/ */
@ -1073,6 +1142,7 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk)
* @{ * @{
*/ */
#if defined(SAI1)
/** /**
* @brief Enable PLLSAI1. * @brief Enable PLLSAI1.
* @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that * @param PLLSAI1Init pointer to an RCC_PLLSAI1InitTypeDef structure that
@ -1161,10 +1231,11 @@ HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void)
} }
/* Disable the PLLSAI1 Clock outputs */ /* Disable the PLLSAI1 Clock outputs */
__HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK | RCC_PLLSAI1_RNGCLK | RCC_PLLSAI1_ADCCLK); __HAL_RCC_PLLSAI1CLKOUT_DISABLE(RCC_PLLSAI1_SAI1CLK | RCC_PLLSAI1_USBCLK | RCC_PLLSAI1_ADCCLK);
return status; return status;
} }
#endif
/***********************************************************************************************/ /***********************************************************************************************/
@ -1287,7 +1358,7 @@ void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource)
GPIO_InitStruct.Pull = GPIO_NOPULL; GPIO_InitStruct.Pull = GPIO_NOPULL;
/* RCC_LSCO1 */ /* RCC_LSCO1 */
if(RCC_LSCOx == RCC_LSCO1) if (RCC_LSCOx == RCC_LSCO1)
{ {
/* LSCO1 Clock Enable */ /* LSCO1 Clock Enable */
__LSCO1_CLK_ENABLE(); __LSCO1_CLK_ENABLE();
@ -1317,23 +1388,23 @@ void HAL_RCCEx_LSCOConfig(uint32_t RCC_LSCOx, uint32_t RCC_LSCOSource)
HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct); HAL_GPIO_Init(LSCO3_GPIO_PORT, &GPIO_InitStruct);
} }
/* Update LSCOSEL clock source in Backup Domain control register */ /* Update LSCOSEL clock source in Backup Domain control register */
if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP)) if (HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
{ {
HAL_PWR_EnableBkUpAccess(); HAL_PWR_EnableBkUpAccess();
backupchanged = SET; backupchanged = SET;
} }
else else
{ {
backupchanged = RESET; backupchanged = RESET;
} }
MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, RCC_LSCOSource | RCC_BDCR_LSCOEN); MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL | RCC_BDCR_LSCOEN, RCC_LSCOSource | RCC_BDCR_LSCOEN);
if (backupchanged == SET) if (backupchanged == SET)
{ {
HAL_PWR_DisableBkUpAccess(); HAL_PWR_DisableBkUpAccess();
} }
} }
@ -1448,12 +1519,12 @@ void HAL_RCCEx_DisableMSIPLLMode(void)
*/ */
HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType) HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType)
{ {
#define FTLSI2TRIM (0xFUL) #define FTLSI2TRIM (0xFUL)
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
assert_param(IS_RCC_TRIMOSC(OscillatorType)); assert_param(IS_RCC_TRIMOSC(OscillatorType));
if(OscillatorType == RCC_OSCILLATORTYPE_LSI2) if (OscillatorType == RCC_OSCILLATORTYPE_LSI2)
{ {
if (LL_RCC_LSI2_IsReady() == 1U) if (LL_RCC_LSI2_IsReady() == 1U)
{ {
@ -1478,7 +1549,7 @@ HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType)
* @} * @}
*/ */
#if defined(CRS)
/** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions /** @defgroup RCCEx_Exported_Functions_Group3 Extended Clock Recovery System Control functions
* @brief Extended Clock Recovery System Control functions * @brief Extended Clock Recovery System Control functions
* *
@ -1646,7 +1717,7 @@ uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout)
{ {
if (Timeout != HAL_MAX_DELAY) if (Timeout != HAL_MAX_DELAY)
{ {
if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
{ {
crsstatus = RCC_CRS_TIMEOUT; crsstatus = RCC_CRS_TIMEOUT;
} }
@ -1833,6 +1904,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
/** /**
* @} * @}
*/ */
#endif
/** /**
* @} * @}
@ -1842,6 +1914,7 @@ __weak void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error)
* @{ * @{
*/ */
#if defined(SAI1)
/** /**
* @brief Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s). * @brief Configure the parameters N & P of PLLSAI1 and enable PLLSAI1 output clock(s).
* @param PLLSAI1 pointer to an RCC_PLLSAI1InitTypeDef structure that * @param PLLSAI1 pointer to an RCC_PLLSAI1InitTypeDef structure that
@ -2046,6 +2119,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_ConfigNR(RCC_PLLSAI1InitTypeDef *PLLSAI1)
return status; return status;
} }
#endif
/** /**
* @brief Return PLL clock (PLLPCLK) frequency used for SAI domain * @brief Return PLL clock (PLLPCLK) frequency used for SAI domain
@ -2085,7 +2159,7 @@ static uint32_t RCC_PLL_GetFreqDomain_P(void)
pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange()); pllinputfreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_GetRange());
break; break;
} }
return __LL_RCC_CALC_PLLCLK_SAI_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), return __LL_RCC_CALC_PLLCLK_ADC_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP()); LL_RCC_PLL_GetN(), LL_RCC_PLL_GetP());
} }
@ -2114,14 +2188,14 @@ static uint32_t RCC_PLL_GetFreqDomain_Q(void)
break; break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U) if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
{ {
pllinputfreq = HSE_VALUE / 2U; pllinputfreq = HSE_VALUE / 2U;
} }
else else
{ {
pllinputfreq = HSE_VALUE; pllinputfreq = HSE_VALUE;
} }
break; break;
@ -2133,6 +2207,7 @@ static uint32_t RCC_PLL_GetFreqDomain_Q(void)
LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ()); LL_RCC_PLL_GetN(), LL_RCC_PLL_GetQ());
} }
#if defined(SAI1)
/** /**
* @brief Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain * @brief Return PLLSAI1 clock (PLLSAI1RCLK) frequency used for ADC domain
* @retval PLLSAI1RCLK clock frequency (in Hz) * @retval PLLSAI1RCLK clock frequency (in Hz)
@ -2197,14 +2272,14 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_P(void)
break; break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U) if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
{ {
pllinputfreq = HSE_VALUE / 2U; pllinputfreq = HSE_VALUE / 2U;
} }
else else
{ {
pllinputfreq = HSE_VALUE; pllinputfreq = HSE_VALUE;
} }
break; break;
default: default:
@ -2238,14 +2313,14 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void)
break; break;
case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */ case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLLSAI1 clock source */
if (LL_RCC_HSE_IsEnabledDiv2() == 1U) if (LL_RCC_HSE_IsEnabledDiv2() == 1U)
{ {
pllinputfreq = HSE_VALUE / 2U; pllinputfreq = HSE_VALUE / 2U;
} }
else else
{ {
pllinputfreq = HSE_VALUE; pllinputfreq = HSE_VALUE;
} }
break; break;
default: default:
@ -2255,7 +2330,7 @@ static uint32_t RCC_PLLSAI1_GetFreqDomain_Q(void)
return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), return __LL_RCC_CALC_PLLSAI1_48M_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(),
LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ()); LL_RCC_PLLSAI1_GetN(), LL_RCC_PLLSAI1_GetQ());
} }
#endif
/** /**
* @} * @}
*/ */

205
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rcc_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rcc_ex.h
View File

@ -6,11 +6,11 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
@ -48,6 +48,8 @@ extern "C" {
/* CRS Flag Error Mask */ /* CRS Flag Error Mask */
#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS)) #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
/* RNG closk selection CLK48 clock mask */
#define CLK48_MASK 0x10000000U
/** /**
* @} * @}
*/ */
@ -62,11 +64,11 @@ extern "C" {
#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \ #define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
((__SOURCE__) == RCC_LSCOSOURCE_LSE)) ((__SOURCE__) == RCC_LSCOSOURCE_LSE))
#if defined(LPUART1) && defined(I2C3) && defined(SAI1) && defined(USB) && defined(RCC_SMPS_SUPPORT)
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \ #define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \ ((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \ (((__SELECTION__) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \ (((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
@ -77,6 +79,17 @@ extern "C" {
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \ (((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \ (((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP)|| \
(((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS)) (((__SELECTION__) & RCC_PERIPHCLK_SMPS) == RCC_PERIPHCLK_SMPS))
#else
#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
((((__SELECTION__) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
(((__SELECTION__) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
(((__SELECTION__) & RCC_PERIPHCLK_LPTIM2) == RCC_PERIPHCLK_LPTIM2) || \
(((__SELECTION__) & RCC_PERIPHCLK_RNG) == RCC_PERIPHCLK_RNG) || \
(((__SELECTION__) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) || \
(((__SELECTION__) & RCC_PERIPHCLK_RFWAKEUP) == RCC_PERIPHCLK_RFWAKEUP))
#endif
#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \ #define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \ (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
@ -84,31 +97,33 @@ extern "C" {
((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_USART1CLKSOURCE_HSI)) ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
#if defined(LPUART1)
#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \ #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \ (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \ ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI)) ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
#endif
#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \ #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \ (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI)) ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
#if defined(I2C3)
#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \ #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \ (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \ ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI)) ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
#endif
#if defined(SAI1)
#define IS_RCC_SAI1CLK(__SOURCE__) \ #define IS_RCC_SAI1CLK(__SOURCE__) \
(((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \ (((__SOURCE__) == RCC_SAI1CLKSOURCE_PLLSAI1) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_PLL) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \ ((__SOURCE__) == RCC_SAI1CLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN)) ((__SOURCE__) == RCC_SAI1CLKSOURCE_PIN))
#endif
#define IS_RCC_LPTIM1CLK(__SOURCE__) \ #define IS_RCC_LPTIM1CLK(__SOURCE__) \
(((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \ (((__SOURCE__) == RCC_LPTIM1CLKSOURCE_PCLK1) || \
@ -123,22 +138,38 @@ extern "C" {
((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE)) ((__SOURCE__) == RCC_LPTIM2CLKSOURCE_LSE))
#define IS_RCC_RNGCLKSOURCE(__SOURCE__) \ #define IS_RCC_RNGCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \ (((__SOURCE__) == RCC_RNGCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RNGCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_MSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_CLK48) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RNGCLKSOURCE_LSE)) ((__SOURCE__) == RCC_RNGCLKSOURCE_LSE))
#if defined(SAI1)
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \ #define IS_RCC_USBCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \ (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLLSAI1) || \
((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_USBCLKSOURCE_MSI)) ((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
#else
#define IS_RCC_USBCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
((__SOURCE__) == RCC_USBCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_USBCLKSOURCE_MSI))
#endif
#if defined(SAI1)
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \ #define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \ (((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \ ((__SOURCE__) == RCC_ADCCLKSOURCE_PLLSAI1) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK)) ((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#else
#define IS_RCC_ADCCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_ADCCLKSOURCE_NONE) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_PLL) || \
((__SOURCE__) == RCC_ADCCLKSOURCE_SYSCLK))
#endif
#define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \ #define IS_RCC_RFWKPCLKSOURCE(__SOURCE__) \
(((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \ (((__SOURCE__) == RCC_RFWKPCLKSOURCE_NONE) || \
@ -146,6 +177,7 @@ extern "C" {
((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \ ((__SOURCE__) == RCC_RFWKPCLKSOURCE_LSI) || \
((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024)) ((__SOURCE__) == RCC_RFWKPCLKSOURCE_HSE_DIV1024))
#if defined(RCC_SMPS_SUPPORT)
#define IS_RCC_SMPSCLKDIV(__DIV__) \ #define IS_RCC_SMPSCLKDIV(__DIV__) \
(((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \ (((__DIV__) == RCC_SMPSCLKDIV_RANGE0) || \
((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \ ((__DIV__) == RCC_SMPSCLKDIV_RANGE1) || \
@ -156,17 +188,21 @@ extern "C" {
(((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI) || \ (((__SOURCE__) == RCC_SMPSCLKSOURCE_HSI) || \
((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI) || \ ((__SOURCE__) == RCC_SMPSCLKSOURCE_MSI) || \
((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE)) ((__SOURCE__) == RCC_SMPSCLKSOURCE_HSE))
#endif
#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((8U <= (__VALUE__)) && ((__VALUE__) <= 86U)) #if defined(SAI1)
#define IS_RCC_PLLSAI1N_VALUE(__VALUE__) ((6U <= (__VALUE__)) && ((__VALUE__) <= 127U))
#define IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32)) #define IS_RCC_PLLSAI1P_VALUE(__VALUE__) ((RCC_PLLP_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLP_DIV32))
#define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8)) #define IS_RCC_PLLSAI1Q_VALUE(__VALUE__) ((RCC_PLLQ_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLQ_DIV8))
#define IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8)) #define IS_RCC_PLLSAI1R_VALUE(__VALUE__) ((RCC_PLLR_DIV2 <= (__VALUE__)) && ((__VALUE__) <= RCC_PLLR_DIV8))
#endif
#define IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2) #define IS_RCC_TRIMOSC(__VALUE__) ((__VALUE__) == RCC_OSCILLATORTYPE_LSI2)
#if defined(CRS)
#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \ #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \ ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) || \
((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB)) ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
@ -187,7 +223,7 @@ extern "C" {
#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \ #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN)) ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
#endif
/** /**
* @} * @}
*/ */
@ -198,6 +234,7 @@ extern "C" {
* @{ * @{
*/ */
#if defined(SAI1)
/** /**
* @brief PLLSAI1 Clock structure definition * @brief PLLSAI1 Clock structure definition
*/ */
@ -205,7 +242,7 @@ typedef struct
{ {
uint32_t PLLN; /*!< PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock. uint32_t PLLN; /*!< PLLN: specifies the multiplication factor for PLLSAI1 VCO output clock.
This parameter must be a number between Min_Data=8 and Max_Data=86. */ This parameter must be a number between Min_Data=6 and Max_Data=127. */
uint32_t PLLP; /*!< PLLP: specifies the division factor for SAI clock. uint32_t PLLP; /*!< PLLP: specifies the division factor for SAI clock.
This parameter must be a value of @ref RCC_PLLP_Clock_Divider */ This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
@ -219,7 +256,7 @@ typedef struct
uint32_t PLLSAI1ClockOut; /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled. uint32_t PLLSAI1ClockOut; /*!< PLLSAI1ClockOut: specifies PLLSAI1 output clock to be enabled.
This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */ This parameter must be a value of @ref RCC_PLLSAI1_Clock_Output */
} RCC_PLLSAI1InitTypeDef; } RCC_PLLSAI1InitTypeDef;
#endif
/** /**
* @brief RCC extended clocks structure definition * @brief RCC extended clocks structure definition
@ -229,23 +266,27 @@ typedef struct
uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured. uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */ This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
#if defined(SAI1)
RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters. RCC_PLLSAI1InitTypeDef PLLSAI1; /*!< PLLSAI1 structure parameters.
This parameter will be used only when PLLSAI1 is selected as Clock This parameter will be used only when PLLSAI1 is selected as Clock
Source for SAI, USB/RNG or ADC */ Source for SAI, USB/RNG or ADC */
#endif
uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source. uint32_t Usart1ClockSelection; /*!< Specifies USART1 clock source.
This parameter can be a value of @ref RCCEx_USART1_Clock_Source */ This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
#if defined(LPUART1)
uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source. uint32_t Lpuart1ClockSelection; /*!< Specifies LPUART1 clock source.
This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */ This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
#endif
uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source. uint32_t I2c1ClockSelection; /*!< Specifies I2C1 clock source.
This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */ This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
#if defined(I2C3)
uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source. uint32_t I2c3ClockSelection; /*!< Specifies I2C3 clock source.
This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */ This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
#endif
uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source. uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source.
This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */ This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
@ -253,9 +294,10 @@ typedef struct
uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source. uint32_t Lptim2ClockSelection; /*!< Specifies LPTIM2 clock source.
This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */ This parameter can be a value of @ref RCCEx_LPTIM2_Clock_Source */
#if defined(SAI1)
uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source. uint32_t Sai1ClockSelection; /*!< Specifies SAI1 clock source.
This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */ This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
#endif
uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG). uint32_t UsbClockSelection; /*!< Specifies USB clock source (warning: same source for RNG).
This parameter can be a value of @ref RCCEx_USB_Clock_Source */ This parameter can be a value of @ref RCCEx_USB_Clock_Source */
@ -273,15 +315,17 @@ typedef struct
uint32_t RFWakeUpClockSelection; /*!< Specifies RF Wake-up clock source. uint32_t RFWakeUpClockSelection; /*!< Specifies RF Wake-up clock source.
This parameter can be a value of @ref RCCEx_RFWKP_Clock_Source */ This parameter can be a value of @ref RCCEx_RFWKP_Clock_Source */
#if defined(RCC_SMPS_SUPPORT)
uint32_t SmpsClockSelection; /*!< Specifies SMPS clock source. uint32_t SmpsClockSelection; /*!< Specifies SMPS clock source.
This parameter can be a value of @ref RCCEx_SMPS_Clock_Source */ This parameter can be a value of @ref RCCEx_SMPS_Clock_Source */
uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor. uint32_t SmpsDivSelection; /*!< Specifies SMPS clock division factor.
This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */ This parameter can be a value of @ref RCCEx_SMPS_Clock_Divider */
#endif
} RCC_PeriphCLKInitTypeDef; } RCC_PeriphCLKInitTypeDef;
#if defined(CRS)
/** /**
* @brief RCC_CRS Init structure definition * @brief RCC_CRS Init structure definition
*/ */
@ -329,7 +373,7 @@ typedef struct
This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/ This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
} RCC_CRSSynchroInfoTypeDef; } RCC_CRSSynchroInfoTypeDef;
#endif
/** /**
* @} * @}
@ -364,25 +408,31 @@ typedef struct
* @{ * @{
*/ */
#define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_USART1 0x00000001U /*!< USART1 Peripheral Clock Selection */
#if defined(LPUART1)
#define RCC_PERIPHCLK_LPUART1 0x00000002U /*!< LPUART1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_LPUART1 0x00000002U /*!< LPUART1 Peripheral Clock Selection */
#endif
#define RCC_PERIPHCLK_I2C1 0x00000004U /*!< I2C1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_I2C1 0x00000004U /*!< I2C1 Peripheral Clock Selection */
#if defined(I2C3)
#define RCC_PERIPHCLK_I2C3 0x00000008U /*!< I2C3 Peripheral Clock Selection */ #define RCC_PERIPHCLK_I2C3 0x00000008U /*!< I2C3 Peripheral Clock Selection */
#endif
#define RCC_PERIPHCLK_LPTIM1 0x00000010U /*!< LPTIM1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_LPTIM1 0x00000010U /*!< LPTIM1 Peripheral Clock Selection */
#define RCC_PERIPHCLK_LPTIM2 0x00000020U /*!< LPTIM2 Peripheral Clock Selection */ #define RCC_PERIPHCLK_LPTIM2 0x00000020U /*!< LPTIM2 Peripheral Clock Selection */
#if defined(SAI1)
#define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */ #define RCC_PERIPHCLK_SAI1 0x00000040U /*!< SAI1 Peripheral Clock Selection */
#define RCC_PERIPHCLK_USB 0x00000100U /*!< USB Peripheral Clock Selection */ #endif
#define RCC_PERIPHCLK_CLK48SEL 0x00000100U /*!< 48 MHz clock source selection */
#define RCC_PERIPHCLK_USB RCC_PERIPHCLK_CLK48SEL /*!< USB Peripheral Clock Selection */
#define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */ #define RCC_PERIPHCLK_RNG 0x00000200U /*!< RNG Peripheral Clock Selection */
#define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */ #define RCC_PERIPHCLK_ADC 0x00000400U /*!< ADC Peripheral Clock Selection */
#define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */ #define RCC_PERIPHCLK_RTC 0x00000800U /*!< RTC Peripheral Clock Selection */
#define RCC_PERIPHCLK_RFWAKEUP 0x00001000U /*!< RF Wakeup Peripheral Clock Selection */ #define RCC_PERIPHCLK_RFWAKEUP 0x00001000U /*!< RF Wakeup Peripheral Clock Selection */
#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPSS Peripheral Clock Selection */ #if defined(RCC_SMPS_SUPPORT)
#define RCC_PERIPHCLK_SMPS 0x00002000U /*!< SMPS Peripheral Clock Selection */
#endif
/** /**
* @} * @}
*/ */
/** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source /** @defgroup RCCEx_USART1_Clock_Source USART1 Clock Source
* @{ * @{
*/ */
@ -394,7 +444,7 @@ typedef struct
* @} * @}
*/ */
#if defined(LPUART1)
/** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source /** @defgroup RCCEx_LPUART1_Clock_Source LPUART1 Clock Source
* @{ * @{
*/ */
@ -405,6 +455,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif
/** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source /** @defgroup RCCEx_I2C1_Clock_Source I2C1 Clock Source
* @{ * @{
@ -416,7 +467,7 @@ typedef struct
* @} * @}
*/ */
#if defined(I2C3)
/** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source /** @defgroup RCCEx_I2C3_Clock_Source I2C3 Clock Source
* @{ * @{
*/ */
@ -426,8 +477,9 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif
#if defined(SAI1)
/** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source /** @defgroup RCCEx_SAI1_Clock_Source SAI1 Clock Source
* @{ * @{
*/ */
@ -438,6 +490,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif
/** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source /** @defgroup RCCEx_LPTIM1_Clock_Source LPTIM1 Clock Source
* @{ * @{
@ -454,9 +507,9 @@ typedef struct
* @{ * @{
*/ */
#define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */ #define RCC_LPTIM2CLKSOURCE_PCLK1 LL_RCC_LPTIM2_CLKSOURCE_PCLK1 /*!< APB1 clock selected as LPTIM2 clock */
#define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM1 clock */ #define RCC_LPTIM2CLKSOURCE_LSI LL_RCC_LPTIM2_CLKSOURCE_LSI /*!< LSI clock selected as LPTIM2 clock */
#define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM1 clock */ #define RCC_LPTIM2CLKSOURCE_HSI LL_RCC_LPTIM2_CLKSOURCE_HSI /*!< HSI clock selected as LPTIM2 clock */
#define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM1 clock */ #define RCC_LPTIM2CLKSOURCE_LSE LL_RCC_LPTIM2_CLKSOURCE_LSE /*!< LSE clock selected as LPTIM2 clock */
/** /**
* @} * @}
*/ */
@ -464,9 +517,12 @@ typedef struct
/** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source /** @defgroup RCCEx_RNG_Clock_Source RNG Clock Source
* @{ * @{
*/ */
#define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48 /*!< CLK48 divided by 3 selected as RNG Clock */ #define RCC_RNGCLKSOURCE_HSI48 (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_HSI48) /*!< HSI48 clock divided by 3 selected as RNG clock */
#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI selected as ADC clock*/ #define RCC_RNGCLKSOURCE_PLL (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_PLL) /*!< PLL "Q" clock divided by 3 selected as RNG clock */
#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE selected as ADC clock*/ #define RCC_RNGCLKSOURCE_MSI (CLK48_MASK | LL_RCC_CLK48_CLKSOURCE_MSI) /*!< MSI clock divided by 3 selected as RNG clock */
#define RCC_RNGCLKSOURCE_CLK48 LL_RCC_RNG_CLKSOURCE_CLK48 /*!< CLK48 divided by 3 selected as RNG Clock */
#define RCC_RNGCLKSOURCE_LSI LL_RCC_RNG_CLKSOURCE_LSI /*!< LSI clock selected as RNG clock */
#define RCC_RNGCLKSOURCE_LSE LL_RCC_RNG_CLKSOURCE_LSE /*!< LSE clock selected as RNG clock */
/** /**
* @} * @}
*/ */
@ -474,12 +530,10 @@ typedef struct
/** @defgroup RCCEx_USB_Clock_Source USB Clock Source /** @defgroup RCCEx_USB_Clock_Source USB Clock Source
* @{ * @{
*/ */
#define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */ #define RCC_USBCLKSOURCE_HSI48 LL_RCC_USB_CLKSOURCE_HSI48 /*!< HSI48 clock selected as USB clock */
#define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_PLLSAI1 LL_RCC_USB_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "Q" clock selected as USB clock */
#define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */ #define RCC_USBCLKSOURCE_PLL LL_RCC_USB_CLKSOURCE_PLL /*!< PLL "Q" clock selected as USB clock */
#define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */ #define RCC_USBCLKSOURCE_MSI LL_RCC_USB_CLKSOURCE_MSI /*!< MSI clock selected as USB clock */
/** /**
* @} * @}
*/ */
@ -489,7 +543,9 @@ typedef struct
*/ */
#define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_NONE LL_RCC_ADC_CLKSOURCE_NONE /*!< None clock selected as ADC clock */
#if defined(SAI1)
#define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_PLLSAI1 LL_RCC_ADC_CLKSOURCE_PLLSAI1 /*!< PLLSAI1 "R" clock selected as ADC clock */
#endif
#define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_PLL LL_RCC_ADC_CLKSOURCE_PLL /*!< PLL "P" clock selected as ADC clock */
#define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */ #define RCC_ADCCLKSOURCE_SYSCLK LL_RCC_ADC_CLKSOURCE_SYSCLK /*!< SYSCLK clock selected as ADC clock */
@ -522,45 +578,38 @@ typedef struct
*/ */
#if defined(RCC_SMPS_SUPPORT)
/** @defgroup RCCEx_SMPS_Clock_Source SMPS Clock Source /** @defgroup RCCEx_SMPS_Clock_Source SMPS Clock Source
* @{ * @{
*/ */
#define RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI /*!< HSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_HSI LL_RCC_SMPS_CLKSOURCE_HSI /*!< HSI selection as smps clock */
#define RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI /*!< MSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_MSI LL_RCC_SMPS_CLKSOURCE_MSI /*!< MSI selection as smps clock */
#define RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE /*!< HSE selection as smps clock */ #define RCC_SMPSCLKSOURCE_HSE LL_RCC_SMPS_CLKSOURCE_HSE /*!< HSE selection as smps clock */
/** /**
* @} * @}
*/ */
/** @defgroup RCC_System_Clock_Source_Status System Clock Source Status /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
* @{ * @{
*/ */
#define RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI /*!< HSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_STATUS_HSI LL_RCC_SMPS_CLKSOURCE_STATUS_HSI /*!< HSI selection as smps clock */
#define RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI /*!< MSI selection as smps clock */ #define RCC_SMPSCLKSOURCE_STATUS_MSI LL_RCC_SMPS_CLKSOURCE_STATUS_MSI /*!< MSI selection as smps clock */
#define RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE /*!< HSE selection as smps clock */ #define RCC_SMPSCLKSOURCE_STATUS_HSE LL_RCC_SMPS_CLKSOURCE_STATUS_HSE /*!< HSE selection as smps clock */
/** /**
* @} * @}
*/ */
/** @defgroup RCCEx_SMPS_Clock_Divider SMPS Clock Division Factor /** @defgroup RCCEx_SMPS_Clock_Divider SMPS Clock Division Factor
* @{ * @{
*/ */
#define RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0 /*!< PLLM division factor = 0 */ #define RCC_SMPSCLKDIV_RANGE0 LL_RCC_SMPS_DIV_0 /*!< PLLM division factor = 0 */
#define RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1 /*!< PLLM division factor = 1 */ #define RCC_SMPSCLKDIV_RANGE1 LL_RCC_SMPS_DIV_1 /*!< PLLM division factor = 1 */
#define RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2 /*!< PLLM division factor = 2 */ #define RCC_SMPSCLKDIV_RANGE2 LL_RCC_SMPS_DIV_2 /*!< PLLM division factor = 2 */
#define RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3 /*!< PLLM division factor = 3 */ #define RCC_SMPSCLKDIV_RANGE3 LL_RCC_SMPS_DIV_3 /*!< PLLM division factor = 3 */
/** /**
* @} * @}
*/ */
#endif
/** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line /** @defgroup RCCEx_EXTI_LINE_LSECSS RCC LSE CSS external interrupt line
* @{ * @{
@ -572,6 +621,7 @@ typedef struct
*/ */
#if defined(CRS)
/** @defgroup RCCEx_CRS_Status RCCEx CRS Status /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
* @{ * @{
*/ */
@ -685,6 +735,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif
/** /**
* @} * @}
@ -697,6 +748,7 @@ typedef struct
/*================================================================================================================*/ /*================================================================================================================*/
#if defined(SAI1)
/** /**
* @brief Macro to configure the PLLSAI1 clock multiplication and division factors. * @brief Macro to configure the PLLSAI1 clock multiplication and division factors.
* *
@ -705,9 +757,9 @@ typedef struct
* @ref __HAL_RCC_PLL_CONFIG() macro) * @ref __HAL_RCC_PLL_CONFIG() macro)
* *
* @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. * @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock.
* This parameter must be a number between 4 and 86. * This parameter must be a number between 6 and 127.
* @note You have to set the PLLN parameter correctly to ensure that the VCO * @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 64 and 344 MHz. * output frequency is between 96 and 344 MHz.
* PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN * PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
* *
* @param __PLLP__ specifies the division factor for SAI clock. * @param __PLLP__ specifies the division factor for SAI clock.
@ -737,9 +789,9 @@ typedef struct
* @ref __HAL_RCC_PLL_CONFIG() macro) * @ref __HAL_RCC_PLL_CONFIG() macro)
* *
* @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock. * @param __PLLN__ specifies the multiplication factor for PLLSAI1 VCO output clock.
* This parameter must be a number between Min_Data=4 and Max_Data=86. * This parameter must be a number between Min_Data=6 and Max_Data=127.
* @note You have to set the PLLN parameter correctly to ensure that the VCO * @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 64 and 344 MHz. * output frequency is between 96 and 344 MHz.
* Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN * Use to set PLLSAI1 clock frequency = f(PLLSAI1) multiplied by PLLN
* *
* @retval None * @retval None
@ -817,7 +869,6 @@ typedef struct
* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
* @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral
* @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz)
* @arg @ref RCC_PLLSAI1_RNGCLK same as RCC_PLLSAI1_USBCLK
* *
* @retval None * @retval None
*/ */
@ -832,7 +883,6 @@ typedef struct
* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
* @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral
* @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz)
* @arg @ref RCC_PLLSAI1_RNGCLK same as RCC_PLLSAI1_USBCLK
* *
* @retval None * @retval None
*/ */
@ -845,7 +895,6 @@ typedef struct
* @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface * @arg @ref RCC_PLLSAI1_SAI1CLK This clock is used to generate an accurate clock to achieve high-quality audio performance on SAI interface
* @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral * @arg @ref RCC_PLLSAI1_ADCCLK Clock used to clock ADC peripheral
* @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz) * @arg @ref RCC_PLLSAI1_USBCLK This clock is used to generate the clock for the USB Device (48 MHz)
* @arg @ref RCC_PLLSAI1_RNGCLK same as RCC_PLLSAI1_USBCLK
* @retval SET / RESET * @retval SET / RESET
*/ */
#define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__)) #define __HAL_RCC_GET_PLLSAI1CLKOUT_CONFIG(__PLLSAI1_CLOCKOUT__) READ_BIT(RCC->PLLSAI1CFGR, (__PLLSAI1_CLOCKOUT__))
@ -876,6 +925,7 @@ typedef struct
* @retval None * @retval None
*/ */
#define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE) #define __HAL_RCC_GET_SAI1_SOURCE() LL_RCC_GetSAIClockSource(LL_RCC_SAI1_CLKSOURCE)
#endif
/** @brief Macro to configure the I2C1 clock (I2C1CLK). /** @brief Macro to configure the I2C1 clock (I2C1CLK).
* *
@ -896,6 +946,7 @@ typedef struct
*/ */
#define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE) #define __HAL_RCC_GET_I2C1_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C1_CLKSOURCE)
#if defined(I2C3)
/** @brief Macro to configure the I2C3 clock (I2C3CLK). /** @brief Macro to configure the I2C3 clock (I2C3CLK).
* *
* @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source. * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
@ -914,6 +965,7 @@ typedef struct
* @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock * @arg @ref RCC_I2C3CLKSOURCE_SYSCLK System Clock selected as I2C3 clock
*/ */
#define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE) #define __HAL_RCC_GET_I2C3_SOURCE() LL_RCC_GetI2CClockSource(LL_RCC_I2C3_CLKSOURCE)
#endif
/** @brief Macro to configure the USART1 clock (USART1CLK). /** @brief Macro to configure the USART1 clock (USART1CLK).
* *
@ -936,6 +988,7 @@ typedef struct
*/ */
#define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE) #define __HAL_RCC_GET_USART1_SOURCE() LL_RCC_GetUSARTClockSource(LL_RCC_USART1_CLKSOURCE)
#if defined(LPUART1)
/** @brief Macro to configure the LPUART clock (LPUARTCLK). /** @brief Macro to configure the LPUART clock (LPUARTCLK).
* *
* @param __LPUART_CLKSOURCE__ specifies the LPUART clock source. * @param __LPUART_CLKSOURCE__ specifies the LPUART clock source.
@ -956,6 +1009,7 @@ typedef struct
* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock * @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
*/ */
#define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE) #define __HAL_RCC_GET_LPUART1_SOURCE() LL_RCC_GetLPUARTClockSource(LL_RCC_LPUART1_CLKSOURCE)
#endif
/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK). /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
* *
@ -1006,19 +1060,40 @@ typedef struct
* *
* @param __RNG_CLKSOURCE__ specifies the RNG clock source. * @param __RNG_CLKSOURCE__ specifies the RNG clock source.
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock * @arg @ref RCC_RNGCLKSOURCE_HSI48 HSI48 clock divided by 3 selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_PLL PLL "Q" clock divided by 3 selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_MSI MSI clock divided by 3 selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock (default HSI48)
* @arg @ref RCC_RNGCLKSOURCE_LSI LSI clock selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE clock selected as RNG clock
* @retval None * @retval None
*/ */
#define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) LL_RCC_SetRNGClockSource(__RNG_CLKSOURCE__) #define __HAL_RCC_RNG_CONFIG(__RNG_CLKSOURCE__) \
do { \
if (((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSI) \
|| ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_LSE) \
|| ((__RNG_CLKSOURCE__) == RCC_RNGCLKSOURCE_CLK48)) \
{ \
LL_RCC_SetRNGClockSource((__RNG_CLKSOURCE__)); \
} \
else \
{ \
uint32_t tmp = (__RNG_CLKSOURCE__) &(~CLK48_MASK); \
LL_RCC_SetRNGClockSource(RCC_RNGCLKSOURCE_CLK48); \
LL_RCC_SetCLK48ClockSource(tmp); \
} \
} while(0U)
/** @brief Macro to get the RNG clock. * @retval The clock source can be one of the following values: /** @brief Macro to get the direct RNG clock.
* @note @ref HAL_RCCEx_GetRngCLKSource can also be called to get direct
* of indirect (48 MHz clock source) RNG clock source.
* @retval The RNG clock source can be one of the following values:
* @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock * @arg @ref RCC_RNGCLKSOURCE_CLK48 CLK48 divided by 3 selected as RNG Clock
* @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_LSI LSI selected as RNG clock
* @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock * @arg @ref RCC_RNGCLKSOURCE_LSE LSE selected as RNG clock
*/ */
#define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE) #define __HAL_RCC_GET_RNG_SOURCE() LL_RCC_GetRNGClockSource(LL_RCC_RNG_CLKSOURCE)
/** @brief Macro to configure the USB clock (USBCLK). /** @brief Macro to configure the USB clock (USBCLK).
* *
* @note USB and RNG peripherals share the same 48MHz clock source. * @note USB and RNG peripherals share the same 48MHz clock source.
@ -1082,6 +1157,7 @@ typedef struct
*/ */
#define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource() #define __HAL_RCC_GET_RFWAKEUP_SOURCE() LL_RCC_GetRFWKPClockSource()
#if defined(RCC_SMPS_SUPPORT)
/** @brief Macro to configure the SMPS clock division factor. /** @brief Macro to configure the SMPS clock division factor.
* *
* @param __SMPSCLKDIV__ specifies the division factor for SMPS clock. * @param __SMPSCLKDIV__ specifies the division factor for SMPS clock.
@ -1134,12 +1210,14 @@ typedef struct
* @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock * @arg @ref RCC_SMPSCLKSOURCE_STATUS_HSE HSE Clock selected as SMPS clock
*/ */
#define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource() #define __HAL_RCC_GET_SMPS_SOURCE_STATUS() LL_RCC_GetSMPSClockSource()
#endif
/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management /** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts. * @brief macros to manage the specified RCC Flags and interrupts.
* @{ * @{
*/ */
#if defined(SAI1)
/** @brief Enable PLLSAI1RDY interrupt. /** @brief Enable PLLSAI1RDY interrupt.
* @retval None * @retval None
*/ */
@ -1164,6 +1242,7 @@ typedef struct
* @retval TRUE or FALSE. * @retval TRUE or FALSE.
*/ */
#define __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady() #define __HAL_RCC_PLLSAI1_GET_FLAG() LL_RCC_PLLSAI1_IsReady()
#endif
/** /**
* @brief Enable the RCC LSE CSS Extended Interrupt C1 Line. * @brief Enable the RCC LSE CSS Extended Interrupt C1 Line.
@ -1275,6 +1354,7 @@ typedef struct
*/ */
#define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS) #define __HAL_RCC_LSECSS_EXTI_GENERATE_SWIT() LL_EXTI_GenerateSWI_0_31(RCC_EXTI_LINE_LSECSS)
#if defined(CRS)
/** /**
* @brief Enable the specified CRS interrupts. * @brief Enable the specified CRS interrupts.
* @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled. * @param __INTERRUPT__ specifies the CRS interrupt sources to be enabled.
@ -1371,12 +1451,13 @@ typedef struct
WRITE_REG(CRS->ICR, (__FLAG__)); \ WRITE_REG(CRS->ICR, (__FLAG__)); \
} \ } \
} while(0) } while(0)
#endif
/** /**
* @} * @}
*/ */
#if defined(CRS)
/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
* @{ * @{
*/ */
@ -1421,6 +1502,7 @@ typedef struct
/** /**
* @} * @}
*/ */
#endif
/** /**
* @} * @}
@ -1438,6 +1520,7 @@ typedef struct
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit); void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk); uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
uint32_t HAL_RCCEx_GetRngCLKSource(void);
/** /**
* @} * @}
@ -1447,8 +1530,10 @@ uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
* @{ * @{
*/ */
#if defined(SAI1)
HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init); HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI1(RCC_PLLSAI1InitTypeDef *PLLSAI1Init);
HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void); HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI1(void);
#endif
void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk); void HAL_RCCEx_WakeUpStopCLKConfig(uint32_t WakeUpClk);
@ -1471,6 +1556,7 @@ HAL_StatusTypeDef HAL_RCCEx_TrimOsc(uint32_t OscillatorType);
* @} * @}
*/ */
#if defined(CRS) #if defined(CRS)
/** @addtogroup RCCEx_Exported_Functions_Group3 /** @addtogroup RCCEx_Exported_Functions_Group3
@ -1491,8 +1577,7 @@ void HAL_RCCEx_CRS_ErrorCallback(uint32_t Error);
* @} * @}
*/ */
#endif /* CRS */ #endif
/** /**
* @} * @}
*/ */

45
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rng.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rng.c
View File

@ -308,7 +308,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
if (pCallback == NULL) if (pCallback == NULL)
{ {
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR; return HAL_ERROR;
} }
/* Process locked */ /* Process locked */
@ -332,7 +332,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
default : default :
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
break; break;
@ -352,7 +352,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
default : default :
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
break; break;
@ -361,7 +361,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Call
else else
{ {
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
} }
@ -407,7 +407,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
default : default :
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
break; break;
@ -427,7 +427,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
default : default :
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
break; break;
@ -436,7 +436,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterCallback(RNG_HandleTypeDef *hrng, HAL_RNG_Ca
else else
{ {
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
} }
@ -460,7 +460,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRN
if (pCallback == NULL) if (pCallback == NULL)
{ {
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
return HAL_ERROR; return HAL_ERROR;
} }
/* Process locked */ /* Process locked */
@ -473,7 +473,7 @@ HAL_StatusTypeDef HAL_RNG_RegisterReadyDataCallback(RNG_HandleTypeDef *hrng, pRN
else else
{ {
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
} }
@ -503,7 +503,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
else else
{ {
/* Update the error code */ /* Update the error code */
hrng->ErrorCode |= HAL_RNG_ERROR_INVALID_CALLBACK; hrng->ErrorCode = HAL_RNG_ERROR_INVALID_CALLBACK;
/* Return error status */ /* Return error status */
status = HAL_ERROR; status = HAL_ERROR;
} }
@ -537,8 +537,16 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng)
/** /**
* @brief Generates a 32-bit random number. * @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag * @note This function checks value of RNG_FLAG_DRDY flag to know if valid
* is automatically cleared. * random number is available in the DR register (RNG_FLAG_DRDY flag set
* whenever a random number is available through the RNG_DR register).
* After transitioning from 0 to 1 (random number available),
* RNG_FLAG_DRDY flag remains high until output buffer becomes empty after reading
* four words from the RNG_DR register, i.e. further function calls
* will immediately return a new u32 random number (additional words are
* available and can be read by the application, till RNG_FLAG_DRDY flag remains high).
* @note When no more random number data is available in DR register, RNG_FLAG_DRDY
* flag is automatically cleared.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG. * the configuration information for RNG.
* @param random32bit pointer to generated random number variable if successful. * @param random32bit pointer to generated random number variable if successful.
@ -568,7 +576,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE)
{ {
hrng->State = HAL_RNG_STATE_READY; hrng->State = HAL_RNG_STATE_READY;
hrng->ErrorCode |= HAL_RNG_ERROR_TIMEOUT; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hrng); __HAL_UNLOCK(hrng);
return HAL_ERROR; return HAL_ERROR;
@ -583,6 +591,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t
} }
else else
{ {
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR; status = HAL_ERROR;
} }
@ -619,6 +628,7 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng)
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hrng); __HAL_UNLOCK(hrng);
hrng->ErrorCode = HAL_RNG_ERROR_BUSY;
status = HAL_ERROR; status = HAL_ERROR;
} }
@ -653,10 +663,14 @@ void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng)
/* RNG clock error interrupt occurred */ /* RNG clock error interrupt occurred */
if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET) if (__HAL_RNG_GET_IT(hrng, RNG_IT_CEI) != RESET)
{ {
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_CLOCK;
rngclockerror = 1U; rngclockerror = 1U;
} }
else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET) else if (__HAL_RNG_GET_IT(hrng, RNG_IT_SEI) != RESET)
{ {
/* Update the error code */
hrng->ErrorCode = HAL_RNG_ERROR_SEED;
rngclockerror = 1U; rngclockerror = 1U;
} }
else else
@ -721,6 +735,11 @@ uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng)
/** /**
* @brief Data Ready callback in non-blocking mode. * @brief Data Ready callback in non-blocking mode.
* @note When RNG_FLAG_DRDY flag value is set, first random number has been read
* from DR register in IRQ Handler and is provided as callback parameter.
* Depending on valid data available in the conditioning output buffer,
* additional words can be read by the application from DR register till
* DRDY bit remains high.
* @param hrng pointer to a RNG_HandleTypeDef structure that contains * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG. * the configuration information for RNG.
* @param random32bit generated random number. * @param random32bit generated random number.

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rng.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rng.h
View File

@ -176,7 +176,9 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t
#define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */ #define HAL_RNG_ERROR_INVALID_CALLBACK 0x00000001U /*!< Invalid Callback error */
#endif /* USE_HAL_RNG_REGISTER_CALLBACKS */ #endif /* USE_HAL_RNG_REGISTER_CALLBACKS */
#define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */ #define HAL_RNG_ERROR_TIMEOUT 0x00000002U /*!< Timeout error */
#define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */
#define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */
#define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */
/** /**
* @} * @}
*/ */

41
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rtc.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.c
View File

@ -87,10 +87,12 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1 The compilation define USE_RTC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback. Use Function @ref HAL_RTC_RegisterCallback() to register an interrupt callback.
[..]
Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks: Function @ref HAL_RTC_RegisterCallback() allows to register following callbacks:
(+) AlarmAEventCallback : RTC Alarm A Event callback. (+) AlarmAEventCallback : RTC Alarm A Event callback.
(+) AlarmBEventCallback : RTC Alarm B Event callback. (+) AlarmBEventCallback : RTC Alarm B Event callback.
@ -101,9 +103,11 @@
(+) Tamper3EventCallback : RTC Tamper 3 Event callback. (+) Tamper3EventCallback : RTC Tamper 3 Event callback.
(+) MspInitCallback : RTC MspInit callback. (+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback. (+) MspDeInitCallback : RTC MspDeInit callback.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
[..]
Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default Use function @ref HAL_RTC_UnRegisterCallback() to reset a callback to the default
weak function. weak function.
@ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle, @ref HAL_RTC_UnRegisterCallback() takes as parameters the HAL peripheral handle,
@ -119,6 +123,7 @@
(+) MspInitCallback : RTC MspInit callback. (+) MspInitCallback : RTC MspInit callback.
(+) MspDeInitCallback : RTC MspDeInit callback. (+) MspDeInitCallback : RTC MspDeInit callback.
[..]
By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET, By default, after the @ref HAL_RTC_Init() and when the state is HAL_RTC_STATE_RESET,
all callbacks are set to the corresponding weak functions : all callbacks are set to the corresponding weak functions :
examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback(). examples @ref AlarmAEventCallback(), @ref WakeUpTimerEventCallback().
@ -128,6 +133,7 @@
If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit() If not, MspInit or MspDeInit are not null, @ref HAL_RTC_Init()/@ref HAL_RTC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
[..]
Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only. Callbacks can be registered/unregistered in HAL_RTC_STATE_READY state only.
Exception done MspInit/MspDeInit that can be registered/unregistered Exception done MspInit/MspDeInit that can be registered/unregistered
in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state, in HAL_RTC_STATE_READY or HAL_RTC_STATE_RESET state,
@ -136,6 +142,7 @@
using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit() using @ref HAL_RTC_RegisterCallback() before calling @ref HAL_RTC_DeInit()
or @ref HAL_RTC_Init() function. or @ref HAL_RTC_Init() function.
[..]
When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_RTC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@ -249,9 +256,13 @@ HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */ hrtc->AlarmBEventCallback = HAL_RTCEx_AlarmBEventCallback; /* Legacy weak AlarmBEventCallback */
hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */ hrtc->TimeStampEventCallback = HAL_RTCEx_TimeStampEventCallback; /* Legacy weak TimeStampEventCallback */
hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
#if defined(RTC_TAMPER1_SUPPORT)
hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
#endif
hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
#if defined(RTC_TAMPER3_SUPPORT)
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
#endif
if(hrtc->MspInitCallback == NULL) if(hrtc->MspInitCallback == NULL)
{ {
@ -463,11 +474,14 @@ HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID (*)
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*)
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
*
* (*) Value not defined in all devices. \n
*
* @param pCallback pointer to the Callback function * @param pCallback pointer to the Callback function
* @retval HAL status * @retval HAL status
*/ */
@ -503,17 +517,21 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
hrtc->WakeUpTimerEventCallback = pCallback; hrtc->WakeUpTimerEventCallback = pCallback;
break; break;
#if defined(RTC_TAMPER1_SUPPORT)
case HAL_RTC_TAMPER1_EVENT_CB_ID : case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = pCallback; hrtc->Tamper1EventCallback = pCallback;
break; break;
#endif
case HAL_RTC_TAMPER2_EVENT_CB_ID : case HAL_RTC_TAMPER2_EVENT_CB_ID :
hrtc->Tamper2EventCallback = pCallback; hrtc->Tamper2EventCallback = pCallback;
break; break;
#if defined(RTC_TAMPER3_SUPPORT)
case HAL_RTC_TAMPER3_EVENT_CB_ID : case HAL_RTC_TAMPER3_EVENT_CB_ID :
hrtc->Tamper3EventCallback = pCallback; hrtc->Tamper3EventCallback = pCallback;
break; break;
#endif
case HAL_RTC_MSPINIT_CB_ID : case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = pCallback; hrtc->MspInitCallback = pCallback;
@ -569,11 +587,14 @@ HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Call
* @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID * @arg @ref HAL_RTC_ALARM_B_EVENT_CB_ID Alarm B Event Callback ID
* @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID * @arg @ref HAL_RTC_TIMESTAMP_EVENT_CB_ID TimeStamp Event Callback ID
* @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID * @arg @ref HAL_RTC_WAKEUPTIMER_EVENT_CB_ID WakeUp Timer Event Callback ID
* @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID * @arg @ref HAL_RTC_TAMPER1_EVENT_CB_ID Tamper 1 Callback ID (*)
* @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID * @arg @ref HAL_RTC_TAMPER2_EVENT_CB_ID Tamper 2 Callback ID
* @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID * @arg @ref HAL_RTC_TAMPER3_EVENT_CB_ID Tamper 3 Callback ID (*)
* @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID * @arg @ref HAL_RTC_MSPINIT_CB_ID Msp Init callback ID
* @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID * @arg @ref HAL_RTC_MSPDEINIT_CB_ID Msp DeInit callback ID
*
* (*) Value not defined in all devices. \n
*
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID) HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID)
@ -603,17 +624,21 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca
hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */ hrtc->WakeUpTimerEventCallback = HAL_RTCEx_WakeUpTimerEventCallback; /* Legacy weak WakeUpTimerEventCallback */
break; break;
#if defined(RTC_TAMPER1_SUPPORT)
case HAL_RTC_TAMPER1_EVENT_CB_ID : case HAL_RTC_TAMPER1_EVENT_CB_ID :
hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */ hrtc->Tamper1EventCallback = HAL_RTCEx_Tamper1EventCallback; /* Legacy weak Tamper1EventCallback */
break; break;
#endif
case HAL_RTC_TAMPER2_EVENT_CB_ID : case HAL_RTC_TAMPER2_EVENT_CB_ID :
hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */ hrtc->Tamper2EventCallback = HAL_RTCEx_Tamper2EventCallback; /* Legacy weak Tamper2EventCallback */
break; break;
#if defined(RTC_TAMPER3_SUPPORT)
case HAL_RTC_TAMPER3_EVENT_CB_ID : case HAL_RTC_TAMPER3_EVENT_CB_ID :
hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */ hrtc->Tamper3EventCallback = HAL_RTCEx_Tamper3EventCallback; /* Legacy weak Tamper3EventCallback */
break; break;
#endif
case HAL_RTC_MSPINIT_CB_ID : case HAL_RTC_MSPINIT_CB_ID :
hrtc->MspInitCallback = HAL_RTC_MspInit; hrtc->MspInitCallback = HAL_RTC_MspInit;

5
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rtc.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc.h
View File

@ -27,7 +27,6 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal_def.h" #include "stm32wbxx_hal_def.h"
#include "stm32wbxx_ll_rtc.h"
/* Include low level driver */ /* Include low level driver */
#include "stm32wbxx_ll_exti.h" #include "stm32wbxx_ll_exti.h"
@ -214,9 +213,13 @@ typedef enum
HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */ HAL_RTC_ALARM_B_EVENT_CB_ID = 0x01U, /*!< RTC Alarm B Event Callback ID */
HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */ HAL_RTC_TIMESTAMP_EVENT_CB_ID = 0x02U, /*!< RTC TimeStamp Event Callback ID */
HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */ HAL_RTC_WAKEUPTIMER_EVENT_CB_ID = 0x03U, /*!< RTC WakeUp Timer Event Callback ID */
#if defined(RTC_TAMPER1_SUPPORT)
HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */ HAL_RTC_TAMPER1_EVENT_CB_ID = 0x04U, /*!< RTC Tamper 1 Callback ID */
#endif
HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */ HAL_RTC_TAMPER2_EVENT_CB_ID = 0x05U, /*!< RTC Tamper 2 Callback ID */
#if defined(RTC_TAMPER3_SUPPORT)
HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */ HAL_RTC_TAMPER3_EVENT_CB_ID = 0x06U, /*!< RTC Tamper 3 Callback ID */
#endif
HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */ HAL_RTC_MSPINIT_CB_ID = 0x0EU, /*!< RTC Msp Init callback ID */
HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */ HAL_RTC_MSPDEINIT_CB_ID = 0x0FU /*!< RTC Msp DeInit callback ID */
}HAL_RTC_CallbackIDTypeDef; }HAL_RTC_CallbackIDTypeDef;

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rtc_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.c
View File

@ -479,8 +479,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef
uint32_t tmpreg; uint32_t tmpreg;
/* Check the parameters */ /* Check the parameters */
assert_param( IS_RTC_TAMPER(sTamper->Tamper)); assert_param(IS_RTC_TAMPER(sTamper->Tamper));
assert_param( IS_RTC_TAMPER_TRIGGER(sTamper->Trigger)); assert_param(IS_RTC_TAMPER_TRIGGER(sTamper->Trigger));
assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase)); assert_param(IS_RTC_TAMPER_ERASE_MODE(sTamper->NoErase));
assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag)); assert_param(IS_RTC_TAMPER_MASKFLAG_STATE(sTamper->MaskFlag));
assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter)); assert_param(IS_RTC_TAMPER_FILTER(sTamper->Filter));

240
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_rtc_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_rtc_ex.h
View File

@ -731,17 +731,18 @@ typedef struct
/**************************************************************************************************/ /**************************************************************************************************/
#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
/** /**
* @brief Enable the RTC Tamper interrupt. * @brief Enable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle. * @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled. * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP1: Tamper1 interrupt (*)
* @arg RTC_IT_TAMP2: Tamper2 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
*
* (*) Value not defined in all devices. \n
*
* @retval None * @retval None
*/ */
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) #define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
@ -751,131 +752,54 @@ typedef struct
* @param __HANDLE__ specifies the RTC handle. * @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled. * @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values: * This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP1: Tamper1 interrupt
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
#elif defined(RTC_TAMPER1_SUPPORT)
/**
* @brief Enable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP1: Tamper1 interrupt (*)
* @arg RTC_IT_TAMP2: Tamper2 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt
* @retval None * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
*/ *
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__)) * (*) Value not defined in all devices. \n
*
/**
* @brief Disable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP1: Tamper1 interrupt
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @retval None * @retval None
*/ */
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__)) #define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
#elif defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Enable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR |= (__INTERRUPT__))
/**
* @brief Disable the RTC Tamper interrupt.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->TAMPCR &= ~(__INTERRUPT__))
#endif
/**************************************************************************************************/ /**************************************************************************************************/
#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
/** /**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not. * @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle. * @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be: * This parameter can be:
* @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP1: Tamper1 interrupt (*)
* @arg RTC_IT_TAMP2: Tamper2 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
*
* (*) Value not defined in all devices. \n
*
* @retval None * @retval None
*/ */
#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \ #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \ ((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U)) ((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
#else
#elif defined(RTC_TAMPER1_SUPPORT) #define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U))
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
* @arg RTC_IT_TAMP1: Tamper1 interrupt
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP1) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 3U)) != 0U) ? 1U : 0U) : \
((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U))
#elif defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) == RTC_IT_TAMP2) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 5U)) != 0U) ? 1U : 0U) : \
((__INTERRUPT__) == RTC_IT_TAMP3) ? (((((__HANDLE__)->Instance->ISR) & ((__INTERRUPT__)>> 7U)) != 0U) ? 1U : 0U))
#endif #endif
/**************************************************************************************************/ /**************************************************************************************************/
#if defined(RTC_TAMPER1_SUPPORT) && defined(RTC_TAMPER3_SUPPORT)
/** /**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not. * @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle. * @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be: * This parameter can be:
* @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP1: Tamper1 interrupt * @arg RTC_IT_TAMP1: Tamper1 interrupt (*)
* @arg RTC_IT_TAMP2: Tamper2 interrupt * @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt * @arg RTC_IT_TAMP3: Tamper3 interrupt (*)
*
* (*) Value not defined in all devices. \n
*
* @retval None * @retval None
*/ */
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) #define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
@ -886,9 +810,12 @@ typedef struct
* @param __HANDLE__ specifies the RTC handle. * @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
* This parameter can be: * This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper1 flag * @arg RTC_FLAG_TAMP1F: Tamper1 flag (*)
* @arg RTC_FLAG_TAMP2F: Tamper2 flag * @arg RTC_FLAG_TAMP2F: Tamper2 flag
* @arg RTC_FLAG_TAMP3F: Tamper3 flag * @arg RTC_FLAG_TAMP3F: Tamper3 flag (*)
*
* (*) Value not defined in all devices. \n
*
* @retval None * @retval None
*/ */
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U) #define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
@ -898,90 +825,16 @@ typedef struct
* @param __HANDLE__ specifies the RTC handle. * @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear. * @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be: * This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper1 flag * @arg RTC_FLAG_TAMP1F: Tamper1 flag (*)
* @arg RTC_FLAG_TAMP2F: Tamper2 flag * @arg RTC_FLAG_TAMP2F: Tamper2 flag
* @arg RTC_FLAG_TAMP3F: Tamper3 flag * @arg RTC_FLAG_TAMP3F: Tamper3 flag (*)
*
* (*) Value not defined in all devices. \n
*
* @retval None * @retval None
*/ */
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) #define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#elif defined(RTC_TAMPER1_SUPPORT)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP1: Tamper1 interrupt
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper1 flag
* @arg RTC_FLAG_TAMP2F: Tamper2 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
/**
* @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F: Tamper1 flag
* @arg RTC_FLAG_TAMP2F: Tamper2 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#elif defined(RTC_TAMPER3_SUPPORT)
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
* @param __HANDLE__ specifies the RTC handle.
* @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TAMP: All tampers interrupts
* @arg RTC_IT_TAMP2: Tamper2 interrupt
* @arg RTC_IT_TAMP3: Tamper3 interrupt
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((((__HANDLE__)->Instance->TAMPCR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)
/**
* @brief Get the selected RTC Tamper's flag status.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag is pending or not.
* This parameter can be:
* @arg RTC_FLAG_TAMP2F: Tamper2 flag
* @arg RTC_FLAG_TAMP3F: Tamper3 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != 0U) ? 1U : 0U)
/**
* @brief Clear the RTC Tamper's pending flags.
* @param __HANDLE__ specifies the RTC handle.
* @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_TAMP2F: Tamper2 flag
* @arg RTC_FLAG_TAMP3F: Tamper3 flag
* @retval None
*/
#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR) = (~((__FLAG__) | RTC_ISR_INIT)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
#endif
/**************************************************************************************************/ /**************************************************************************************************/
@ -1332,31 +1185,18 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t
#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \ #define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \
RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT)) RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
#elif defined(RTC_TAMPER1_SUPPORT) #else
#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP1F| \ #define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP2F | \
RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \ RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \ RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \ RTC_FLAG_INITF | RTC_FLAG_RSF | RTC_FLAG_INITS | \
RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF | \ RTC_FLAG_SHPF | RTC_FLAG_WUTWF |RTC_FLAG_ALRBWF | \
RTC_FLAG_ALRAWF)) RTC_FLAG_ALRAWF))
#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E | RTC_TAMPCR_TAMP1E)) #define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP2E))
#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER1_INTERRUPT | RTC_TAMPER2_INTERRUPT | \ #define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER2_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
RTC_ALL_TAMPER_INTERRUPT))
#elif defined(RTC_TAMPER3_SUPPORT)
#define RTC_FLAGS_MASK ((uint32_t) (RTC_FLAG_RECALPF | RTC_FLAG_TAMP3F | RTC_FLAG_TAMP2F | \
RTC_FLAG_TSOVF | RTC_FLAG_TSF | \
RTC_FLAG_WUTF | RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | \
RTC_FLAG_INITF | RTC_FLAG_RSF | \
RTC_FLAG_INITS | RTC_FLAG_SHPF | RTC_FLAG_WUTWF | \
RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF))
#define RTC_TAMPCR_TAMPXE ((uint32_t) (RTC_TAMPCR_TAMP3E | RTC_TAMPCR_TAMP2E))
#define RTC_TAMPCR_TAMPXIE ((uint32_t) (RTC_TAMPER2_INTERRUPT | \
RTC_TAMPER3_INTERRUPT | RTC_ALL_TAMPER_INTERRUPT))
#endif #endif
#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18) /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */ #define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT (EXTI_IMR1_IM18) /*!< External interrupt line 18 Connected to the RTC Tamper and Time Stamp events */

207
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_sai.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_sai.c
View File

@ -139,12 +139,13 @@
*** Callback registration *** *** Callback registration ***
============================= =============================
[..]
The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1 The compilation define USE_HAL_SAI_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use functions @ref HAL_SAI_RegisterCallback() to register a user callback. Use functions HAL_SAI_RegisterCallback() to register a user callback.
Function @ref HAL_SAI_RegisterCallback() allows to register following callbacks: [..]
Function HAL_SAI_RegisterCallback() allows to register following callbacks:
(+) RxCpltCallback : SAI receive complete. (+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete. (+) RxHalfCpltCallback : SAI receive half complete.
(+) TxCpltCallback : SAI transmit complete. (+) TxCpltCallback : SAI transmit complete.
@ -152,13 +153,16 @@
(+) ErrorCallback : SAI error. (+) ErrorCallback : SAI error.
(+) MspInitCallback : SAI MspInit. (+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit. (+) MspDeInitCallback : SAI MspDeInit.
[..]
This function takes as parameters the HAL peripheral handle, the callback ID This function takes as parameters the HAL peripheral handle, the callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
Use function @ref HAL_SAI_UnRegisterCallback() to reset a callback to the default [..]
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
weak (surcharged) function. weak (surcharged) function.
@ref HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle, HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
and the callback ID. and the callback ID.
[..]
This function allows to reset following callbacks: This function allows to reset following callbacks:
(+) RxCpltCallback : SAI receive complete. (+) RxCpltCallback : SAI receive complete.
(+) RxHalfCpltCallback : SAI receive half complete. (+) RxHalfCpltCallback : SAI receive half complete.
@ -168,23 +172,26 @@
(+) MspInitCallback : SAI MspInit. (+) MspInitCallback : SAI MspInit.
(+) MspDeInitCallback : SAI MspDeInit. (+) MspDeInitCallback : SAI MspDeInit.
By default, after the @ref HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET [..]
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
all callbacks are reset to the corresponding legacy weak (surcharged) functions: all callbacks are reset to the corresponding legacy weak (surcharged) functions:
examples @ref HAL_SAI_RxCpltCallback(), @ref HAL_SAI_ErrorCallback(). examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
Exception done for MspInit and MspDeInit callbacks that are respectively Exception done for MspInit and MspDeInit callbacks that are respectively
reset to the legacy weak (surcharged) functions in the @ref HAL_SAI_Init reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
and @ref HAL_SAI_DeInit only when these callbacks are null (not registered beforehand). and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
If not, MspInit or MspDeInit are not null, the @ref HAL_SAI_Init and @ref HAL_SAI_DeInit If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
keep and use the user MspInit/MspDeInit callbacks (registered beforehand). keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
[..]
Callbacks can be registered/unregistered in READY state only. Callbacks can be registered/unregistered in READY state only.
Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
during the Init/DeInit. during the Init/DeInit.
In that case first register the MspInit/MspDeInit user callbacks In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_SAI_RegisterCallback before calling @ref HAL_SAI_DeInit using HAL_SAI_RegisterCallback before calling HAL_SAI_DeInit
or @ref HAL_SAI_Init function. or HAL_SAI_Init function.
[..]
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used. and weak (surcharged) callbacks are used.
@ -211,13 +218,15 @@
* @{ * @{
*/ */
#ifdef HAL_SAI_MODULE_ENABLED
#if defined (SAI1)
/** @defgroup SAI SAI /** @defgroup SAI SAI
* @brief SAI HAL module driver * @brief SAI HAL module driver
* @{ * @{
*/ */
#ifdef HAL_SAI_MODULE_ENABLED
/* Private typedef -----------------------------------------------------------*/ /* Private typedef -----------------------------------------------------------*/
/** @defgroup SAI_Private_Typedefs SAI Private Typedefs /** @defgroup SAI_Private_Typedefs SAI Private Typedefs
* @{ * @{
@ -360,7 +369,6 @@ HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protoco
*/ */
HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai) HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
{ {
uint32_t tmpregisterGCR;
uint32_t ckstr_bits; uint32_t ckstr_bits;
uint32_t syncen_bits; uint32_t syncen_bits;
@ -454,22 +462,6 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
/* SAI Block Synchro Configuration -----------------------------------------*/ /* SAI Block Synchro Configuration -----------------------------------------*/
/* This setting must be done with both audio block (A & B) disabled */ /* This setting must be done with both audio block (A & B) disabled */
switch (hsai->Init.SynchroExt)
{
case SAI_SYNCEXT_DISABLE :
tmpregisterGCR = 0;
break;
case SAI_SYNCEXT_OUTBLOCKA_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCOUT_0;
break;
case SAI_SYNCEXT_OUTBLOCKB_ENABLE :
tmpregisterGCR = SAI_GCR_SYNCOUT_1;
break;
default :
tmpregisterGCR = 0;
break;
}
switch (hsai->Init.Synchro) switch (hsai->Init.Synchro)
{ {
case SAI_ASYNCHRONOUS : case SAI_ASYNCHRONOUS :
@ -478,19 +470,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
case SAI_SYNCHRONOUS : case SAI_SYNCHRONOUS :
syncen_bits = SAI_xCR1_SYNCEN_0; syncen_bits = SAI_xCR1_SYNCEN_0;
break; break;
case SAI_SYNCHRONOUS_EXT_SAI1 :
syncen_bits = SAI_xCR1_SYNCEN_1;
break;
case SAI_SYNCHRONOUS_EXT_SAI2 :
syncen_bits = SAI_xCR1_SYNCEN_1;
tmpregisterGCR |= SAI_GCR_SYNCIN_0;
break;
default : default :
syncen_bits = 0; syncen_bits = 0;
break; break;
} }
SAI1->GCR = tmpregisterGCR; SAI1->GCR = 0;
if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV) if (hsai->Init.AudioFrequency != SAI_AUDIO_FREQUENCY_MCKDIV)
{ {
@ -508,8 +493,26 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE) if (hsai->Init.NoDivider == SAI_MASTERDIVIDER_DISABLE)
{ {
/* NODIV = 1 */ /* NODIV = 1 */
uint32_t tmpframelength;
if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
{
/* For SPDIF protocol, frame length is set by hardware to 64 */
tmpframelength = 64U;
}
else if (hsai->Init.Protocol == SAI_AC97_PROTOCOL)
{
/* For AC97 protocol, frame length is set by hardware to 256 */
tmpframelength = 256U;
}
else
{
/* For free protocol, frame length is set by user */
tmpframelength = hsai->FrameInit.FrameLength;
}
/* (freq x 10) to keep Significant digits */ /* (freq x 10) to keep Significant digits */
tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * hsai->FrameInit.FrameLength); tmpval = (freq * 10U) / (hsai->Init.AudioFrequency * tmpframelength);
} }
else else
{ {
@ -526,6 +529,12 @@ HAL_StatusTypeDef HAL_SAI_Init(SAI_HandleTypeDef *hsai)
{ {
hsai->Init.Mckdiv += 1U; hsai->Init.Mckdiv += 1U;
} }
/* For SPDIF protocol, SAI shall provide a bit clock twice faster the symbol-rate */
if (hsai->Init.Protocol == SAI_SPDIF_PROTOCOL)
{
hsai->Init.Mckdiv = hsai->Init.Mckdiv >> 1;
}
} }
/* Check the SAI Block master clock divider parameter */ /* Check the SAI Block master clock divider parameter */
assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv)); assert_param(IS_SAI_BLOCK_MASTER_DIVIDER(hsai->Init.Mckdiv));
@ -1338,29 +1347,17 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
/* Abort the SAI Tx DMA Stream */ /* Abort the SAI Tx DMA Stream */
if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
{ {
if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) /* No need to check the returned value of HAL_DMA_Abort. */
{ /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
/* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ (void) HAL_DMA_Abort(hsai->hdmatx);
if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
{
status = HAL_ERROR;
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
}
}
} }
/* Abort the SAI Rx DMA Stream */ /* Abort the SAI Rx DMA Stream */
if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
{ {
if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) /* No need to check the returned value of HAL_DMA_Abort. */
{ /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
/* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ (void) HAL_DMA_Abort(hsai->hdmarx);
if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
{
status = HAL_ERROR;
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
}
}
} }
/* Disable SAI peripheral */ /* Disable SAI peripheral */
@ -1403,29 +1400,17 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
/* Abort the SAI Tx DMA Stream */ /* Abort the SAI Tx DMA Stream */
if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL)) if ((hsai->State == HAL_SAI_STATE_BUSY_TX) && (hsai->hdmatx != NULL))
{ {
if (HAL_DMA_Abort(hsai->hdmatx) != HAL_OK) /* No need to check the returned value of HAL_DMA_Abort. */
{ /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
/* If the DMA Tx errorCode is different from DMA No Transfer then return Error */ (void) HAL_DMA_Abort(hsai->hdmatx);
if (hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
{
status = HAL_ERROR;
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
}
}
} }
/* Abort the SAI Rx DMA Stream */ /* Abort the SAI Rx DMA Stream */
if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL)) if ((hsai->State == HAL_SAI_STATE_BUSY_RX) && (hsai->hdmarx != NULL))
{ {
if (HAL_DMA_Abort(hsai->hdmarx) != HAL_OK) /* No need to check the returned value of HAL_DMA_Abort. */
{ /* Only HAL_DMA_ERROR_NO_XFER can be returned in case of error and it's not an error for SAI. */
/* If the DMA Rx errorCode is different from DMA No Transfer then return Error */ (void) HAL_DMA_Abort(hsai->hdmarx);
if (hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
{
status = HAL_ERROR;
hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
}
}
} }
} }
@ -1584,6 +1569,12 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u
return HAL_ERROR; return HAL_ERROR;
} }
/* Enable the interrupts for error handling */
__HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
/* Enable SAI Rx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
/* Check if the SAI is already enabled */ /* Check if the SAI is already enabled */
if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U) if ((hsai->Instance->CR1 & SAI_xCR1_SAIEN) == 0U)
{ {
@ -1591,12 +1582,6 @@ HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, u
__HAL_SAI_ENABLE(hsai); __HAL_SAI_ENABLE(hsai);
} }
/* Enable the interrupts for error handling */
__HAL_SAI_ENABLE_IT(hsai, SAI_InterruptFlag(hsai, SAI_MODE_DMA));
/* Enable SAI Rx DMA Request */
hsai->Instance->CR1 |= SAI_xCR1_DMAEN;
/* Process Unlocked */ /* Process Unlocked */
__HAL_UNLOCK(hsai); __HAL_UNLOCK(hsai);
@ -1739,6 +1724,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
/* SAI AFSDET interrupt occurred ----------------------------------*/ /* SAI AFSDET interrupt occurred ----------------------------------*/
else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET)) else if (((itflags & SAI_FLAG_AFSDET) == SAI_FLAG_AFSDET) && ((itsources & SAI_IT_AFSDET) == SAI_IT_AFSDET))
{ {
/* Clear the SAI AFSDET flag */
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_AFSDET);
/* Change the SAI error code */ /* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET; hsai->ErrorCode |= HAL_SAI_ERROR_AFSDET;
@ -1802,6 +1790,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
/* SAI LFSDET interrupt occurred ----------------------------------*/ /* SAI LFSDET interrupt occurred ----------------------------------*/
else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET)) else if (((itflags & SAI_FLAG_LFSDET) == SAI_FLAG_LFSDET) && ((itsources & SAI_IT_LFSDET) == SAI_IT_LFSDET))
{ {
/* Clear the SAI LFSDET flag */
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_LFSDET);
/* Change the SAI error code */ /* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET; hsai->ErrorCode |= HAL_SAI_ERROR_LFSDET;
@ -1865,6 +1856,9 @@ void HAL_SAI_IRQHandler(SAI_HandleTypeDef *hsai)
/* SAI WCKCFG interrupt occurred ----------------------------------*/ /* SAI WCKCFG interrupt occurred ----------------------------------*/
else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG)) else if (((itflags & SAI_FLAG_WCKCFG) == SAI_FLAG_WCKCFG) && ((itsources & SAI_IT_WCKCFG) == SAI_IT_WCKCFG))
{ {
/* Clear the SAI WCKCFG flag */
__HAL_SAI_CLEAR_FLAG(hsai, SAI_FLAG_WCKCFG);
/* Change the SAI error code */ /* Change the SAI error code */
hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG; hsai->ErrorCode |= HAL_SAI_ERROR_WCKCFG;
@ -2125,20 +2119,16 @@ static HAL_StatusTypeDef SAI_InitI2S(SAI_HandleTypeDef *hsai, uint32_t protocol,
return HAL_ERROR; return HAL_ERROR;
} }
switch (protocol) if (protocol == SAI_I2S_STANDARD)
{ {
case SAI_I2S_STANDARD : hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW;
hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_LOW; hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT;
hsai->FrameInit.FSOffset = SAI_FS_BEFOREFIRSTBIT; }
break; else
case SAI_I2S_MSBJUSTIFIED : {
case SAI_I2S_LSBJUSTIFIED : /* SAI_I2S_MSBJUSTIFIED or SAI_I2S_LSBJUSTIFIED */
hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH; hsai->FrameInit.FSPolarity = SAI_FS_ACTIVE_HIGH;
hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT; hsai->FrameInit.FSOffset = SAI_FS_FIRSTBIT;
break;
default :
status = HAL_ERROR;
break;
} }
/* Frame definition */ /* Frame definition */
@ -2220,17 +2210,14 @@ static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol,
hsai->SlotInit.SlotNumber = nbslot; hsai->SlotInit.SlotNumber = nbslot;
hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL; hsai->SlotInit.SlotActive = SAI_SLOTACTIVE_ALL;
switch (protocol) if (protocol == SAI_PCM_SHORT)
{ {
case SAI_PCM_SHORT : hsai->FrameInit.ActiveFrameLength = 1;
hsai->FrameInit.ActiveFrameLength = 1; }
break; else
case SAI_PCM_LONG : {
hsai->FrameInit.ActiveFrameLength = 13; /* SAI_PCM_LONG */
break; hsai->FrameInit.ActiveFrameLength = 13;
default :
status = HAL_ERROR;
break;
} }
switch (datasize) switch (datasize)
@ -2745,13 +2732,15 @@ static void SAI_DMAAbort(DMA_HandleTypeDef *hdma)
* @} * @}
*/ */
/**
* @}
*/
#endif /* SAI1 */
#endif /* HAL_SAI_MODULE_ENABLED */ #endif /* HAL_SAI_MODULE_ENABLED */
/** /**
* @} * @}
*/ */
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

7
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_sai.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_sai.h
View File

@ -32,6 +32,8 @@ extern "C" {
* @{ * @{
*/ */
#if defined (SAI1)
/** @addtogroup SAI /** @addtogroup SAI
* @{ * @{
*/ */
@ -153,6 +155,7 @@ typedef struct
/** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition /** @defgroup SAI_Frame_Structure_definition SAI Frame Structure definition
* @brief SAI Frame Init structure definition * @brief SAI Frame Init structure definition
* @note For SPDIF and AC97 protocol, these parameters are not used (set by hardware).
* @{ * @{
*/ */
typedef struct typedef struct
@ -185,6 +188,8 @@ typedef struct
/** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition /** @defgroup SAI_Slot_Structure_definition SAI Slot Structure definition
* @brief SAI Block Slot Init Structure definition * @brief SAI Block Slot Init Structure definition
* @note For SPDIF protocol, these parameters are not used (set by hardware).
* @note For AC97 protocol, only SlotActive parameter is used (the others are set by hardware).
* @{ * @{
*/ */
typedef struct typedef struct
@ -948,6 +953,8 @@ uint32_t HAL_SAI_GetError(SAI_HandleTypeDef *hsai);
* @} * @}
*/ */
#endif /* SAI1 */
/** /**
* @} * @}
*/ */

4
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_sai_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_sai_ex.c
View File

@ -29,6 +29,8 @@
*/ */
#ifdef HAL_SAI_MODULE_ENABLED #ifdef HAL_SAI_MODULE_ENABLED
#if defined (SAI1)
/** @defgroup SAIEx SAIEx /** @defgroup SAIEx SAIEx
* @brief SAI Extended HAL module driver * @brief SAI Extended HAL module driver
* @{ * @{
@ -123,6 +125,8 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
* @} * @}
*/ */
#endif /* SAI1 */
#endif /* HAL_SAI_MODULE_ENABLED */ #endif /* HAL_SAI_MODULE_ENABLED */
/** /**
* @} * @}

5
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_sai_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_sai_ex.h
View File

@ -32,6 +32,8 @@ extern "C" {
* @{ * @{
*/ */
#if defined (SAI1)
/** @addtogroup SAIEx /** @addtogroup SAIEx
* @{ * @{
*/ */
@ -92,10 +94,11 @@ HAL_StatusTypeDef HAL_SAIEx_ConfigPdmMicDelay(SAI_HandleTypeDef *hsai, SAIEx_Pdm
* @} * @}
*/ */
#endif /* SAI1 */
/** /**
* @} * @}
*/ */
#ifdef __cplusplus #ifdef __cplusplus
} }
#endif #endif

11
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_smartcard.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard.c
View File

@ -917,7 +917,7 @@ HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsmartcard, uin
return HAL_TIMEOUT; return HAL_TIMEOUT;
} }
*ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF); *ptmpdata = (uint8_t)(hsmartcard->Instance->RDR & (uint8_t)0x00FF);
*ptmpdata++; ptmpdata++;
} }
/* At end of Rx process, restore hsmartcard->RxState to Ready */ /* At end of Rx process, restore hsmartcard->RxState to Ready */
@ -2287,6 +2287,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
SMARTCARD_ClockSourceTypeDef clocksource; SMARTCARD_ClockSourceTypeDef clocksource;
HAL_StatusTypeDef ret = HAL_OK; HAL_StatusTypeDef ret = HAL_OK;
const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U}; const uint16_t SMARTCARDPrescTable[12] = {1U, 2U, 4U, 6U, 8U, 10U, 12U, 16U, 32U, 64U, 128U, 256U};
uint32_t pclk;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance)); assert_param(IS_SMARTCARD_INSTANCE(hsmartcard->Instance));
@ -2341,7 +2342,7 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
/*-------------------------- USART GTPR Configuration ----------------------*/ /*-------------------------- USART GTPR Configuration ----------------------*/
tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos)); tmpreg = (hsmartcard->Init.Prescaler | ((uint32_t)hsmartcard->Init.GuardTime << USART_GTPR_GT_Pos));
MODIFY_REG(hsmartcard->Instance->GTPR, (USART_GTPR_GT | USART_GTPR_PSC), tmpreg); MODIFY_REG(hsmartcard->Instance->GTPR, (uint16_t)(USART_GTPR_GT | USART_GTPR_PSC), (uint16_t)tmpreg);
/*-------------------------- USART RTOR Configuration ----------------------*/ /*-------------------------- USART RTOR Configuration ----------------------*/
tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos); tmpreg = ((uint32_t)hsmartcard->Init.BlockLength << USART_RTOR_BLEN_Pos);
@ -2358,13 +2359,15 @@ static HAL_StatusTypeDef SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsmartcard
switch (clocksource) switch (clocksource)
{ {
case SMARTCARD_CLOCKSOURCE_PCLK2: case SMARTCARD_CLOCKSOURCE_PCLK2:
tmpreg = (uint16_t)(((HAL_RCC_GetPCLK2Freq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); pclk = HAL_RCC_GetPCLK2Freq();
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break; break;
case SMARTCARD_CLOCKSOURCE_HSI: case SMARTCARD_CLOCKSOURCE_HSI:
tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); tmpreg = (uint16_t)(((HSI_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break; break;
case SMARTCARD_CLOCKSOURCE_SYSCLK: case SMARTCARD_CLOCKSOURCE_SYSCLK:
tmpreg = (uint16_t)(((HAL_RCC_GetSysClockFreq() / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); pclk = HAL_RCC_GetSysClockFreq();
tmpreg = (uint16_t)(((pclk / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);
break; break;
case SMARTCARD_CLOCKSOURCE_LSE: case SMARTCARD_CLOCKSOURCE_LSE:
tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate); tmpreg = (uint16_t)(((uint16_t)(LSE_VALUE / SMARTCARDPrescTable[hsmartcard->Init.ClockPrescaler]) + (hsmartcard->Init.BaudRate / 2U)) / hsmartcard->Init.BaudRate);

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_smartcard.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard.h
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_smartcard_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard_ex.c
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_smartcard_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smartcard_ex.h
View File

16
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_smbus.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smbus.c
View File

@ -89,12 +89,12 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1 The compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback() Use Functions @ref HAL_SMBUS_RegisterCallback() or @ref HAL_SMBUS_RegisterAddrCallback()
to register an interrupt callback. to register an interrupt callback.
[..]
Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks: Function @ref HAL_SMBUS_RegisterCallback() allows to register following callbacks:
(+) MasterTxCpltCallback : callback for Master transmission end of transfer. (+) MasterTxCpltCallback : callback for Master transmission end of transfer.
(+) MasterRxCpltCallback : callback for Master reception end of transfer. (+) MasterRxCpltCallback : callback for Master reception end of transfer.
@ -106,9 +106,9 @@
(+) MspDeInitCallback : callback for Msp DeInit. (+) MspDeInitCallback : callback for Msp DeInit.
This function takes as parameters the HAL peripheral handle, the Callback ID This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
[..]
For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback. For specific callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_RegisterAddrCallback.
[..]
Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default Use function @ref HAL_SMBUS_UnRegisterCallback to reset a callback to the default
weak function. weak function.
@ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle, @ref HAL_SMBUS_UnRegisterCallback takes as parameters the HAL peripheral handle,
@ -122,9 +122,9 @@
(+) ErrorCallback : callback for error detection. (+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init. (+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit. (+) MspDeInitCallback : callback for Msp DeInit.
[..]
For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback. For callback AddrCallback use dedicated register callbacks : @ref HAL_SMBUS_UnRegisterAddrCallback.
[..]
By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET By default, after the @ref HAL_SMBUS_Init() and when the state is @ref HAL_I2C_STATE_RESET
all callbacks are set to the corresponding weak functions: all callbacks are set to the corresponding weak functions:
examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback(). examples @ref HAL_SMBUS_MasterTxCpltCallback(), @ref HAL_SMBUS_MasterRxCpltCallback().
@ -133,7 +133,7 @@
these callbacks are null (not registered beforehand). these callbacks are null (not registered beforehand).
If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit() If MspInit or MspDeInit are not null, the @ref HAL_SMBUS_Init()/ @ref HAL_SMBUS_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only. Callbacks can be registered/unregistered in @ref HAL_I2C_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state, in @ref HAL_I2C_STATE_READY or @ref HAL_I2C_STATE_RESET state,
@ -141,7 +141,7 @@
Then, the user first registers the MspInit/MspDeInit user callbacks Then, the user first registers the MspInit/MspDeInit user callbacks
using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit() using @ref HAL_SMBUS_RegisterCallback() before calling @ref HAL_SMBUS_DeInit()
or @ref HAL_SMBUS_Init() function. or @ref HAL_SMBUS_Init() function.
[..]
When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or When the compilation flag USE_HAL_SMBUS_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_smbus.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_smbus.h
View File

102
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_spi.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.c
View File

@ -65,16 +65,16 @@
Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback. Use Functions HAL_SPI_RegisterCallback() to register an interrupt callback.
Function HAL_SPI_RegisterCallback() allows to register following callbacks: Function HAL_SPI_RegisterCallback() allows to register following callbacks:
(+) TxCpltCallback : SPI Tx Completed callback (++) TxCpltCallback : SPI Tx Completed callback
(+) RxCpltCallback : SPI Rx Completed callback (++) RxCpltCallback : SPI Rx Completed callback
(+) TxRxCpltCallback : SPI TxRx Completed callback (++) TxRxCpltCallback : SPI TxRx Completed callback
(+) TxHalfCpltCallback : SPI Tx Half Completed callback (++) TxHalfCpltCallback : SPI Tx Half Completed callback
(+) RxHalfCpltCallback : SPI Rx Half Completed callback (++) RxHalfCpltCallback : SPI Rx Half Completed callback
(+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
(+) ErrorCallback : SPI Error callback (++) ErrorCallback : SPI Error callback
(+) AbortCpltCallback : SPI Abort callback (++) AbortCpltCallback : SPI Abort callback
(+) MspInitCallback : SPI Msp Init callback (++) MspInitCallback : SPI Msp Init callback
(+) MspDeInitCallback : SPI Msp DeInit callback (++) MspDeInitCallback : SPI Msp DeInit callback
This function takes as parameters the HAL peripheral handle, the Callback ID This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
@ -84,17 +84,18 @@
HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle, HAL_SPI_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
This function allows to reset following callbacks: This function allows to reset following callbacks:
(+) TxCpltCallback : SPI Tx Completed callback (++) TxCpltCallback : SPI Tx Completed callback
(+) RxCpltCallback : SPI Rx Completed callback (++) RxCpltCallback : SPI Rx Completed callback
(+) TxRxCpltCallback : SPI TxRx Completed callback (++) TxRxCpltCallback : SPI TxRx Completed callback
(+) TxHalfCpltCallback : SPI Tx Half Completed callback (++) TxHalfCpltCallback : SPI Tx Half Completed callback
(+) RxHalfCpltCallback : SPI Rx Half Completed callback (++) RxHalfCpltCallback : SPI Rx Half Completed callback
(+) TxRxHalfCpltCallback : SPI TxRx Half Completed callback (++) TxRxHalfCpltCallback : SPI TxRx Half Completed callback
(+) ErrorCallback : SPI Error callback (++) ErrorCallback : SPI Error callback
(+) AbortCpltCallback : SPI Abort callback (++) AbortCpltCallback : SPI Abort callback
(+) MspInitCallback : SPI Msp Init callback (++) MspInitCallback : SPI Msp Init callback
(+) MspDeInitCallback : SPI Msp DeInit callback (++) MspDeInitCallback : SPI Msp DeInit callback
[..]
By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET By default, after the HAL_SPI_Init() and when the state is HAL_SPI_STATE_RESET
all callbacks are set to the corresponding weak functions: all callbacks are set to the corresponding weak functions:
examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback(). examples HAL_SPI_MasterTxCpltCallback(), HAL_SPI_MasterRxCpltCallback().
@ -104,6 +105,7 @@
If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit() If MspInit or MspDeInit are not null, the HAL_SPI_Init()/ HAL_SPI_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only. Callbacks can be registered/unregistered in HAL_SPI_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered Exception done MspInit/MspDeInit functions that can be registered/unregistered
in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state, in HAL_SPI_STATE_READY or HAL_SPI_STATE_RESET state,
@ -112,7 +114,8 @@
using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit() using HAL_SPI_RegisterCallback() before calling HAL_SPI_DeInit()
or HAL_SPI_Init() function. or HAL_SPI_Init() function.
When The compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or [..]
When the compilation define USE_HAL_PPP_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registering feature is not available not defined, the callback registering feature is not available
and weak (surcharged) callbacks are used. and weak (surcharged) callbacks are used.
@ -269,8 +272,8 @@ static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_
*/ */
/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions /** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
* @brief Initialization and Configuration functions * @brief Initialization and Configuration functions
* *
@verbatim @verbatim
=============================================================================== ===============================================================================
##### Initialization and de-initialization functions ##### ##### Initialization and de-initialization functions #####
@ -535,7 +538,8 @@ __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
* @param pCallback pointer to the Callback function * @param pCallback pointer to the Callback function
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback) HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID,
pSPI_CallbackTypeDef pCallback)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
@ -745,8 +749,8 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca
*/ */
/** @defgroup SPI_Exported_Functions_Group2 IO operation functions /** @defgroup SPI_Exported_Functions_Group2 IO operation functions
* @brief Data transfers functions * @brief Data transfers functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### IO operation functions ##### ##### IO operation functions #####
@ -1872,7 +1876,8 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData,
} }
/* Enable the Tx DMA Stream/Channel */ /* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
hspi->TxXferCount))
{ {
/* Update SPI error code */ /* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@ -2014,7 +2019,8 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u
hspi->hdmarx->XferAbortCallback = NULL; hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */ /* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
hspi->RxXferCount))
{ {
/* Update SPI error code */ /* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@ -2181,7 +2187,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->hdmarx->XferAbortCallback = NULL; hspi->hdmarx->XferAbortCallback = NULL;
/* Enable the Rx DMA Stream/Channel */ /* Enable the Rx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount)) if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr,
hspi->RxXferCount))
{ {
/* Update SPI error code */ /* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@ -2202,7 +2209,8 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *
hspi->hdmatx->XferAbortCallback = NULL; hspi->hdmatx->XferAbortCallback = NULL;
/* Enable the Tx DMA Stream/Channel */ /* Enable the Tx DMA Stream/Channel */
if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount)) if (HAL_OK != HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR,
hspi->TxXferCount))
{ {
/* Update SPI error code */ /* Update SPI error code */
SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
@ -2242,11 +2250,12 @@ error :
* - Set handle State to READY * - Set handle State to READY
* @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed. * @note This procedure is executed in blocking mode : when exiting function, Abort is considered as completed.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
{ {
HAL_StatusTypeDef errorcode; HAL_StatusTypeDef errorcode;
__IO uint32_t count, resetcount; __IO uint32_t count;
__IO uint32_t resetcount;
/* Initialized local variable */ /* Initialized local variable */
errorcode = HAL_OK; errorcode = HAL_OK;
@ -2269,8 +2278,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (hspi->State != HAL_SPI_STATE_ABORT);
while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */ /* Reset Timeout Counter */
count = resetcount; count = resetcount;
} }
@ -2287,8 +2295,7 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (hspi->State != HAL_SPI_STATE_ABORT);
while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */ /* Reset Timeout Counter */
count = resetcount; count = resetcount;
} }
@ -2403,12 +2410,13 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi)
* @note This procedure is executed in Interrupt mode, meaning that abort procedure could be * @note This procedure is executed in Interrupt mode, meaning that abort procedure could be
* considered as completed only when user abort complete callback is executed (not when exiting function). * considered as completed only when user abort complete callback is executed (not when exiting function).
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi) HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
{ {
HAL_StatusTypeDef errorcode; HAL_StatusTypeDef errorcode;
uint32_t abortcplt ; uint32_t abortcplt ;
__IO uint32_t count, resetcount; __IO uint32_t count;
__IO uint32_t resetcount;
/* Initialized local variable */ /* Initialized local variable */
errorcode = HAL_OK; errorcode = HAL_OK;
@ -2432,8 +2440,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (hspi->State != HAL_SPI_STATE_ABORT);
while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */ /* Reset Timeout Counter */
count = resetcount; count = resetcount;
} }
@ -2450,8 +2457,7 @@ HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (hspi->State != HAL_SPI_STATE_ABORT);
while (hspi->State != HAL_SPI_STATE_ABORT);
/* Reset Timeout Counter */ /* Reset Timeout Counter */
count = resetcount; count = resetcount;
} }
@ -2667,7 +2673,8 @@ void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
} }
/* SPI in Error Treatment --------------------------------------------------*/ /* SPI in Error Treatment --------------------------------------------------*/
if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET)) if (((SPI_CHECK_FLAG(itflag, SPI_FLAG_MODF) != RESET) || (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
|| (SPI_CHECK_FLAG(itflag, SPI_FLAG_FRE) != RESET)) && (SPI_CHECK_IT_SOURCE(itsource, SPI_IT_ERR) != RESET))
{ {
/* SPI Overrun error interrupt occurred ----------------------------------*/ /* SPI Overrun error interrupt occurred ----------------------------------*/
if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET) if (SPI_CHECK_FLAG(itflag, SPI_FLAG_OVR) != RESET)
@ -4164,8 +4171,7 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */ /* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
@ -4206,8 +4212,7 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_TXEIE));
if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) if (SPI_EndRxTxTransaction(hspi, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)
{ {
@ -4238,8 +4243,7 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi)
break; break;
} }
count--; count--;
} } while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
while (HAL_IS_BIT_SET(hspi->Instance->CR2, SPI_CR2_RXNEIE));
/* Control the BSY flag */ /* Control the BSY flag */
if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_BSY, RESET, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK)

14
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_spi.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi.h
View File

@ -383,7 +383,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
#define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */
#define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */
#define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */
#define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR | SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL) #define SPI_FLAG_MASK (SPI_SR_RXNE | SPI_SR_TXE | SPI_SR_BSY | SPI_SR_CRCERR\
| SPI_SR_MODF | SPI_SR_OVR | SPI_SR_FRE | SPI_SR_FTLVL | SPI_SR_FRLVL)
/** /**
* @} * @}
*/ */
@ -433,7 +434,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
} while(0) } while(0)
#else #else
#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
#endif #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */
/** @brief Enable the specified SPI interrupts. /** @brief Enable the specified SPI interrupts.
* @param __HANDLE__ specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
@ -469,7 +470,8 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
* @arg SPI_IT_ERR: Error interrupt enable * @arg SPI_IT_ERR: Error interrupt enable
* @retval The new state of __IT__ (TRUE or FALSE). * @retval The new state of __IT__ (TRUE or FALSE).
*/ */
#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2\
& (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Check whether the specified SPI flag is set or not. /** @brief Check whether the specified SPI flag is set or not.
* @param __HANDLE__ specifies the SPI Handle. * @param __HANDLE__ specifies the SPI Handle.
@ -529,9 +531,9 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to
*/ */
#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \
do{ \ do{ \
__IO uint32_t tmpreg_fre = 0x00U; \ __IO uint32_t tmpreg_fre = 0x00U; \
tmpreg_fre = (__HANDLE__)->Instance->SR; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \
UNUSED(tmpreg_fre); \ UNUSED(tmpreg_fre); \
}while(0U) }while(0U)
/** @brief Enable the SPI peripheral. /** @brief Enable the SPI peripheral.

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_spi_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.c
View File

0
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_spi_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_spi_ex.h
View File

105
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_tim.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.c
View File

@ -98,18 +98,22 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1 The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
[..]
Use Function @ref HAL_TIM_RegisterCallback() to register a callback. Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
@ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle, @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
the Callback ID and a pointer to the user callback function. the Callback ID and a pointer to the user callback function.
[..]
Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
weak function. weak function.
@ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle, @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
[..]
These functions allow to register/unregister following callbacks: These functions allow to register/unregister following callbacks:
(+) Base_MspInitCallback : TIM Base Msp Init Callback. (+) Base_MspInitCallback : TIM Base Msp Init Callback.
(+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback. (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
@ -140,15 +144,18 @@
(+) BreakCallback : TIM Break Callback. (+) BreakCallback : TIM Break Callback.
(+) Break2Callback : TIM Break2 Callback. (+) Break2Callback : TIM Break2 Callback.
[..]
By default, after the Init and when the state is HAL_TIM_STATE_RESET By default, after the Init and when the state is HAL_TIM_STATE_RESET
all interrupt callbacks are set to the corresponding weak functions: all interrupt callbacks are set to the corresponding weak functions:
examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback(). examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
[..]
Exception done for MspInit and MspDeInit functions that are reset to the legacy weak Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
functionalities in the Init / DeInit only when these callbacks are null functionalities in the Init / DeInit only when these callbacks are null
(not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init / DeInit
keep and use the user MspInit / MspDeInit callbacks(registered beforehand) keep and use the user MspInit / MspDeInit callbacks(registered beforehand)
[..]
Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only. Callbacks can be registered / unregistered in HAL_TIM_STATE_READY state only.
Exception done MspInit / MspDeInit that can be registered / unregistered Exception done MspInit / MspDeInit that can be registered / unregistered
in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state, in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
@ -156,6 +163,7 @@ all interrupt callbacks are set to the corresponding weak functions:
In that case first register the MspInit/MspDeInit user callbacks In that case first register the MspInit/MspDeInit user callbacks
using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function. using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
[..]
When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@ -224,7 +232,7 @@ static void TIM_DMAPeriodElapsedHalfCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma); static void TIM_DMATriggerHalfCplt(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig); TIM_SlaveConfigTypeDef *sSlaveConfig);
/** /**
* @} * @}
*/ */
@ -235,8 +243,8 @@ static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
*/ */
/** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions /** @defgroup TIM_Exported_Functions_Group1 TIM Time Base functions
* @brief Time Base functions * @brief Time Base functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Time Base functions ##### ##### Time Base functions #####
@ -567,8 +575,8 @@ HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
*/ */
/** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions /** @defgroup TIM_Exported_Functions_Group2 TIM Output Compare functions
* @brief TIM Output Compare functions * @brief TIM Output Compare functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Output Compare functions ##### ##### TIM Output Compare functions #####
@ -937,7 +945,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
{ {
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
@ -1144,8 +1152,8 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
/** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions /** @defgroup TIM_Exported_Functions_Group3 TIM PWM functions
* @brief TIM PWM functions * @brief TIM PWM functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM PWM functions ##### ##### TIM PWM functions #####
@ -1722,8 +1730,8 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
*/ */
/** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions /** @defgroup TIM_Exported_Functions_Group4 TIM Input Capture functions
* @brief TIM Input Capture functions * @brief TIM Input Capture functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Input Capture functions ##### ##### TIM Input Capture functions #####
@ -2257,8 +2265,8 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
/** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions /** @defgroup TIM_Exported_Functions_Group5 TIM One Pulse functions
* @brief TIM One Pulse functions * @brief TIM One Pulse functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM One Pulse functions ##### ##### TIM One Pulse functions #####
@ -2571,8 +2579,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
*/ */
/** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions /** @defgroup TIM_Exported_Functions_Group6 TIM Encoder functions
* @brief TIM Encoder functions * @brief TIM Encoder functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Encoder functions ##### ##### TIM Encoder functions #####
@ -2624,8 +2632,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_Ini
assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode)); assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection)); assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC1Polarity));
assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity)); assert_param(IS_TIM_ENCODERINPUT_POLARITY(sConfig->IC2Polarity));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler)); assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter)); assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
@ -2974,7 +2982,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chan
* @param Length The length of data to be transferred from TIM peripheral to memory. * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
@ -3157,8 +3166,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
* @} * @}
*/ */
/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management /** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
* @brief TIM IRQ handler management * @brief TIM IRQ handler management
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### IRQ handler management ##### ##### IRQ handler management #####
@ -3371,8 +3380,8 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
*/ */
/** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions /** @defgroup TIM_Exported_Functions_Group8 TIM Peripheral Control functions
* @brief TIM Peripheral Control functions * @brief TIM Peripheral Control functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Peripheral Control functions ##### ##### Peripheral Control functions #####
@ -3746,9 +3755,14 @@ HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim,
* This parameter can be one of the following values: * This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @note To output a waveform with a minimum delay user can enable the fast
* mode by calling the @ref __HAL_TIM_ENABLE_OCxFAST macro. Then CCx
* output is forced in response to the edge detection on TIx input,
* without taking in account the comparison.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel) HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
uint32_t OutputChannel, uint32_t InputChannel)
{ {
TIM_OC_InitTypeDef temp1; TIM_OC_InitTypeDef temp1;
@ -3948,7 +3962,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */ /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3964,7 +3979,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */ /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3980,7 +3996,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */ /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -3996,7 +4013,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */ /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -4012,7 +4030,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */ /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_COMMUTATION], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -4028,7 +4047,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ; htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
/* Enable the DMA channel */ /* Enable the DMA channel */
if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK) if (HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer,
(uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8U) + 1U) != HAL_OK)
{ {
return HAL_ERROR; return HAL_ERROR;
} }
@ -4157,8 +4177,8 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t B
* @note This function should be used only when BurstLength is equal to DMA data transfer length. * @note This function should be used only when BurstLength is equal to DMA data transfer length.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t *BurstBuffer, uint32_t BurstLength) uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
@ -4484,7 +4504,7 @@ HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim,
/* When OCRef clear feature is used with ETR source, ETR prescaler must be off */ /* When OCRef clear feature is used with ETR source, ETR prescaler must be off */
if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1) if (sClearInputConfig->ClearInputPrescaler != TIM_CLEARINPUTPRESCALER_DIV1)
{ {
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim); __HAL_UNLOCK(htim);
return HAL_ERROR; return HAL_ERROR;
} }
@ -4805,9 +4825,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
htim->State = HAL_TIM_STATE_BUSY; htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{ {
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim); __HAL_UNLOCK(htim);
return HAL_ERROR; return HAL_ERROR;
} }
@ -4835,7 +4855,7 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveC
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig) TIM_SlaveConfigTypeDef *sSlaveConfig)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance)); assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
@ -4846,9 +4866,9 @@ HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim,
htim->State = HAL_TIM_STATE_BUSY; htim->State = HAL_TIM_STATE_BUSY;
if(TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK) if (TIM_SlaveTimer_SetConfig(htim, sSlaveConfig) != HAL_OK)
{ {
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
__HAL_UNLOCK(htim); __HAL_UNLOCK(htim);
return HAL_ERROR; return HAL_ERROR;
} }
@ -4938,8 +4958,8 @@ uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
*/ */
/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions /** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
* @brief TIM Callbacks functions * @brief TIM Callbacks functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### TIM Callbacks functions ##### ##### TIM Callbacks functions #####
@ -5143,7 +5163,8 @@ __weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
* @param pCallback pointer to the callback function * @param pCallback pointer to the callback function
* @retval status * @retval status
*/ */
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback) HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback)
{ {
HAL_StatusTypeDef status = HAL_OK; HAL_StatusTypeDef status = HAL_OK;
@ -5603,8 +5624,8 @@ HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_Ca
*/ */
/** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions /** @defgroup TIM_Exported_Functions_Group10 TIM Peripheral State functions
* @brief TIM Peripheral State functions * @brief TIM Peripheral State functions
* *
@verbatim @verbatim
============================================================================== ==============================================================================
##### Peripheral State functions ##### ##### Peripheral State functions #####
@ -6390,7 +6411,7 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
* @retval None * @retval None
*/ */
static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, static HAL_StatusTypeDef TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef *sSlaveConfig) TIM_SlaveConfigTypeDef *sSlaveConfig)
{ {
uint32_t tmpsmcr; uint32_t tmpsmcr;
uint32_t tmpccmr1; uint32_t tmpccmr1;

269
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_tim.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim.h
View File

@ -167,7 +167,7 @@ typedef struct
This parameter can be a value of @ref TIM_Encoder_Mode */ This parameter can be a value of @ref TIM_Encoder_Mode */
uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC1Selection; /*!< Specifies the input. uint32_t IC1Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */ This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -179,7 +179,7 @@ typedef struct
This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */ This parameter can be a value of @ref TIM_Encoder_Input_Polarity */
uint32_t IC2Selection; /*!< Specifies the input. uint32_t IC2Selection; /*!< Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */ This parameter can be a value of @ref TIM_Input_Capture_Selection */
@ -235,7 +235,12 @@ typedef struct
uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection uint32_t MasterOutputTrigger2; /*!< Trigger output2 (TRGO2) selection
This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */ This parameter can be a value of @ref TIM_Master_Mode_Selection_2 */
uint32_t MasterSlaveMode; /*!< Master/slave mode selection uint32_t MasterSlaveMode; /*!< Master/slave mode selection
This parameter can be a value of @ref TIM_Master_Slave_Mode */ This parameter can be a value of @ref TIM_Master_Slave_Mode
@note When the Master/slave mode is enabled, the effect of
an event on the trigger input (TRGI) is delayed to allow a
perfect synchronization between the current timer and its
slaves (through TRGO). It is not mandatory in case of timer
synchronization mode. */
} TIM_MasterConfigTypeDef; } TIM_MasterConfigTypeDef;
/** /**
@ -611,6 +616,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @} * @}
*/ */
/** @defgroup TIM_Encoder_Input_Polarity TIM Encoder Input Polarity
* @{
*/
#define TIM_ENCODERINPUTPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Encoder input with rising edge polarity */
#define TIM_ENCODERINPUTPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Encoder input with falling edge polarity */
/**
* @}
*/
/** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
* @{ * @{
*/ */
@ -1119,15 +1133,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE(__HANDLE__) \ #define __HAL_TIM_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \ { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \ { \
(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
} \ } \
} \ } \
} while(0) } while(0)
/** /**
* @brief Disable the TIM main Output. * @brief Disable the TIM main Output.
@ -1136,15 +1150,15 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/ */
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \ #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \ do { \
if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \ if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0UL) \
{ \ { \
if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \ if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0UL) \
{ \ { \
(__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \ (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
} \ } \
} \ } \
} while(0) } while(0)
/** /**
* @brief Disable the TIM main Output. * @brief Disable the TIM main Output.
@ -1279,7 +1293,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
* @arg TIM_IT_BREAK: Break interrupt * @arg TIM_IT_BREAK: Break interrupt
* @retval The state of TIM_IT (SET or RESET). * @retval The state of TIM_IT (SET or RESET).
*/ */
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) \
== (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits. /** @brief Clear the TIM interrupt pending bits.
* @param __HANDLE__ TIM handle * @param __HANDLE__ TIM handle
@ -1327,8 +1342,7 @@ mode.
* @param __HANDLE__ TIM handle. * @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT) * @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/ */
#define __HAL_TIM_GET_COUNTER(__HANDLE__) \ #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
((__HANDLE__)->Instance->CNT)
/** /**
* @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function. * @brief Set the TIM Autoreload Register value on runtime without calling another time any Init function.
@ -1337,18 +1351,17 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \ do{ \
(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \ (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0) } while(0)
/** /**
* @brief Get the TIM Autoreload Register value on runtime. * @brief Get the TIM Autoreload Register value on runtime.
* @param __HANDLE__ TIM handle. * @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR) * @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/ */
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) \ #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
((__HANDLE__)->Instance->ARR)
/** /**
* @brief Set the TIM Clock Division value on runtime without calling another time any Init function. * @brief Set the TIM Clock Division value on runtime without calling another time any Init function.
@ -1361,11 +1374,11 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
do{ \ do{ \
(__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \ (__HANDLE__)->Instance->CR1 &= (~TIM_CR1_CKD); \
(__HANDLE__)->Instance->CR1 |= (__CKD__); \ (__HANDLE__)->Instance->CR1 |= (__CKD__); \
(__HANDLE__)->Init.ClockDivision = (__CKD__); \ (__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0) } while(0)
/** /**
* @brief Get the TIM Clock Division value on runtime. * @brief Get the TIM Clock Division value on runtime.
@ -1375,8 +1388,7 @@ mode.
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
* @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/ */
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) \ #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/** /**
* @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function. * @brief Set the TIM Input Capture prescaler on runtime without calling another time HAL_TIM_IC_ConfigChannel() function.
@ -1396,10 +1408,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
do{ \ do{ \
TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
} while(0) } while(0)
/** /**
* @brief Get the TIM Input Capture prescaler on runtime. * @brief Get the TIM Input Capture prescaler on runtime.
@ -1437,12 +1449,12 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4 = (__COMPARE__)) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5 = (__COMPARE__)) :\
((__HANDLE__)->Instance->CCR6 = (__COMPARE__))) ((__HANDLE__)->Instance->CCR6 = (__COMPARE__)))
/** /**
* @brief Get the TIM Capture Compare Register value on runtime. * @brief Get the TIM Capture Compare Register value on runtime.
@ -1458,12 +1470,12 @@ mode.
* @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy) * @retval 16-bit or 32-bit value of the capture/compare register (TIMx_CCRy)
*/ */
#define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCR1) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCR2) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCR3) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCR4) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCR5) :\
((__HANDLE__)->Instance->CCR6)) ((__HANDLE__)->Instance->CCR6))
/** /**
* @brief Set the TIM Output compare preload. * @brief Set the TIM Output compare preload.
@ -1479,12 +1491,12 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_ENABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE)) ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6PE))
/** /**
* @brief Reset the TIM Output compare preload. * @brief Reset the TIM Output compare preload.
@ -1500,12 +1512,62 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \ #define __HAL_TIM_DISABLE_OCxPRELOAD(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC1PE) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1PE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_OC2PE) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2PE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC3PE) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3PE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_OC4PE) :\ ((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4PE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC5PE) :\ ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5PE) :\
((__HANDLE__)->Instance->CCMR3 &= (uint16_t)~TIM_CCMR3_OC6PE)) ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6PE))
/**
* @brief Enable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is enabled an active edge on the trigger input acts
* like a compare match on CCx output. Delay to sample the trigger
* input and to activate CCx output is reduced to 3 clock cycles.
* @note Fast mode acts only if the channel is configured in PWM1 or PWM2 mode.
* @retval None
*/
#define __HAL_TIM_ENABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 |= TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 |= TIM_CCMR3_OC6FE))
/**
* @brief Disable fast mode for a given channel.
* @param __HANDLE__ TIM handle.
* @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
* @note When fast mode is disabled CCx output behaves normally depending
* on counter and CCRx values even when the trigger is ON. The minimum
* delay to activate CCx output when an active edge occurs on the
* trigger input is 5 clock cycles.
* @retval None
*/
#define __HAL_TIM_DISABLE_OCxFAST(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE) :\
((__CHANNEL__) == TIM_CHANNEL_4) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE) :\
((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC5FE) :\
((__HANDLE__)->Instance->CCMR3 &= ~TIM_CCMR3_OC6FE))
/** /**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register. * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1515,8 +1577,7 @@ mode.
* enabled) * enabled)
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_ENABLE(__HANDLE__) \ #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
((__HANDLE__)->Instance->CR1|= TIM_CR1_URS)
/** /**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register. * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register.
@ -1529,8 +1590,7 @@ mode.
* _ Update generation through the slave mode controller * _ Update generation through the slave mode controller
* @retval None * @retval None
*/ */
#define __HAL_TIM_URS_DISABLE(__HANDLE__) \ #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
((__HANDLE__)->Instance->CR1&=~TIM_CR1_URS)
/** /**
* @brief Set the TIM Capture x input polarity on runtime. * @brief Set the TIM Capture x input polarity on runtime.
@ -1548,10 +1608,10 @@ mode.
* @retval None * @retval None
*/ */
#define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
do{ \ do{ \
TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
}while(0) }while(0)
/** /**
* @} * @}
@ -1635,6 +1695,9 @@ mode.
#define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \ #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
((__STATE__) == TIM_OCNIDLESTATE_RESET)) ((__STATE__) == TIM_OCNIDLESTATE_RESET))
#define IS_TIM_ENCODERINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_RISING) || \
((__POLARITY__) == TIM_ENCODERINPUTPOLARITY_FALLING))
#define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
@ -1853,28 +1916,28 @@ mode.
((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER)) ((__TRIGGER__) == TIM_SLAVEMODE_COMBINED_RESETTRIGGER))
#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U))) ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8U)))
#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC) :\
((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) ((__HANDLE__)->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC))
#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\
((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U)))) ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U))))
#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP))) ((__HANDLE__)->Instance->CCER &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP)))
/** /**
* @} * @}
@ -2012,7 +2075,8 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel
HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
/* Non-Blocking mode: DMA */ /* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1,
uint32_t *pData2, uint16_t Length);
HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
/** /**
* @} * @}
@ -2036,17 +2100,19 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel); HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef *sConfig, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig, uint32_t OutputChannel, uint32_t InputChannel); HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef *sConfig,
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig, uint32_t Channel); uint32_t OutputChannel, uint32_t InputChannel);
HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef *sClearInputConfig,
uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig); HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef *sClockSourceConfig);
HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef *sSlaveConfig);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
uint32_t *BurstBuffer, uint32_t BurstLength); uint32_t BurstRequestSrc, uint32_t *BurstBuffer, uint32_t BurstLength);
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -2072,7 +2138,8 @@ void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
/* Callbacks Register/UnRegister functions ***********************************/ /* Callbacks Register/UnRegister functions ***********************************/
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1) #if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID,
pTIM_CallbackTypeDef pCallback);
HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID); HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
@ -2102,8 +2169,8 @@ HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions /** @defgroup TIM_Private_Functions TIM Private Functions
* @{ * @{
*/ */
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure); void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter); void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config); void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
@ -2122,8 +2189,8 @@ void TIM_ResetCallback(TIM_HandleTypeDef *htim);
#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/** /**
* @} * @}
*/ */
/* End of private functions --------------------------------------------------*/ /* End of private functions --------------------------------------------------*/
/** /**

74
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_tim_ex.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.c
View File

@ -74,7 +74,7 @@
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
****************************************************************************** ******************************************************************************
*/ */
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal.h" #include "stm32wbxx_hal.h"
@ -1478,7 +1478,8 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1533,7 +1534,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1589,7 +1591,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource) HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
uint32_t CommutationSource)
{ {
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance)); assert_param(IS_TIM_COMMUTATION_EVENT_INSTANCE(htim->Instance));
@ -1644,7 +1647,7 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
uint32_t tmpsmcr; uint32_t tmpsmcr;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_SYNCHRO_INSTANCE(htim->Instance)); assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger)); assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode)); assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
@ -1677,16 +1680,19 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
/* Select the TRGO source */ /* Select the TRGO source */
tmpcr2 |= sMasterConfig->MasterOutputTrigger; tmpcr2 |= sMasterConfig->MasterOutputTrigger;
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx CR2 */ /* Update TIMx CR2 */
htim->Instance->CR2 = tmpcr2; htim->Instance->CR2 = tmpcr2;
/* Update TIMx SMCR */ if (IS_TIM_SLAVE_INSTANCE(htim->Instance))
htim->Instance->SMCR = tmpsmcr; {
/* Reset the MSM Bit */
tmpsmcr &= ~TIM_SMCR_MSM;
/* Set master mode */
tmpsmcr |= sMasterConfig->MasterSlaveMode;
/* Update TIMx SMCR */
htim->Instance->SMCR = tmpsmcr;
}
/* Change the htim state */ /* Change the htim state */
htim->State = HAL_TIM_STATE_READY; htim->State = HAL_TIM_STATE_READY;
@ -1702,6 +1708,9 @@ HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
* @param htim TIM handle * @param htim TIM handle
* @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfigTypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral. * contains the BDTR Register configuration information for the TIM peripheral.
* @note Interrupts can be generated when an active level is detected on the
* break input, the break 2 input or the system break input. Break
* interrupt can be enabled by calling the @ref __HAL_TIM_ENABLE_IT macro.
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
@ -1774,10 +1783,10 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
{ {
uint32_t tmporx; uint32_t tmporx;
uint32_t bkin_enable_mask = 0U; uint32_t bkin_enable_mask;
uint32_t bkin_polarity_mask = 0U; uint32_t bkin_polarity_mask;
uint32_t bkin_enable_bitpos = 0U; uint32_t bkin_enable_bitpos;
uint32_t bkin_polarity_bitpos = 0U; uint32_t bkin_polarity_bitpos;
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance)); assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
@ -1794,10 +1803,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
case TIM_BREAKINPUTSOURCE_BKIN: case TIM_BREAKINPUTSOURCE_BKIN:
{ {
bkin_enable_mask = TIM1_AF1_BKINE; bkin_enable_mask = TIM1_AF1_BKINE;
bkin_enable_bitpos = TIM1_AF1_BKINE_Pos;
bkin_polarity_mask = TIM1_AF1_BKINP; bkin_polarity_mask = TIM1_AF1_BKINP;
bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos; bkin_polarity_bitpos = TIM1_AF1_BKINP_Pos;
break; break;
} }
#if defined(COMP1) && defined(COMP2)
case TIM_BREAKINPUTSOURCE_COMP1: case TIM_BREAKINPUTSOURCE_COMP1:
{ {
bkin_enable_mask = TIM1_AF1_BKCMP1E; bkin_enable_mask = TIM1_AF1_BKCMP1E;
@ -1814,9 +1825,16 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos; bkin_polarity_bitpos = TIM1_AF1_BKCMP2P_Pos;
break; break;
} }
#endif /* COMP1 && COMP2 */
default: default:
{
bkin_enable_mask = 0U;
bkin_polarity_mask = 0U;
bkin_enable_bitpos = 0U;
bkin_polarity_bitpos = 0U;
break; break;
}
} }
switch (BreakInput) switch (BreakInput)
@ -1875,29 +1893,29 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
* @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1 * @arg TIM_TIM1_ETR_ADC1_AWD1: TIM1_ETR is connected to ADC1 AWD1
* @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2 * @arg TIM_TIM1_ETR_ADC1_AWD2: TIM1_ETR is connected to ADC1 AWD2
* @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3 * @arg TIM_TIM1_ETR_ADC1_AWD3: TIM1_ETR is connected to ADC1 AWD3
* @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output * @arg TIM_TIM1_ETR_COMP1: TIM1_ETR is connected to COMP1 output (*)
* @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output * @arg TIM_TIM1_ETR_COMP2: TIM1_ETR is connected to COMP2 output (*)
* field2 can have the following values: * field2 can have the following values:
* @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to I/O * @arg TIM_TIM1_TI1_GPIO: TIM1 TI1 is connected to I/O
* @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output * @arg TIM_TIM1_TI1_COMP1: TIM1 TI1 is connected to COMP1 output (*)
* *
* For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3): * For TIM2, the parameter is a combination of 3 fields (field1 | field2 | field3):
* *
* field1 can have the following values: * field1 can have the following values:
* @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1 * @arg TIM_TIM2_ITR1_NONE: No internal trigger on TIM2_ITR1
* @arg TIM_TIM2_ITR1_USB: TIM2_ITR1 is connected to USB SOF * @arg TIM_TIM2_ITR1_USB: TIM2_ITR1 is connected to USB SOF (*)
* *
* field2 can have the following values: * field2 can have the following values:
* @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to I/O * @arg TIM_TIM2_ETR_GPIO: TIM2_ETR is connected to I/O
* @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE * @arg TIM_TIM2_ETR_LSE: TIM2_ETR is connected to LSE
* @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output * @arg TIM_TIM2_ETR_COMP1: TIM2_ETR is connected to COMP1 output (*)
* @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output * @arg TIM_TIM2_ETR_COMP2: TIM2_ETR is connected to COMP2 output (*)
* *
* field3 can have the following values: * field3 can have the following values:
* @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to I/O * @arg TIM_TIM2_TI4_GPIO: TIM2 TI4 is connected to I/O
* @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output * @arg TIM_TIM2_TI4_COMP1: TIM2 TI4 is connected to COMP1 output (*)
* @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output * @arg TIM_TIM2_TI4_COMP2: TIM2 TI4 is connected to COMP2 output (*)
* @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output * @arg TIM_TIM2_TI4_COMP1_COMP2: TIM2 TI4 is connected to logical OR between COMP1 and COMP2 output (*)
* *
* For TIM16, the parameter can have the following values: * For TIM16, the parameter can have the following values:
* @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to I/O * @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to I/O
@ -1907,10 +1925,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
* *
* For TIM17, the parameter can have the following values: * For TIM17, the parameter can have the following values:
* @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to I/O * @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to I/O
* @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (contraints: MSI clock < 1/4 TIM APB clock) * @arg TIM_TIM17_TI1_MSI: TIM17 TI1 is connected to MSI (constraint: MSI clock < 1/4 TIM APB clock)
* @arg TIM_TIM17_TI1_HSE: TIM17 TI1 is connected to HSE div 32 * @arg TIM_TIM17_TI1_HSE: TIM17 TI1 is connected to HSE div 32
* @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO * @arg TIM_TIM17_TI1_MCO: TIM17 TI1 is connected to MCO
* *
* (*) Value not defined in all devices.
*
* @retval HAL status * @retval HAL status
*/ */
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap) HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
@ -2110,7 +2130,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
*/ */
/* Private functions ---------------------------------------------------------*/ /* Private functions ---------------------------------------------------------*/
/** @addtogroup TIMEx_Private_Functions /** @defgroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */

75
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_tim_ex.h → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tim_ex.h
View File

@ -91,24 +91,40 @@ TIMEx_BreakInputConfigTypeDef;
#define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */ #define TIM_TIM1_ETR_ADC1_AWD1 TIM1_OR_ETR_ADC1_RMP_0 /* !< TIM1_ETR is connected to ADC1 AWD1 */
#define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */ #define TIM_TIM1_ETR_ADC1_AWD2 TIM1_OR_ETR_ADC1_RMP_1 /* !< TIM1_ETR is connected to ADC1 AWD2 */
#define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */ #define TIM_TIM1_ETR_ADC1_AWD3 (TIM1_OR_ETR_ADC1_RMP_0 | TIM1_OR_ETR_ADC1_RMP_1) /* !< TIM1_ETR is connected to ADC1 AWD3 */
#if defined(COMP1)
#define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */ #define TIM_TIM1_ETR_COMP1 TIM1_AF1_ETRSEL_0 /* !< TIM1_ETR is connected to COMP1 output */
#endif /* COMP1 */
#if defined(COMP2)
#define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */ #define TIM_TIM1_ETR_COMP2 TIM1_AF1_ETRSEL_1 /* !< TIM1_ETR is connected to COMP2 output */
#endif /* COMP2 */
#define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */ #define TIM_TIM1_TI1_GPIO 0x00000000U /* !< TIM1 Input capture 1 is connected to I/0 */
#define TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */ #define TIM_TIM1_TI1_COMP1 TIM1_OR_TI1_RMP /* !< TIM1 Input capture 1is connected to COMP1 OUT */
#define TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */ #define TIM_TIM2_ITR_NC 0x00000000U /* !< TIM2 Internal trigger ITR is not connected */
#if defined(USB)
#define TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */ #define TIM_TIM2_ITR_USB TIM2_OR_ITR1_RMP /* !< TIM2 Internal trigger ITR is connected to USBFS SOF */
#endif /* USB */
#define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */ #define TIM_TIM2_ETR_GPIO 0x00000000U /* !< TIM2 External trigger ETR is connected to I/O */
#define TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */ #define TIM_TIM2_ETR_LSE TIM2_OR_ETR_RMP /* !< TIM2 External trigger ETR is connected to LSE */
#if defined(COMP1)
#define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */ #define TIM_TIM2_ETR_COMP1 TIM2_AF1_ETRSEL_0 /* !< TIM2_ETR is connected to COMP1 output */
#endif /* COMP1 */
#if defined(COMP2)
#define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */ #define TIM_TIM2_ETR_COMP2 TIM2_AF1_ETRSEL_1 /* !< TIM2_ETR is connected to COMP2 output */
#endif /* COMP2 */
#define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */ #define TIM_TIM2_TI4_GPIO 0x00000000U /* !< TIM2_TI4 is connected to I/O */
#if defined(COMP1)
#define TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */ #define TIM_TIM2_TI4_COMP1 TIM2_OR_TI4_RMP_0 /* !< TIM2_TI4 is connected to COMP1 OUT */
#endif /* COMP1 */
#if defined(COMP2)
#define TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */ #define TIM_TIM2_TI4_COMP2 TIM2_OR_TI4_RMP_1 /* !< TIM2_TI4 is connected to COMP1 OUT */
#endif /* COMP2 */
#if defined(COMP1) && defined(COMP2)
#define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */ #define TIM_TIM2_TI4_COMP1_COMP2 (TIM2_OR_TI4_RMP_0 | TIM2_OR_TI4_RMP_1) /* !< TIM2_TI4 is connected to COMP1 and COMP2 OUT */
#endif /* COMP1 && COMP2 */
#define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */ #define TIM_TIM16_TI1_GPIO 0x00000000U /* !< TIM16_TI1 is connected to I/O */
#define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */ #define TIM_TIM16_TI1_LSI TIM16_OR_TI1_RMP_0 /* !< TIM16_TI1 is connected to LSI Clock */
@ -136,8 +152,12 @@ TIMEx_BreakInputConfigTypeDef;
* @{ * @{
*/ */
#define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */ #define TIM_BREAKINPUTSOURCE_BKIN 0x00000001U /* !< An external source (GPIO) is connected to the BKIN pin */
#if defined(COMP1)
#define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP1 0x00000002U /* !< The COMP1 output is connected to the break input */
#endif /* COMP1 */
#if defined(COMP2)
#define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */ #define TIM_BREAKINPUTSOURCE_COMP2 0x00000004U /* !< The COMP2 output is connected to the break input */
#endif /* COMP2 */
/** /**
* @} * @}
*/ */
@ -189,10 +209,15 @@ TIMEx_BreakInputConfigTypeDef;
(((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \ (((__BREAKINPUT__) == TIM_BREAKINPUT_BRK) || \
((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2)) ((__BREAKINPUT__) == TIM_BREAKINPUT_BRK2))
#if defined(COMP1) && defined(COMP2)
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \ #define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \ (((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \ ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP1) || \
((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2)) ((__SOURCE__) == TIM_BREAKINPUTSOURCE_COMP2))
#else
#define IS_TIM_BREAKINPUTSOURCE(__SOURCE__) \
(((__SOURCE__) == TIM_BREAKINPUTSOURCE_BKIN))
#endif
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \ #define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) \
(((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \ (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
@ -213,9 +238,9 @@ TIMEx_BreakInputConfigTypeDef;
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions /** @addtogroup TIMEx_Exported_Functions_Group1 Extended Timer Hall Sensor functions
* @brief Timer Hall Sensor functions * @brief Timer Hall Sensor functions
* @{ * @{
*/ */
/* Timer Hall Sensor functions **********************************************/ /* Timer Hall Sensor functions **********************************************/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef *sConfig);
HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim); HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim);
@ -237,9 +262,9 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim);
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions /** @addtogroup TIMEx_Exported_Functions_Group2 Extended Timer Complementary Output Compare functions
* @brief Timer Complementary Output Compare functions * @brief Timer Complementary Output Compare functions
* @{ * @{
*/ */
/* Timer Complementary Output Compare functions *****************************/ /* Timer Complementary Output Compare functions *****************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -257,9 +282,9 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions /** @addtogroup TIMEx_Exported_Functions_Group3 Extended Timer Complementary PWM functions
* @brief Timer Complementary PWM functions * @brief Timer Complementary PWM functions
* @{ * @{
*/ */
/* Timer Complementary PWM functions ****************************************/ /* Timer Complementary PWM functions ****************************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel); HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
@ -276,9 +301,9 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions /** @addtogroup TIMEx_Exported_Functions_Group4 Extended Timer Complementary One Pulse functions
* @brief Timer Complementary One Pulse functions * @brief Timer Complementary One Pulse functions
* @{ * @{
*/ */
/* Timer Complementary One Pulse functions **********************************/ /* Timer Complementary One Pulse functions **********************************/
/* Blocking mode: Polling */ /* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
@ -292,16 +317,22 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
*/ */
/** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions /** @addtogroup TIMEx_Exported_Functions_Group5 Extended Peripheral Control functions
* @brief Peripheral Control functions * @brief Peripheral Control functions
* @{ * @{
*/ */
/* Extended Control functions ************************************************/ /* Extended Control functions ************************************************/
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef *sMasterConfig); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim, TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig); HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger,
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput, TIMEx_BreakInputConfigTypeDef *sBreakInputConfig); uint32_t CommutationSource);
HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim,
TIM_MasterConfigTypeDef *sMasterConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
TIM_BreakDeadTimeConfigTypeDef *sBreakDeadTimeConfig);
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput,
TIMEx_BreakInputConfigTypeDef *sBreakInputConfig);
HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels); HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Channels);
HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
/** /**
@ -337,7 +368,7 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim);
/* End of exported functions -------------------------------------------------*/ /* End of exported functions -------------------------------------------------*/
/* Private functions----------------------------------------------------------*/ /* Private functions----------------------------------------------------------*/
/** @defgroup TIMEx_Private_Functions TIMEx Private Functions /** @addtogroup TIMEx_Private_Functions TIMEx Private Functions
* @{ * @{
*/ */
void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma); void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma);

14
targets/TARGET_STM/TARGET_STM32WB/device/stm32wbxx_hal_tsc.c → targets/TARGET_STM/TARGET_STM32WB/STM32Cube_FW/STM32WBxx_HAL_Driver/stm32wbxx_hal_tsc.c
View File

@ -79,28 +79,34 @@
*** Callback registration *** *** Callback registration ***
============================================= =============================================
[..]
The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1 The compilation flag USE_HAL_TSC_REGISTER_CALLBACKS when set to 1
allows the user to configure dynamically the driver callbacks. allows the user to configure dynamically the driver callbacks.
Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback. Use Functions @ref HAL_TSC_RegisterCallback() to register an interrupt callback.
[..]
Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks: Function @ref HAL_TSC_RegisterCallback() allows to register following callbacks:
(+) ConvCpltCallback : callback for conversion complete process. (+) ConvCpltCallback : callback for conversion complete process.
(+) ErrorCallback : callback for error detection. (+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init. (+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit. (+) MspDeInitCallback : callback for Msp DeInit.
[..]
This function takes as parameters the HAL peripheral handle, the Callback ID This function takes as parameters the HAL peripheral handle, the Callback ID
and a pointer to the user callback function. and a pointer to the user callback function.
[..]
Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default Use function @ref HAL_TSC_UnRegisterCallback to reset a callback to the default
weak function. weak function.
@ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle, @ref HAL_TSC_UnRegisterCallback takes as parameters the HAL peripheral handle,
and the Callback ID. and the Callback ID.
[..]
This function allows to reset following callbacks: This function allows to reset following callbacks:
(+) ConvCpltCallback : callback for conversion complete process. (+) ConvCpltCallback : callback for conversion complete process.
(+) ErrorCallback : callback for error detection. (+) ErrorCallback : callback for error detection.
(+) MspInitCallback : callback for Msp Init. (+) MspInitCallback : callback for Msp Init.
(+) MspDeInitCallback : callback for Msp DeInit. (+) MspDeInitCallback : callback for Msp DeInit.
[..]
By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET By default, after the @ref HAL_TSC_Init() and when the state is @ref HAL_TSC_STATE_RESET
all callbacks are set to the corresponding weak functions: all callbacks are set to the corresponding weak functions:
examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback(). examples @ref HAL_TSC_ConvCpltCallback(), @ref HAL_TSC_ErrorCallback().
@ -110,6 +116,7 @@
If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit() If MspInit or MspDeInit are not null, the @ref HAL_TSC_Init()/ @ref HAL_TSC_DeInit()
keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
[..]
Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only. Callbacks can be registered/unregistered in @ref HAL_TSC_STATE_READY state only.
Exception done MspInit/MspDeInit functions that can be registered/unregistered Exception done MspInit/MspDeInit functions that can be registered/unregistered
in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state, in @ref HAL_TSC_STATE_READY or @ref HAL_TSC_STATE_RESET state,
@ -118,6 +125,7 @@
using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit() using @ref HAL_TSC_RegisterCallback() before calling @ref HAL_TSC_DeInit()
or @ref HAL_TSC_Init() function. or @ref HAL_TSC_Init() function.
[..]
When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or When the compilation flag USE_HAL_TSC_REGISTER_CALLBACKS is set to 0 or
not defined, the callback registration feature is not available and all callbacks not defined, the callback registration feature is not available and all callbacks
are set to the corresponding weak functions. are set to the corresponding weak functions.
@ -171,11 +179,11 @@
****************************************************************************** ******************************************************************************
* @attention * @attention
* *
* <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
* All rights reserved.</center></h2> * All rights reserved.</center></h2>
* *
* This software component is licensed by ST under BSD 3-Clause license, * This software component is licensed by ST under BSD 3-Clause license,
* the "License"; You may not use this file except in compliance with the * the "License"; You may not use this file except in compliance with the
* License. You may obtain a copy of the License at: * License. You may obtain a copy of the License at:
* opensource.org/licenses/BSD-3-Clause * opensource.org/licenses/BSD-3-Clause
* *
@ -185,6 +193,7 @@
/* Includes ------------------------------------------------------------------*/ /* Includes ------------------------------------------------------------------*/
#include "stm32wbxx_hal.h" #include "stm32wbxx_hal.h"
#if defined(TSC)
/** @addtogroup STM32WBxx_HAL_Driver /** @addtogroup STM32WBxx_HAL_Driver
* @{ * @{
*/ */
@ -1109,4 +1118,5 @@ static uint32_t TSC_extract_groups(uint32_t iomask)
* @} * @}
*/ */
#endif /* TSC */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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