mirror of https://github.com/ARMmbed/mbed-os.git
Fixed a bug of serial interrupt
I fixed a bug of serial interrupt as below. Serial TX/RX interrupt was not occur when TX/RX end.pull/703/head
Masao Hamanaka
parent
e53ae9e840
commit
cde105eaa5
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@ -142,7 +142,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
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b0 SPB2DT - Serial port break data : High-level */
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//obj->uart->SCSPTR |= 0x0000u;
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obj->uart->SCSCR = 0x0030;
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obj->uart->SCSCR = 0x00F0;
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// pinout the chosen uart
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pinmap_pinout(tx, PinMap_UART_TX);
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@ -156,10 +156,11 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
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case P_SCIF4: obj->index = 4; break;
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case P_SCIF5: obj->index = 5; break;
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case P_SCIF6: obj->index = 6; break;
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case P_SCIF7: obj->index = 7; break;
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}
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uart_data[obj->index].sw_rts.pin = NC;
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uart_data[obj->index].sw_cts.pin = NC;
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serial_set_flow_control(obj, FlowControlNone, NC, NC);
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// serial_set_flow_control(obj, FlowControlNone, NC, NC);
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is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
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@ -219,11 +220,105 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
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* INTERRUPTS HANDLING
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******************************************************************************/
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void uart0_irq() {irq_handler(0, RxIrq);//dummy call
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static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
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uint16_t dummy_read;
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/* Clear TDFE */
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switch (index) {
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case 0:
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dummy_read = SCFSR_0;
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SCFSR_0 = (dummy_read & ~0x0060);
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break;
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case 1:
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dummy_read = SCFSR_1;
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SCFSR_1 = (dummy_read & ~0x0060);
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break;
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case 2:
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dummy_read = SCFSR_2;
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SCFSR_2 = (dummy_read & ~0x0060);
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break;
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case 3:
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dummy_read = SCFSR_3;
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SCFSR_3 = (dummy_read & ~0x0060);
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break;
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case 4:
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dummy_read = SCFSR_4;
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SCFSR_4 = (dummy_read & ~0x0060);
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break;
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case 5:
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dummy_read = SCFSR_5;
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SCFSR_5 = (dummy_read & ~0x0060);
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break;
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case 6:
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dummy_read = SCFSR_6;
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SCFSR_6 = (dummy_read & ~0x0060);
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break;
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case 7:
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dummy_read = SCFSR_7;
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SCFSR_7 = (dummy_read & ~0x0060);
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break;
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}
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void uart1_irq() {/*uart_irq((LPC_UART1->IIR >> 1) & 0x7, 1, (LPC_UART_TypeDef*)LPC_UART1);*/}
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void uart2_irq() {/*uart_irq((LPC_UART2->IIR >> 1) & 0x7, 2, (LPC_UART_TypeDef*)LPC_UART2);*/}
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void uart3_irq() {/*uart_irq((LPC_UART3->IIR >> 1) & 0x7, 3, (LPC_UART_TypeDef*)LPC_UART3);*/}
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irq_handler(uart_data[index].serial_irq_id, TxIrq);
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GIC_EndInterrupt(irq_num);
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}
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static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
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uint16_t dummy_read;
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/* Clear RDF */
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switch (index) {
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case 0:
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dummy_read = SCFSR_0;
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SCFSR_0 = (dummy_read & ~0x0003);
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break;
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case 1:
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dummy_read = SCFSR_1;
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SCFSR_1 = (dummy_read & ~0x0003);
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break;
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case 2:
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dummy_read = SCFSR_2;
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SCFSR_2 = (dummy_read & ~0x0003);
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break;
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case 3:
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dummy_read = SCFSR_3;
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SCFSR_3 = (dummy_read & ~0x0003);
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break;
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case 4:
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dummy_read = SCFSR_4;
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SCFSR_4 = (dummy_read & ~0x0003);
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break;
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case 5:
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dummy_read = SCFSR_5;
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SCFSR_5 = (dummy_read & ~0x0003);
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break;
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case 6:
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dummy_read = SCFSR_6;
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SCFSR_6 = (dummy_read & ~0x0003);
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break;
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case 7:
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dummy_read = SCFSR_7;
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SCFSR_7 = (dummy_read & ~0x0003);
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break;
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}
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irq_handler(uart_data[index].serial_irq_id, RxIrq);
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GIC_EndInterrupt(irq_num);
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}
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/* TX handler */
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void uart0_tx_irq() {uart_tx_irq(SCIFTXI0_IRQn, 0);}
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void uart1_tx_irq() {uart_tx_irq(SCIFTXI1_IRQn, 1);}
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void uart2_tx_irq() {uart_tx_irq(SCIFTXI2_IRQn, 2);}
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void uart3_tx_irq() {uart_tx_irq(SCIFTXI3_IRQn, 3);}
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void uart4_tx_irq() {uart_tx_irq(SCIFTXI4_IRQn, 4);}
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void uart5_tx_irq() {uart_tx_irq(SCIFTXI5_IRQn, 5);}
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void uart6_tx_irq() {uart_tx_irq(SCIFTXI6_IRQn, 6);}
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void uart7_tx_irq() {uart_tx_irq(SCIFTXI7_IRQn, 7);}
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/* RX handler */
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void uart0_rx_irq() {uart_rx_irq(SCIFRXI0_IRQn, 0);}
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void uart1_rx_irq() {uart_rx_irq(SCIFRXI1_IRQn, 1);}
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void uart2_rx_irq() {uart_rx_irq(SCIFRXI2_IRQn, 2);}
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void uart3_rx_irq() {uart_rx_irq(SCIFRXI3_IRQn, 3);}
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void uart4_rx_irq() {uart_rx_irq(SCIFRXI4_IRQn, 4);}
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void uart5_rx_irq() {uart_rx_irq(SCIFRXI5_IRQn, 5);}
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void uart6_rx_irq() {uart_rx_irq(SCIFRXI6_IRQn, 6);}
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void uart7_rx_irq() {uart_rx_irq(SCIFRXI7_IRQn, 7);}
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void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
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irq_handler = handler;
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@ -231,27 +326,72 @@ void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
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}
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static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
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/* IRQn_Type irq_n = (IRQn_Type)0;
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uint32_t vector = 0;
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switch ((int)obj->uart) {
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case UART_0: irq_n=UART0_IRQn; vector = (uint32_t)&uart0_irq; break;
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case UART_1: irq_n=UART1_IRQn; vector = (uint32_t)&uart1_irq; break;
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case UART_2: irq_n=UART2_IRQn; vector = (uint32_t)&uart2_irq; break;
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case UART_3: irq_n=UART3_IRQn; vector = (uint32_t)&uart3_irq; break;
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switch (obj->index){
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case 0:
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InterruptHandlerRegister(SCIFTXI0_IRQn, (void (*)(uint32_t))uart0_tx_irq);
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InterruptHandlerRegister(SCIFRXI0_IRQn, (void (*)(uint32_t))uart0_rx_irq);
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GIC_SetPriority(SCIFTXI0_IRQn, 5);
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GIC_SetPriority(SCIFRXI0_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI0_IRQn);
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GIC_EnableIRQ(SCIFRXI0_IRQn);
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break;
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case 1:
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InterruptHandlerRegister(SCIFTXI1_IRQn, (void (*)(uint32_t))uart1_tx_irq);
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InterruptHandlerRegister(SCIFRXI1_IRQn, (void (*)(uint32_t))uart1_rx_irq);
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GIC_SetPriority(SCIFTXI1_IRQn, 5);
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GIC_SetPriority(SCIFRXI1_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI1_IRQn);
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GIC_EnableIRQ(SCIFRXI1_IRQn);
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break;
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case 2:
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InterruptHandlerRegister(SCIFTXI2_IRQn, (void (*)(uint32_t))uart2_tx_irq);
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InterruptHandlerRegister(SCIFRXI2_IRQn, (void (*)(uint32_t))uart2_rx_irq);
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GIC_SetPriority(SCIFTXI2_IRQn, 5);
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GIC_SetPriority(SCIFRXI2_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI2_IRQn);
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GIC_EnableIRQ(SCIFRXI2_IRQn);
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break;
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case 3:
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InterruptHandlerRegister(SCIFTXI3_IRQn, (void (*)(uint32_t))uart3_tx_irq);
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InterruptHandlerRegister(SCIFRXI3_IRQn, (void (*)(uint32_t))uart3_rx_irq);
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GIC_SetPriority(SCIFTXI3_IRQn, 5);
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GIC_SetPriority(SCIFRXI3_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI3_IRQn);
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GIC_EnableIRQ(SCIFRXI3_IRQn);
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break;
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case 4:
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InterruptHandlerRegister(SCIFTXI4_IRQn, (void (*)(uint32_t))uart4_tx_irq);
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InterruptHandlerRegister(SCIFRXI4_IRQn, (void (*)(uint32_t))uart4_rx_irq);
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GIC_SetPriority(SCIFTXI4_IRQn, 5);
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GIC_SetPriority(SCIFRXI4_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI4_IRQn);
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GIC_EnableIRQ(SCIFRXI4_IRQn);
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break;
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case 5:
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InterruptHandlerRegister(SCIFTXI5_IRQn, (void (*)(uint32_t))uart5_tx_irq);
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InterruptHandlerRegister(SCIFRXI5_IRQn, (void (*)(uint32_t))uart5_rx_irq);
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GIC_SetPriority(SCIFTXI5_IRQn, 5);
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GIC_SetPriority(SCIFRXI5_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI5_IRQn);
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GIC_EnableIRQ(SCIFRXI5_IRQn);
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break;
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case 6:
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InterruptHandlerRegister(SCIFTXI6_IRQn, (void (*)(uint32_t))uart6_tx_irq);
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InterruptHandlerRegister(SCIFRXI6_IRQn, (void (*)(uint32_t))uart6_rx_irq);
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GIC_SetPriority(SCIFTXI6_IRQn, 5);
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GIC_SetPriority(SCIFRXI6_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI6_IRQn);
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GIC_EnableIRQ(SCIFRXI6_IRQn);
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break;
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case 7:
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InterruptHandlerRegister(SCIFTXI7_IRQn, (void (*)(uint32_t))uart7_tx_irq);
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InterruptHandlerRegister(SCIFRXI7_IRQn, (void (*)(uint32_t))uart7_rx_irq);
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GIC_SetPriority(SCIFTXI7_IRQn, 5);
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GIC_SetPriority(SCIFRXI7_IRQn, 5);
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GIC_EnableIRQ(SCIFTXI7_IRQn);
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GIC_EnableIRQ(SCIFRXI7_IRQn);
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break;
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}
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if (enable) {
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obj->uart->IER |= 1 << irq;
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//NVIC_SetVector(irq_n, vector);
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//NVIC_EnableIRQ(irq_n);
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} else if ((TxIrq == irq) || (uart_data[obj->index].rx_irq_set_api + uart_data[obj->index].rx_irq_set_flow == 0)) { // disable
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int all_disabled = 0;
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SerialIrq other_irq = (irq == RxIrq) ? (TxIrq) : (RxIrq);
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obj->uart->IER &= ~(1 << irq);
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all_disabled = (obj->uart->IER & (1 << other_irq)) == 0;
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if (all_disabled) ;
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//NVIC_DisableIRQ(irq_n);
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}*/
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}
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void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
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