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CMSIS system for KL05Z update 

- clocking from external 32kHz is set by default
pull/176/head
0xc0170 2014-02-19 08:52:59 +01:00
parent 111cad58e9
commit cd46fa2a73
2 changed files with 260 additions and 111 deletions
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214
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.c
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@ -1,78 +1,214 @@
/*
** ###################################################################
** Processors: MKL05Z32FK4
** MKL05Z32LC4
** MKL05Z32VLF4
**
** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
**
** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
** Version: rev. 1.6, 2013-04-11
**
** Abstract:
** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device.
**
** Copyright: 2013 Freescale, Inc. All Rights Reserved.
**
** http: www.freescale.com
** mail: support@freescale.com
**
** Revisions:
** - rev. 1.0 (2012-06-08)
** Initial version.
** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1.
** - rev. 1.2 (2012-08-01)
** Device type UARTLP changed to UART0.
** Missing PORTB_IRQn interrupt number definition added.
** - rev. 1.3 (2012-10-04)
** Update according to reference manual rev. 3.
** - rev. 1.4 (2012-11-22)
** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
** - rev. 1.5 (2013-04-05)
** Changed start of doxygen comment.
** - rev. 1.6 (2013-04-11)
** SystemInit methods updated with predefined initialization sequence.
**
** ###################################################################
*/
/*!
* @file MKL05Z4
* @version 1.6
* @date 2013-04-11
* @brief Device specific configuration file for MKL05Z4 (implementation file)
*
* Provides a system configuration function and a global variable that contains
* the system frequency. It configures the device and initializes the oscillator
* (PLL) that is part of the microcontroller device.
*/
#include <stdint.h> #include <stdint.h>
#include "MKL05Z4.h" #include "MKL05Z4.h"
#define DISABLE_WDOG 1 #define DISABLE_WDOG 1
#define CLOCK_SETUP 1
/* Predefined clock setups /* Predefined clock setups
Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode 0 ... Multipurpose Clock Generator (MCG) in FLL Engaged Internal (FEI) mode
Reference clock source for MCG module is the slow internal clock source 32.768kHz Reference clock source for MCG module is the slow internal clock source 32.768kHz
Core clock = 47.97MHz, BusClock = 23.48MHz Core clock = 41.94MHz, BusClock = 20.97MHz
1 ... Multipurpose Clock Generator (MCG) in FLL Engaged External (FEE) mode
Reference clock source for MCG module is an external crystal 32.768kHz
Core clock = 47.97MHz, BusClock = 23.98MHz
2 ... Multipurpose Clock Generator (MCG) in FLL Bypassed Low Power Internal (BLPI) mode
Core clock/Bus clock derived directly from an fast internal 4MHz clock with no multiplication
Core clock = 4MHz, BusClock = 4MHz
*/ */
/*----------------------------------------------------------------------------
Define clock source values
*----------------------------------------------------------------------------*/
#if (CLOCK_SETUP == 0)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 41943040u /* Default System clock value */
#elif (CLOCK_SETUP == 1)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */ #define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */ #define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */ #define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */ #define DEFAULT_SYSTEM_CLOCK 47972352u /* Default System clock value */
#elif (CLOCK_SETUP == 2)
#define CPU_XTAL_CLK_HZ 32768u /* Value of the external crystal or oscillator clock frequency in Hz */
#define CPU_INT_SLOW_CLK_HZ 32768u /* Value of the slow internal oscillator clock frequency in Hz */
#define CPU_INT_FAST_CLK_HZ 4000000u /* Value of the fast internal oscillator clock frequency in Hz */
#define DEFAULT_SYSTEM_CLOCK 4000000u /* Default System clock value */
#endif /* (CLOCK_SETUP == 2) */
/* ----------------------------------------------------------------------------
-- Core clock
---------------------------------------------------------------------------- */
uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
/* ----------------------------------------------------------------------------
-- SystemInit()
---------------------------------------------------------------------------- */
void SystemInit (void) { void SystemInit (void) {
#if (DISABLE_WDOG) #if (DISABLE_WDOG)
/* Disable the WDOG module */ /* Disable the WDOG module */
/* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */ /* SIM_COPC: COPT=0,COPCLKS=0,COPW=0 */
SIM->COPC = (uint32_t)0x00u; SIM->COPC = (uint32_t)0x00u;
#endif /* (DISABLE_WDOG) */ #endif /* (DISABLE_WDOG) */
#if (CLOCK_SETUP == 0)
SIM->SCGC5 |= (SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTA_MASK); /* Enable clock gate for ports to enable pin routing */ /* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
/* SIM_SCGC5: LPTMR=1 */
SIM->SCGC5 |= SIM_SCGC5_LPTMR_MASK;
/* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */ SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* SIM_SOPT1: OSC32KSEL=0 */
SIM->SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
/* SIM_SOPT2: TPMSRC=2 */
SIM->SOPT2 = (uint32_t)((SIM->SOPT2 & (uint32_t)~(uint32_t)(SIM_SOPT2_TPMSRC(0x01))) |
(uint32_t)(SIM_SOPT2_TPMSRC(0x02))); /* Set the TPM clock */
/* PORTA_PCR3: ISF=0,MUX=0 */
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* MCG_SC: FCRDIV=1 */
MCG->SC = (uint8_t)((MCG->SC & (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x06))) |
(uint8_t)(MCG_SC_FCRDIV(0x01)));
/* Switch to FEI Mode */ /* Switch to FEI Mode */
/* MCG_C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */ /* MCG->C1: CLKS=0,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG->C1 = MCG_C1_CLKS(0x00) |
MCG_C1_IREFS_MASK | MCG_C1_IRCLKEN_MASK; MCG_C1_FRDIV(0x00) |
/* MCG_C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */ MCG_C1_IREFS_MASK |
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK); MCG_C1_IRCLKEN_MASK;
/* MCG_C4: DMX32=1,DRST_DRS=1 */ /* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=0 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(MCG_C4_DRST_DRS(0x02))) | MCG->C2 = MCG_C2_RANGE0(0x00);
(uint8_t)(MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x01))); /* MCG_C4: DMX32=0,DRST_DRS=1 */
/* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */ MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
MCG_C4_DMX32_MASK |
MCG_C4_DRST_DRS(0x02)
)) | (uint8_t)(
MCG_C4_DRST_DRS(0x01)
));
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK; OSC0->CR = OSC_CR_ERCLKEN_MASK;
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */ while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
} }
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */ while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
} }
#elif (CLOCK_SETUP == 1)
/* SIM->SCGC5: PORTA=1 */
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; /* Enable clock gate for ports to enable pin routing */
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=1,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x01)); /* Update system prescalers */
/* PORTA->PCR[3]: ISF=0,MUX=0 */
PORTA->PCR[3] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* PORTA->PCR[4]: ISF=0,MUX=0 */
PORTA->PCR[4] &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
/* Switch to FEE Mode */
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_EREFS0_MASK);
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK;
/* MCG->C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
/* MCG->C4: DMX32=1,DRST_DRS=1 */
MCG->C4 = (uint8_t)((MCG->C4 & (uint8_t)~(uint8_t)(
MCG_C4_DRST_DRS(0x02)
)) | (uint8_t)(
MCG_C4_DMX32_MASK |
MCG_C4_DRST_DRS(0x01)
));
while((MCG->S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
}
while((MCG->S & 0x0CU) != 0x00U) { /* Wait until output of the FLL is selected */
}
#elif (CLOCK_SETUP == 2)
/* SIM->CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
SIM->CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
/* MCG->SC: FCRDIV=0 */
MCG->SC &= (uint8_t)~(uint8_t)(MCG_SC_FCRDIV(0x07));
/* Switch to FBI Mode */
/* MCG->C1: CLKS=1,FRDIV=0,IREFS=1,IRCLKEN=1,IREFSTEN=0 */
MCG->C1 = MCG_C1_CLKS(0x01) |
MCG_C1_FRDIV(0x00) |
MCG_C1_IREFS_MASK |
MCG_C1_IRCLKEN_MASK;
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=0,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_IRCS_MASK);
/* MCG->C4: DMX32=0,DRST_DRS=0 */
MCG->C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
/* OSC0->CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
OSC0->CR = OSC_CR_ERCLKEN_MASK;
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & 0x0CU) != 0x04U) { /* Wait until internal reference clock is selected as MCG output */
}
/* Switch to BLPI Mode */
/* MCG->C2: LOCRE0=0,??=0,RANGE0=0,HGO0=0,EREFS0=0,LP=1,IRCS=1 */
MCG->C2 = (MCG_C2_RANGE0(0x00) | MCG_C2_LP_MASK | MCG_C2_IRCS_MASK);
while((MCG->S & MCG_S_IREFST_MASK) == 0x00U) { /* Check that the source of the FLL reference clock is the internal reference clock. */
}
while((MCG->S & MCG_S_IRCST_MASK) == 0x00U) { /* Check that the fast external reference clock is selected. */
}
#endif /* (CLOCK_SETUP == 2) */
} }
/* ----------------------------------------------------------------------------
-- SystemCoreClockUpdate()
---------------------------------------------------------------------------- */
void SystemCoreClockUpdate (void) { void SystemCoreClockUpdate (void) {
uint32_t MCGOUTClock; uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
uint8_t Divider; uint8_t Divider;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) { if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x0u) {
/* FLL is selected */ /* Output of FLL is selected */
if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) { if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u) {
/* External reference clock is selected */ /* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT)); Divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */ MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u) { } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
MCGOUTClock /= 32u; /* If high range is enabled, additional 32 divider is active */
}
} else {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
} } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x0u)) */
/* Select correct multiplier to calculate the MCG output clock */ /* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) { switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u: case 0x0u:
@ -106,17 +242,15 @@ void SystemCoreClockUpdate(void) {
/* Internal reference clock is selected */ /* Internal reference clock is selected */
if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) { if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u) {
MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */ MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
} else { } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */ MCGOUTClock = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast internal reference clock selected */
} } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x0u)) */
} else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) { } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u) {
/* External reference clock is selected */ /* External reference clock is selected */
MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */ MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
} else { } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
/* Reserved value */ /* Reserved value */
return; return;
} } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80u)) */
SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT))); SystemCoreClock = (MCGOUTClock / (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
} }

31
libraries/mbed/targets/cmsis/TARGET_Freescale/TARGET_KLXX/TARGET_KL05Z/system_MKL05Z4.h
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@ -1,37 +1,52 @@
/* /*
** ################################################################### ** ###################################################################
** Processor: MKL05Z128VLK4 ** Processors: MKL05Z32FK4
** MKL05Z32LC4
** MKL05Z32VLF4
**
** Compilers: ARM Compiler ** Compilers: ARM Compiler
** Freescale C/C++ for Embedded ARM ** Freescale C/C++ for Embedded ARM
** GNU C Compiler ** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM ** IAR ANSI C/C++ Compiler for ARM
** **
** Reference manual: KL05RM, Rev.1, Jun 2012 ** Reference manual: KL05P48M48SF1RM, Rev.3, Sep 2012
** Version: rev. 1.1, 2012-06-21 ** Version: rev. 1.6, 2013-04-11
** **
** Abstract: ** Abstract:
** Provides a system configuration function and a global variable that ** Provides a system configuration function and a global variable that
** contains the system frequency. It configures the device and initializes ** contains the system frequency. It configures the device and initializes
** the oscillator (PLL) that is part of the microcontroller device. ** the oscillator (PLL) that is part of the microcontroller device.
** **
** Copyright: 2012 Freescale Semiconductor, Inc. All Rights Reserved. ** Copyright: 2013 Freescale, Inc. All Rights Reserved.
** **
** http: www.freescale.com ** http: www.freescale.com
** mail: support@freescale.com ** mail: support@freescale.com
** **
** Revisions: ** Revisions:
** - rev. 1.0 (2012-06-13) ** - rev. 1.0 (2012-06-08)
** Initial version. ** Initial version.
** - rev. 1.1 (2012-06-21) ** - rev. 1.1 (2012-06-21)
** Update according to reference manual rev. 1. ** Update according to reference manual rev. 1.
** - rev. 1.2 (2012-08-01)
** Device type UARTLP changed to UART0.
** Missing PORTB_IRQn interrupt number definition added.
** - rev. 1.3 (2012-10-04)
** Update according to reference manual rev. 3.
** - rev. 1.4 (2012-11-22)
** MCG module - bit LOLS in MCG_S register renamed to LOLS0.
** NV registers - bit EZPORT_DIS in NV_FOPT register removed.
** - rev. 1.5 (2013-04-05)
** Changed start of doxygen comment.
** - rev. 1.6 (2013-04-11)
** SystemInit methods updated with predefined initialization sequence.
** **
** ################################################################### ** ###################################################################
*/ */
/** /*!
* @file MKL05Z4 * @file MKL05Z4
* @version 1.1 * @version 1.6
* @date 2012-06-21 * @date 2013-04-11
* @brief Device specific configuration file for MKL05Z4 (header file) * @brief Device specific configuration file for MKL05Z4 (header file)
* *
* Provides a system configuration function and a global variable that contains * Provides a system configuration function and a global variable that contains