From ccd95f1e14d6da8c5afd47c44d7aaa21707f1989 Mon Sep 17 00:00:00 2001 From: Marcelo Salazar Date: Tue, 12 May 2020 23:03:07 +0100 Subject: [PATCH] Remove nRF51 targets The following public nRF51 targets are being removed: - NRF51822 - NRF51_DK - NRF51_MICROBIT --- TESTS/mbed_hal/critical_section/main.cpp | 8 +- .../blockdevice/COMPONENT_SD/mbed_lib.json | 6 - features/frameworks/mbed-trace/Jenkinsfile | 2 - platform/source/mbed_board.c | 2 +- .../components/libraries/crc16/crc16.h | 51 - .../libraries/scheduler/app_scheduler.h | 152 - .../components/libraries/util/app_error.h | 92 - .../components/libraries/util/app_util.h | 234 - .../s110_nrf51822_8.0.0_licence_agreement.txt | 90 - .../s110_nrf51822_8.0.0_softdevice.hex | 5649 -------------- .../s130_nrf51_1.0.0_licence_agreement.txt | 90 - .../s130_nrf51_1.0.0_softdevice.hex | 6861 ---------------- .../TARGET_MCU_NRF51822/PeripheralNames.h | 58 - .../TARGET_MCU_NRF51822/PortNames.h | 30 - .../TARGET_NRF51822_MKIT/PinNames.h | 153 - .../TARGET_NRF51822_MKIT/device.h | 38 - .../TARGET_NRF51822_SBKIT/PinNames.h | 106 - .../TARGET_NRF51822_SBKIT/device.h | 57 - .../TARGET_NRF51_DK/PinNames.h | 178 - .../TARGET_NRF51_DK/device.h | 38 - .../TARGET_NRF51_MICROBIT/PinNames.h | 184 - .../TARGET_NRF51_MICROBIT/device.h | 38 - .../TARGET_MCU_NRF51822/analogin_api.c | 84 - .../TARGET_MCU_NORDIC_16K/startup_nRF51822.S | 186 - .../TARGET_MCU_NORDIC_32K/nRF51822.sct | 30 - .../TARGET_MCU_NORDIC_32K/startup_nRF51822.S | 195 - .../TARGET_MCU_NRF51_16K_S110/nRF51822.sct | 30 - .../TARGET_MCU_NRF51_16K_S130/nRF51822.sct | 30 - .../TARGET_MCU_NORDIC_32K/NRF51822.ld | 157 - .../TARGET_MCU_NRF51_16K_S110/NRF51822.ld | 157 - .../TARGET_MCU_NRF51_16K_S130/NRF51822.ld | 157 - .../TOOLCHAIN_GCC_ARM/startup_NRF51822.S | 243 - .../TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf | 46 - .../startup_NRF51822_IAR.S | 237 - .../TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf | 46 - .../startup_NRF51822_IAR.S | 237 - .../s110_nrf51822_7.1.0_softdevice.bin | Bin 86540 -> 0 bytes .../TARGET_MCU_NRF51822/device/cmsis.h | 13 - .../TARGET_MCU_NRF51822/device/cmsis_nvic.c | 103 - .../TARGET_MCU_NRF51822/device/cmsis_nvic.h | 53 - .../device/compiler_abstraction.h | 109 - .../TARGET_MCU_NRF51822/device/nrf.h | 61 - .../TARGET_MCU_NRF51822/device/nrf51.h | 1262 --- .../device/nrf51_bitfields.h | 6894 ----------------- .../device/nrf51_deprecated.h | 440 -- .../TARGET_MCU_NRF51822/device/nrf_delay.h | 74 - .../TARGET_MCU_NRF51822/device/system_nrf51.c | 187 - .../TARGET_MCU_NRF51822/device/system_nrf51.h | 68 - .../TARGET_MCU_NRF51822/gpio_api.c | 58 - .../TARGET_MCU_NRF51822/gpio_irq_api.c | 127 - .../TARGET_MCU_NRF51822/gpio_object.h | 56 - .../TARGET_MCU_NRF51822/i2c_api.c | 368 - .../TARGET_MCU_NRF51822/objects.h | 86 - .../TARGET_MCU_NRF51822/pinmap.c | 32 - .../TARGET_MCU_NRF51822/port_api.c | 84 - .../TARGET_MCU_NRF51822/pwmout_api.c | 385 - .../TARGET_MCU_NRF51822/serial_api.c | 359 - .../TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c | 33 - .../TARGET_MCU_NRF51822/spi_api.c | 375 - .../TARGET_MCU_NRF51822/twi_config.h | 20 - .../TARGET_MCU_NRF51822/twi_master.c | 304 - .../TARGET_MCU_NRF51822/twi_master.h | 112 - .../TARGET_MCU_NRF51822/us_ticker.c | 618 -- .../PeripheralNames.h | 81 - .../TARGET_MCU_NRF51822_UNIFIED/PortNames.h | 53 - .../TARGET_NRF51_DK/PinNames.h | 199 - .../TARGET_NRF51_DK/device.h | 38 - .../analogin_api.c | 94 - .../TARGET_MCU_NORDIC_16K/startup_nRF51822.S | 189 - .../TARGET_MCU_NORDIC_32K/nRF51822.sct | 33 - .../TARGET_MCU_NORDIC_32K/startup_nRF51822.S | 198 - .../TARGET_MCU_NRF51_16K_S110/nRF51822.sct | 33 - .../TARGET_MCU_NRF51_16K_S130/nRF51822.sct | 33 - .../TARGET_MCU_NORDIC_32K/NRF51822.ld | 171 - .../TARGET_MCU_NRF51_16K_S110/NRF51822.ld | 157 - .../TARGET_MCU_NRF51_16K_S130/NRF51822.ld | 169 - .../TOOLCHAIN_GCC_ARM/startup_NRF51822.S | 253 - .../TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf | 48 - .../TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf | 48 - .../TOOLCHAIN_IAR/startup_NRF51822_IAR.S | 234 - .../device/cmsis.h | 13 - .../device/cmsis_nvic.c | 43 - .../device/cmsis_nvic.h | 53 - .../device/system_nrf51.c | 192 - .../device/system_nrf51.h | 78 - .../TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c | 299 - .../sdk/drivers_nrf/adc/nrf_drv_adc.c | 281 - .../sdk/drivers_nrf/adc/nrf_drv_adc.h | 324 - .../sdk/nrf_drv_config.h | 495 -- .../softdevice/s130/headers/nrf51/nrf_mbr.h | 202 - .../sdk/softdevice/s130/headers/nrf_ble.h | 635 -- .../sdk/softdevice/s130/headers/nrf_ble_err.h | 93 - .../sdk/softdevice/s130/headers/nrf_ble_gap.h | 1745 ----- .../softdevice/s130/headers/nrf_ble_gatt.h | 215 - .../softdevice/s130/headers/nrf_ble_gattc.h | 572 -- .../softdevice/s130/headers/nrf_ble_gatts.h | 725 -- .../sdk/softdevice/s130/headers/nrf_ble_hci.h | 134 - .../softdevice/s130/headers/nrf_ble_l2cap.h | 205 - .../softdevice/s130/headers/nrf_ble_ranges.h | 129 - .../softdevice/s130/headers/nrf_ble_types.h | 208 - .../sdk/softdevice/s130/headers/nrf_error.h | 90 - .../softdevice/s130/headers/nrf_error_sdm.h | 70 - .../softdevice/s130/headers/nrf_error_soc.h | 85 - .../sdk/softdevice/s130/headers/nrf_nvic.h | 486 -- .../sdk/softdevice/s130/headers/nrf_sd_def.h | 50 - .../sdk/softdevice/s130/headers/nrf_sdm.h | 274 - .../sdk/softdevice/s130/headers/nrf_soc.h | 911 --- .../sdk/softdevice/s130/headers/nrf_svc.h | 91 - .../s130/hex/s130_nrf51_2.0.0_softdevice.hex | 6783 ---------------- .../sdk_patch/sdk_config.h | 17 - .../TARGET_NRF5x/TARGET_NRF51/common_rtc.c | 253 - .../TARGET_NRF5x/TARGET_NRF51/common_rtc.h | 53 - .../TARGET_NRF5x/TARGET_NRF51/flash_api.c | 207 - .../TARGET_NRF5x/TARGET_NRF51/gpio_api.c | 271 - .../TARGET_NRF5x/TARGET_NRF51/i2c_api.c | 776 -- .../TARGET_NRF51/irq_handlers_hw.h | 55 - .../TARGET_NRF51/nordic_critical.c | 107 - .../TARGET_NRF5x/TARGET_NRF51/objects.h | 98 - .../TARGET_NRF51/reloc_vector_table.c | 76 - .../TARGET_NRF5x/TARGET_NRF51/serial_api.c | 720 -- .../TARGET_NRF5x/TARGET_NRF51/sleep.c | 93 - .../TARGET_NRF5x/TARGET_NRF51/spi_api.c | 650 -- .../TARGET_NRF5x/TARGET_NRF51/trng_api.c | 181 - .../TARGET_NRF5x/TARGET_NRF51/us_ticker.c | 146 - .../TARGET_NRF5x/TARGET_NRF51/us_ticker.h | 26 - targets/TARGET_NORDIC/mbed_rtx.h | 18 +- targets/targets.json | 551 -- tools/export/cmake/__init__.py | 1 - tools/export/codeblocks/__init__.py | 7 - tools/export/gnuarmeclipse/__init__.py | 1 - tools/export/iar/iar_definitions.json | 6 - tools/export/makefile/__init__.py | 1 - tools/export/mcuxpresso/__init__.py | 1 - tools/export/nb/__init__.py | 1 - tools/export/uvision/__init__.py | 1 - tools/singletest.py | 3 +- tools/targets/__init__.py | 69 - tools/test/examples/examples.json | 2 +- tools/tests.py | 8 +- 139 files changed, 8 insertions(+), 50136 deletions(-) delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_licence_agreement.txt delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PeripheralNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PortNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/PinNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/device.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/PinNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/device.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/s110_nrf51822_7.1.0_softdevice.bin delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/compiler_abstraction.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_bitfields.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_deprecated.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf_delay.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c delete mode 100755 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pinmap.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/port_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c delete mode 100755 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c delete mode 100755 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c delete mode 100755 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_config.h delete mode 100755 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.c delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.h delete mode 100644 targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PortNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h delete mode 100644 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targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk_patch/sdk_config.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/gpio_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/i2c_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/irq_handlers_hw.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/nordic_critical.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/objects.h delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/reloc_vector_table.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/serial_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/sleep.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/spi_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/trng_api.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.c delete mode 100644 targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.h diff --git a/TESTS/mbed_hal/critical_section/main.cpp b/TESTS/mbed_hal/critical_section/main.cpp index eb70768d86..0741b0fccb 100644 --- a/TESTS/mbed_hal/critical_section/main.cpp +++ b/TESTS/mbed_hal/critical_section/main.cpp @@ -29,18 +29,12 @@ using utest::v1::Case; bool test_are_interrupts_enabled(void) { - // NRF51 targets don't disable interrupts when in critical section, instead they mask application interrupts. - // This is due to SoftDevice BLE stack (BLE to be operational requires some interrupts to be always enabled) -#if defined(TARGET_NRF51) - // check if APP interrupts are masked for other NRF51 boards - return ((NVIC->ISER[0] & __NRF_NVIC_APP_IRQS_0) != 0); -#else #if defined(__CORTEX_A9) return ((__get_CPSR() & 0x80) == 0); #else return ((__get_PRIMASK() & 0x1) == 0); #endif -#endif + } diff --git a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json index db26329e56..33551eec93 100644 --- a/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json +++ b/components/storage/blockdevice/COMPONENT_SD/mbed_lib.json @@ -89,12 +89,6 @@ "SPI_CLK": "PD_14", "SPI_CS": "PD_13" }, - "nRF51822": { - "SPI_MOSI": "p12", - "SPI_MISO": "p13", - "SPI_CLK": "p15", - "SPI_CS": "p14" - }, "RZ_A1H": { "SPI_MOSI": "P8_5", "SPI_MISO": "P8_6", diff --git a/features/frameworks/mbed-trace/Jenkinsfile b/features/frameworks/mbed-trace/Jenkinsfile index 387354b7f1..2793e1c6bc 100644 --- a/features/frameworks/mbed-trace/Jenkinsfile +++ b/features/frameworks/mbed-trace/Jenkinsfile @@ -13,7 +13,6 @@ properties ([ def morpheusTargets = [ //"LPC1768", //"NUCLEO_F401RE", - //"NRF51DK", "K64F" ] // Map morpheus toolchains to compiler labels on Jenkins @@ -26,7 +25,6 @@ def toolchains = [ def yottaTargets = [ "frdm-k64f-gcc": "gcc", "frdm-k64f-armcc": "armcc", - "nrf51dk-gcc": "gcc", "stm32f429i-disco-gcc": "gcc", "x86-linux-native": "linux && astyle" ] diff --git a/platform/source/mbed_board.c b/platform/source/mbed_board.c index 93e63adedd..c6220a4c4a 100644 --- a/platform/source/mbed_board.c +++ b/platform/source/mbed_board.c @@ -25,7 +25,7 @@ WEAK MBED_NORETURN void mbed_die(void) { -#if !defined (NRF51_H) && !defined(TARGET_EFM32) +#if !defined(TARGET_EFM32) core_util_critical_section_enter(); #endif gpio_t led_err; diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h deleted file mode 100644 index 57f6251354..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/crc16/crc16.h +++ /dev/null @@ -1,51 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup crc_compute CRC compute - * @{ - * @ingroup hci_transport - * - * @brief This module implements the CRC-16 calculation in the blocks. - */ - -#ifndef CRC16_H__ -#define CRC16_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Function for calculating CRC-16 in blocks. - * - * Feed each consecutive data block into this function, along with the current value of p_crc as - * returned by the previous call of this function. The first call of this function should pass NULL - * as the initial value of the crc in p_crc. - * - * @param[in] p_data The input data block for computation. - * @param[in] size The size of the input data block in bytes. - * @param[in] p_crc The previous calculated CRC-16 value or NULL if first call. - * - * @return The updated CRC-16 value, based on the input supplied. - */ -uint16_t crc16_compute(const uint8_t * p_data, uint32_t size, const uint16_t * p_crc); - -#ifdef __cplusplus -} -#endif - -#endif // CRC16_H__ - -/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h deleted file mode 100644 index 05117cb48f..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/scheduler/app_scheduler.h +++ /dev/null @@ -1,152 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_scheduler Scheduler - * @{ - * @ingroup app_common - * - * @brief The scheduler is used for transferring execution from the interrupt context to the main - * context. - * - * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events - * when using the Scheduler. - * - * @section app_scheduler_req Requirements: - * - * @subsection main_context_logic Logic in main context: - * - * - Define an event handler for each type of event expected. - * - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the - * application main loop. - * - Call app_sched_execute() from the main loop each time the application wakes up because of an - * event (typically when sd_app_evt_wait() returns). - * - * @subsection int_context_logic Logic in interrupt context: - * - * - In the interrupt handler, call app_sched_event_put() - * with the appropriate data and event handler. This will insert an event into the - * scheduler's queue. The app_sched_execute() function will pull this event and call its - * handler in the main context. - * - * @if (SD_S110 && !SD_S310) - * For an example usage of the scheduler, see the implementations of - * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard. - * @endif - * - * @image html scheduler_working.jpg The high level design of the scheduler - */ - -#ifndef APP_SCHEDULER_H__ -#define APP_SCHEDULER_H__ - -#include -#include "app_error.h" - -#define APP_SCHED_EVENT_HEADER_SIZE 8 /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */ - -/**@brief Compute number of bytes required to hold the scheduler buffer. - * - * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. - * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events - * that can be scheduled for execution). - * - * @return Required scheduler buffer size (in bytes). - */ -#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE) \ - (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1)) - -/**@brief Scheduler event handler type. */ -typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size); - -/**@brief Macro for initializing the event scheduler. - * - * @details It will also handle dimensioning and allocation of the memory buffer required by the - * scheduler, making sure the buffer is correctly aligned. - * - * @param[in] EVENT_SIZE Maximum size of events to be passed through the scheduler. - * @param[in] QUEUE_SIZE Number of entries in scheduler queue (i.e. the maximum number of events - * that can be scheduled for execution). - * - * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it - * several times as long as it is from the same location, e.g. to do a reinitialization). - */ -#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE) \ - do \ - { \ - static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)), \ - sizeof(uint32_t))]; \ - uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF); \ - APP_ERROR_CHECK(ERR_CODE); \ - } while (0) - -/**@brief Function for initializing the Scheduler. - * - * @details It must be called before entering the main loop. - * - * @param[in] max_event_size Maximum size of events to be passed through the scheduler. - * @param[in] queue_size Number of entries in scheduler queue (i.e. the maximum number of - * events that can be scheduled for execution). - * @param[in] p_evt_buffer Pointer to memory buffer for holding the scheduler queue. It must - * be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer - * must be aligned to a 4 byte boundary. - * - * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both - * allocate the scheduler buffer, and also align the buffer correctly. - * - * @retval NRF_SUCCESS Successful initialization. - * @retval NRF_ERROR_INVALID_PARAM Invalid parameter (buffer not aligned to a 4 byte - * boundary). - */ -uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer); - -/**@brief Function for executing all scheduled events. - * - * @details This function must be called from within the main loop. It will execute all events - * scheduled since the last time it was called. - */ -void app_sched_execute(void); - -/**@brief Function for scheduling an event. - * - * @details Puts an event into the event queue. - * - * @param[in] p_event_data Pointer to event data to be scheduled. - * @param[in] event_size Size of event data to be scheduled. - * @param[in] handler Event handler to receive the event. - * - * @return NRF_SUCCESS on success, otherwise an error code. - */ -uint32_t app_sched_event_put(void * p_event_data, - uint16_t event_size, - app_sched_event_handler_t handler); - -#ifdef APP_SCHEDULER_WITH_PAUSE -/**@brief A function to pause the scheduler. - * - * @details When the scheduler is paused events are not pulled from the scheduler queue for - * processing. The function can be called multiple times. To unblock the scheduler the - * function @ref app_sched_resume has to be called the same number of times. - */ -void app_sched_pause(void); - -/**@brief A function to resume a scheduler. - * - * @details To unblock the scheduler this function has to be called the same number of times as - * @ref app_sched_pause function. - */ -void app_sched_resume(void); -#endif -#endif // APP_SCHEDULER_H__ - -/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h deleted file mode 100644 index 2711170419..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_error.h +++ /dev/null @@ -1,92 +0,0 @@ -/* Copyright (c) 2013 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_error Common application error handler - * @{ - * @ingroup app_common - * - * @brief Common application error handler and macros for utilizing a common error handler. - */ - -#ifndef APP_ERROR_H__ -#define APP_ERROR_H__ - -#include -#include -#include "nrf_error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@brief Function for error handling, which is called when an error has occurred. - * - * @param[in] error_code Error code supplied to the handler. - * @param[in] line_num Line number where the handler is called. - * @param[in] p_file_name Pointer to the file name. - */ -void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name); - -#ifdef __cplusplus -} -#endif - -/**@brief Macro for calling error handler function. - * - * @param[in] ERR_CODE Error code supplied to the error handler. - */ -#ifdef DEBUG -#define APP_ERROR_HANDLER(ERR_CODE) \ - do \ - { \ - app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__); \ - } while (0) -#else -#define APP_ERROR_HANDLER(ERR_CODE) \ - do \ - { \ - app_error_handler((ERR_CODE), 0, 0); \ - } while (0) -#endif -/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS. - * - * @param[in] ERR_CODE Error code supplied to the error handler. - */ -#define APP_ERROR_CHECK(ERR_CODE) \ - do \ - { \ - const uint32_t LOCAL_ERR_CODE = (ERR_CODE); \ - if (LOCAL_ERR_CODE != NRF_SUCCESS) \ - { \ - APP_ERROR_HANDLER(LOCAL_ERR_CODE); \ - } \ - } while (0) - -/**@brief Macro for calling error handler function if supplied boolean value is false. - * - * @param[in] BOOLEAN_VALUE Boolean value to be evaluated. - */ -#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE) \ - do \ - { \ - const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \ - if (!LOCAL_BOOLEAN_VALUE) \ - { \ - APP_ERROR_HANDLER(0); \ - } \ - } while (0) - -#endif // APP_ERROR_H__ - -/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h deleted file mode 100644 index 7b0ef5a06a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/nordic_sdk/components/libraries/util/app_util.h +++ /dev/null @@ -1,234 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -/** @file - * - * @defgroup app_util Utility Functions and Definitions - * @{ - * @ingroup app_common - * - * @brief Various types and definitions available to all applications. - */ - -#ifndef APP_UTIL_H__ -#define APP_UTIL_H__ - -#include -#include -#include "compiler_abstraction.h" - -enum -{ - UNIT_0_625_MS = 625, /**< Number of microseconds in 0.625 milliseconds. */ - UNIT_1_25_MS = 1250, /**< Number of microseconds in 1.25 milliseconds. */ - UNIT_10_MS = 10000 /**< Number of microseconds in 10 milliseconds. */ -}; - -/**@brief Macro for doing static (i.e. compile time) assertion. - * - * @note If the assertion fails when compiling using Keil, the compiler will report error message - * "error: #94: the size of an array must be greater than zero" (while gcc will list the - * symbol static_assert_failed, making the error message more readable). - * If the supplied expression can not be evaluated at compile time, Keil will report - * "error: #28: expression must have a constant value". - * - * @note The macro is intentionally implemented not using do while(0), allowing it to be used - * outside function blocks (e.g. close to global type- and variable declarations). - * If used in a code block, it must be used before any executable code in this block. - * - * @param[in] EXPR Constant expression to be verified. - */ - -#if defined(__GNUC__) -#define STATIC_ASSERT(EXPR) typedef char __attribute__((unused)) static_assert_failed[(EXPR) ? 1 : -1] -#elif defined(__ICCARM__) -#define STATIC_ASSERT(EXPR) extern char static_assert_failed[(EXPR) ? 1 : -1] -#else -#define STATIC_ASSERT(EXPR) typedef char static_assert_failed[(EXPR) ? 1 : -1] -#endif - - -/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */ -typedef uint8_t uint16_le_t[2]; - -/**@brief type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */ -typedef uint8_t uint32_le_t[4]; - -/**@brief Byte array type. */ -typedef struct -{ - uint16_t size; /**< Number of array entries. */ - uint8_t * p_data; /**< Pointer to array entries. */ -} uint8_array_t; - -/**@brief Perform rounded integer division (as opposed to truncating the result). - * - * @param[in] A Numerator. - * @param[in] B Denominator. - * - * @return Rounded (integer) result of dividing A by B. - */ -#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B)) - -/**@brief Check if the integer provided is a power of two. - * - * @param[in] A Number to be tested. - * - * @return true if value is power of two. - * @return false if value not power of two. - */ -#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) ) - -/**@brief To convert milliseconds to ticks. - * @param[in] TIME Number of milliseconds to convert. - * @param[in] RESOLUTION Unit to be converted to in [us/ticks]. - */ -#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION)) - - -/**@brief Perform integer division, making sure the result is rounded up. - * - * @details One typical use for this is to compute the number of objects with size B is needed to - * hold A number of bytes. - * - * @param[in] A Numerator. - * @param[in] B Denominator. - * - * @return Integer result of dividing A by B, rounded up. - */ -#define CEIL_DIV(A, B) \ - /*lint -save -e573 */ \ - ((((A) - 1) / (B)) + 1) \ - /*lint -restore */ - -/**@brief Function for encoding a uint16 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8); - return sizeof(uint16_t); -} - -/**@brief Function for encoding a uint32 value. - * - * @param[in] value Value to be encoded. - * @param[out] p_encoded_data Buffer where the encoded data is to be written. - * - * @return Number of bytes written. - */ -static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data) -{ - p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0); - p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8); - p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16); - p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24); - return sizeof(uint32_t); -} - -/**@brief Function for decoding a uint16 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) | - (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 )); -} - -/**@brief Function for decoding a uint32 value. - * - * @param[in] p_encoded_data Buffer where the encoded data is stored. - * - * @return Decoded value. - */ -static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data) -{ - return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0) | - (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8) | - (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) | - (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 )); -} - -/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts. - * - * @details The calculation is based on a linearized version of the battery's discharge - * curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and - * is considered to be the lower boundary. - * - * The discharge curve for CR2032 is non-linear. In this model it is split into - * 4 linear sections: - * - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV) - * - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV) - * - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV) - * - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV) - * - * These numbers are by no means accurate. Temperature and - * load in the actual application is not accounted for! - * - * @param[in] mvolts The voltage in mV - * - * @return Battery level in percent. -*/ -static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts) -{ - uint8_t battery_level; - - if (mvolts >= 3000) - { - battery_level = 100; - } - else if (mvolts > 2900) - { - battery_level = 100 - ((3000 - mvolts) * 58) / 100; - } - else if (mvolts > 2740) - { - battery_level = 42 - ((2900 - mvolts) * 24) / 160; - } - else if (mvolts > 2440) - { - battery_level = 18 - ((2740 - mvolts) * 12) / 300; - } - else if (mvolts > 2100) - { - battery_level = 6 - ((2440 - mvolts) * 6) / 340; - } - else - { - battery_level = 0; - } - - return battery_level; -} - -/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary. - * - * @param[in] p Pointer value to be checked. - * - * @return TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise. - */ -static __INLINE bool is_word_aligned(void * p) -{ - return (((uintptr_t)p & 0x03) == 0); -} - -#endif // APP_UTIL_H__ - -/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt deleted file mode 100644 index b01ccf590e..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_licence_agreement.txt +++ /dev/null @@ -1,90 +0,0 @@ -S110/S120/S130 license agreement - -NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT - -License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120 and S130 Bluetooth SoftDevice software packages ("SoftDevice"). -You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before -downloading, installing and/or using any software or content in the SoftDevice provided herewith. - -YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS -OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF -THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS. - -IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE -INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE. - -1. Grant of License -Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license -("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated -in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this -agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit. - -2. Title -Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and -other intellectual property rights in and to the SoftDevice. - -3. No Modifications or Reverse Engineering -Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code -parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code. - -4. Distribution Restrictions -Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party. -Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein. -Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee -necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making -such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice. - -5. No Other Rights -Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be -contrary to this Agreement. - -6. Fees -Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to -comply with the Agreement. - -7. DISCLAIMER OF WARRANTY -THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS -LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR -THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE -IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE -REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE. -LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEE’S -INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT. - -8. No Support -Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how, -bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice. - -9. Limitation of Liability -In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of -procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any -special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract, -tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers, -licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or -limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliates’ liability shall be limited to -USD 50. - -10. Breach of Contract -Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably -attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both -direct and indirect costs for Nordic and its licensors. - -11. Indemnity -Licensee undertakes to indemnify, hold harmless and defend Nordic and its directors, officers, affiliates, shareholders, licensors, employees and -agents from and against any claims or lawsuits, including attorney's fees, that arise or result of the Licensee’s execution of the License and which -is not due to causes for which Nordic is responsible. - -12. Governing Law -This Agreement shall be construed according to the laws of Norway, and hereby submits to the exclusive jurisdiction of the Oslo tingrett. - -13. Assignment -Licensee shall not assign this Agreement or any rights or obligations hereunder without the prior written consent of Nordic. - -14. Termination -Without prejudice to any other rights, Nordic may cancel this Agreement if Licensee does not abide by the terms and conditions of this -Agreement. Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any -other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology. - -15. Third party beneficiaries -Nordic’s licensors are intended third party beneficiaries under this Agreement. \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex deleted file mode 100644 index 7551e41c5b..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s110_nrf51822_8_0_0/s110_nrf51822_8.0.0_softdevice.hex +++ /dev/null @@ -1,5649 +0,0 @@ -:020000040000FA -:10000000C0070000D1060000D1000000B1060000CA -:1000100000000000000000000000000000000000E0 -:100020000000000000000000000000005107000078 -:100030000000000000000000DB000000E500000000 -:10004000EF000000F9000000030100000D010000B6 -:1000500017010000210100002B0100003501000004 -:100060003F01000049010000530100005D01000054 -:1000700067010000710100007B01000085010000A4 -:100080008F01000099010000A3010000AD010000F4 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-:1068C00000000000000000000000000000000000C8 -:1068D00000000000000000000000000000000000B8 -:1068E00000000000000000000000000000000000A8 -:1068F0000000000000000000000000000000000098 -:106900000000000000000000196401000000000009 -:0869100000000000000000007F -:00000001FF diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_licence_agreement.txt b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_licence_agreement.txt deleted file mode 100644 index b01ccf590e..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_licence_agreement.txt +++ /dev/null @@ -1,90 +0,0 @@ -S110/S120/S130 license agreement - -NORDIC SEMICONDUCTOR ASA SOFTDEVICE LICENSE AGREEMENT - -License Agreement for the Nordic Semiconductor ASA ("Nordic") S110, S120 and S130 Bluetooth SoftDevice software packages ("SoftDevice"). -You ("You" "Licensee") must carefully and thoroughly read this License Agreement ("Agreement"), and accept to adhere to this Agreement before -downloading, installing and/or using any software or content in the SoftDevice provided herewith. - -YOU ACCEPT THIS LICENSE AGREEMENT BY (A) CLICKING ACCEPT OR AGREE TO THIS LICENSE AGREEMENT, WHERE THIS -OPTION IS MADE AVAILABLE TO YOU; OR (B) BY ACTUALLY USING THE SOFTDEVICE, IN THIS CASE YOU AGREE THAT THE USE OF -THE SOFTDEVICE CONSTITUTES ACCEPTANCE OF THE LICENSING AGREEMENT FROM THAT POINT ONWARDS. - -IF YOU DO NOT AGREE TO BE BOUND BY THE TERMS OF THIS AGREEMENT, THEN DO NOT DOWNLOAD, INSTALL/COMPLETE -INSTALLATION OF, OR IN ANY OTHER WAY MAKE USE OF THE SOFTDEVICE. - -1. Grant of License -Subject to the terms in this Agreement Nordic grants Licensee a limited, non-exclusive, non-transferable, non-sub licensable, revocable license -("License"): (a) to use the SoftDevice solely in connection with a Nordic integrated circuit, and (b) to distribute the SoftDevice solely as integrated -in Licensee Product. Licensee shall not use the SoftDevice for any purpose other than specifically authorized herein. It is a material breach of this -agreement to use or modify the SoftDevice for use on any wireless connectivity integrated circuit other than a Nordic integrated circuit. - -2. Title -Nordic retains full rights, title, and ownership to the SoftDevice and any and all patents, copyrights, trade secrets, trade names, trademarks, and -other intellectual property rights in and to the SoftDevice. - -3. No Modifications or Reverse Engineering -Licensee shall not, modify, reverse engineer, disassemble, decompile or otherwise attempt to discover the source code of any non-source code -parts of the SoftDevice including, but not limited to pre-compiled hex files, binaries and object code. - -4. Distribution Restrictions -Except as set forward in Section 1 above, the Licensee may not disclose or distribute any or all parts of the SoftDevice to any third party. -Licensee agrees to provide reasonable security precautions to prevent unauthorized access to or use of the SoftDevice as proscribed herein. -Licensee also agrees that use of and access to the SoftDevice will be strictly limited to the employees and subcontractors of the Licensee -necessary for the performance of development, verification and production tasks under this Agreement. The Licensee is responsible for making -such employees and subcontractors comply with the obligations concerning use and non-disclosure of the SoftDevice. - -5. No Other Rights -Licensee shall use the SoftDevice only in compliance with this Agreement and shall refrain from using the SoftDevice in any way that may be -contrary to this Agreement. - -6. Fees -Nordic grants the License to the Licensee free of charge provided that the Licensee undertakes the obligations in the Agreement and warrants to -comply with the Agreement. - -7. DISCLAIMER OF WARRANTY -THE SOFTDEVICE IS PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND EXPRESS OR IMPLIED AND NEITHER NORDIC, ITS -LICENSORS OR AFFILIATES NOR THE COPYRIGHT HOLDERS MAKE ANY REPRESENTATIONS OR WARRANTIES, EXPRESS OR -IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE OR -THAT THE SOFTDEVICE WILL NOT INFRINGE ANY THIRD PARTY PATENTS, COPYRIGHTS, TRADEMARKS OR OTHER RIGHTS. THERE -IS NO WARRANTY BY NORDIC OR BY ANY OTHER PARTY THAT THE FUNCTIONS CONTAINED IN THE SOFTDEVICE WILL MEET THE -REQUIREMENTS OF LICENSEE OR THAT THE OPERATION OF THE SOFTDEVICE WILL BE UNINTERRUPTED OR ERROR-FREE. -LICENSEE ASSUMES ALL RESPONSIBILITY AND RISK FOR THE SELECTION OF THE SOFTDEVICE TO ACHIEVE LICENSEE’S -INTENDED RESULTS AND FOR THE INSTALLATION, USE AND RESULTS OBTAINED FROM IT. - -8. No Support -Nordic is not obligated to furnish or make available to Licensee any further information, software, technical information, know-how, show-how, -bug-fixes or support. Nordic reserves the right to make changes to the SoftDevice without further notice. - -9. Limitation of Liability -In no event shall Nordic, its employees or suppliers, licensors or affiliates be liable for any lost profits, revenue, sales, data or costs of -procurement of substitute goods or services, property damage, personal injury, interruption of business, loss of business information or for any -special, direct, indirect, incidental, economic, punitive, special or consequential damages, however caused and whether arising under contract, -tort, negligence, or other theory of liability arising out of the use of or inability to use the SoftDevice, even if Nordic or its employees or suppliers, -licensors or affiliates are advised of the possibility of such damages. Because some countries/states/jurisdictions do not allow the exclusion or -limitation of liability, but may allow liability to be limited, in such cases, Nordic, its employees or licensors or affiliates’ liability shall be limited to -USD 50. - -10. Breach of Contract -Upon a breach of contract by the Licensee, Nordic and its licensor are entitled to damages in respect of any direct loss which can be reasonably -attributed to the breach by the Licensee. If the Licensee has acted with gross negligence or willful misconduct, the Licensee shall cover both -direct and indirect costs for Nordic and its licensors. - -11. Indemnity -Licensee undertakes to indemnify, hold harmless and defend Nordic and its directors, officers, affiliates, shareholders, licensors, employees and -agents from and against any claims or lawsuits, including attorney's fees, that arise or result of the Licensee’s execution of the License and which -is not due to causes for which Nordic is responsible. - -12. Governing Law -This Agreement shall be construed according to the laws of Norway, and hereby submits to the exclusive jurisdiction of the Oslo tingrett. - -13. Assignment -Licensee shall not assign this Agreement or any rights or obligations hereunder without the prior written consent of Nordic. - -14. Termination -Without prejudice to any other rights, Nordic may cancel this Agreement if Licensee does not abide by the terms and conditions of this -Agreement. Upon termination Licensee must promptly cease the use of the License and destroy all copies of the Licensed Technology and any -other material provided by Nordic or its affiliate, or produced by the Licensee in connection with the Agreement or the Licensed Technology. - -15. Third party beneficiaries -Nordic’s licensors are intended third party beneficiaries under this Agreement. \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex deleted file mode 100644 index 39d4e59629..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/Lib/s130_nrf51822_1_0_0/s130_nrf51_1.0.0_softdevice.hex +++ /dev/null @@ -1,6861 +0,0 @@ -:020000040000FA -:10000000C0070000D1060000D1000000B1060000CA -:1000100000000000000000000000000000000000E0 -:100020000000000000000000000000005107000078 -:100030000000000000000000DB000000E500000000 -:10004000EF000000F9000000030100000D010000B6 -:1000500017010000210100002B0100003501000004 -:100060003F01000049010000530100005D01000054 -:1000700067010000710100007B01000085010000A4 -:100080008F01000099010000A3010000AD010000F4 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-:10B460007006120DB413000014035A06A009000060 -:10B470006004F208840D0000A8B401000800002058 -:10B480001000000004110000B8B4010018000020F2 -:10B490006C0100000AB10100D8B401008401002051 -:10B4A0006C20000020110000024801688907FCD5CB -:10B4B0007047000000E200E0013536010001005451 -:10B4C0003720FB349B5F80B4800010026801337F1B -:08B4D0000102A029E449B101C9 -:00000001FF diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PeripheralNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PeripheralNames.h deleted file mode 100644 index 4a75b2d7a5..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PeripheralNames.h +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define STDIO_UART_TX TX_PIN_NUMBER -#define STDIO_UART_RX RX_PIN_NUMBER -#define STDIO_UART UART_0 - -typedef enum { - UART_0 = (int)NRF_UART0_BASE -} UARTName; - - -typedef enum { - SPI_0 = (int)NRF_SPI0_BASE, - SPI_1 = (int)NRF_SPI1_BASE, - SPIS = (int)NRF_SPIS1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2 -} PWMName; - -typedef enum { - I2C_0 = (int)NRF_TWI0_BASE, - I2C_1 = (int)NRF_TWI1_BASE -} I2CName; - -typedef enum { - ADC0_0 = (int)NRF_ADC_BASE -} ADCName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PortNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PortNames.h deleted file mode 100644 index 9196c20d8a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/PortNames.h +++ /dev/null @@ -1,30 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0 //GPIO pins 0-31 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h deleted file mode 100644 index 031b2ad26a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/PinNames.h +++ /dev/null @@ -1,153 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, -// p31=31, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - LED1 = p18, - LED2 = p19, - LED3 = p18, - LED4 = p19, - - BUTTON1 = p16, - BUTTON2 = p17, - - RX_PIN_NUMBER = p11, - TX_PIN_NUMBER = p9, - CTS_PIN_NUMBER = p10, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p20, - SPI_PSELMISO0 = p22, - SPI_PSELSS0 = p24, - SPI_PSELSCK0 = p25, - - SPI_PSELMOSI1 = p12, - SPI_PSELMISO1 = p13, - SPI_PSELSS1 = p14, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p12, - SPIS_PSELMISO = p13, - SPIS_PSELSS = p14, - SPIS_PSELSCK = p15, - - I2C_SDA0 = p22, - I2C_SCL0 = p20, - - I2C_SDA1 = p13, - I2C_SCL1 = p15, - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h deleted file mode 100644 index 17cccb19bf..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_MKIT/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'provides' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'provides' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h deleted file mode 100644 index cc9ad70e58..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/PinNames.h +++ /dev/null @@ -1,106 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p5 = 5, - p8 = 8, - p9 = 9, - p11 = 11, - p12 = 12, - p15 = 15, - p16 = 16, - p18 = 18, - p20 = 20, - p21 = 21, - p24 = 24, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_5 = p5, - - P0_8 = p8, - P0_9 = p9, - P0_11 = p11, - P0_12 = p12, - P0_15 = p15, - - P0_16 = p16, - P0_18 = p18, - P0_20 = p20, - P0_21 = p21, - - P0_24 = p24, - - LED1 = p16, - LED2 = p12, - LED3 = p15, - LEDR = LED1, - LEDG = LED2, - LEDB = LED3, - - BUTTON1 = p8, - BUTTON2 = p18, - - RX_PIN_NUMBER = p21, - TX_PIN_NUMBER = p24, - CTS_PIN_NUMBER = p0, - RTS_PIN_NUMBER = p20, - - SPI_PSELMOSI0 = p2, - SPI_PSELMISO0 = p5, - SPI_PSELSS0 = p1, - SPI_PSELSCK0 = p3, - - I2C_SDA0 = p9, - I2C_SCL0 = p11, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h deleted file mode 100644 index 9d5a5e2109..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51822_SBKIT/device.h +++ /dev/null @@ -1,57 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - -#define DEVICE_PORTIN 1 -#define DEVICE_PORTOUT 1 -#define DEVICE_PORTINOUT 1 - -#define DEVICE_INTERRUPTIN 1 - -#define DEVICE_ANALOGIN 1 -#define DEVICE_ANALOGOUT 0 - -#define DEVICE_SERIAL 1 - -#define DEVICE_I2C 1 -#define DEVICE_I2CSLAVE 0 - -#define DEVICE_SPI 1 -#define DEVICE_SPISLAVE 1 - -#define DEVICE_CAN 0 - -#define DEVICE_RTC 0 - -#define DEVICE_ETHERNET 0 - -#define DEVICE_PWMOUT 1 - -#define DEVICE_SEMIHOST 0 -#define DEVICE_LOCALFILESYSTEM 0 - -#define DEVICE_SLEEP 1 - -#define DEVICE_DEBUG_AWARENESS 0 - -#define DEVICE_STDIO_MESSAGES 0 - -#define DEVICE_ERROR_PATTERN 1 - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/PinNames.h deleted file mode 100644 index be8ff8b4cf..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/PinNames.h +++ /dev/null @@ -1,178 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - LED1 = p21, - LED2 = p22, - LED3 = p23, - LED4 = p24, - - BUTTON1 = p17, - BUTTON2 = p18, - BUTTON3 = p19, - BUTTON4 = p20, - - RX_PIN_NUMBER = p11, - TX_PIN_NUMBER = p9, - CTS_PIN_NUMBER = p10, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p25, - SPI_PSELMISO0 = p28, - SPI_PSELSS0 = p24, - SPI_PSELSCK0 = p29, - - SPI_PSELMOSI1 = p13, - SPI_PSELMISO1 = p14, - SPI_PSELSS1 = p12, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p13, - SPIS_PSELMISO = p14, - SPIS_PSELSS = p12, - SPIS_PSELSCK = p15, - - I2C_SDA0 = p30, - I2C_SCL0 = p7, - - D0 = p12, - D1 = p13, - D2 = p14, - D3 = p15, - D4 = p16, - D5 = p17, - D6 = p18, - D7 = p19, - - D8 = p20, - D9 = p23, - D10 = p24, - D11 = p25, - D12 = p28, - D13 = p29, - - D14 = p30, - D15 = p7, - - A0 = p1, - A1 = p2, - A2 = p3, - A3 = p4, - A4 = p5, - A5 = p6, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/device.h deleted file mode 100644 index 2427e752ea..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_DK/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/PinNames.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/PinNames.h deleted file mode 100644 index b2f1583cdb..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/PinNames.h +++ /dev/null @@ -1,184 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -#define PORT_SHIFT 3 - -typedef enum { - //MCU PINS - P0_0 = 0, - P0_1 = 1, - P0_2 = 2, - P0_3 = 3, - P0_4 = 4, - P0_5 = 5, - P0_6 = 6, - P0_7 = 7, - P0_8 = 8, - P0_9 = 9, - P0_10 = 10, - P0_11 = 11, - P0_12 = 12, - P0_13 = 13, - P0_14 = 14, - P0_15 = 15, - P0_16 = 16, - P0_17 = 17, - P0_18 = 18, - P0_19 = 19, - P0_20 = 20, - P0_21 = 21, - P0_22 = 22, - P0_23 = 23, - P0_24 = 24, - P0_25 = 25, - P0_26 = 26, - P0_27 = 27, - P0_28 = 28, - P0_29 = 29, - P0_30 = 30, - - //MICROBIT EDGE CONNECTOR PINS - P0 = P0_3, - P1 = P0_2, - P2 = P0_1, - P3 = P0_4, - P4 = P0_5, - P5 = P0_17, - P6 = P0_12, - P7 = P0_11, - P8 = P0_18, - P9 = P0_10, - P10 = P0_6, - P11 = P0_26, - P12 = P0_20, - P13 = P0_23, - P14 = P0_22, - P15 = P0_21, - P16 = P0_16, - P19 = P0_0, - P20 = P0_30, - - //PADS - PAD3 = P0_1, - PAD2 = P0_2, - PAD1 = P0_3, - - - //LED MATRIX COLS - COL1 = P0_4, - COL2 = P0_5, - COL3 = P0_6, - COL4 = P0_7, - COL5 = P0_8, - COL6 = P0_9, - COL7 = P0_10, - COL8 = P0_11, - COL9 = P0_12, - - //LED MATRIX ROWS - ROW1 = P0_13, - ROW2 = P0_14, - ROW3 = P0_15, - - //NORMAL PIN (NO SPECIFIED FUNCTIONALITY) - //PIN_16 - - // BUTTON A - BUTTON_A = P0_17, - - - //NORMAL PIN (NO SPECIFIED FUNCTIONALITY) - //PIN_18 - - //TARGET RESET - TGT_NRESET = P0_19, - - //NORMAL PIN (NO SPECIFIED FUNCTIONALITY) - //PIN_20 - - //MASTER OUT SLAVE IN - MOSI = P0_21, - - //MASTER IN SLAVE OUT - MISO = P0_22, - - //SERIAL CLOCK - SCK = P0_23, - - // RX AND TX PINS - TGT_TX = P0_24, - TGT_RX = P0_25, - - //BUTTON B - BUTTON_B = P0_26, - - //ACCEL INTERRUPT PINS (MMA8653FC) - ACCEL_INT2 = P0_27, - ACCEL_INT1 = P0_28, - - //MAGENETOMETER INTERRUPT PIN (MAG3110) - MAG_INT1 = P0_29, - - // Not connected - NC = (int)0xFFFFFFFF, - - RX_PIN_NUMBER = TGT_RX, - TX_PIN_NUMBER = TGT_TX, - CTS_PIN_NUMBER = 31, //unused ** REQUIRES A PROPER FIX ** - RTS_PIN_NUMBER = 31, //unused - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - LED1 = PAD1, - LED2 = PAD2, - LED3 = PAD3, - LED4 = P0_16, - - //SDA (SERIAL DATA LINE) - I2C_SDA0 = P0_30, - - //SCL (SERIAL CLOCK LINE) - I2C_SCL0 = P0_0 - -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/device.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/device.h deleted file mode 100644 index 2427e752ea..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/TARGET_NRF51_MICROBIT/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c deleted file mode 100644 index acfef12aff..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/analogin_api.c +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "cmsis.h" -#include "pinmap.h" - -#define ANALOGIN_MEDIAN_FILTER 1 -#define ADC_10BIT_RANGE 0x3FF -#define ADC_RANGE ADC_10BIT_RANGE - -static const PinMap PinMap_ADC[] = { - {P0_1, ADC0_0, 4}, - {P0_2, ADC0_0, 8}, - {P0_3, ADC0_0, 16}, - {P0_4, ADC0_0, 32}, - {P0_5, ADC0_0, 64}, - {P0_6, ADC0_0, 128}, - {P0_26, ADC0_0, 1}, - {P0_27, ADC0_0, 2}, - {NC, NC, 0} -}; - -void analogin_init(analogin_t *obj, PinName pin) -{ - int analogInputPin = 0; - const PinMap *map = PinMap_ADC; - - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); //(NRF_ADC_Type *) - MBED_ASSERT(obj->adc != (ADCName)NC); - - while (map->pin != NC) { - if (map->pin == pin) { - analogInputPin = map->function; - break; - } - map++; - } - obj->adc_pin = (uint8_t)analogInputPin; - - NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled; - NRF_ADC->CONFIG = (ADC_CONFIG_RES_10bit << ADC_CONFIG_RES_Pos) | - (ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling << ADC_CONFIG_INPSEL_Pos) | - (ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling << ADC_CONFIG_REFSEL_Pos) | - (analogInputPin << ADC_CONFIG_PSEL_Pos) | - (ADC_CONFIG_EXTREFSEL_None << ADC_CONFIG_EXTREFSEL_Pos); -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - NRF_ADC->CONFIG &= ~ADC_CONFIG_PSEL_Msk; - NRF_ADC->CONFIG |= obj->adc_pin << ADC_CONFIG_PSEL_Pos; - NRF_ADC->EVENTS_END = 0; - NRF_ADC->TASKS_START = 1; - - while (!NRF_ADC->EVENTS_END) { - } - - return (uint16_t)NRF_ADC->RESULT; // 10 bit -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - return (float)value * (1.0f / (float)ADC_RANGE); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S deleted file mode 100644 index fd2c2bbf8c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S +++ /dev/null @@ -1,186 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2013 Nordic Semiconductor. -;Licensed under the Apache License, Version 2.0 (the "License"); -;you may not use this file except in compliance with the License. -;You may obtain a copy of the License at -;http://www.apache.org/licenses/LICENSE-2.0 -;Unless required by applicable law or agreed to in writing, software -;distributed under the License is distributed on an "AS IS" BASIS, -;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;See the License for the specific language governing permissions and -;limitations under the License. - -; Description message - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler ;UART0 - DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler ;GPIOTE - DCD ADC_IRQHandler ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler ;TIMER1 - DCD TIMER2_IRQHandler ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler ;WDT - DCD RTC1_IRQHandler ;RTC1 - DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler ;SWI1 - DCD SWI2_IRQHandler ;SWI2 - DCD SWI3_IRQHandler ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk - ORRS R2, R2, R1 - STR R2, [R0] - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT SPI0_TWI0_IRQHandler [WEAK] - EXPORT SPI1_TWI1_IRQHandler [WEAK] - EXPORT GPIOTE_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT RTC1_IRQHandler [WEAK] - EXPORT QDEC_IRQHandler [WEAK] - EXPORT LPCOMP_COMP_IRQHandler [WEAK] - EXPORT SWI0_IRQHandler [WEAK] - EXPORT SWI1_IRQHandler [WEAK] - EXPORT SWI2_IRQHandler [WEAK] - EXPORT SWI3_IRQHandler [WEAK] - EXPORT SWI4_IRQHandler [WEAK] - EXPORT SWI5_IRQHandler [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UART0_IRQHandler -SPI0_TWI0_IRQHandler -SPI1_TWI1_IRQHandler -GPIOTE_IRQHandler -ADC_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -RTC0_IRQHandler -TEMP_IRQHandler -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler -RTC1_IRQHandler -QDEC_IRQHandler -LPCOMP_COMP_IRQHandler -SWI0_IRQHandler -SWI1_IRQHandler -SWI2_IRQHandler -SWI3_IRQHandler -SWI4_IRQHandler -SWI5_IRQHandler - - B . - ENDP - ALIGN - END - diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct deleted file mode 100644 index b063955385..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct +++ /dev/null @@ -1,30 +0,0 @@ -#! armcc -E - -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00008000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x1C000 0x0024000 { - ER_IROM1 0x1C000 0x0024000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20002800 0x00005800 { - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20002800+0x00005800 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S deleted file mode 100644 index 1b33dc34ec..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S +++ /dev/null @@ -1,195 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2013 Nordic Semiconductor. -;Licensed under the Apache License, Version 2.0 (the "License"); -;you may not use this file except in compliance with the License. -;You may obtain a copy of the License at -;http://www.apache.org/licenses/LICENSE-2.0 -;Unless required by applicable law or agreed to in writing, software -;distributed under the License is distributed on an "AS IS" BASIS, -;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;See the License for the specific language governing permissions and -;limitations under the License. - -; Description message - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler ;UART0 - DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler ;GPIOTE - DCD ADC_IRQHandler ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler ;TIMER1 - DCD TIMER2_IRQHandler ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler ;WDT - DCD RTC1_IRQHandler ;RTC1 - DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_IRQHandler ;LPCOMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler ;SWI1 - DCD SWI2_IRQHandler ;SWI2 - DCD SWI3_IRQHandler ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address -NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk - - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - ORRS R2, R2, R1 - STR R2, [R0] - - LDR R0, =NRF_POWER_RAMONB_ADDRESS - LDR R2, [R0] - ORRS R2, R2, R1 - STR R2, [R0] - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT SPI0_TWI0_IRQHandler [WEAK] - EXPORT SPI1_TWI1_IRQHandler [WEAK] - EXPORT GPIOTE_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT TIMER2_IRQHandler [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler [WEAK] - EXPORT RTC1_IRQHandler [WEAK] - EXPORT QDEC_IRQHandler [WEAK] - EXPORT LPCOMP_IRQHandler [WEAK] - EXPORT SWI0_IRQHandler [WEAK] - EXPORT SWI1_IRQHandler [WEAK] - EXPORT SWI2_IRQHandler [WEAK] - EXPORT SWI3_IRQHandler [WEAK] - EXPORT SWI4_IRQHandler [WEAK] - EXPORT SWI5_IRQHandler [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UART0_IRQHandler -SPI0_TWI0_IRQHandler -SPI1_TWI1_IRQHandler -GPIOTE_IRQHandler -ADC_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -TIMER2_IRQHandler -RTC0_IRQHandler -TEMP_IRQHandler -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler -RTC1_IRQHandler -QDEC_IRQHandler -LPCOMP_IRQHandler -SWI0_IRQHandler -SWI1_IRQHandler -SWI2_IRQHandler -SWI3_IRQHandler -SWI4_IRQHandler -SWI5_IRQHandler - - B . - ENDP - ALIGN - END - diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct deleted file mode 100644 index 1a3cd8ec11..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct +++ /dev/null @@ -1,30 +0,0 @@ -#! armcc -E - -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00004000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x18000 0x0028000 { - ER_IROM1 0x18000 0x0028000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20002000 0x00002000 { - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20002000+0x00002000 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct deleted file mode 100644 index acdeb8ba15..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct +++ /dev/null @@ -1,30 +0,0 @@ -#! armcc -E - -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00004000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x1C000 0x0024000 { - ER_IROM1 0x1C000 0x0024000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM1 0x20002800 0x00001800 { - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20002800+0x00001800 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld deleted file mode 100644 index 88357ce3e9..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x800 -#endif - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000 - RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0x5800 -} - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - __HeapBase = .; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld deleted file mode 100644 index 98c31c677f..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x800 -#endif - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000 - RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 -} - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - __HeapBase = .; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld deleted file mode 100644 index b342ad8db0..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x800 -#endif - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000 - RAM (rwx) : ORIGIN = 0x20002800, LENGTH = 0x1800 -} - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - __HeapBase = .; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S deleted file mode 100644 index f9a7f9fb35..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S +++ /dev/null @@ -1,243 +0,0 @@ -/* -Copyright (c) 2013, Nordic Semiconductor ASA -All rights reserved. - -Redistribution and use in source and binary forms, with or without -modification, are permitted provided that the following conditions are met: - -* Redistributions of source code must retain the above copyright notice, this - list of conditions and the following disclaimer. - -* Redistributions in binary form must reproduce the above copyright notice, - this list of conditions and the following disclaimer in the documentation - and/or other materials provided with the distribution. - -* Neither the name of Nordic Semiconductor ASA nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - -THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -*/ - -/* -NOTE: Template files (including this one) are application specific and therefore -expected to be copied into the application project folder prior to its use! -*/ - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 - .globl __StackTop - .globl __StackLimit -__StackLimit: - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 - .globl __HeapBase - .globl __HeapLimit - - .section .Vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long POWER_CLOCK_IRQHandler /*POWER_CLOCK */ - .long RADIO_IRQHandler /*RADIO */ - .long UART0_IRQHandler /*UART0 */ - .long SPI0_TWI0_IRQHandler /*SPI0_TWI0 */ - .long SPI1_TWI1_IRQHandler /*SPI1_TWI1 */ - .long 0 /*Reserved */ - .long GPIOTE_IRQHandler /*GPIOTE */ - .long ADC_IRQHandler /*ADC */ - .long TIMER0_IRQHandler /*TIMER0 */ - .long TIMER1_IRQHandler /*TIMER1 */ - .long TIMER2_IRQHandler /*TIMER2 */ - .long RTC0_IRQHandler /*RTC0 */ - .long TEMP_IRQHandler /*TEMP */ - .long RNG_IRQHandler /*RNG */ - .long ECB_IRQHandler /*ECB */ - .long CCM_AAR_IRQHandler /*CCM_AAR */ - .long WDT_IRQHandler /*WDT */ - .long RTC1_IRQHandler /*RTC1 */ - .long QDEC_IRQHandler /*QDEC */ - .long LPCOMP_IRQHandler /*LPCOMP */ - .long SWI0_IRQHandler /*SWI0 */ - .long SWI1_IRQHandler /*SWI1 */ - .long SWI2_IRQHandler /*SWI2 */ - .long SWI3_IRQHandler /*SWI3 */ - .long SWI4_IRQHandler /*SWI4 */ - .long SWI5_IRQHandler /*SWI5 */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - .long 0 /*Reserved */ - - - .size __Vectors, . - __Vectors - -/* Reset Handler */ - - .equ NRF_POWER_RAMON_ADDRESS, 0x40000524 - .equ NRF_POWER_RAMON_RAMxON_ONMODE_Msk, 0x3 - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - .fnstart - -/* Make sure ALL RAM banks are powered on */ - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk - ORRS R2, R1 - STR R2, [R0] - -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC0 - -.LC1: - subs r3, 4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .LC1 -.LC0: - - LDR R0, =SystemInit - BLX R0 - LDR R0, =_start - BX R0 - - .pool - .cantunwind - .fnend - .size Reset_Handler,.-Reset_Handler - - .section ".text" - - -/* Dummy Exception Handlers (infinite loops which can be modified) */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler - IRQ RADIO_IRQHandler - IRQ UART0_IRQHandler - IRQ SPI0_TWI0_IRQHandler - IRQ SPI1_TWI1_IRQHandler - IRQ GPIOTE_IRQHandler - IRQ ADC_IRQHandler - IRQ TIMER0_IRQHandler - IRQ TIMER1_IRQHandler - IRQ TIMER2_IRQHandler - IRQ RTC0_IRQHandler - IRQ TEMP_IRQHandler - IRQ RNG_IRQHandler - IRQ ECB_IRQHandler - IRQ CCM_AAR_IRQHandler - IRQ WDT_IRQHandler - IRQ RTC1_IRQHandler - IRQ QDEC_IRQHandler - IRQ LPCOMP_IRQHandler - IRQ SWI0_IRQHandler - IRQ SWI1_IRQHandler - IRQ SWI2_IRQHandler - IRQ SWI3_IRQHandler - IRQ SWI4_IRQHandler - IRQ SWI5_IRQHandler - - - .end diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf deleted file mode 100644 index a269934a6c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf +++ /dev/null @@ -1,46 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00016000; -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x900; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __code_start_soft_device__ = 0x0; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, - block HEAP }; - -/*This is used for mbed applications build inside the Embedded workbench -Applications build with the python scritps use a hex merge so need to merge it -inside the linker. The linker can only use binary files so the hex merge is not possible -through the linker. That is why a binary is used instead of a hex image for the embedded project. -*/ -if(isdefinedsymbol(SOFT_DEVICE_BIN)) -{ - place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; -} \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S deleted file mode 100644 index b1e263009c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S +++ /dev/null @@ -1,237 +0,0 @@ -;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. -;; The information contained herein is confidential property of Nordic -;; Semiconductor ASA.Terms and conditions of usage are described in detail -;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. -;; Licensees are granted free, non-transferable use of the information. NO -;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from -;; the file. - -;; Description message - - MODULE ?cstartup - - ;; Stack size default : 1024 - ;; Heap size default : 2048 - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -;__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler ;UART0 - DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler ;GPIOTE - DCD ADC_IRQHandler ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler ;TIMER1 - DCD TIMER2_IRQHandler ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler ;WDT - DCD RTC1_IRQHandler ;RTC1 - DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler ;SWI1 - DCD SWI2_IRQHandler ;SWI2 - DCD SWI3_IRQHandler ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk - ORRS R2, R2, R1 - STR R2, [R0] - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RADIO_IRQHandler - B . - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler - B . - PUBWEAK SPI0_TWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI0_TWI0_IRQHandler - B . - PUBWEAK SPI1_TWI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_TWI1_IRQHandler - B . - PUBWEAK GPIOTE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIOTE_IRQHandler - B . - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B . - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B . - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B . - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B . - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC0_IRQHandler - B . - PUBWEAK TEMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TEMP_IRQHandler - B . - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B . - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ECB_IRQHandler - B . - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCM_AAR_IRQHandler - B . - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler - B . - PUBWEAK RTC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC1_IRQHandler - B . - PUBWEAK QDEC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QDEC_IRQHandler - B . - PUBWEAK LPCOMP_COMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LPCOMP_COMP_IRQHandler - B . - PUBWEAK SWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI0_IRQHandler - B . - PUBWEAK SWI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI1_IRQHandler - B . - PUBWEAK SWI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI2_IRQHandler - B . - PUBWEAK SWI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI3_IRQHandler - B . - PUBWEAK SWI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI4_IRQHandler - B . - PUBWEAK SWI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI5_IRQHandler - B . - - - END diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf deleted file mode 100644 index 14274a6f2d..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf +++ /dev/null @@ -1,46 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x00016000; -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x000160c0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20002000; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x1800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __code_start_soft_device__ = 0x0; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block CSTACK, - block HEAP }; - -/*This is used for mbed applications build inside the Embedded workbench -Applications build with the python scritps use a hex merge so need to merge it -inside the linker. The linker can only use binary files so the hex merge is not possible -through the linker. That is why a binary is used instead of a hex image for the embedded project. -*/ -if(isdefinedsymbol(SOFT_DEVICE_BIN)) -{ - place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S deleted file mode 100644 index c0a2b08eab..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S +++ /dev/null @@ -1,237 +0,0 @@ -;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. -;; The information contained herein is confidential property of Nordic -;; Semiconductor ASA.Terms and conditions of usage are described in detail -;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. -;; Licensees are granted free, non-transferable use of the information. NO -;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from -;; the file. - -;; Description message - - MODULE ?cstartup - - ;; Stack size default : 1024 - ;; Heap size default : 2048 - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -;__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler ;UART0 - DCD SPI0_TWI0_IRQHandler ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler ;GPIOTE - DCD ADC_IRQHandler ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler ;TIMER1 - DCD TIMER2_IRQHandler ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler ;WDT - DCD RTC1_IRQHandler ;RTC1 - DCD QDEC_IRQHandler ;QDEC - DCD LPCOMP_COMP_IRQHandler ;LPCOMP_COMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler ;SWI1 - DCD SWI2_IRQHandler ;SWI2 - DCD SWI3_IRQHandler ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk - ORRS R2, R2, R1 - STR R2, [R0] - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RADIO_IRQHandler - B . - PUBWEAK UART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler - B . - PUBWEAK SPI0_TWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI0_TWI0_IRQHandler - B . - PUBWEAK SPI1_TWI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_TWI1_IRQHandler - B . - PUBWEAK GPIOTE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIOTE_IRQHandler - B . - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B . - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B . - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B . - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B . - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC0_IRQHandler - B . - PUBWEAK TEMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TEMP_IRQHandler - B . - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B . - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ECB_IRQHandler - B . - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCM_AAR_IRQHandler - B . - PUBWEAK WDT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler - B . - PUBWEAK RTC1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC1_IRQHandler - B . - PUBWEAK QDEC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QDEC_IRQHandler - B . - PUBWEAK LPCOMP_COMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LPCOMP_COMP_IRQHandler - B . - PUBWEAK SWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI0_IRQHandler - B . - PUBWEAK SWI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI1_IRQHandler - B . - PUBWEAK SWI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI2_IRQHandler - B . - PUBWEAK SWI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI3_IRQHandler - B . - PUBWEAK SWI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI4_IRQHandler - B . - PUBWEAK SWI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI5_IRQHandler - B . - - - END \ No newline at end of file diff --git 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zosR0llS;MYD`GWGi*`T%CID_OK1sEwDI<0rYVRP8J2*;_uO;OuaE5dKKqj}&GxZPEXb~BWvq}1 z409|Tul(D2Wdsu?3os11d5oR7Q($-p3cUhLK4WKbUWD^asOH=Tfn{$L0JvvLb}1r} zE(XL3S#x->vTR_GVVt%-f3JCf9a|zU6;=zl__;O8%*ulgg|~&7LktOLmNg6i2d>3J A-2eap diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis.h deleted file mode 100644 index b73fdadde8..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC407x_8x specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "nrf.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.c deleted file mode 100644 index 5fe8d89d6f..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.c +++ /dev/null @@ -1,103 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -/* In the M0, there is no VTOR. In the LPC range such as the LPC11U, - * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), - * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF - * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0 - * - * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH - * above the vector table before 0x200 will actually go to RAM. So we need to provide - * a solution where the compiler gets the right results based on the memory map - * - * Option 1 - We allocate and copy 0x200 of RAM rather than just the table - * - const data and instructions before 0x200 will be copied to and fetched/exec from RAM - * - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0 - * - * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there - * - No flash accesses will go to ram, as there will be nothing there - * - RAM only needs to be allocated for the vectors, as all other ram addresses are normal - * - RAM overhead: 0, FLASH overhead: 320 bytes - * - * Option 2 is the one to go for, as RAM is the most valuable resource - */ - - -#define NVIC_RAM_VECTOR_ADDRESS (0x10000000) // Location of vectors in RAM -#define NVIC_FLASH_VECTOR_ADDRESS (0x0) // Initial vector position in flash -/* -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - uint32_t i; - - // Copy and switch to dynamic vectors if the first time called - if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) { - uint32_t *old_vectors = vectors; - vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - for (i=0; iVTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS; - } - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - uint32_t *vectors = (uint32_t*)SCB->VTOR; - return vectors[IRQn + 16]; -}*/ - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) { - // int i; - // Space for dynamic vectors, initialised to allocate in R/W - static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS; - /* - // Copy and switch to dynamic vectors if first time called - if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) { - uint32_t *old_vectors = (uint32_t *)0; // FLASH vectors are at 0x0 - for(i = 0; i < NVIC_NUM_VECTORS; i++) { - vectors[i] = old_vectors[i]; - } - LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block - }*/ - - // Set the vector - vectors[IRQn + 16] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) { - // We can always read vectors at 0x0, as the addresses are remapped - uint32_t *vectors = (uint32_t*)0; - - // Return the vector - return vectors[IRQn + 16]; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.h deleted file mode 100644 index ab365b2a79..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/cmsis_nvic.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "nrf51.h" -#include "cmsis.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/compiler_abstraction.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/compiler_abstraction.h deleted file mode 100644 index 18d70eb207..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/compiler_abstraction.h +++ /dev/null @@ -1,109 +0,0 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef _COMPILER_ABSTRACTION_H -#define _COMPILER_ABSTRACTION_H - -/*lint ++flb "Enter library region" */ - -#if defined ( __CC_ARM ) - - #ifndef __ASM - #define __ASM __asm /*!< asm keyword for ARM Compiler */ - #endif - - #ifndef __INLINE - #define __INLINE __inline /*!< inline keyword for ARM Compiler */ - #endif - - #ifndef __WEAK - #define __WEAK __weak /*!< weak keyword for ARM Compiler */ - #endif - - #define GET_SP() __current_sp() /*!> read current SP function for ARM Compiler */ - -#elif defined ( __ICCARM__ ) - - #ifndef __ASM - #define __ASM __asm /*!< asm keyword for IAR Compiler */ - #endif - - #ifndef __INLINE - #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ - #endif - - #ifndef __WEAK - #define __WEAK __weak /*!> define weak function for IAR Compiler */ - #endif - - #define GET_SP() __get_SP() /*!> read current SP function for IAR Compiler */ - -#elif defined ( __GNUC__ ) - - #ifndef __ASM - #define __ASM __asm /*!< asm keyword for GNU Compiler */ - #endif - - #ifndef __INLINE - #define __INLINE inline /*!< inline keyword for GNU Compiler */ - #endif - - #ifndef __WEAK - #define __WEAK __attribute__((weak)) /*!< weak keyword for GNU Compiler */ - #endif - - #define GET_SP() gcc_current_sp() /*!> read current SP function for GNU Compiler */ - - static inline unsigned int gcc_current_sp(void) - { - register unsigned sp asm("sp"); - return sp; - } - -#elif defined ( __TASKING__ ) - - #ifndef __ASM - #define __ASM __asm /*!< asm keyword for TASKING Compiler */ - #endif - - #ifndef __INLINE - #define __INLINE inline /*!< inline keyword for TASKING Compiler */ - #endif - - #ifndef __WEAK - #define __WEAK __attribute__((weak)) /*!< weak keyword for TASKING Compiler */ - #endif - - #define GET_SP() __get_MSP() /*!> read current SP function for TASKING Compiler */ - -#endif - -/*lint --flb "Leave library region" */ - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf.h deleted file mode 100644 index 195a356f73..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF_H -#define NRF_H - -#if defined(_WIN32) - /* Do not include nrf51 specific files when building for PC host */ -#elif defined(__unix) - /* Do not include nrf51 specific files when building for PC host */ -#elif defined(__APPLE__) - /* Do not include nrf51 specific files when building for PC host */ -#else - - /* Family selection for family includes. */ - #if defined (NRF51) - #include "nrf51.h" - #include "nrf51_bitfields.h" - #include "nrf51_deprecated.h" - #elif defined (NRF52) - #include "nrf52.h" - #include "nrf52_bitfields.h" - #include "nrf51_to_nrf52.h" - #else - #error "Device family must be defined. See nrf.h." - #endif /* NRF51, NRF52 */ - - #include "compiler_abstraction.h" - -#endif /* _WIN32 || __unix || __APPLE__ */ - -#endif /* NRF_H */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51.h deleted file mode 100644 index cd72adea8e..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51.h +++ /dev/null @@ -1,1262 +0,0 @@ -/* - * Copyright (c) Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF51_H -#define NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - - -/* ------------------------- Interrupt Number Definition ------------------------ */ - -typedef enum { -/* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */ - Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */ - NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */ - HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */ - SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */ - DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */ - PendSV_IRQn = -2, /*!< 14 Pendable request for system service */ - SysTick_IRQn = -1, /*!< 15 System Tick Timer */ -/* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */ - POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */ - RADIO_IRQn = 1, /*!< 1 RADIO */ - UART0_IRQn = 2, /*!< 2 UART0 */ - SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */ - SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */ - GPIOTE_IRQn = 6, /*!< 6 GPIOTE */ - ADC_IRQn = 7, /*!< 7 ADC */ - TIMER0_IRQn = 8, /*!< 8 TIMER0 */ - TIMER1_IRQn = 9, /*!< 9 TIMER1 */ - TIMER2_IRQn = 10, /*!< 10 TIMER2 */ - RTC0_IRQn = 11, /*!< 11 RTC0 */ - TEMP_IRQn = 12, /*!< 12 TEMP */ - RNG_IRQn = 13, /*!< 13 RNG */ - ECB_IRQn = 14, /*!< 14 ECB */ - CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */ - WDT_IRQn = 16, /*!< 16 WDT */ - RTC1_IRQn = 17, /*!< 17 RTC1 */ - QDEC_IRQn = 18, /*!< 18 QDEC */ - LPCOMP_IRQn = 19, /*!< 19 LPCOMP */ - SWI0_IRQn = 20, /*!< 20 SWI0 */ - SWI1_IRQn = 21, /*!< 21 SWI1 */ - SWI2_IRQn = 22, /*!< 22 SWI2 */ - SWI3_IRQn = 23, /*!< 23 SWI3 */ - SWI4_IRQn = 24, /*!< 24 SWI4 */ - SWI5_IRQn = 25 /*!< 25 SWI5 */ -} IRQn_Type; - - -/** @addtogroup Configuration_of_CMSIS - * @{ - */ - - -/* ================================================================================ */ -/* ================ Processor and Core Peripheral Section ================ */ -/* ================================================================================ */ - -/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */ -#define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */ -#define __MPU_PRESENT 0 /*!< MPU present or not */ -#define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */ -#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ -/** @} */ /* End of group Configuration_of_CMSIS */ - -#include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */ -#include "system_nrf51.h" /*!< nrf51 System */ - - -/* ================================================================================ */ -/* ================ Device Specific Peripheral Section ================ */ -/* ================================================================================ */ - - -/** @addtogroup Device_Peripheral_Registers - * @{ - */ - - -/* ------------------- Start of section using anonymous unions ------------------ */ -#if defined(__CC_ARM) - #pragma push - #pragma anon_unions -#elif defined(__ICCARM__) - #pragma language=extended -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) -/* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning 586 -#else - #warning Not supported compiler type -#endif - - -typedef struct { - __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */ - __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */ - __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */ - __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */ - __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */ - __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */ -} AMLI_RAMPRI_Type; - -typedef struct { - __IO uint32_t SCK; /*!< Pin select for SCK. */ - __IO uint32_t MOSI; /*!< Pin select for MOSI. */ - __IO uint32_t MISO; /*!< Pin select for MISO. */ -} SPIM_PSEL_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer. */ - __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */ - __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */ -} SPIM_RXD_Type; - -typedef struct { - __IO uint32_t PTR; /*!< Data pointer. */ - __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */ - __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */ -} SPIM_TXD_Type; - -typedef struct { - __O uint32_t EN; /*!< Enable channel group. */ - __O uint32_t DIS; /*!< Disable channel group. */ -} PPI_TASKS_CHG_Type; - -typedef struct { - __IO uint32_t EEP; /*!< Channel event end-point. */ - __IO uint32_t TEP; /*!< Channel task end-point. */ -} PPI_CH_Type; - - -/* ================================================================================ */ -/* ================ POWER ================ */ -/* ================================================================================ */ - - -/** - * @brief Power Control. (POWER) - */ - -typedef struct { /*!< POWER Structure */ - __I uint32_t RESERVED0[30]; - __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */ - __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */ - __I uint32_t RESERVED1[34]; - __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __IO uint32_t RESETREAS; /*!< Reset reason. */ - __I uint32_t RESERVED4[9]; - __I uint32_t RAMSTATUS; /*!< Ram status register. */ - __I uint32_t RESERVED5[53]; - __O uint32_t SYSTEMOFF; /*!< System off register. */ - __I uint32_t RESERVED6[3]; - __IO uint32_t POFCON; /*!< Power failure configuration. */ - __I uint32_t RESERVED7[2]; - __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained - register. */ - __I uint32_t RESERVED8; - __IO uint32_t RAMON; /*!< Ram on/off. */ - __I uint32_t RESERVED9[7]; - __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register - is a retained register. */ - __I uint32_t RESERVED10[3]; - __IO uint32_t RAMONB; /*!< Ram on/off. */ - __I uint32_t RESERVED11[8]; - __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */ - __I uint32_t RESERVED12[291]; - __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */ -} NRF_POWER_Type; - - -/* ================================================================================ */ -/* ================ CLOCK ================ */ -/* ================================================================================ */ - - -/** - * @brief Clock control. (CLOCK) - */ - -typedef struct { /*!< CLOCK Structure */ - __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */ - __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */ - __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */ - __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */ - __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */ - __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */ - __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */ - __I uint32_t RESERVED0[57]; - __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */ - __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */ - __I uint32_t RESERVED1; - __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */ - __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */ - __I uint32_t RESERVED2[124]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[63]; - __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */ - __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */ - __I uint32_t RESERVED4; - __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */ - __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */ - __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is - triggered. */ - __I uint32_t RESERVED5[62]; - __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */ - __I uint32_t RESERVED6[7]; - __IO uint32_t CTIV; /*!< Calibration timer interval. */ - __I uint32_t RESERVED7[5]; - __IO uint32_t XTALFREQ; /*!< Crystal frequency. */ -} NRF_CLOCK_Type; - - -/* ================================================================================ */ -/* ================ MPU ================ */ -/* ================================================================================ */ - - -/** - * @brief Memory Protection Unit. (MPU) - */ - -typedef struct { /*!< MPU Structure */ - __I uint32_t RESERVED0[330]; - __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */ - __IO uint32_t RLENR0; /*!< Length of RAM region 0. */ - __I uint32_t RESERVED1[52]; - __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */ - __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */ - __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */ - __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */ -} NRF_MPU_Type; - - -/* ================================================================================ */ -/* ================ AMLI ================ */ -/* ================================================================================ */ - - -/** - * @brief AHB Multi-Layer Interface. (AMLI) - */ - -typedef struct { /*!< AMLI Structure */ - __I uint32_t RESERVED0[896]; - AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */ -} NRF_AMLI_Type; - - -/* ================================================================================ */ -/* ================ RADIO ================ */ -/* ================================================================================ */ - - -/** - * @brief The radio. (RADIO) - */ - -typedef struct { /*!< RADIO Structure */ - __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */ - __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */ - __O uint32_t TASKS_START; /*!< Start radio. */ - __O uint32_t TASKS_STOP; /*!< Stop radio. */ - __O uint32_t TASKS_DISABLE; /*!< Disable radio. */ - __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */ - __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */ - __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */ - __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */ - __I uint32_t RESERVED0[55]; - __IO uint32_t EVENTS_READY; /*!< Ready event. */ - __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */ - __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */ - __IO uint32_t EVENTS_END; /*!< End event. */ - __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */ - __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */ - __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */ - __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI - sample is ready for readout at the RSSISAMPLE register. */ - __I uint32_t RESERVED1[2]; - __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */ - __I uint32_t RESERVED2[53]; - __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED4[61]; - __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */ - __I uint32_t RESERVED5; - __I uint32_t RXMATCH; /*!< Received address. */ - __I uint32_t RXCRC; /*!< Received CRC. */ - __I uint32_t DAI; /*!< Device address match index. */ - __I uint32_t RESERVED6[60]; - __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */ - __IO uint32_t FREQUENCY; /*!< Frequency. */ - __IO uint32_t TXPOWER; /*!< Output power. */ - __IO uint32_t MODE; /*!< Data rate and modulation. */ - __IO uint32_t PCNF0; /*!< Packet configuration 0. */ - __IO uint32_t PCNF1; /*!< Packet configuration 1. */ - __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */ - __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */ - __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */ - __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */ - __IO uint32_t TXADDRESS; /*!< Transmit address select. */ - __IO uint32_t RXADDRESSES; /*!< Receive address select. */ - __IO uint32_t CRCCNF; /*!< CRC configuration. */ - __IO uint32_t CRCPOLY; /*!< CRC polynomial. */ - __IO uint32_t CRCINIT; /*!< CRC initial value. */ - __IO uint32_t TEST; /*!< Test features enable register. */ - __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */ - __I uint32_t RSSISAMPLE; /*!< RSSI sample. */ - __I uint32_t RESERVED7; - __I uint32_t STATE; /*!< Current radio state. */ - __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */ - __I uint32_t RESERVED8[2]; - __IO uint32_t BCC; /*!< Bit counter compare. */ - __I uint32_t RESERVED9[39]; - __IO uint32_t DAB[8]; /*!< Device address base segment. */ - __IO uint32_t DAP[8]; /*!< Device address prefix. */ - __IO uint32_t DACNF; /*!< Device address match configuration. */ - __I uint32_t RESERVED10[56]; - __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */ - __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */ - __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */ - __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */ - __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */ - __I uint32_t RESERVED11[561]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_RADIO_Type; - - -/* ================================================================================ */ -/* ================ UART ================ */ -/* ================================================================================ */ - - -/** - * @brief Universal Asynchronous Receiver/Transmitter. (UART) - */ - -typedef struct { /*!< UART Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */ - __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */ - __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */ - __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */ - __I uint32_t RESERVED0[3]; - __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */ - __I uint32_t RESERVED1[56]; - __IO uint32_t EVENTS_CTS; /*!< CTS activated. */ - __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */ - __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */ - __I uint32_t RESERVED2[4]; - __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */ - __I uint32_t RESERVED3; - __IO uint32_t EVENTS_ERROR; /*!< Error detected. */ - __I uint32_t RESERVED4[7]; - __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */ - __I uint32_t RESERVED5[46]; - __IO uint32_t SHORTS; /*!< Shortcuts for UART. */ - __I uint32_t RESERVED6[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED7[93]; - __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED8[31]; - __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */ - __I uint32_t RESERVED9; - __IO uint32_t PSELRTS; /*!< Pin select for RTS. */ - __IO uint32_t PSELTXD; /*!< Pin select for TXD. */ - __IO uint32_t PSELCTS; /*!< Pin select for CTS. */ - __IO uint32_t PSELRXD; /*!< Pin select for RXD. */ - __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced. - Once read the character is consumed. If read when no character - available, the UART will stop working. */ - __O uint32_t TXD; /*!< TXD register. */ - __I uint32_t RESERVED10; - __IO uint32_t BAUDRATE; /*!< UART Baudrate. */ - __I uint32_t RESERVED11[17]; - __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */ - __I uint32_t RESERVED12[675]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_UART_Type; - - -/* ================================================================================ */ -/* ================ SPI ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI master 0. (SPI) - */ - -typedef struct { /*!< SPI Structure */ - __I uint32_t RESERVED0[66]; - __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */ - __I uint32_t RESERVED1[126]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[125]; - __IO uint32_t ENABLE; /*!< Enable SPI. */ - __I uint32_t RESERVED3; - __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ - __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ - __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ - __I uint32_t RESERVED4; - __I uint32_t RXD; /*!< RX data. */ - __IO uint32_t TXD; /*!< TX data. */ - __I uint32_t RESERVED5; - __IO uint32_t FREQUENCY; /*!< SPI frequency */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED7[681]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_SPI_Type; - - -/* ================================================================================ */ -/* ================ TWI ================ */ -/* ================================================================================ */ - - -/** - * @brief Two-wire interface master 0. (TWI) - */ - -typedef struct { /*!< TWI Structure */ - __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */ - __I uint32_t RESERVED1[2]; - __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */ - __I uint32_t RESERVED2; - __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */ - __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */ - __I uint32_t RESERVED3[56]; - __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */ - __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */ - __I uint32_t RESERVED4[4]; - __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */ - __I uint32_t RESERVED5; - __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */ - __I uint32_t RESERVED6[4]; - __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */ - __I uint32_t RESERVED7[3]; - __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */ - __I uint32_t RESERVED8[45]; - __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */ - __I uint32_t RESERVED9[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED10[110]; - __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */ - __I uint32_t RESERVED11[14]; - __IO uint32_t ENABLE; /*!< Enable two-wire master. */ - __I uint32_t RESERVED12; - __IO uint32_t PSELSCL; /*!< Pin select for SCL. */ - __IO uint32_t PSELSDA; /*!< Pin select for SDA. */ - __I uint32_t RESERVED13[2]; - __I uint32_t RXD; /*!< RX data register. */ - __IO uint32_t TXD; /*!< TX data register. */ - __I uint32_t RESERVED14; - __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */ - __I uint32_t RESERVED15[24]; - __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */ - __I uint32_t RESERVED16[668]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_TWI_Type; - - -/* ================================================================================ */ -/* ================ SPIS ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI slave 1. (SPIS) - */ - -typedef struct { /*!< SPIS Structure */ - __I uint32_t RESERVED0[9]; - __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */ - __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */ - __I uint32_t RESERVED1[54]; - __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */ - __I uint32_t RESERVED2[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */ - __I uint32_t RESERVED3[5]; - __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */ - __I uint32_t RESERVED4[53]; - __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */ - __I uint32_t RESERVED5[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED6[61]; - __I uint32_t SEMSTAT; /*!< Semaphore status. */ - __I uint32_t RESERVED7[15]; - __IO uint32_t STATUS; /*!< Status from last transaction. */ - __I uint32_t RESERVED8[47]; - __IO uint32_t ENABLE; /*!< Enable SPIS. */ - __I uint32_t RESERVED9; - __IO uint32_t PSELSCK; /*!< Pin select for SCK. */ - __IO uint32_t PSELMISO; /*!< Pin select for MISO. */ - __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */ - __IO uint32_t PSELCSN; /*!< Pin select for CSN. */ - __I uint32_t RESERVED10[7]; - __IO uint32_t RXDPTR; /*!< RX data pointer. */ - __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */ - __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */ - __I uint32_t RESERVED11; - __IO uint32_t TXDPTR; /*!< TX data pointer. */ - __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */ - __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */ - __I uint32_t RESERVED12; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED13; - __IO uint32_t DEF; /*!< Default character. */ - __I uint32_t RESERVED14[24]; - __IO uint32_t ORC; /*!< Over-read character. */ - __I uint32_t RESERVED15[654]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_SPIS_Type; - - -/* ================================================================================ */ -/* ================ SPIM ================ */ -/* ================================================================================ */ - - -/** - * @brief SPI master with easyDMA 1. (SPIM) - */ - -typedef struct { /*!< SPIM Structure */ - __I uint32_t RESERVED0[4]; - __O uint32_t TASKS_START; /*!< Start SPI transaction. */ - __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */ - __I uint32_t RESERVED1; - __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */ - __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */ - __I uint32_t RESERVED2[56]; - __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */ - __I uint32_t RESERVED3[2]; - __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */ - __I uint32_t RESERVED4[3]; - __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */ - __I uint32_t RESERVED5[10]; - __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */ - __I uint32_t RESERVED6[109]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED7[125]; - __IO uint32_t ENABLE; /*!< Enable SPIM. */ - __I uint32_t RESERVED8; - SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */ - __I uint32_t RESERVED9[4]; - __IO uint32_t FREQUENCY; /*!< SPI frequency. */ - __I uint32_t RESERVED10[3]; - SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */ - __I uint32_t RESERVED11; - SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */ - __I uint32_t RESERVED12; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED13[26]; - __IO uint32_t ORC; /*!< Over-read character. */ - __I uint32_t RESERVED14[654]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_SPIM_Type; - - -/* ================================================================================ */ -/* ================ GPIOTE ================ */ -/* ================================================================================ */ - - -/** - * @brief GPIO tasks and events. (GPIOTE) - */ - -typedef struct { /*!< GPIOTE Structure */ - __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */ - __I uint32_t RESERVED1[27]; - __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */ - __I uint32_t RESERVED2[97]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[129]; - __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */ - __I uint32_t RESERVED4[695]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_GPIOTE_Type; - - -/* ================================================================================ */ -/* ================ ADC ================ */ -/* ================================================================================ */ - - -/** - * @brief Analog to digital converter. (ADC) - */ - -typedef struct { /*!< ADC Structure */ - __O uint32_t TASKS_START; /*!< Start an ADC conversion. */ - __O uint32_t TASKS_STOP; /*!< Stop ADC. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[61]; - __I uint32_t BUSY; /*!< ADC busy register. */ - __I uint32_t RESERVED3[63]; - __IO uint32_t ENABLE; /*!< ADC enable. */ - __IO uint32_t CONFIG; /*!< ADC configuration register. */ - __I uint32_t RESULT; /*!< Result of ADC conversion. */ - __I uint32_t RESERVED4[700]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_ADC_Type; - - -/* ================================================================================ */ -/* ================ TIMER ================ */ -/* ================================================================================ */ - - -/** - * @brief Timer 0. (TIMER) - */ - -typedef struct { /*!< TIMER Structure */ - __O uint32_t TASKS_START; /*!< Start Timer. */ - __O uint32_t TASKS_STOP; /*!< Stop Timer. */ - __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */ - __O uint32_t TASKS_CLEAR; /*!< Clear timer. */ - __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */ - __I uint32_t RESERVED0[11]; - __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ - __I uint32_t RESERVED2[44]; - __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */ - __I uint32_t RESERVED3[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED4[126]; - __IO uint32_t MODE; /*!< Timer Mode selection. */ - __IO uint32_t BITMODE; /*!< Sets timer behaviour. */ - __I uint32_t RESERVED5; - __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source - clock frequency is divided by 2^SCALE. */ - __I uint32_t RESERVED6[11]; - __IO uint32_t CC[4]; /*!< Capture/compare registers. */ - __I uint32_t RESERVED7[683]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_TIMER_Type; - - -/* ================================================================================ */ -/* ================ RTC ================ */ -/* ================================================================================ */ - - -/** - * @brief Real time counter 0. (RTC) - */ - -typedef struct { /*!< RTC Structure */ - __O uint32_t TASKS_START; /*!< Start RTC Counter. */ - __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */ - __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */ - __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */ - __I uint32_t RESERVED0[60]; - __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */ - __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */ - __I uint32_t RESERVED1[14]; - __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */ - __I uint32_t RESERVED2[109]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[13]; - __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */ - __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives - the value of EVTEN. */ - __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register - gives the value of EVTEN. */ - __I uint32_t RESERVED4[110]; - __I uint32_t COUNTER; /*!< Current COUNTER value. */ - __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). - Must be written when RTC is STOPed. */ - __I uint32_t RESERVED5[13]; - __IO uint32_t CC[4]; /*!< Capture/compare registers. */ - __I uint32_t RESERVED6[683]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_RTC_Type; - - -/* ================================================================================ */ -/* ================ TEMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Temperature Sensor. (TEMP) - */ - -typedef struct { /*!< TEMP Structure */ - __O uint32_t TASKS_START; /*!< Start temperature measurement. */ - __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[127]; - __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */ - __I uint32_t RESERVED3[700]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_TEMP_Type; - - -/* ================================================================================ */ -/* ================ RNG ================ */ -/* ================================================================================ */ - - -/** - * @brief Random Number Generator. (RNG) - */ - -typedef struct { /*!< RNG Structure */ - __O uint32_t TASKS_START; /*!< Start the random number generator. */ - __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */ - __I uint32_t RESERVED1[63]; - __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */ - __I uint32_t RESERVED3[126]; - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t VALUE; /*!< RNG random number. */ - __I uint32_t RESERVED4[700]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_RNG_Type; - - -/* ================================================================================ */ -/* ================ ECB ================ */ -/* ================================================================================ */ - - -/** - * @brief AES ECB Mode Encryption. (ECB) - */ - -typedef struct { /*!< ECB Structure */ - __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this - will not initiate a new encryption and the ERRORECB event will - be triggered. */ - __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running, - this will will trigger the ERRORECB event. */ - __I uint32_t RESERVED0[62]; - __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */ - __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an - error. */ - __I uint32_t RESERVED1[127]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[126]; - __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */ - __I uint32_t RESERVED3[701]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_ECB_Type; - - -/* ================================================================================ */ -/* ================ AAR ================ */ -/* ================================================================================ */ - - -/** - * @brief Accelerated Address Resolver. (AAR) - */ - -typedef struct { /*!< AAR Structure */ - __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK - data structure. */ - __I uint32_t RESERVED0; - __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */ - __I uint32_t RESERVED1[61]; - __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */ - __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */ - __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */ - __I uint32_t RESERVED2[126]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t STATUS; /*!< Resolution status. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable AAR. */ - __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */ - __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */ - __I uint32_t RESERVED5; - __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage - during resolution. A minimum of 3 bytes must be reserved. */ - __I uint32_t RESERVED6[697]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_AAR_Type; - - -/* ================================================================================ */ -/* ================ CCM ================ */ -/* ================================================================================ */ - - -/** - * @brief AES CCM Mode Encryption. (CCM) - */ - -typedef struct { /*!< CCM Structure */ - __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by - itself when completed. */ - __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when - completed. */ - __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */ - __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */ - __IO uint32_t EVENTS_ERROR; /*!< Error happened. */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< CCM enable. */ - __IO uint32_t MODE; /*!< Operation mode. */ - __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */ - __IO uint32_t INPTR; /*!< Pointer to the input packet. */ - __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */ - __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage - during resolution. A minimum of 43 bytes must be reserved. */ - __I uint32_t RESERVED5[697]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_CCM_Type; - - -/* ================================================================================ */ -/* ================ WDT ================ */ -/* ================================================================================ */ - - -/** - * @brief Watchdog Timer. (WDT) - */ - -typedef struct { /*!< WDT Structure */ - __O uint32_t TASKS_START; /*!< Start the watchdog. */ - __I uint32_t RESERVED0[63]; - __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */ - __I uint32_t RESERVED1[128]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED2[61]; - __I uint32_t RUNSTATUS; /*!< Watchdog running status. */ - __I uint32_t REQSTATUS; /*!< Request status. */ - __I uint32_t RESERVED3[63]; - __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */ - __IO uint32_t RREN; /*!< Reload request enable. */ - __IO uint32_t CONFIG; /*!< Configuration register. */ - __I uint32_t RESERVED4[60]; - __O uint32_t RR[8]; /*!< Reload requests registers. */ - __I uint32_t RESERVED5[631]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_WDT_Type; - - -/* ================================================================================ */ -/* ================ QDEC ================ */ -/* ================================================================================ */ - - -/** - * @brief Rotary decoder. (QDEC) - */ - -typedef struct { /*!< QDEC Structure */ - __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */ - __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */ - __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers, - and clears the ACC registers. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */ - __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and - ACC register different than zero. */ - __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */ - __I uint32_t RESERVED1[61]; - __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[125]; - __IO uint32_t ENABLE; /*!< Enable the QDEC. */ - __IO uint32_t LEDPOL; /*!< LED output pin polarity. */ - __IO uint32_t SAMPLEPER; /*!< Sample period. */ - __I int32_t SAMPLE; /*!< Motion sample value. */ - __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */ - __I int32_t ACC; /*!< Accumulated valid transitions register. */ - __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC - task. */ - __IO uint32_t PSELLED; /*!< Pin select for LED output. */ - __IO uint32_t PSELA; /*!< Pin select for phase A input. */ - __IO uint32_t PSELB; /*!< Pin select for phase B input. */ - __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */ - __I uint32_t RESERVED4[5]; - __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */ - __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */ - __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC - task. */ - __I uint32_t RESERVED5[684]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_QDEC_Type; - - -/* ================================================================================ */ -/* ================ LPCOMP ================ */ -/* ================================================================================ */ - - -/** - * @brief Low power comparator. (LPCOMP) - */ - -typedef struct { /*!< LPCOMP Structure */ - __O uint32_t TASKS_START; /*!< Start the comparator. */ - __O uint32_t TASKS_STOP; /*!< Stop the comparator. */ - __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */ - __I uint32_t RESERVED0[61]; - __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */ - __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */ - __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */ - __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */ - __I uint32_t RESERVED1[60]; - __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */ - __I uint32_t RESERVED2[64]; - __IO uint32_t INTENSET; /*!< Interrupt enable set register. */ - __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */ - __I uint32_t RESERVED3[61]; - __I uint32_t RESULT; /*!< Result of last compare. */ - __I uint32_t RESERVED4[63]; - __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */ - __IO uint32_t PSEL; /*!< Input pin select. */ - __IO uint32_t REFSEL; /*!< Reference select. */ - __IO uint32_t EXTREFSEL; /*!< External reference select. */ - __I uint32_t RESERVED5[4]; - __IO uint32_t ANADETECT; /*!< Analog detect configuration. */ - __I uint32_t RESERVED6[694]; - __IO uint32_t POWER; /*!< Peripheral power control. */ -} NRF_LPCOMP_Type; - - -/* ================================================================================ */ -/* ================ SWI ================ */ -/* ================================================================================ */ - - -/** - * @brief SW Interrupts. (SWI) - */ - -typedef struct { /*!< SWI Structure */ - __I uint32_t UNUSED; /*!< Unused. */ -} NRF_SWI_Type; - - -/* ================================================================================ */ -/* ================ NVMC ================ */ -/* ================================================================================ */ - - -/** - * @brief Non Volatile Memory Controller. (NVMC) - */ - -typedef struct { /*!< NVMC Structure */ - __I uint32_t RESERVED0[256]; - __I uint32_t READY; /*!< Ready flag. */ - __I uint32_t RESERVED1[64]; - __IO uint32_t CONFIG; /*!< Configuration register. */ - - union { - __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */ - __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */ - }; - __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */ - __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */ - __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */ -} NRF_NVMC_Type; - - -/* ================================================================================ */ -/* ================ PPI ================ */ -/* ================================================================================ */ - - -/** - * @brief PPI controller. (PPI) - */ - -typedef struct { /*!< PPI Structure */ - PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */ - __I uint32_t RESERVED0[312]; - __IO uint32_t CHEN; /*!< Channel enable. */ - __IO uint32_t CHENSET; /*!< Channel enable set. */ - __IO uint32_t CHENCLR; /*!< Channel enable clear. */ - __I uint32_t RESERVED1; - PPI_CH_Type CH[16]; /*!< PPI Channel. */ - __I uint32_t RESERVED2[156]; - __IO uint32_t CHG[4]; /*!< Channel group configuration. */ -} NRF_PPI_Type; - - -/* ================================================================================ */ -/* ================ FICR ================ */ -/* ================================================================================ */ - - -/** - * @brief Factory Information Configuration. (FICR) - */ - -typedef struct { /*!< FICR Structure */ - __I uint32_t RESERVED0[4]; - __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */ - __I uint32_t CODESIZE; /*!< Code memory size in pages. */ - __I uint32_t RESERVED1[4]; - __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */ - __I uint32_t PPFC; /*!< Pre-programmed factory code present. */ - __I uint32_t RESERVED2; - __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */ - - union { - __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is - kept for backward compatinility purposes. Use SIZERAMBLOCKS - instead. */ - __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */ - }; - __I uint32_t RESERVED3[5]; - __I uint32_t CONFIGID; /*!< Configuration identifier. */ - __I uint32_t DEVICEID[2]; /*!< Device identifier. */ - __I uint32_t RESERVED4[6]; - __I uint32_t ER[4]; /*!< Encryption root. */ - __I uint32_t IR[4]; /*!< Identity root. */ - __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */ - __I uint32_t DEVICEADDR[2]; /*!< Device address. */ - __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */ - __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit - mode. */ - __I uint32_t RESERVED5[10]; - __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit - mode. */ -} NRF_FICR_Type; - - -/* ================================================================================ */ -/* ================ UICR ================ */ -/* ================================================================================ */ - - -/** - * @brief User Information Configuration. (UICR) - */ - -typedef struct { /*!< UICR Structure */ - __IO uint32_t CLENR0; /*!< Length of code region 0. */ - __IO uint32_t RBPCONF; /*!< Readback protection configuration. */ - __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */ - __I uint32_t RESERVED0; - __I uint32_t FWID; /*!< Firmware ID. */ - - union { - __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */ - __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */ - }; - __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */ - __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */ -} NRF_UICR_Type; - - -/* ================================================================================ */ -/* ================ GPIO ================ */ -/* ================================================================================ */ - - -/** - * @brief General purpose input and output. (GPIO) - */ - -typedef struct { /*!< GPIO Structure */ - __I uint32_t RESERVED0[321]; - __IO uint32_t OUT; /*!< Write GPIO port. */ - __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */ - __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */ - __I uint32_t IN; /*!< Read GPIO port. */ - __IO uint32_t DIR; /*!< Direction of GPIO pins. */ - __IO uint32_t DIRSET; /*!< DIR set register. */ - __IO uint32_t DIRCLR; /*!< DIR clear register. */ - __I uint32_t RESERVED1[120]; - __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */ -} NRF_GPIO_Type; - - -/* -------------------- End of section using anonymous unions ------------------- */ -#if defined(__CC_ARM) - #pragma pop -#elif defined(__ICCARM__) - /* leave anonymous unions enabled */ -#elif defined(__GNUC__) - /* anonymous unions are enabled by default */ -#elif defined(__TMS470__) - /* anonymous unions are enabled by default */ -#elif defined(__TASKING__) - #pragma warning restore -#else - #warning Not supported compiler type -#endif - - - - -/* ================================================================================ */ -/* ================ Peripheral memory map ================ */ -/* ================================================================================ */ - -#define NRF_POWER_BASE 0x40000000UL -#define NRF_CLOCK_BASE 0x40000000UL -#define NRF_MPU_BASE 0x40000000UL -#define NRF_AMLI_BASE 0x40000000UL -#define NRF_RADIO_BASE 0x40001000UL -#define NRF_UART0_BASE 0x40002000UL -#define NRF_SPI0_BASE 0x40003000UL -#define NRF_TWI0_BASE 0x40003000UL -#define NRF_SPI1_BASE 0x40004000UL -#define NRF_TWI1_BASE 0x40004000UL -#define NRF_SPIS1_BASE 0x40004000UL -#define NRF_SPIM1_BASE 0x40004000UL -#define NRF_GPIOTE_BASE 0x40006000UL -#define NRF_ADC_BASE 0x40007000UL -#define NRF_TIMER0_BASE 0x40008000UL -#define NRF_TIMER1_BASE 0x40009000UL -#define NRF_TIMER2_BASE 0x4000A000UL -#define NRF_RTC0_BASE 0x4000B000UL -#define NRF_TEMP_BASE 0x4000C000UL -#define NRF_RNG_BASE 0x4000D000UL -#define NRF_ECB_BASE 0x4000E000UL -#define NRF_AAR_BASE 0x4000F000UL -#define NRF_CCM_BASE 0x4000F000UL -#define NRF_WDT_BASE 0x40010000UL -#define NRF_RTC1_BASE 0x40011000UL -#define NRF_QDEC_BASE 0x40012000UL -#define NRF_LPCOMP_BASE 0x40013000UL -#define NRF_SWI_BASE 0x40014000UL -#define NRF_NVMC_BASE 0x4001E000UL -#define NRF_PPI_BASE 0x4001F000UL -#define NRF_FICR_BASE 0x10000000UL -#define NRF_UICR_BASE 0x10001000UL -#define NRF_GPIO_BASE 0x50000000UL - - -/* ================================================================================ */ -/* ================ Peripheral declaration ================ */ -/* ================================================================================ */ - -#define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE) -#define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE) -#define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE) -#define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE) -#define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE) -#define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE) -#define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE) -#define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE) -#define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE) -#define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE) -#define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE) -#define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE) -#define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE) -#define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE) -#define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE) -#define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE) -#define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE) -#define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE) -#define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE) -#define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE) -#define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE) -#define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE) -#define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE) -#define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE) -#define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE) -#define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE) -#define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE) -#define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE) -#define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE) -#define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE) -#define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE) -#define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE) -#define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE) - - -/** @} */ /* End of group Device_Peripheral_Registers */ -/** @} */ /* End of group nrf51 */ -/** @} */ /* End of group Nordic Semiconductor */ - -#ifdef __cplusplus -} -#endif - - -#endif /* nrf51_H */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_bitfields.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_bitfields.h deleted file mode 100644 index a5e562eb9f..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_bitfields.h +++ /dev/null @@ -1,6894 +0,0 @@ -/* - * Copyright (c) Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef __NRF51_BITS_H -#define __NRF51_BITS_H - -/*lint ++flb "Enter library region" */ - -/* Peripheral: AAR */ -/* Description: Accelerated Address Resolver. */ - -/* Register: AAR_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on NOTRESOLVED event. */ -#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on RESOLVED event. */ -#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on END event. */ -#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: AAR_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on NOTRESOLVED event. */ -#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */ -#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on RESOLVED event. */ -#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */ -#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDKSGEN event. */ -#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: AAR_STATUS */ -/* Description: Resolution status. */ - -/* Bits 3..0 : The IRK used last time an address was resolved. */ -#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */ - -/* Register: AAR_ENABLE */ -/* Description: Enable AAR. */ - -/* Bits 1..0 : Enable AAR. */ -#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */ -#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */ - -/* Register: AAR_NIRK */ -/* Description: Number of Identity root Keys in the IRK data structure. */ - -/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */ -#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */ -#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */ - -/* Register: AAR_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: ADC */ -/* Description: Analog to digital converter. */ - -/* Register: ADC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on END event. */ -#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */ -#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: ADC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on END event. */ -#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */ -#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: ADC_BUSY */ -/* Description: ADC busy register. */ - -/* Bit 0 : ADC busy register. */ -#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */ -#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */ -#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */ -#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */ - -/* Register: ADC_ENABLE */ -/* Description: ADC enable. */ - -/* Bits 1..0 : ADC enable. */ -#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */ -#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */ - -/* Register: ADC_CONFIG */ -/* Description: ADC configuration register. */ - -/* Bits 17..16 : ADC external reference pin selection. */ -#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */ -#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */ -#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */ -#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */ - -/* Bits 15..8 : ADC analog pin selection. */ -#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */ -#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */ -#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */ - -/* Bits 6..5 : ADC reference selection. */ -#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */ -#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */ -#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */ -#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */ -#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */ - -/* Bits 4..2 : ADC input selection. */ -#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */ -#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */ -#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */ -#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */ - -/* Bits 1..0 : ADC resolution. */ -#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */ -#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */ -#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */ -#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */ -#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */ - -/* Register: ADC_RESULT */ -/* Description: Result of ADC conversion. */ - -/* Bits 9..0 : Result of ADC conversion. */ -#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ - -/* Register: ADC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: AMLI */ -/* Description: AHB Multi-Layer Interface. */ - -/* Register: AMLI_RAMPRI_CPU0 */ -/* Description: Configurable priority configuration register for CPU0. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_SPIS1 */ -/* Description: Configurable priority configuration register for SPIS1. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_RADIO */ -/* Description: Configurable priority configuration register for RADIO. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_ECB */ -/* Description: Configurable priority configuration register for ECB. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_CCM */ -/* Description: Configurable priority configuration register for CCM. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Register: AMLI_RAMPRI_AAR */ -/* Description: Configurable priority configuration register for AAR. */ - -/* Bits 31..28 : Configuration field for RAM block 7. */ -#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 27..24 : Configuration field for RAM block 6. */ -#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 23..20 : Configuration field for RAM block 5. */ -#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 19..16 : Configuration field for RAM block 4. */ -#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 15..12 : Configuration field for RAM block 3. */ -#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 11..8 : Configuration field for RAM block 2. */ -#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 7..4 : Configuration field for RAM block 1. */ -#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */ - -/* Bits 3..0 : Configuration field for RAM block 0. */ -#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */ -#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */ - - -/* Peripheral: CCM */ -/* Description: AES CCM Mode Encryption. */ - -/* Register: CCM_SHORTS */ -/* Description: Shortcuts for the CCM. */ - -/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */ -#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: CCM_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on ERROR event. */ -#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on ENDCRYPT event. */ -#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on ENDKSGEN event. */ -#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: CCM_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on ERROR event. */ -#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */ -#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on ENDCRYPT event. */ -#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */ -#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDKSGEN event. */ -#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */ -#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */ -#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */ -#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: CCM_MICSTATUS */ -/* Description: CCM RX MIC check result. */ - -/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */ -#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */ -#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */ -#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */ - -/* Register: CCM_ENABLE */ -/* Description: CCM enable. */ - -/* Bits 1..0 : CCM enable. */ -#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */ -#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */ - -/* Register: CCM_MODE */ -/* Description: Operation mode. */ - -/* Bit 0 : CCM mode operation. */ -#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */ -#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */ - -/* Register: CCM_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: CLOCK */ -/* Description: Clock control. */ - -/* Register: CLOCK_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 4 : Enable interrupt on CTTO event. */ -#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on DONE event. */ -#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: CLOCK_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 4 : Disable interrupt on CTTO event. */ -#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */ -#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on DONE event. */ -#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */ -#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */ -#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: CLOCK_HFCLKRUN */ -/* Description: Task HFCLKSTART trigger status. */ - -/* Bit 0 : Task HFCLKSTART trigger status. */ -#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */ -#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */ - -/* Register: CLOCK_HFCLKSTAT */ -/* Description: High frequency clock status. */ - -/* Bit 16 : State for the HFCLK. */ -#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */ -#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */ - -/* Bit 0 : Active clock source for the HF clock. */ -#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */ -#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */ - -/* Register: CLOCK_LFCLKRUN */ -/* Description: Task LFCLKSTART triggered status. */ - -/* Bit 0 : Task LFCLKSTART triggered status. */ -#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */ -#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */ -#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */ - -/* Register: CLOCK_LFCLKSTAT */ -/* Description: Low frequency clock status. */ - -/* Bit 16 : State for the LF clock. */ -#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */ -#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */ -#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */ - -/* Bits 1..0 : Active clock source for the LF clock. */ -#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */ -#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */ -#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */ - -/* Register: CLOCK_LFCLKSRCCOPY */ -/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ - -/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ -#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ - -/* Register: CLOCK_LFCLKSRC */ -/* Description: Clock source for the LFCLK clock. */ - -/* Bits 1..0 : Clock source. */ -#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */ -#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */ -#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */ -#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */ - -/* Register: CLOCK_CTIV */ -/* Description: Calibration timer interval. */ - -/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */ -#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */ -#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */ - -/* Register: CLOCK_XTALFREQ */ -/* Description: Crystal frequency. */ - -/* Bits 7..0 : External Xtal frequency selection. */ -#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */ -#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */ - - -/* Peripheral: ECB */ -/* Description: AES ECB Mode Encryption. */ - -/* Register: ECB_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 1 : Enable interrupt on ERRORECB event. */ -#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on ENDECB event. */ -#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: ECB_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 1 : Disable interrupt on ERRORECB event. */ -#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */ -#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on ENDECB event. */ -#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */ -#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */ -#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */ -#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: ECB_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: FICR */ -/* Description: Factory Information Configuration. */ - -/* Register: FICR_PPFC */ -/* Description: Pre-programmed factory code present. */ - -/* Bits 7..0 : Pre-programmed factory code present. */ -#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */ -#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */ -#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */ -#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */ - -/* Register: FICR_CONFIGID */ -/* Description: Configuration identifier. */ - -/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */ -#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */ -#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */ - -/* Bits 15..0 : Hardware Identification Number. */ -#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */ -#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */ - -/* Register: FICR_DEVICEADDRTYPE */ -/* Description: Device address type. */ - -/* Bit 0 : Device address type. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */ -#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */ - -/* Register: FICR_OVERRIDEEN */ -/* Description: Radio calibration override enable. */ - -/* Bit 3 : Override default values for BLE_1Mbit mode. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */ -#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */ - -/* Bit 0 : Override default values for NRF_1Mbit mode. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */ -#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */ - - -/* Peripheral: GPIO */ -/* Description: General purpose input and output. */ - -/* Register: GPIO_OUT */ -/* Description: Write GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */ - -/* Register: GPIO_OUTSET */ -/* Description: Set individual bits in GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */ - -/* Register: GPIO_OUTCLR */ -/* Description: Clear individual bits in GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */ -#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */ -#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */ - -/* Register: GPIO_IN */ -/* Description: Read GPIO port. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */ -#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */ - -/* Register: GPIO_DIR */ -/* Description: Direction of GPIO pins. */ - -/* Bit 31 : Pin 31. */ -#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */ - -/* Bit 30 : Pin 30. */ -#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */ - -/* Bit 29 : Pin 29. */ -#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */ - -/* Bit 28 : Pin 28. */ -#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */ - -/* Bit 27 : Pin 27. */ -#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */ - -/* Bit 26 : Pin 26. */ -#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */ - -/* Bit 25 : Pin 25. */ -#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */ - -/* Bit 24 : Pin 24. */ -#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */ - -/* Bit 23 : Pin 23. */ -#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */ - -/* Bit 22 : Pin 22. */ -#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */ - -/* Bit 21 : Pin 21. */ -#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */ - -/* Bit 20 : Pin 20. */ -#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */ - -/* Bit 19 : Pin 19. */ -#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */ - -/* Bit 18 : Pin 18. */ -#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */ - -/* Bit 17 : Pin 17. */ -#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */ - -/* Bit 16 : Pin 16. */ -#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */ - -/* Bit 15 : Pin 15. */ -#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */ - -/* Bit 14 : Pin 14. */ -#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */ - -/* Bit 13 : Pin 13. */ -#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */ - -/* Bit 12 : Pin 12. */ -#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */ - -/* Bit 11 : Pin 11. */ -#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */ - -/* Bit 10 : Pin 10. */ -#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */ - -/* Bit 9 : Pin 9. */ -#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */ - -/* Bit 8 : Pin 8. */ -#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */ - -/* Bit 7 : Pin 7. */ -#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */ - -/* Bit 6 : Pin 6. */ -#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */ - -/* Bit 5 : Pin 5. */ -#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */ - -/* Bit 4 : Pin 4. */ -#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */ - -/* Bit 3 : Pin 3. */ -#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */ - -/* Bit 2 : Pin 2. */ -#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */ - -/* Bit 1 : Pin 1. */ -#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */ - -/* Bit 0 : Pin 0. */ -#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */ - -/* Register: GPIO_DIRSET */ -/* Description: DIR set register. */ - -/* Bit 31 : Set as output pin 31. */ -#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */ - -/* Bit 30 : Set as output pin 30. */ -#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */ - -/* Bit 29 : Set as output pin 29. */ -#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */ - -/* Bit 28 : Set as output pin 28. */ -#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */ - -/* Bit 27 : Set as output pin 27. */ -#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */ - -/* Bit 26 : Set as output pin 26. */ -#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */ - -/* Bit 25 : Set as output pin 25. */ -#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */ - -/* Bit 24 : Set as output pin 24. */ -#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */ - -/* Bit 23 : Set as output pin 23. */ -#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */ - -/* Bit 22 : Set as output pin 22. */ -#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */ - -/* Bit 21 : Set as output pin 21. */ -#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */ - -/* Bit 20 : Set as output pin 20. */ -#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */ - -/* Bit 19 : Set as output pin 19. */ -#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */ - -/* Bit 18 : Set as output pin 18. */ -#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */ - -/* Bit 17 : Set as output pin 17. */ -#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */ - -/* Bit 16 : Set as output pin 16. */ -#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */ - -/* Bit 15 : Set as output pin 15. */ -#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */ - -/* Bit 14 : Set as output pin 14. */ -#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */ - -/* Bit 13 : Set as output pin 13. */ -#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */ - -/* Bit 12 : Set as output pin 12. */ -#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */ - -/* Bit 11 : Set as output pin 11. */ -#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */ - -/* Bit 10 : Set as output pin 10. */ -#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */ - -/* Bit 9 : Set as output pin 9. */ -#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */ - -/* Bit 8 : Set as output pin 8. */ -#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */ - -/* Bit 7 : Set as output pin 7. */ -#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */ - -/* Bit 6 : Set as output pin 6. */ -#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */ - -/* Bit 5 : Set as output pin 5. */ -#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */ - -/* Bit 4 : Set as output pin 4. */ -#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */ - -/* Bit 3 : Set as output pin 3. */ -#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */ - -/* Bit 2 : Set as output pin 2. */ -#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */ - -/* Bit 1 : Set as output pin 1. */ -#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */ - -/* Bit 0 : Set as output pin 0. */ -#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */ - -/* Register: GPIO_DIRCLR */ -/* Description: DIR clear register. */ - -/* Bit 31 : Set as input pin 31. */ -#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */ -#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 30 : Set as input pin 30. */ -#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */ -#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 29 : Set as input pin 29. */ -#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */ -#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 28 : Set as input pin 28. */ -#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */ -#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 27 : Set as input pin 27. */ -#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */ -#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 26 : Set as input pin 26. */ -#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */ -#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 25 : Set as input pin 25. */ -#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */ -#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 24 : Set as input pin 24. */ -#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */ -#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 23 : Set as input pin 23. */ -#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */ -#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 22 : Set as input pin 22. */ -#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */ -#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 21 : Set as input pin 21. */ -#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */ -#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 20 : Set as input pin 20. */ -#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */ -#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 19 : Set as input pin 19. */ -#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */ -#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 18 : Set as input pin 18. */ -#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */ -#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 17 : Set as input pin 17. */ -#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */ -#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 16 : Set as input pin 16. */ -#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */ -#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 15 : Set as input pin 15. */ -#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */ -#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 14 : Set as input pin 14. */ -#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */ -#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 13 : Set as input pin 13. */ -#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */ -#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 12 : Set as input pin 12. */ -#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */ -#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 11 : Set as input pin 11. */ -#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */ -#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 10 : Set as input pin 10. */ -#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */ -#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 9 : Set as input pin 9. */ -#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */ -#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 8 : Set as input pin 8. */ -#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */ -#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 7 : Set as input pin 7. */ -#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */ -#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 6 : Set as input pin 6. */ -#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */ -#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 5 : Set as input pin 5. */ -#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */ -#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 4 : Set as input pin 4. */ -#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */ -#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 3 : Set as input pin 3. */ -#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */ -#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 2 : Set as input pin 2. */ -#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */ -#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 1 : Set as input pin 1. */ -#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */ -#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */ - -/* Bit 0 : Set as input pin 0. */ -#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */ -#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */ -#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */ -#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */ - -/* Register: GPIO_PIN_CNF */ -/* Description: Configuration of GPIO pins. */ - -/* Bits 17..16 : Pin sensing mechanism. */ -#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */ -#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */ -#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */ -#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */ - -/* Bits 10..8 : Drive configuration. */ -#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */ -#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */ -#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */ -#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */ -#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */ - -/* Bits 3..2 : Pull-up or -down configuration. */ -#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */ -#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */ -#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */ -#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */ -#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */ - -/* Bit 1 : Connect or disconnect input path. */ -#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */ -#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */ -#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */ - -/* Bit 0 : Pin direction. */ -#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */ -#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */ -#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */ -#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */ - - -/* Peripheral: GPIOTE */ -/* Description: GPIO tasks and events. */ - -/* Register: GPIOTE_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 31 : Enable interrupt on PORT event. */ -#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on IN[3] event. */ -#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on IN[2] event. */ -#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on IN[1] event. */ -#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on IN[0] event. */ -#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: GPIOTE_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 31 : Disable interrupt on PORT event. */ -#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */ -#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on IN[3] event. */ -#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */ -#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on IN[2] event. */ -#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */ -#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on IN[1] event. */ -#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */ -#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on IN[0] event. */ -#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */ -#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */ -#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */ -#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: GPIOTE_CONFIG */ -/* Description: Channel configuration registers. */ - -/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */ -#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */ -#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */ -#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */ - -/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */ -#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */ -#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */ -#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */ -#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */ -#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */ - -/* Bits 12..8 : Pin select. */ -#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */ -#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */ - -/* Bits 1..0 : Mode */ -#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */ -#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */ -#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */ -#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */ - -/* Register: GPIOTE_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: LPCOMP */ -/* Description: Low power comparator. */ - -/* Register: LPCOMP_SHORTS */ -/* Description: Shortcuts for the LPCOMP. */ - -/* Bit 4 : Shortcut between CROSS event and STOP task. */ -#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */ -#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between UP event and STOP task. */ -#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */ -#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between DOWN event and STOP task. */ -#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */ -#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between RADY event and STOP task. */ -#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */ -#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between READY event and SAMPLE task. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: LPCOMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 3 : Enable interrupt on CROSS event. */ -#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on UP event. */ -#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on DOWN event. */ -#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: LPCOMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 3 : Disable interrupt on CROSS event. */ -#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */ -#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on UP event. */ -#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */ -#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */ -#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on DOWN event. */ -#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */ -#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: LPCOMP_RESULT */ -/* Description: Result of last compare. */ - -/* Bit 0 : Result of last compare. Decision point SAMPLE task. */ -#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */ -#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */ -#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */ - -/* Register: LPCOMP_ENABLE */ -/* Description: Enable the LPCOMP. */ - -/* Bits 1..0 : Enable or disable LPCOMP. */ -#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */ -#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */ - -/* Register: LPCOMP_PSEL */ -/* Description: Input pin select. */ - -/* Bits 2..0 : Analog input pin select. */ -#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */ -#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */ -#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */ -#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */ - -/* Register: LPCOMP_REFSEL */ -/* Description: Reference select. */ - -/* Bits 2..0 : Reference select. */ -#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */ -#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */ -#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */ - -/* Register: LPCOMP_EXTREFSEL */ -/* Description: External reference select. */ - -/* Bit 0 : External analog reference pin selection. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */ -#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */ - -/* Register: LPCOMP_ANADETECT */ -/* Description: Analog detect configuration. */ - -/* Bits 1..0 : Analog detect configuration. */ -#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */ -#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */ -#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */ -#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */ - -/* Register: LPCOMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: MPU */ -/* Description: Memory Protection Unit. */ - -/* Register: MPU_PERR0 */ -/* Description: Configuration of peripherals in mpu regions. */ - -/* Bit 31 : PPI region configuration. */ -#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */ -#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */ -#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 30 : NVMC region configuration. */ -#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */ -#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */ -#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 19 : LPCOMP region configuration. */ -#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */ -#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ -#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 18 : QDEC region configuration. */ -#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */ -#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */ -#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 17 : RTC1 region configuration. */ -#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */ -#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */ -#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 16 : WDT region configuration. */ -#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */ -#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */ -#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 15 : CCM and AAR region configuration. */ -#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */ -#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */ -#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 14 : ECB region configuration. */ -#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */ -#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */ -#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 13 : RNG region configuration. */ -#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */ -#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */ -#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 12 : TEMP region configuration. */ -#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */ -#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */ -#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 11 : RTC0 region configuration. */ -#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */ -#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */ -#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 10 : TIMER2 region configuration. */ -#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */ -#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */ -#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 9 : TIMER1 region configuration. */ -#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */ -#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */ -#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 8 : TIMER0 region configuration. */ -#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */ -#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */ -#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 7 : ADC region configuration. */ -#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */ -#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */ -#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 6 : GPIOTE region configuration. */ -#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */ -#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */ -#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 4 : SPI1 and TWI1 region configuration. */ -#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */ -#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */ -#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 3 : SPI0 and TWI0 region configuration. */ -#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */ -#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */ -#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 2 : UART0 region configuration. */ -#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */ -#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */ -#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 1 : RADIO region configuration. */ -#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */ -#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */ -#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Bit 0 : POWER_CLOCK region configuration. */ -#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */ -#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */ -#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */ -#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */ - -/* Register: MPU_PROTENSET0 */ -/* Description: Erase and write protection bit enable set register. */ - -/* Bit 31 : Protection enable for region 31. */ -#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */ -#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */ -#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 30 : Protection enable for region 30. */ -#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */ -#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */ -#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 29 : Protection enable for region 29. */ -#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */ -#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */ -#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 28 : Protection enable for region 28. */ -#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */ -#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */ -#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 27 : Protection enable for region 27. */ -#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */ -#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */ -#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 26 : Protection enable for region 26. */ -#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */ -#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */ -#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 25 : Protection enable for region 25. */ -#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */ -#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */ -#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 24 : Protection enable for region 24. */ -#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */ -#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */ -#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 23 : Protection enable for region 23. */ -#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */ -#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */ -#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 22 : Protection enable for region 22. */ -#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */ -#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */ -#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 21 : Protection enable for region 21. */ -#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */ -#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */ -#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 20 : Protection enable for region 20. */ -#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */ -#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */ -#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 19 : Protection enable for region 19. */ -#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */ -#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */ -#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 18 : Protection enable for region 18. */ -#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */ -#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */ -#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 17 : Protection enable for region 17. */ -#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */ -#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */ -#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 16 : Protection enable for region 16. */ -#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */ -#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */ -#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 15 : Protection enable for region 15. */ -#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */ -#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */ -#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 14 : Protection enable for region 14. */ -#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */ -#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */ -#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 13 : Protection enable for region 13. */ -#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */ -#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */ -#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 12 : Protection enable for region 12. */ -#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */ -#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */ -#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 11 : Protection enable for region 11. */ -#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */ -#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */ -#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 10 : Protection enable for region 10. */ -#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */ -#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */ -#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 9 : Protection enable for region 9. */ -#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */ -#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */ -#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 8 : Protection enable for region 8. */ -#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */ -#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */ -#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 7 : Protection enable for region 7. */ -#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */ -#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */ -#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 6 : Protection enable for region 6. */ -#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */ -#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */ -#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 5 : Protection enable for region 5. */ -#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */ -#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */ -#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 4 : Protection enable for region 4. */ -#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */ -#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */ -#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 3 : Protection enable for region 3. */ -#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */ -#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */ -#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 2 : Protection enable for region 2. */ -#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */ -#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */ -#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 1 : Protection enable for region 1. */ -#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */ -#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */ -#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 0 : Protection enable for region 0. */ -#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */ -#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */ -#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */ - -/* Register: MPU_PROTENSET1 */ -/* Description: Erase and write protection bit enable set register. */ - -/* Bit 31 : Protection enable for region 63. */ -#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */ -#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */ -#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 30 : Protection enable for region 62. */ -#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */ -#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */ -#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 29 : Protection enable for region 61. */ -#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */ -#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */ -#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 28 : Protection enable for region 60. */ -#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */ -#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */ -#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 27 : Protection enable for region 59. */ -#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */ -#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */ -#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 26 : Protection enable for region 58. */ -#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */ -#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */ -#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 25 : Protection enable for region 57. */ -#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */ -#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */ -#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 24 : Protection enable for region 56. */ -#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */ -#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */ -#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 23 : Protection enable for region 55. */ -#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */ -#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */ -#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 22 : Protection enable for region 54. */ -#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */ -#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */ -#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 21 : Protection enable for region 53. */ -#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */ -#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */ -#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 20 : Protection enable for region 52. */ -#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */ -#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */ -#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 19 : Protection enable for region 51. */ -#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */ -#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */ -#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 18 : Protection enable for region 50. */ -#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */ -#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */ -#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 17 : Protection enable for region 49. */ -#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */ -#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */ -#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 16 : Protection enable for region 48. */ -#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */ -#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */ -#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 15 : Protection enable for region 47. */ -#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */ -#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */ -#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 14 : Protection enable for region 46. */ -#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */ -#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */ -#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 13 : Protection enable for region 45. */ -#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */ -#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */ -#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 12 : Protection enable for region 44. */ -#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */ -#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */ -#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 11 : Protection enable for region 43. */ -#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */ -#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */ -#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 10 : Protection enable for region 42. */ -#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */ -#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */ -#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 9 : Protection enable for region 41. */ -#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */ -#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */ -#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 8 : Protection enable for region 40. */ -#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */ -#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */ -#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 7 : Protection enable for region 39. */ -#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */ -#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */ -#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 6 : Protection enable for region 38. */ -#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */ -#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */ -#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 5 : Protection enable for region 37. */ -#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */ -#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */ -#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 4 : Protection enable for region 36. */ -#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */ -#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */ -#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 3 : Protection enable for region 35. */ -#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */ -#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */ -#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 2 : Protection enable for region 34. */ -#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */ -#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */ -#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 1 : Protection enable for region 33. */ -#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */ -#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */ -#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */ - -/* Bit 0 : Protection enable for region 32. */ -#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */ -#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */ -#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */ -#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */ -#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */ - -/* Register: MPU_DISABLEINDEBUG */ -/* Description: Disable erase and write protection mechanism in debug mode. */ - -/* Bit 0 : Disable protection mechanism in debug mode. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */ -#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */ - -/* Register: MPU_PROTBLOCKSIZE */ -/* Description: Erase and write protection block size. */ - -/* Bits 1..0 : Erase and write protection block size. */ -#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */ -#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */ -#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */ - - -/* Peripheral: NVMC */ -/* Description: Non Volatile Memory Controller. */ - -/* Register: NVMC_READY */ -/* Description: Ready flag. */ - -/* Bit 0 : NVMC ready. */ -#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */ -#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */ -#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */ -#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */ - -/* Register: NVMC_CONFIG */ -/* Description: Configuration register. */ - -/* Bits 1..0 : Program write enable. */ -#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */ -#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */ -#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */ -#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */ -#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */ - -/* Register: NVMC_ERASEALL */ -/* Description: Register for erasing all non-volatile user memory. */ - -/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */ -#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */ -#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */ -#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */ - -/* Register: NVMC_ERASEUICR */ -/* Description: Register for start erasing User Information Congfiguration Registers. */ - -/* Bit 0 : It can only be used when all contents of code region 1 are erased. */ -#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */ -#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */ -#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */ - - -/* Peripheral: POWER */ -/* Description: Power Control. */ - -/* Register: POWER_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on POFWARN event. */ -#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ -#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ -#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: POWER_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on POFWARN event. */ -#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */ -#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */ -#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */ -#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: POWER_RESETREAS */ -/* Description: Reset reason. */ - -/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */ -#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */ -#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */ -#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */ - -/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */ -#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */ -#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */ - -/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */ -#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */ -#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */ -#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */ - -/* Bit 3 : Reset from CPU lock-up detected. */ -#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */ -#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */ - -/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */ -#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */ -#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */ -#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */ - -/* Bit 1 : Reset from watchdog detected. */ -#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */ -#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */ -#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */ - -/* Bit 0 : Reset from pin-reset detected. */ -#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */ -#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */ -#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */ - -/* Register: POWER_RAMSTATUS */ -/* Description: Ram status register. */ - -/* Bit 3 : RAM block 3 status. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */ -#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */ - -/* Bit 2 : RAM block 2 status. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */ -#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */ - -/* Bit 1 : RAM block 1 status. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */ -#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */ - -/* Bit 0 : RAM block 0 status. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */ -#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */ -#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */ - -/* Register: POWER_SYSTEMOFF */ -/* Description: System off register. */ - -/* Bit 0 : Enter system off mode. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */ -#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */ - -/* Register: POWER_POFCON */ -/* Description: Power failure configuration. */ - -/* Bits 2..1 : Set threshold level. */ -#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */ -#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */ -#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */ -#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */ -#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */ - -/* Bit 0 : Power failure comparator enable. */ -#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */ -#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */ -#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */ -#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */ - -/* Register: POWER_GPREGRET */ -/* Description: General purpose retention register. This register is a retained register. */ - -/* Bits 7..0 : General purpose retention register. */ -#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */ -#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */ - -/* Register: POWER_RAMON */ -/* Description: Ram on/off. */ - -/* Bit 17 : RAM block 1 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */ -#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */ - -/* Bit 16 : RAM block 0 behaviour in OFF mode. */ -#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */ -#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */ -#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */ - -/* Bit 1 : RAM block 1 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */ -#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */ -#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */ - -/* Bit 0 : RAM block 0 behaviour in ON mode. */ -#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */ -#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */ -#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */ - -/* Register: POWER_RESET */ -/* Description: Pin reset functionality configuration register. This register is a retained register. */ - -/* Bit 0 : Enable or disable pin reset in debug interface mode. */ -#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */ -#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */ -#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */ -#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */ - -/* Register: POWER_RAMONB */ -/* Description: Ram on/off. */ - -/* Bit 17 : RAM block 3 behaviour in OFF mode. */ -#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */ -#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */ -#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */ -#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */ - -/* Bit 16 : RAM block 2 behaviour in OFF mode. */ -#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */ -#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */ -#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */ -#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */ - -/* Bit 1 : RAM block 3 behaviour in ON mode. */ -#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */ -#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */ -#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */ -#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */ - -/* Bit 0 : RAM block 2 behaviour in ON mode. */ -#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */ -#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */ -#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */ -#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */ - -/* Register: POWER_DCDCEN */ -/* Description: DCDC converter enable configuration register. */ - -/* Bit 0 : Enable DCDC converter. */ -#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */ -#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */ -#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */ - -/* Register: POWER_DCDCFORCE */ -/* Description: DCDC power-up force register. */ - -/* Bit 1 : DCDC power-up force on. */ -#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */ -#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */ -#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */ -#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */ - -/* Bit 0 : DCDC power-up force off. */ -#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */ -#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */ -#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */ -#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */ - - -/* Peripheral: PPI */ -/* Description: PPI controller. */ - -/* Register: PPI_CHEN */ -/* Description: Channel enable. */ - -/* Bit 31 : Enable PPI channel 31. */ -#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 30 : Enable PPI channel 30. */ -#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 29 : Enable PPI channel 29. */ -#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 28 : Enable PPI channel 28. */ -#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 27 : Enable PPI channel 27. */ -#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 26 : Enable PPI channel 26. */ -#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 25 : Enable PPI channel 25. */ -#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 24 : Enable PPI channel 24. */ -#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 23 : Enable PPI channel 23. */ -#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 22 : Enable PPI channel 22. */ -#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 21 : Enable PPI channel 21. */ -#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 20 : Enable PPI channel 20. */ -#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 15 : Enable PPI channel 15. */ -#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 14 : Enable PPI channel 14. */ -#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 13 : Enable PPI channel 13. */ -#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 12 : Enable PPI channel 12. */ -#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 11 : Enable PPI channel 11. */ -#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 10 : Enable PPI channel 10. */ -#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 9 : Enable PPI channel 9. */ -#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 8 : Enable PPI channel 8. */ -#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 7 : Enable PPI channel 7. */ -#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 6 : Enable PPI channel 6. */ -#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 5 : Enable PPI channel 5. */ -#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 4 : Enable PPI channel 4. */ -#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 3 : Enable PPI channel 3. */ -#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */ -#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */ - -/* Bit 2 : Enable PPI channel 2. */ -#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 1 : Enable PPI channel 1. */ -#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */ - -/* Bit 0 : Enable PPI channel 0. */ -#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */ - -/* Register: PPI_CHENSET */ -/* Description: Channel enable set. */ - -/* Bit 31 : Enable PPI channel 31. */ -#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 30 : Enable PPI channel 30. */ -#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 29 : Enable PPI channel 29. */ -#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 28 : Enable PPI channel 28. */ -#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 27 : Enable PPI channel 27. */ -#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 26 : Enable PPI channel 26. */ -#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 25 : Enable PPI channel 25. */ -#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 24 : Enable PPI channel 24. */ -#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 23 : Enable PPI channel 23. */ -#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 22 : Enable PPI channel 22. */ -#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 21 : Enable PPI channel 21. */ -#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 20 : Enable PPI channel 20. */ -#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 15 : Enable PPI channel 15. */ -#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 14 : Enable PPI channel 14. */ -#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 13 : Enable PPI channel 13. */ -#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 12 : Enable PPI channel 12. */ -#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 11 : Enable PPI channel 11. */ -#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 10 : Enable PPI channel 10. */ -#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 9 : Enable PPI channel 9. */ -#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 8 : Enable PPI channel 8. */ -#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 7 : Enable PPI channel 7. */ -#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 6 : Enable PPI channel 6. */ -#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 5 : Enable PPI channel 5. */ -#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 4 : Enable PPI channel 4. */ -#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 3 : Enable PPI channel 3. */ -#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 2 : Enable PPI channel 2. */ -#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 1 : Enable PPI channel 1. */ -#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */ - -/* Bit 0 : Enable PPI channel 0. */ -#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */ - -/* Register: PPI_CHENCLR */ -/* Description: Channel enable clear. */ - -/* Bit 31 : Disable PPI channel 31. */ -#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 30 : Disable PPI channel 30. */ -#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 29 : Disable PPI channel 29. */ -#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 28 : Disable PPI channel 28. */ -#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 27 : Disable PPI channel 27. */ -#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 26 : Disable PPI channel 26. */ -#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 25 : Disable PPI channel 25. */ -#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 24 : Disable PPI channel 24. */ -#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 23 : Disable PPI channel 23. */ -#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 22 : Disable PPI channel 22. */ -#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 21 : Disable PPI channel 21. */ -#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 20 : Disable PPI channel 20. */ -#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 15 : Disable PPI channel 15. */ -#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 14 : Disable PPI channel 14. */ -#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 13 : Disable PPI channel 13. */ -#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 12 : Disable PPI channel 12. */ -#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 11 : Disable PPI channel 11. */ -#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 10 : Disable PPI channel 10. */ -#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 9 : Disable PPI channel 9. */ -#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 8 : Disable PPI channel 8. */ -#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 7 : Disable PPI channel 7. */ -#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 6 : Disable PPI channel 6. */ -#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 5 : Disable PPI channel 5. */ -#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 4 : Disable PPI channel 4. */ -#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 3 : Disable PPI channel 3. */ -#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 2 : Disable PPI channel 2. */ -#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 1 : Disable PPI channel 1. */ -#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */ - -/* Bit 0 : Disable PPI channel 0. */ -#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */ -#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */ -#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */ - -/* Register: PPI_CHG */ -/* Description: Channel group configuration. */ - -/* Bit 31 : Include CH31 in channel group. */ -#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */ -#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */ -#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */ - -/* Bit 30 : Include CH30 in channel group. */ -#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */ -#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */ -#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */ - -/* Bit 29 : Include CH29 in channel group. */ -#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */ -#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */ -#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */ - -/* Bit 28 : Include CH28 in channel group. */ -#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */ -#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */ -#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */ - -/* Bit 27 : Include CH27 in channel group. */ -#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */ -#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */ -#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */ - -/* Bit 26 : Include CH26 in channel group. */ -#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */ -#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */ -#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */ - -/* Bit 25 : Include CH25 in channel group. */ -#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */ -#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */ -#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */ - -/* Bit 24 : Include CH24 in channel group. */ -#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */ -#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */ -#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */ - -/* Bit 23 : Include CH23 in channel group. */ -#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */ -#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */ -#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */ - -/* Bit 22 : Include CH22 in channel group. */ -#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */ -#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */ -#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */ - -/* Bit 21 : Include CH21 in channel group. */ -#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */ -#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */ -#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */ - -/* Bit 20 : Include CH20 in channel group. */ -#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */ -#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */ -#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */ - -/* Bit 15 : Include CH15 in channel group. */ -#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */ -#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */ -#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */ - -/* Bit 14 : Include CH14 in channel group. */ -#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */ -#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */ -#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */ - -/* Bit 13 : Include CH13 in channel group. */ -#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */ -#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */ -#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */ - -/* Bit 12 : Include CH12 in channel group. */ -#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */ -#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */ -#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */ - -/* Bit 11 : Include CH11 in channel group. */ -#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */ -#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */ -#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */ - -/* Bit 10 : Include CH10 in channel group. */ -#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */ -#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */ -#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */ - -/* Bit 9 : Include CH9 in channel group. */ -#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */ -#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */ -#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */ - -/* Bit 8 : Include CH8 in channel group. */ -#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */ -#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */ -#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */ - -/* Bit 7 : Include CH7 in channel group. */ -#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */ -#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */ -#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */ - -/* Bit 6 : Include CH6 in channel group. */ -#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */ -#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */ -#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */ - -/* Bit 5 : Include CH5 in channel group. */ -#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */ -#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */ -#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */ - -/* Bit 4 : Include CH4 in channel group. */ -#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */ -#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */ -#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */ - -/* Bit 3 : Include CH3 in channel group. */ -#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */ -#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */ -#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */ - -/* Bit 2 : Include CH2 in channel group. */ -#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */ -#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */ -#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */ - -/* Bit 1 : Include CH1 in channel group. */ -#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */ -#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */ -#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */ - -/* Bit 0 : Include CH0 in channel group. */ -#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */ -#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */ -#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */ -#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */ - - -/* Peripheral: QDEC */ -/* Description: Rotary decoder. */ - -/* Register: QDEC_SHORTS */ -/* Description: Shortcuts for the QDEC. */ - -/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */ -#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: QDEC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on ACCOF event. */ -#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on REPORTRDY event. */ -#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on SAMPLERDY event. */ -#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: QDEC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on ACCOF event. */ -#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */ -#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on REPORTRDY event. */ -#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */ -#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on SAMPLERDY event. */ -#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */ -#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: QDEC_ENABLE */ -/* Description: Enable the QDEC. */ - -/* Bit 0 : Enable or disable QDEC. */ -#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */ -#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */ - -/* Register: QDEC_LEDPOL */ -/* Description: LED output pin polarity. */ - -/* Bit 0 : LED output pin polarity. */ -#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */ -#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */ -#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */ - -/* Register: QDEC_SAMPLEPER */ -/* Description: Sample period. */ - -/* Bits 2..0 : Sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */ -#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */ -#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */ - -/* Register: QDEC_SAMPLE */ -/* Description: Motion sample value. */ - -/* Bits 31..0 : Last sample taken in compliment to 2. */ -#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */ -#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */ - -/* Register: QDEC_REPORTPER */ -/* Description: Number of samples to generate an EVENT_REPORTRDY. */ - -/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */ -#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */ -#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */ -#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */ - -/* Register: QDEC_DBFEN */ -/* Description: Enable debouncer input filters. */ - -/* Bit 0 : Enable debounce input filters. */ -#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */ -#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */ -#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */ - -/* Register: QDEC_LEDPRE */ -/* Description: Time LED is switched ON before the sample. */ - -/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */ -#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */ -#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */ - -/* Register: QDEC_ACCDBL */ -/* Description: Accumulated double (error) transitions register. */ - -/* Bits 3..0 : Accumulated double (error) transitions. */ -#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */ -#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */ - -/* Register: QDEC_ACCDBLREAD */ -/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */ - -/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */ -#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */ - -/* Register: QDEC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RADIO */ -/* Description: The radio. */ - -/* Register: RADIO_SHORTS */ -/* Description: Shortcuts for the radio. */ - -/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 5 : Shortcut between END event and START task. */ -#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */ -#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */ -#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between DISABLED event and RXEN task. */ -#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */ -#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between DISABLED event and TXEN task. */ -#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */ -#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between END event and DISABLE task. */ -#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */ -#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between READY event and START task. */ -#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */ -#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */ -#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */ -#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: RADIO_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 10 : Enable interrupt on BCMATCH event. */ -#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on RSSIEND event. */ -#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 6 : Enable interrupt on DEVMISS event. */ -#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 5 : Enable interrupt on DEVMATCH event. */ -#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 4 : Enable interrupt on DISABLED event. */ -#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 3 : Enable interrupt on END event. */ -#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on PAYLOAD event. */ -#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on ADDRESS event. */ -#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on READY event. */ -#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RADIO_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 10 : Disable interrupt on BCMATCH event. */ -#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */ -#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on RSSIEND event. */ -#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */ -#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 6 : Disable interrupt on DEVMISS event. */ -#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */ -#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 5 : Disable interrupt on DEVMATCH event. */ -#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */ -#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 4 : Disable interrupt on DISABLED event. */ -#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */ -#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 3 : Disable interrupt on END event. */ -#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */ -#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on PAYLOAD event. */ -#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */ -#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on ADDRESS event. */ -#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ -#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on READY event. */ -#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */ -#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RADIO_CRCSTATUS */ -/* Description: CRC status of received packet. */ - -/* Bit 0 : CRC status of received packet. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */ -#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */ - -/* Register: RADIO_RXMATCH */ -/* Description: Received address. */ - -/* Bits 2..0 : Logical address in which previous packet was received. */ -#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */ -#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */ - -/* Register: RADIO_RXCRC */ -/* Description: Received CRC. */ - -/* Bits 23..0 : CRC field of previously received packet. */ -#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */ -#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */ - -/* Register: RADIO_DAI */ -/* Description: Device address match index. */ - -/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */ -#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */ -#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */ - -/* Register: RADIO_FREQUENCY */ -/* Description: Frequency. */ - -/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */ -#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ - -/* Register: RADIO_TXPOWER */ -/* Description: Output power. */ - -/* Bits 7..0 : Radio output power. Decision point: TXEN task. */ -#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */ -#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */ -#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */ -#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */ - -/* Register: RADIO_MODE */ -/* Description: Data rate and modulation. */ - -/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */ -#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */ -#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */ - -/* Register: RADIO_PCNF0 */ -/* Description: Packet configuration 0. */ - -/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */ -#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */ -#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */ - -/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */ -#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */ -#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */ - -/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */ -#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */ -#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */ - -/* Register: RADIO_PCNF1 */ -/* Description: Packet configuration 1. */ - -/* Bit 25 : Packet whitening enable. */ -#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */ -#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */ -#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */ - -/* Bit 24 : On air endianness of packet length field. Decision point: START task. */ -#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */ -#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */ -#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */ - -/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */ -#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */ -#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */ - -/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */ -#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */ -#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */ - -/* Bits 7..0 : Maximum length of packet payload in number of bytes. */ -#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */ -#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */ - -/* Register: RADIO_PREFIX0 */ -/* Description: Prefixes bytes for logical addresses 0 to 3. */ - -/* Bits 31..24 : Address prefix 3. Decision point: START task. */ -#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */ -#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */ - -/* Bits 23..16 : Address prefix 2. Decision point: START task. */ -#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */ -#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */ - -/* Bits 15..8 : Address prefix 1. Decision point: START task. */ -#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */ -#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */ - -/* Bits 7..0 : Address prefix 0. Decision point: START task. */ -#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */ -#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */ - -/* Register: RADIO_PREFIX1 */ -/* Description: Prefixes bytes for logical addresses 4 to 7. */ - -/* Bits 31..24 : Address prefix 7. Decision point: START task. */ -#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */ -#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */ - -/* Bits 23..16 : Address prefix 6. Decision point: START task. */ -#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */ -#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */ - -/* Bits 15..8 : Address prefix 5. Decision point: START task. */ -#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */ -#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */ - -/* Bits 7..0 : Address prefix 4. Decision point: START task. */ -#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */ -#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */ - -/* Register: RADIO_TXADDRESS */ -/* Description: Transmit address select. */ - -/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */ -#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */ -#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */ - -/* Register: RADIO_RXADDRESSES */ -/* Description: Receive address select. */ - -/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */ -#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */ -#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */ -#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */ -#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */ -#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */ -#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */ -#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */ - -/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */ -#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */ -#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */ -#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */ - -/* Register: RADIO_CRCCNF */ -/* Description: CRC configuration. */ - -/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */ -#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */ -#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */ -#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */ -#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */ - -/* Bits 1..0 : CRC length. Decision point: START task. */ -#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */ -#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */ -#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */ -#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */ -#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */ -#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */ - -/* Register: RADIO_CRCPOLY */ -/* Description: CRC polynomial. */ - -/* Bits 23..0 : CRC polynomial. Decision point: START task. */ -#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */ -#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */ - -/* Register: RADIO_CRCINIT */ -/* Description: CRC initial value. */ - -/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */ -#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */ -#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */ - -/* Register: RADIO_TEST */ -/* Description: Test features enable register. */ - -/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */ -#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */ -#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */ -#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */ -#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */ - -/* Bit 0 : Constant carrier. Decision point: TXEN task. */ -#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */ -#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */ -#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */ -#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */ - -/* Register: RADIO_TIFS */ -/* Description: Inter Frame Spacing in microseconds. */ - -/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */ -#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */ -#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */ - -/* Register: RADIO_RSSISAMPLE */ -/* Description: RSSI sample. */ - -/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */ -#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */ - -/* Register: RADIO_STATE */ -/* Description: Current radio state. */ - -/* Bits 3..0 : Current radio state. */ -#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */ -#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */ -#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */ -#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */ -#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */ -#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */ -#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */ -#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */ -#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */ -#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */ -#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */ - -/* Register: RADIO_DATAWHITEIV */ -/* Description: Data whitening initial value. */ - -/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */ -#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */ - -/* Register: RADIO_DAP */ -/* Description: Device address prefix. */ - -/* Bits 15..0 : Device address prefix. */ -#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */ -#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */ - -/* Register: RADIO_DACNF */ -/* Description: Device address match configuration. */ - -/* Bit 15 : TxAdd for device address 7. */ -#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */ -#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */ - -/* Bit 14 : TxAdd for device address 6. */ -#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */ -#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */ - -/* Bit 13 : TxAdd for device address 5. */ -#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */ -#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */ - -/* Bit 12 : TxAdd for device address 4. */ -#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */ -#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */ - -/* Bit 11 : TxAdd for device address 3. */ -#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */ -#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */ - -/* Bit 10 : TxAdd for device address 2. */ -#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */ -#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */ - -/* Bit 9 : TxAdd for device address 1. */ -#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */ -#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */ - -/* Bit 8 : TxAdd for device address 0. */ -#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */ -#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */ - -/* Bit 7 : Enable or disable device address matching using device address 7. */ -#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */ -#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */ -#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */ - -/* Bit 6 : Enable or disable device address matching using device address 6. */ -#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */ -#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */ -#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */ - -/* Bit 5 : Enable or disable device address matching using device address 5. */ -#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */ -#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */ -#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */ - -/* Bit 4 : Enable or disable device address matching using device address 4. */ -#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */ -#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */ -#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */ - -/* Bit 3 : Enable or disable device address matching using device address 3. */ -#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */ -#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */ -#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */ - -/* Bit 2 : Enable or disable device address matching using device address 2. */ -#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */ -#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */ -#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */ - -/* Bit 1 : Enable or disable device address matching using device address 1. */ -#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */ -#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */ -#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */ - -/* Bit 0 : Enable or disable device address matching using device address 0. */ -#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */ -#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */ -#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */ -#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */ - -/* Register: RADIO_OVERRIDE0 */ -/* Description: Trim value override register 0. */ - -/* Bits 31..0 : Trim value override 0. */ -#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */ -#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */ - -/* Register: RADIO_OVERRIDE1 */ -/* Description: Trim value override register 1. */ - -/* Bits 31..0 : Trim value override 1. */ -#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */ -#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */ - -/* Register: RADIO_OVERRIDE2 */ -/* Description: Trim value override register 2. */ - -/* Bits 31..0 : Trim value override 2. */ -#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */ -#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */ - -/* Register: RADIO_OVERRIDE3 */ -/* Description: Trim value override register 3. */ - -/* Bits 31..0 : Trim value override 3. */ -#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */ -#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */ - -/* Register: RADIO_OVERRIDE4 */ -/* Description: Trim value override register 4. */ - -/* Bit 31 : Enable or disable override of default trim values. */ -#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */ -#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */ -#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */ - -/* Bits 27..0 : Trim value override 4. */ -#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */ -#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */ - -/* Register: RADIO_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RNG */ -/* Description: Random Number Generator. */ - -/* Register: RNG_SHORTS */ -/* Description: Shortcuts for the RNG. */ - -/* Bit 0 : Shortcut between VALRDY event and STOP task. */ -#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */ -#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: RNG_INTENSET */ -/* Description: Interrupt enable set register */ - -/* Bit 0 : Enable interrupt on VALRDY event. */ -#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RNG_INTENCLR */ -/* Description: Interrupt enable clear register */ - -/* Bit 0 : Disable interrupt on VALRDY event. */ -#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */ -#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RNG_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 0 : Digital error correction enable. */ -#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */ -#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */ -#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */ - -/* Register: RNG_VALUE */ -/* Description: RNG random number. */ - -/* Bits 7..0 : Generated random number. */ -#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */ -#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */ - -/* Register: RNG_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: RTC */ -/* Description: Real time counter 0. */ - -/* Register: RTC_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on COMPARE[3] event. */ -#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 18 : Enable interrupt on COMPARE[2] event. */ -#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 17 : Enable interrupt on COMPARE[1] event. */ -#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 16 : Enable interrupt on COMPARE[0] event. */ -#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on OVRFLW event. */ -#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on TICK event. */ -#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: RTC_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on COMPARE[3] event. */ -#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 18 : Disable interrupt on COMPARE[2] event. */ -#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 17 : Disable interrupt on COMPARE[1] event. */ -#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 16 : Disable interrupt on COMPARE[0] event. */ -#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on OVRFLW event. */ -#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on TICK event. */ -#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */ -#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */ -#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: RTC_EVTEN */ -/* Description: Configures event enable routing to PPI for each RTC event. */ - -/* Bit 19 : COMPARE[3] event enable. */ -#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 18 : COMPARE[2] event enable. */ -#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 17 : COMPARE[1] event enable. */ -#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 16 : COMPARE[0] event enable. */ -#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 1 : OVRFLW event enable. */ -#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */ - -/* Bit 0 : TICK event enable. */ -#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */ - -/* Register: RTC_EVTENSET */ -/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */ - -/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */ -#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */ - -/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */ -#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */ - -/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */ -#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */ - -/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */ -#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */ - -/* Bit 1 : Enable routing to PPI of OVRFLW event. */ -#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */ - -/* Bit 0 : Enable routing to PPI of TICK event. */ -#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */ - -/* Register: RTC_EVTENCLR */ -/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */ - -/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */ -#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */ -#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */ -#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */ -#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 1 : Disable routing to PPI of OVRFLW event. */ -#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */ -#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */ - -/* Bit 0 : Disable routing to PPI of TICK event. */ -#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */ -#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */ -#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */ -#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */ -#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */ - -/* Register: RTC_COUNTER */ -/* Description: Current COUNTER value. */ - -/* Bits 23..0 : Counter value. */ -#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */ -#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */ - -/* Register: RTC_PRESCALER */ -/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */ - -/* Bits 11..0 : RTC PRESCALER value. */ -#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: RTC_CC */ -/* Description: Capture/compare registers. */ - -/* Bits 23..0 : Compare value. */ -#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */ -#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */ - -/* Register: RTC_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPI */ -/* Description: SPI master 0. */ - -/* Register: SPI_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 2 : Enable interrupt on READY event. */ -#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPI_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 2 : Disable interrupt on READY event. */ -#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */ -#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */ -#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPI_ENABLE */ -/* Description: Enable SPI. */ - -/* Bits 2..0 : Enable or disable SPI. */ -#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */ -#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */ - -/* Register: SPI_RXD */ -/* Description: RX data. */ - -/* Bits 7..0 : RX data from last transfer. */ -#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: SPI_TXD */ -/* Description: TX data. */ - -/* Bits 7..0 : TX data for next transfer. */ -#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: SPI_FREQUENCY */ -/* Description: SPI frequency */ - -/* Bits 31..0 : SPI data rate. */ -#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */ -#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */ -#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */ -#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */ -#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */ - -/* Register: SPI_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPI_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPIM */ -/* Description: SPI master with easyDMA 1. */ - -/* Register: SPIM_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on STARTED event. */ -#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */ -#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 8 : Enable interrupt on ENDTX event. */ -#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 4 : Enable interrupt on ENDRX event. */ -#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on STOPPED event. */ -#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPIM_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on STARTED event. */ -#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */ -#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 8 : Disable interrupt on ENDTX event. */ -#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */ -#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 4 : Disable interrupt on ENDRX event. */ -#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on STOPPED event. */ -#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPIM_ENABLE */ -/* Description: Enable SPIM. */ - -/* Bits 3..0 : Enable or disable SPIM. */ -#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */ -#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */ - -/* Register: SPIM_FREQUENCY */ -/* Description: SPI frequency. */ - -/* Bits 31..0 : SPI master data rate. */ -#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */ -#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */ -#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */ - -/* Register: SPIM_RXD_PTR */ -/* Description: Data pointer. */ - -/* Bits 31..0 : Data pointer. */ -#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIM_RXD_MAXCNT */ -/* Description: Maximum number of buffer bytes to receive. */ - -/* Bits 7..0 : Maximum number of buffer bytes to receive. */ -#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIM_RXD_AMOUNT */ -/* Description: Number of bytes received in the last transaction. */ - -/* Bits 7..0 : Number of bytes received in the last transaction. */ -#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIM_TXD_PTR */ -/* Description: Data pointer. */ - -/* Bits 31..0 : Data pointer. */ -#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */ -#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */ - -/* Register: SPIM_TXD_MAXCNT */ -/* Description: Maximum number of buffer bytes to send. */ - -/* Bits 7..0 : Maximum number of buffer bytes to send. */ -#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */ -#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */ - -/* Register: SPIM_TXD_AMOUNT */ -/* Description: Number of bytes sent in the last transaction. */ - -/* Bits 7..0 : Number of bytes sent in the last transaction. */ -#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */ -#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */ - -/* Register: SPIM_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPIM_ORC */ -/* Description: Over-read character. */ - -/* Bits 7..0 : Over-read character. */ -#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - -/* Register: SPIM_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: SPIS */ -/* Description: SPI slave 1. */ - -/* Register: SPIS_SHORTS */ -/* Description: Shortcuts for SPIS. */ - -/* Bit 2 : Shortcut between END event and the ACQUIRE task. */ -#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */ -#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */ -#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: SPIS_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 10 : Enable interrupt on ACQUIRED event. */ -#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 4 : enable interrupt on ENDRX event. */ -#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on END event. */ -#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: SPIS_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 10 : Disable interrupt on ACQUIRED event. */ -#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */ -#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 4 : Disable interrupt on ENDRX event. */ -#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */ -#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */ -#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on END event. */ -#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */ -#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */ -#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */ -#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */ -#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: SPIS_SEMSTAT */ -/* Description: Semaphore status. */ - -/* Bits 1..0 : Semaphore status. */ -#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */ -#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */ -#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */ -#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */ -#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */ - -/* Register: SPIS_STATUS */ -/* Description: Status from last transaction. */ - -/* Bit 1 : RX buffer overflow detected, and prevented. */ -#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */ -#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */ -#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */ -#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */ - -/* Bit 0 : TX buffer overread detected, and prevented. */ -#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */ -#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */ -#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */ -#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */ - -/* Register: SPIS_ENABLE */ -/* Description: Enable SPIS. */ - -/* Bits 2..0 : Enable or disable SPIS. */ -#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */ -#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */ - -/* Register: SPIS_MAXRX */ -/* Description: Maximum number of bytes in the receive buffer. */ - -/* Bits 7..0 : Maximum number of bytes in the receive buffer. */ -#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */ -#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */ - -/* Register: SPIS_AMOUNTRX */ -/* Description: Number of bytes received in last granted transaction. */ - -/* Bits 7..0 : Number of bytes received in last granted transaction. */ -#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */ -#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */ - -/* Register: SPIS_MAXTX */ -/* Description: Maximum number of bytes in the transmit buffer. */ - -/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */ -#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */ -#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */ - -/* Register: SPIS_AMOUNTTX */ -/* Description: Number of bytes transmitted in last granted transaction. */ - -/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */ -#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */ -#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */ - -/* Register: SPIS_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 2 : Serial clock (SCK) polarity. */ -#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */ -#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */ -#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */ -#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */ - -/* Bit 1 : Serial clock (SCK) phase. */ -#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */ -#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */ -#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */ -#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */ - -/* Bit 0 : Bit order. */ -#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */ -#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */ -#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */ -#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */ - -/* Register: SPIS_DEF */ -/* Description: Default character. */ - -/* Bits 7..0 : Default character. */ -#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */ -#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */ - -/* Register: SPIS_ORC */ -/* Description: Over-read character. */ - -/* Bits 7..0 : Over-read character. */ -#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */ -#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */ - -/* Register: SPIS_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TEMP */ -/* Description: Temperature Sensor. */ - -/* Register: TEMP_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on DATARDY event. */ -#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TEMP_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on DATARDY event. */ -#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */ -#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TEMP_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TIMER */ -/* Description: Timer 0. */ - -/* Register: TIMER_SHORTS */ -/* Description: Shortcuts for Timer. */ - -/* Bit 11 : Shortcut between CC[3] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */ -#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 10 : Shortcut between CC[2] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */ -#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 9 : Shortcut between CC[1] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */ -#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 8 : Shortcut between CC[0] event and the STOP task. */ -#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */ -#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */ -#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: TIMER_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 19 : Enable interrupt on COMPARE[3] */ -#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 18 : Enable interrupt on COMPARE[2] */ -#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 17 : Enable interrupt on COMPARE[1] */ -#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 16 : Enable interrupt on COMPARE[0] */ -#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TIMER_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 19 : Disable interrupt on COMPARE[3] */ -#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */ -#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 18 : Disable interrupt on COMPARE[2] */ -#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */ -#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 17 : Disable interrupt on COMPARE[1] */ -#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */ -#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 16 : Disable interrupt on COMPARE[0] */ -#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */ -#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */ -#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */ -#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TIMER_MODE */ -/* Description: Timer Mode selection. */ - -/* Bit 0 : Select Normal or Counter mode. */ -#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */ -#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */ -#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */ -#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */ - -/* Register: TIMER_BITMODE */ -/* Description: Sets timer behaviour. */ - -/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */ -#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */ -#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */ -#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */ - -/* Register: TIMER_PRESCALER */ -/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */ - -/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */ -#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */ -#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */ - -/* Register: TIMER_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: TWI */ -/* Description: Two-wire interface master 0. */ - -/* Register: TWI_SHORTS */ -/* Description: Shortcuts for TWI. */ - -/* Bit 1 : Shortcut between BB event and the STOP task. */ -#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */ -#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */ -#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 0 : Shortcut between BB event and the SUSPEND task. */ -#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */ -#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */ -#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: TWI_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 18 : Enable interrupt on SUSPENDED event. */ -#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 14 : Enable interrupt on BB event. */ -#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 9 : Enable interrupt on ERROR event. */ -#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on TXDSENT event. */ -#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on READY event. */ -#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on STOPPED event. */ -#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: TWI_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 18 : Disable interrupt on SUSPENDED event. */ -#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */ -#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 14 : Disable interrupt on BB event. */ -#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */ -#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */ -#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 9 : Disable interrupt on ERROR event. */ -#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on TXDSENT event. */ -#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */ -#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on RXDREADY event. */ -#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */ -#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on STOPPED event. */ -#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */ -#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */ -#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */ -#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: TWI_ERRORSRC */ -/* Description: Two-wire error source. Write error field to 1 to clear error. */ - -/* Bit 2 : NACK received after sending a data byte. */ -#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */ -#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */ -#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 1 : NACK received after sending the address. */ -#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */ -#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */ -#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */ -#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ -#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ -#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ - -/* Register: TWI_ENABLE */ -/* Description: Enable two-wire master. */ - -/* Bits 2..0 : Enable or disable W2M */ -#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */ -#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */ - -/* Register: TWI_RXD */ -/* Description: RX data register. */ - -/* Bits 7..0 : RX data from last transfer. */ -#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: TWI_TXD */ -/* Description: TX data register. */ - -/* Bits 7..0 : TX data for next transfer. */ -#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: TWI_FREQUENCY */ -/* Description: Two-wire frequency. */ - -/* Bits 31..0 : Two-wire master clock frequency. */ -#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */ -#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */ -#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */ - -/* Register: TWI_ADDRESS */ -/* Description: Address used in the two-wire transfer. */ - -/* Bits 6..0 : Two-wire address. */ -#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */ -#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */ - -/* Register: TWI_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: UART */ -/* Description: Universal Asynchronous Receiver/Transmitter. */ - -/* Register: UART_SHORTS */ -/* Description: Shortcuts for UART. */ - -/* Bit 4 : Shortcut between NCTS event and STOPRX task. */ -#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */ -#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Bit 3 : Shortcut between CTS event and STARTRX task. */ -#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */ -#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */ -#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */ - -/* Register: UART_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 17 : Enable interrupt on RXTO event. */ -#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 9 : Enable interrupt on ERROR event. */ -#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 7 : Enable interrupt on TXRDY event. */ -#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 2 : Enable interrupt on RXRDY event. */ -#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 1 : Enable interrupt on NCTS event. */ -#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Bit 0 : Enable interrupt on CTS event. */ -#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: UART_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 17 : Disable interrupt on RXTO event. */ -#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */ -#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */ -#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 9 : Disable interrupt on ERROR event. */ -#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */ -#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */ -#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 7 : Disable interrupt on TXRDY event. */ -#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */ -#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 2 : Disable interrupt on RXRDY event. */ -#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */ -#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 1 : Disable interrupt on NCTS event. */ -#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */ -#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */ -#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Bit 0 : Disable interrupt on CTS event. */ -#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */ -#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */ -#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */ -#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */ -#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: UART_ERRORSRC */ -/* Description: Error source. Write error field to 1 to clear error. */ - -/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */ -#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */ -#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */ -#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */ -#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */ -#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */ -#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */ - -/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */ -#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */ -#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */ -#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */ -#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */ - -/* Register: UART_ENABLE */ -/* Description: Enable UART and acquire IOs. */ - -/* Bits 2..0 : Enable or disable UART and acquire IOs. */ -#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */ -#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */ -#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */ -#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */ - -/* Register: UART_RXD */ -/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */ - -/* Bits 7..0 : RX data from previous transfer. Double buffered. */ -#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */ -#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */ - -/* Register: UART_TXD */ -/* Description: TXD register. */ - -/* Bits 7..0 : TX data for transfer. */ -#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */ -#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */ - -/* Register: UART_BAUDRATE */ -/* Description: UART Baudrate. */ - -/* Bits 31..0 : UART baudrate. */ -#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */ -#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */ -#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */ - -/* Register: UART_CONFIG */ -/* Description: Configuration of parity and hardware flow control register. */ - -/* Bits 3..1 : Include parity bit. */ -#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */ -#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */ -#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */ -#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */ - -/* Bit 0 : Hardware flow control. */ -#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */ -#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */ -#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */ -#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */ - -/* Register: UART_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/* Peripheral: UICR */ -/* Description: User Information Configuration. */ - -/* Register: UICR_RBPCONF */ -/* Description: Readback protection configuration. */ - -/* Bits 15..8 : Readback protect all code in the device. */ -#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */ -#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */ -#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */ -#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */ - -/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */ -#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */ -#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */ -#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */ -#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */ - -/* Register: UICR_XTALFREQ */ -/* Description: Reset value for CLOCK XTALFREQ register. */ - -/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */ -#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */ -#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */ -#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */ - -/* Register: UICR_FWID */ -/* Description: Firmware ID. */ - -/* Bits 15..0 : Identification number for the firmware loaded into the chip. */ -#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */ -#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */ - - -/* Peripheral: WDT */ -/* Description: Watchdog Timer. */ - -/* Register: WDT_INTENSET */ -/* Description: Interrupt enable set register. */ - -/* Bit 0 : Enable interrupt on TIMEOUT event. */ -#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ -#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ -#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */ - -/* Register: WDT_INTENCLR */ -/* Description: Interrupt enable clear register. */ - -/* Bit 0 : Disable interrupt on TIMEOUT event. */ -#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */ -#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */ -#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */ -#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */ - -/* Register: WDT_RUNSTATUS */ -/* Description: Watchdog running status. */ - -/* Bit 0 : Watchdog running status. */ -#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */ -#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */ -#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */ - -/* Register: WDT_REQSTATUS */ -/* Description: Request status. */ - -/* Bit 7 : Request status for RR[7]. */ -#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */ - -/* Bit 6 : Request status for RR[6]. */ -#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */ - -/* Bit 5 : Request status for RR[5]. */ -#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */ - -/* Bit 4 : Request status for RR[4]. */ -#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */ - -/* Bit 3 : Request status for RR[3]. */ -#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */ - -/* Bit 2 : Request status for RR[2]. */ -#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */ - -/* Bit 1 : Request status for RR[1]. */ -#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */ - -/* Bit 0 : Request status for RR[0]. */ -#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */ -#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */ - -/* Register: WDT_RREN */ -/* Description: Reload request enable. */ - -/* Bit 7 : Enable or disable RR[7] register. */ -#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */ -#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */ -#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */ -#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */ - -/* Bit 6 : Enable or disable RR[6] register. */ -#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */ -#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */ -#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */ -#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */ - -/* Bit 5 : Enable or disable RR[5] register. */ -#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */ -#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */ -#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */ -#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */ - -/* Bit 4 : Enable or disable RR[4] register. */ -#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */ -#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */ -#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */ -#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */ - -/* Bit 3 : Enable or disable RR[3] register. */ -#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */ -#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */ -#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */ -#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */ - -/* Bit 2 : Enable or disable RR[2] register. */ -#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */ -#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */ -#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */ -#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */ - -/* Bit 1 : Enable or disable RR[1] register. */ -#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */ -#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */ -#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */ -#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */ - -/* Bit 0 : Enable or disable RR[0] register. */ -#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */ -#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */ -#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */ -#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */ - -/* Register: WDT_CONFIG */ -/* Description: Configuration register. */ - -/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */ -#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */ -#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */ -#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */ -#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */ - -/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */ -#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */ -#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */ -#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */ - -/* Register: WDT_RR */ -/* Description: Reload requests registers. */ - -/* Bits 31..0 : Reload register. */ -#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */ -#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */ -#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */ - -/* Register: WDT_POWER */ -/* Description: Peripheral power control. */ - -/* Bit 0 : Peripheral power control. */ -#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */ -#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */ -#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */ -#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */ - - -/*lint --flb "Leave library region" */ -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_deprecated.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_deprecated.h deleted file mode 100644 index 4c60f0b59a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf51_deprecated.h +++ /dev/null @@ -1,440 +0,0 @@ -/* - * Copyright (c) Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of other - * contributors to this software may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef NRF51_DEPRECATED_H -#define NRF51_DEPRECATED_H - -/*lint ++flb "Enter library region */ - -/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and - * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these - * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead. - */ - -/* NVMC */ -/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */ -#define ERASEPROTECTEDPAGE ERASEPCR0 - - -/* LPCOMP */ -/* The interrupt ISR was renamed. Adding old name to the macros. */ -#define LPCOMP_COMP_IRQHandler LPCOMP_IRQHandler -#define LPCOMP_COMP_IRQn LPCOMP_IRQn - - -/* MPU */ -/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */ -#define MPU_PERR0_LPCOMP_COMP_Pos MPU_PERR0_LPCOMP_Pos -#define MPU_PERR0_LPCOMP_COMP_Msk MPU_PERR0_LPCOMP_Msk -#define MPU_PERR0_LPCOMP_COMP_InRegion1 MPU_PERR0_LPCOMP_InRegion1 -#define MPU_PERR0_LPCOMP_COMP_InRegion0 MPU_PERR0_LPCOMP_InRegion0 - - -/* POWER */ -/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ -#define POWER_RAMON_OFFRAM3_Pos (19UL) -#define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) -#define POWER_RAMON_OFFRAM3_RAM3Off (0UL) -#define POWER_RAMON_OFFRAM3_RAM3On (1UL) -/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ -#define POWER_RAMON_OFFRAM2_Pos (18UL) -#define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) -#define POWER_RAMON_OFFRAM2_RAM2Off (0UL) -#define POWER_RAMON_OFFRAM2_RAM2On (1UL) -/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ -#define POWER_RAMON_ONRAM3_Pos (3UL) -#define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) -#define POWER_RAMON_ONRAM3_RAM3Off (0UL) -#define POWER_RAMON_ONRAM3_RAM3On (1UL) -/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */ -#define POWER_RAMON_ONRAM2_Pos (2UL) -#define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) -#define POWER_RAMON_ONRAM2_RAM2Off (0UL) -#define POWER_RAMON_ONRAM2_RAM2On (1UL) - - -/* RADIO */ -/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */ -#define RADIO_TXPOWER_TXPOWER_Neg40dBm RADIO_TXPOWER_TXPOWER_Neg30dBm -/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */ -#define RADIO_CRCCNF_SKIP_ADDR_Pos RADIO_CRCCNF_SKIPADDR_Pos -#define RADIO_CRCCNF_SKIP_ADDR_Msk RADIO_CRCCNF_SKIPADDR_Msk -#define RADIO_CRCCNF_SKIP_ADDR_Include RADIO_CRCCNF_SKIPADDR_Include -#define RADIO_CRCCNF_SKIP_ADDR_Skip RADIO_CRCCNF_SKIPADDR_Skip -/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */ -#define RADIO_TEST_PLL_LOCK_Pos RADIO_TEST_PLLLOCK_Pos -#define RADIO_TEST_PLL_LOCK_Msk RADIO_TEST_PLLLOCK_Msk -#define RADIO_TEST_PLL_LOCK_Disabled RADIO_TEST_PLLLOCK_Disabled -#define RADIO_TEST_PLL_LOCK_Enabled RADIO_TEST_PLLLOCK_Enabled -/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */ -#define RADIO_TEST_CONST_CARRIER_Pos RADIO_TEST_CONSTCARRIER_Pos -#define RADIO_TEST_CONST_CARRIER_Msk RADIO_TEST_CONSTCARRIER_Msk -#define RADIO_TEST_CONST_CARRIER_Disabled RADIO_TEST_CONSTCARRIER_Disabled -#define RADIO_TEST_CONST_CARRIER_Enabled RADIO_TEST_CONSTCARRIER_Enabled - - -/* FICR */ -/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */ -#define SIZERAMBLOCK0 SIZERAMBLOCKS -#define SIZERAMBLOCK1 SIZERAMBLOCKS -#define SIZERAMBLOCK2 SIZERAMBLOCK[2] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ -#define SIZERAMBLOCK3 SIZERAMBLOCK[3] /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */ -/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */ -#define DEVICEID0 DEVICEID[0] -#define DEVICEID1 DEVICEID[1] -/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */ -#define ER0 ER[0] -#define ER1 ER[1] -#define ER2 ER[2] -#define ER3 ER[3] -/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */ -#define IR0 IR[0] -#define IR1 IR[1] -#define IR2 IR[2] -#define IR3 IR[3] -/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */ -#define DEVICEADDR0 DEVICEADDR[0] -#define DEVICEADDR1 DEVICEADDR[1] - - -/* PPI */ -/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */ -#define TASKS_CHG0EN TASKS_CHG[0].EN -#define TASKS_CHG0DIS TASKS_CHG[0].DIS -#define TASKS_CHG1EN TASKS_CHG[1].EN -#define TASKS_CHG1DIS TASKS_CHG[1].DIS -#define TASKS_CHG2EN TASKS_CHG[2].EN -#define TASKS_CHG2DIS TASKS_CHG[2].DIS -#define TASKS_CHG3EN TASKS_CHG[3].EN -#define TASKS_CHG3DIS TASKS_CHG[3].DIS -/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */ -#define CH0_EEP CH[0].EEP -#define CH0_TEP CH[0].TEP -#define CH1_EEP CH[1].EEP -#define CH1_TEP CH[1].TEP -#define CH2_EEP CH[2].EEP -#define CH2_TEP CH[2].TEP -#define CH3_EEP CH[3].EEP -#define CH3_TEP CH[3].TEP -#define CH4_EEP CH[4].EEP -#define CH4_TEP CH[4].TEP -#define CH5_EEP CH[5].EEP -#define CH5_TEP CH[5].TEP -#define CH6_EEP CH[6].EEP -#define CH6_TEP CH[6].TEP -#define CH7_EEP CH[7].EEP -#define CH7_TEP CH[7].TEP -#define CH8_EEP CH[8].EEP -#define CH8_TEP CH[8].TEP -#define CH9_EEP CH[9].EEP -#define CH9_TEP CH[9].TEP -#define CH10_EEP CH[10].EEP -#define CH10_TEP CH[10].TEP -#define CH11_EEP CH[11].EEP -#define CH11_TEP CH[11].TEP -#define CH12_EEP CH[12].EEP -#define CH12_TEP CH[12].TEP -#define CH13_EEP CH[13].EEP -#define CH13_TEP CH[13].TEP -#define CH14_EEP CH[14].EEP -#define CH14_TEP CH[14].TEP -#define CH15_EEP CH[15].EEP -#define CH15_TEP CH[15].TEP -/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */ -#define CHG0 CHG[0] -#define CHG1 CHG[1] -#define CHG2 CHG[2] -#define CHG3 CHG[3] -/* All bitfield macros for the CHGx registers therefore changed name. */ -#define PPI_CHG0_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG0_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG0_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG0_CH15_Included PPI_CHG_CH15_Included -#define PPI_CHG0_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG0_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG0_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG0_CH14_Included PPI_CHG_CH14_Included -#define PPI_CHG0_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG0_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG0_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG0_CH13_Included PPI_CHG_CH13_Included -#define PPI_CHG0_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG0_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG0_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG0_CH12_Included PPI_CHG_CH12_Included -#define PPI_CHG0_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG0_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG0_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG0_CH11_Included PPI_CHG_CH11_Included -#define PPI_CHG0_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG0_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG0_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG0_CH10_Included PPI_CHG_CH10_Included -#define PPI_CHG0_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG0_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG0_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG0_CH9_Included PPI_CHG_CH9_Included -#define PPI_CHG0_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG0_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG0_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG0_CH8_Included PPI_CHG_CH8_Included -#define PPI_CHG0_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG0_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG0_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG0_CH7_Included PPI_CHG_CH7_Included -#define PPI_CHG0_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG0_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG0_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG0_CH6_Included PPI_CHG_CH6_Included -#define PPI_CHG0_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG0_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG0_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG0_CH5_Included PPI_CHG_CH5_Included -#define PPI_CHG0_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG0_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG0_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG0_CH4_Included PPI_CHG_CH4_Included -#define PPI_CHG0_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG0_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG0_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG0_CH3_Included PPI_CHG_CH3_Included -#define PPI_CHG0_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG0_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG0_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG0_CH2_Included PPI_CHG_CH2_Included -#define PPI_CHG0_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG0_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG0_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG0_CH1_Included PPI_CHG_CH1_Included -#define PPI_CHG0_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG0_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG0_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG0_CH0_Included PPI_CHG_CH0_Included -#define PPI_CHG1_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG1_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG1_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG1_CH15_Included PPI_CHG_CH15_Included -#define PPI_CHG1_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG1_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG1_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG1_CH14_Included PPI_CHG_CH14_Included -#define PPI_CHG1_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG1_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG1_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG1_CH13_Included PPI_CHG_CH13_Included -#define PPI_CHG1_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG1_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG1_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG1_CH12_Included PPI_CHG_CH12_Included -#define PPI_CHG1_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG1_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG1_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG1_CH11_Included PPI_CHG_CH11_Included -#define PPI_CHG1_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG1_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG1_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG1_CH10_Included PPI_CHG_CH10_Included -#define PPI_CHG1_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG1_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG1_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG1_CH9_Included PPI_CHG_CH9_Included -#define PPI_CHG1_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG1_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG1_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG1_CH8_Included PPI_CHG_CH8_Included -#define PPI_CHG1_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG1_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG1_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG1_CH7_Included PPI_CHG_CH7_Included -#define PPI_CHG1_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG1_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG1_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG1_CH6_Included PPI_CHG_CH6_Included -#define PPI_CHG1_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG1_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG1_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG1_CH5_Included PPI_CHG_CH5_Included -#define PPI_CHG1_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG1_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG1_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG1_CH4_Included PPI_CHG_CH4_Included -#define PPI_CHG1_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG1_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG1_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG1_CH3_Included PPI_CHG_CH3_Included -#define PPI_CHG1_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG1_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG1_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG1_CH2_Included PPI_CHG_CH2_Included -#define PPI_CHG1_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG1_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG1_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG1_CH1_Included PPI_CHG_CH1_Included -#define PPI_CHG1_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG1_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG1_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG1_CH0_Included PPI_CHG_CH0_Included -#define PPI_CHG2_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG2_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG2_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG2_CH15_Included PPI_CHG_CH15_Included -#define PPI_CHG2_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG2_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG2_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG2_CH14_Included PPI_CHG_CH14_Included -#define PPI_CHG2_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG2_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG2_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG2_CH13_Included PPI_CHG_CH13_Included -#define PPI_CHG2_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG2_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG2_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG2_CH12_Included PPI_CHG_CH12_Included -#define PPI_CHG2_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG2_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG2_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG2_CH11_Included PPI_CHG_CH11_Included -#define PPI_CHG2_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG2_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG2_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG2_CH10_Included PPI_CHG_CH10_Included -#define PPI_CHG2_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG2_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG2_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG2_CH9_Included PPI_CHG_CH9_Included -#define PPI_CHG2_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG2_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG2_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG2_CH8_Included PPI_CHG_CH8_Included -#define PPI_CHG2_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG2_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG2_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG2_CH7_Included PPI_CHG_CH7_Included -#define PPI_CHG2_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG2_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG2_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG2_CH6_Included PPI_CHG_CH6_Included -#define PPI_CHG2_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG2_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG2_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG2_CH5_Included PPI_CHG_CH5_Included -#define PPI_CHG2_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG2_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG2_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG2_CH4_Included PPI_CHG_CH4_Included -#define PPI_CHG2_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG2_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG2_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG2_CH3_Included PPI_CHG_CH3_Included -#define PPI_CHG2_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG2_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG2_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG2_CH2_Included PPI_CHG_CH2_Included -#define PPI_CHG2_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG2_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG2_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG2_CH1_Included PPI_CHG_CH1_Included -#define PPI_CHG2_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG2_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG2_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG2_CH0_Included PPI_CHG_CH0_Included -#define PPI_CHG3_CH15_Pos PPI_CHG_CH15_Pos -#define PPI_CHG3_CH15_Msk PPI_CHG_CH15_Msk -#define PPI_CHG3_CH15_Excluded PPI_CHG_CH15_Excluded -#define PPI_CHG3_CH15_Included PPI_CHG_CH15_Included -#define PPI_CHG3_CH14_Pos PPI_CHG_CH14_Pos -#define PPI_CHG3_CH14_Msk PPI_CHG_CH14_Msk -#define PPI_CHG3_CH14_Excluded PPI_CHG_CH14_Excluded -#define PPI_CHG3_CH14_Included PPI_CHG_CH14_Included -#define PPI_CHG3_CH13_Pos PPI_CHG_CH13_Pos -#define PPI_CHG3_CH13_Msk PPI_CHG_CH13_Msk -#define PPI_CHG3_CH13_Excluded PPI_CHG_CH13_Excluded -#define PPI_CHG3_CH13_Included PPI_CHG_CH13_Included -#define PPI_CHG3_CH12_Pos PPI_CHG_CH12_Pos -#define PPI_CHG3_CH12_Msk PPI_CHG_CH12_Msk -#define PPI_CHG3_CH12_Excluded PPI_CHG_CH12_Excluded -#define PPI_CHG3_CH12_Included PPI_CHG_CH12_Included -#define PPI_CHG3_CH11_Pos PPI_CHG_CH11_Pos -#define PPI_CHG3_CH11_Msk PPI_CHG_CH11_Msk -#define PPI_CHG3_CH11_Excluded PPI_CHG_CH11_Excluded -#define PPI_CHG3_CH11_Included PPI_CHG_CH11_Included -#define PPI_CHG3_CH10_Pos PPI_CHG_CH10_Pos -#define PPI_CHG3_CH10_Msk PPI_CHG_CH10_Msk -#define PPI_CHG3_CH10_Excluded PPI_CHG_CH10_Excluded -#define PPI_CHG3_CH10_Included PPI_CHG_CH10_Included -#define PPI_CHG3_CH9_Pos PPI_CHG_CH9_Pos -#define PPI_CHG3_CH9_Msk PPI_CHG_CH9_Msk -#define PPI_CHG3_CH9_Excluded PPI_CHG_CH9_Excluded -#define PPI_CHG3_CH9_Included PPI_CHG_CH9_Included -#define PPI_CHG3_CH8_Pos PPI_CHG_CH8_Pos -#define PPI_CHG3_CH8_Msk PPI_CHG_CH8_Msk -#define PPI_CHG3_CH8_Excluded PPI_CHG_CH8_Excluded -#define PPI_CHG3_CH8_Included PPI_CHG_CH8_Included -#define PPI_CHG3_CH7_Pos PPI_CHG_CH7_Pos -#define PPI_CHG3_CH7_Msk PPI_CHG_CH7_Msk -#define PPI_CHG3_CH7_Excluded PPI_CHG_CH7_Excluded -#define PPI_CHG3_CH7_Included PPI_CHG_CH7_Included -#define PPI_CHG3_CH6_Pos PPI_CHG_CH6_Pos -#define PPI_CHG3_CH6_Msk PPI_CHG_CH6_Msk -#define PPI_CHG3_CH6_Excluded PPI_CHG_CH6_Excluded -#define PPI_CHG3_CH6_Included PPI_CHG_CH6_Included -#define PPI_CHG3_CH5_Pos PPI_CHG_CH5_Pos -#define PPI_CHG3_CH5_Msk PPI_CHG_CH5_Msk -#define PPI_CHG3_CH5_Excluded PPI_CHG_CH5_Excluded -#define PPI_CHG3_CH5_Included PPI_CHG_CH5_Included -#define PPI_CHG3_CH4_Pos PPI_CHG_CH4_Pos -#define PPI_CHG3_CH4_Msk PPI_CHG_CH4_Msk -#define PPI_CHG3_CH4_Excluded PPI_CHG_CH4_Excluded -#define PPI_CHG3_CH4_Included PPI_CHG_CH4_Included -#define PPI_CHG3_CH3_Pos PPI_CHG_CH3_Pos -#define PPI_CHG3_CH3_Msk PPI_CHG_CH3_Msk -#define PPI_CHG3_CH3_Excluded PPI_CHG_CH3_Excluded -#define PPI_CHG3_CH3_Included PPI_CHG_CH3_Included -#define PPI_CHG3_CH2_Pos PPI_CHG_CH2_Pos -#define PPI_CHG3_CH2_Msk PPI_CHG_CH2_Msk -#define PPI_CHG3_CH2_Excluded PPI_CHG_CH2_Excluded -#define PPI_CHG3_CH2_Included PPI_CHG_CH2_Included -#define PPI_CHG3_CH1_Pos PPI_CHG_CH1_Pos -#define PPI_CHG3_CH1_Msk PPI_CHG_CH1_Msk -#define PPI_CHG3_CH1_Excluded PPI_CHG_CH1_Excluded -#define PPI_CHG3_CH1_Included PPI_CHG_CH1_Included -#define PPI_CHG3_CH0_Pos PPI_CHG_CH0_Pos -#define PPI_CHG3_CH0_Msk PPI_CHG_CH0_Msk -#define PPI_CHG3_CH0_Excluded PPI_CHG_CH0_Excluded -#define PPI_CHG3_CH0_Included PPI_CHG_CH0_Included - - - -/*lint --flb "Leave library region" */ - -#endif /* NRF51_DEPRECATED_H */ - diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf_delay.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf_delay.h deleted file mode 100644 index be4b9f4e15..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/nrf_delay.h +++ /dev/null @@ -1,74 +0,0 @@ -#ifndef _NRF_DELAY_H -#define _NRF_DELAY_H - -// #include "nrf.h" - -/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */ -#if defined ( __CC_ARM ) -static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us) -{ -loop - SUBS R0, R0, #1 - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - NOP - BNE loop - BX LR -} -#elif defined ( __ICCARM__ ) -static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) -{ -__ASM ( -"loop:\n\t" - " SUBS R0, R0, #1\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " NOP\n\t" - " BNE loop\n\t"); -} -#elif defined ( __GNUC__ ) -static __INLINE void nrf_delay_us(uint32_t volatile number_of_us) -{ - do - { - __ASM volatile ( - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - "NOP\n\t" - ); - } while (--number_of_us); -} -#endif - -void nrf_delay_ms(uint32_t volatile number_of_ms); - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.c deleted file mode 100644 index 46119472d2..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.c +++ /dev/null @@ -1,187 +0,0 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#include -#include -#include "nrf.h" -#include "nrf_delay.h" -#include "system_nrf51.h" - -/*lint ++flb "Enter library region" */ - -#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ - -static bool is_manual_peripheral_setup_needed(void); -static bool is_disabled_in_debug_needed(void); -static void init_clock(void); - - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK; -} - -void SystemInit(void) -{ -#if defined(TARGET_NRF_32MHZ_XTAL) - /* For 32MHz HFCLK XTAL such as Taiyo Yuden - Physically, tiny footprint XTAL oscillate higher freq. To make BLE modules smaller, some modules - are using 32MHz XTAL. - This code wriging the value 0xFFFFFF00 to the UICR (User Information Configuration Register) - at address 0x10001008, to make nRF51 works with 32MHz system clock. This register will be overwritten - by SoftDevice to 0xFFFFFFFF, the default value. Each hex files built with mbed classic online compiler - contain SoftDevice, so that, this code run once just after the hex file will be flashed onto nRF51. - After changing the value, nRF51 need to reboot. */ - if (*(uint32_t *)0x10001008 == 0xFFFFFFFF) - { - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - *(uint32_t *)0x10001008 = 0xFFFFFF00; - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - while (true){} - } -#endif - - /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. - It can also be done in the application main() function. */ - - /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required - to enable the use of peripherals" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. The side effect of executing these instructions in the devices - that do not need it is that the new peripherals in the second generation devices (LPCOMP for - example) will not be available. */ - if (is_manual_peripheral_setup_needed()) - { - *(uint32_t volatile *)0x40000504 = 0xC007FFDF; - *(uint32_t volatile *)0x40006C18 = 0x00008000; - } - - /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - register is incorrect" found at Product Anomaly document four your device found at - https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ - if (is_disabled_in_debug_needed()) - { - NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; - } - - // Start the external 32khz crystal oscillator. - init_clock(); -} - -void init_clock(void) -{ - /* For compatibility purpose, the default behaviour is to first attempt to initialise an - external clock, and after a timeout, use the internal RC one. To avoid this wait, boards that - don't have an external oscillator can set TARGET_NRF_LFCLK_RC directly. */ - uint32_t i = 0; - const uint32_t polling_period = 200; - const uint32_t timeout = 1000000; - -#if defined(TARGET_NRF_LFCLK_RC) - NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); -#else - NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_Xtal << CLOCK_LFCLKSRC_SRC_Pos); -#endif - NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; - NRF_CLOCK->TASKS_LFCLKSTART = 1; - - /* Wait for the external oscillator to start up. - nRF51822 product specification (8.1.5) gives a typical value of 300ms for external clock - startup duration, and a maximum value of 1s. When using the internal RC source, typical delay - will be 390µs, so we use a polling period of 200µs. - - We can't use us_ticker at this point, so we have to rely on a less precise method for - measuring our timeout. Because of this, the actual timeout will be slightly longer than 1 - second, which isn't an issue at all, since this fallback should only be used as a safety net. - */ - for (i = 0; i < (timeout / polling_period); i++) { - if (NRF_CLOCK->EVENTS_LFCLKSTARTED != 0) - return; - nrf_delay_us(polling_period); - } - - /* Fallback to internal clock. Belt and braces, since the internal clock is used by default - whilst no external source is running. This is not only a sanity check, but it also allows - code down the road (e.g. ble initialisation) to directly know which clock is used. */ - NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_RC << CLOCK_LFCLKSRC_SRC_Pos); - NRF_CLOCK->TASKS_LFCLKSTART = 1; - while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { - // Do nothing. - } -} - -static bool is_manual_peripheral_setup_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} - -static bool is_disabled_in_debug_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} - -/*lint --flb "Leave library region" */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.h deleted file mode 100644 index ae613609dd..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/device/system_nrf51.h +++ /dev/null @@ -1,68 +0,0 @@ -/* Copyright (c) 2013, Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * * Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. - * - * * Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * - * * Neither the name of Nordic Semiconductor ASA nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ -#ifndef SYSTEM_NRF51_H -#define SYSTEM_NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF51_H */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_api.c deleted file mode 100644 index eb077c9f10..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_api.c +++ /dev/null @@ -1,58 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "pinmap.h" - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - - obj->mask = (1ul << pin); - - obj->reg_set = &NRF_GPIO->OUTSET; - obj->reg_clr = &NRF_GPIO->OUTCLR; - obj->reg_in = &NRF_GPIO->IN; - obj->reg_dir = &NRF_GPIO->DIR; -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - pin_mode(obj->pin, mode); -} - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - switch (direction) { - case PIN_INPUT: - NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - break; - case PIN_OUTPUT: - NRF_GPIO->PIN_CNF[obj->pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - break; - } -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c deleted file mode 100644 index 9d2fcad2c4..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_irq_api.c +++ /dev/null @@ -1,127 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include -#include "cmsis.h" - -#include "gpio_irq_api.h" -#include "mbed_error.h" - -#define CHANNEL_NUM 31 - -static uint32_t channel_ids[CHANNEL_NUM] = {0}; //each pin will be given an id, if id is 0 the pin can be ignored. -static uint8_t channel_enabled[CHANNEL_NUM] = {0}; -static uint32_t portRISE = 0; -static uint32_t portFALL = 0; -static gpio_irq_handler irq_handler; - -#ifdef __cplusplus -extern "C" { -#endif -void GPIOTE_IRQHandler(void) -{ - volatile uint32_t newVal = NRF_GPIO->IN; - - if ((NRF_GPIOTE->EVENTS_PORT != 0) && ((NRF_GPIOTE->INTENSET & GPIOTE_INTENSET_PORT_Msk) != 0)) { - NRF_GPIOTE->EVENTS_PORT = 0; - - for (uint8_t i = 0; i<31; i++) { - if (channel_ids[i]>0) { - if (channel_enabled[i]) { - if( ((newVal>>i)&1) && ( ( (NRF_GPIO->PIN_CNF[i] >>GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) != GPIO_PIN_CNF_SENSE_Low) && ( (portRISE>>i)&1) ){ - irq_handler(channel_ids[i], IRQ_RISE); - } else if ((((newVal >> i) & 1) == 0) && - (((NRF_GPIO->PIN_CNF[i] >> GPIO_PIN_CNF_SENSE_Pos) & GPIO_PIN_CNF_SENSE_Low) == GPIO_PIN_CNF_SENSE_Low) && - ((portFALL >> i) & 1)) { - irq_handler(channel_ids[i], IRQ_FALL); - } - } - - if (NRF_GPIO->PIN_CNF[i] & GPIO_PIN_CNF_SENSE_Msk) { - NRF_GPIO->PIN_CNF[i] &= ~(GPIO_PIN_CNF_SENSE_Msk); - - if (newVal >> i & 1) { - NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); - } else { - NRF_GPIO->PIN_CNF[i] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); - } - } - } - } - } -} - -#ifdef __cplusplus -} -#endif - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - if (pin == NC) { - return -1; - } - - irq_handler = handler; - obj->ch = pin; - NRF_GPIOTE->EVENTS_PORT = 0; - channel_ids[pin] = id; - channel_enabled[pin] = 1; - NRF_GPIOTE->INTENSET = GPIOTE_INTENSET_PORT_Set << GPIOTE_INTENSET_PORT_Pos; - - NVIC_SetPriority(GPIOTE_IRQn, 3); - NVIC_EnableIRQ (GPIOTE_IRQn); - return 0; -} - -void gpio_irq_free(gpio_irq_t *obj) -{ - channel_ids[obj->ch] = 0; -} - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - NRF_GPIO->PIN_CNF[obj->ch] &= ~(GPIO_PIN_CNF_SENSE_Msk); - if (enable) { - if (event == IRQ_RISE) { - portRISE |= (1 << obj->ch); - } else if (event == IRQ_FALL) { - portFALL |= (1 << obj->ch); - } - } else { - if (event == IRQ_RISE) { - portRISE &= ~(1 << obj->ch); - } else if (event == IRQ_FALL) { - portFALL &= ~(1 << obj->ch); - } - } - - if (((portRISE >> obj->ch) & 1) || ((portFALL >> obj->ch) & 1)) { - if ((NRF_GPIO->IN >> obj->ch) & 1) { - NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_Low << GPIO_PIN_CNF_SENSE_Pos); // | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos); - } else { - NRF_GPIO->PIN_CNF[obj->ch] |= (GPIO_PIN_CNF_SENSE_High << GPIO_PIN_CNF_SENSE_Pos); //| (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos); - } - } -} - -void gpio_irq_enable(gpio_irq_t *obj) -{ - channel_enabled[obj->ch] = 1; -} - -void gpio_irq_disable(gpio_irq_t *obj) -{ - channel_enabled[obj->ch] = 0; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h deleted file mode 100644 index fe6d6c1e05..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/gpio_object.h +++ /dev/null @@ -1,56 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_GPIO_OBJECT_H -#define MBED_GPIO_OBJECT_H - -#include "mbed_assert.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef struct { - PinName pin; - uint32_t mask; - - __IO uint32_t *reg_dir; - __IO uint32_t *reg_set; - __IO uint32_t *reg_clr; - __I uint32_t *reg_in; -} gpio_t; - -static inline void gpio_write(gpio_t *obj, int value) { - MBED_ASSERT(obj->pin != (PinName)NC); - if (value) - *obj->reg_set = obj->mask; - else - *obj->reg_clr = obj->mask; -} - -static inline int gpio_read(gpio_t *obj) { - MBED_ASSERT(obj->pin != (PinName)NC); - return ((*obj->reg_in & obj->mask) ? 1 : 0); -} - -static inline int gpio_is_connected(const gpio_t *obj) { - return obj->pin != (PinName)NC; -} - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c deleted file mode 100644 index c45d5d4170..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/i2c_api.c +++ /dev/null @@ -1,368 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "i2c_api.h" - -#if DEVICE_I2C - -#include "cmsis.h" -#include "pinmap.h" -#include "twi_master.h" -#include "mbed_error.h" - -// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address. -// They can't be used at the same time. So we use two global variable to track the usage. -// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference -volatile i2c_spi_peripheral_t i2c0_spi0_peripheral = {0, 0, 0, 0}; -volatile i2c_spi_peripheral_t i2c1_spi1_peripheral = {0, 0, 0, 0}; - -// Pinmap used for testing only -static const PinMap PinMap_I2C_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - {P0_18, 0, 0}, - {P0_19, 0, 0}, - {P0_20, 0, 0}, - {P0_21, 0, 0}, - {P0_22, 0, 0}, - {P0_23, 0, 0}, - {P0_24, 0, 0}, - {P0_25, 0, 0}, - {P0_28, 0, 0}, - {P0_29, 0, 0}, - {P0_30, 0, 0}, - {NC, NC, 0} -}; - -void i2c_interface_enable(i2c_t *obj) -{ - obj->i2c->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos); -} - -void twi_master_init(i2c_t *obj, PinName sda, PinName scl, int frequency) -{ - NRF_GPIO->PIN_CNF[scl] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | - (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)); - - NRF_GPIO->PIN_CNF[sda] = ((GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos) | - (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | - (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) | - (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) | - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)); - - obj->i2c->PSELSCL = scl; - obj->i2c->PSELSDA = sda; - // set default frequency at 100k - i2c_frequency(obj, frequency); - i2c_interface_enable(obj); -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - NRF_TWI_Type *i2c = NULL; - - if (i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C && - i2c0_spi0_peripheral.sda_mosi == (uint8_t)sda && - i2c0_spi0_peripheral.scl_miso == (uint8_t)scl) { - // The I2C with the same pins is already initialized - i2c = (NRF_TWI_Type *)I2C_0; - obj->peripheral = 0x1; - } else if (i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_I2C && - i2c1_spi1_peripheral.sda_mosi == (uint8_t)sda && - i2c1_spi1_peripheral.scl_miso == (uint8_t)scl) { - // The I2C with the same pins is already initialized - i2c = (NRF_TWI_Type *)I2C_1; - obj->peripheral = 0x2; - } else if (i2c0_spi0_peripheral.usage == 0) { - i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C; - i2c0_spi0_peripheral.sda_mosi = (uint8_t)sda; - i2c0_spi0_peripheral.scl_miso = (uint8_t)scl; - - i2c = (NRF_TWI_Type *)I2C_0; - obj->peripheral = 0x1; - } else if (i2c1_spi1_peripheral.usage == 0) { - i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_I2C; - i2c1_spi1_peripheral.sda_mosi = (uint8_t)sda; - i2c1_spi1_peripheral.scl_miso = (uint8_t)scl; - - i2c = (NRF_TWI_Type *)I2C_1; - obj->peripheral = 0x2; - } else { - // No available peripheral - error("No available I2C"); - } - - twi_master_init_and_clear(i2c); - - obj->i2c = i2c; - obj->scl = scl; - obj->sda = sda; - obj->i2c->EVENTS_ERROR = 0; - obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; - obj->i2c->POWER = 0; - - for (int i = 0; i<100; i++) { - } - - obj->i2c->POWER = 1; - twi_master_init(obj, sda, scl, 100000); -} - -void i2c_reset(i2c_t *obj) -{ - obj->i2c->EVENTS_ERROR = 0; - obj->i2c->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; - obj->i2c->POWER = 0; - for (int i = 0; i<100; i++) { - } - - obj->i2c->POWER = 1; - twi_master_init(obj, obj->sda, obj->scl, obj->freq); -} - -int i2c_start(i2c_t *obj) -{ - int status = 0; - i2c_reset(obj); - obj->address_set = 0; - return status; -} - -int i2c_stop(i2c_t *obj) -{ - int timeOut = 100000; - obj->i2c->EVENTS_STOPPED = 0; - // write the stop bit - obj->i2c->TASKS_STOP = 1; - while (!obj->i2c->EVENTS_STOPPED) { - timeOut--; - if (timeOut<0) { - return 1; - } - } - obj->address_set = 0; - i2c_reset(obj); - return 0; -} - -int i2c_do_write(i2c_t *obj, int value) -{ - int timeOut = 100000; - obj->i2c->TXD = value; - while (!obj->i2c->EVENTS_TXDSENT) { - timeOut--; - if (timeOut<0) { - return 1; - } - } - obj->i2c->EVENTS_TXDSENT = 0; - return 0; -} - -int i2c_do_read(i2c_t *obj, char *data, int last) -{ - int timeOut = 100000; - - if (last) { - // To trigger stop task when a byte is received, - // must be set before resume task. - obj->i2c->SHORTS = 2; - } - - obj->i2c->TASKS_RESUME = 1; - - while (!obj->i2c->EVENTS_RXDREADY) { - timeOut--; - if (timeOut<0) { - return 1; - } - } - obj->i2c->EVENTS_RXDREADY = 0; - *data = obj->i2c->RXD; - - return 0; -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - if (hz<250000) { - obj->freq = 100000; - obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos); - } else if (hz<400000) { - obj->freq = 250000; - obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K250 << TWI_FREQUENCY_FREQUENCY_Pos); - } else { - obj->freq = 400000; - obj->i2c->FREQUENCY = (TWI_FREQUENCY_FREQUENCY_K400 << TWI_FREQUENCY_FREQUENCY_Pos); - } -} - -int checkError(i2c_t *obj) -{ - if (obj->i2c->EVENTS_ERROR == 1) { - if (obj->i2c->ERRORSRC & TWI_ERRORSRC_ANACK_Msk) { - obj->i2c->EVENTS_ERROR = 0; - obj->i2c->TASKS_STOP = 1; - return I2C_ERROR_BUS_BUSY; - } - - obj->i2c->EVENTS_ERROR = 0; - obj->i2c->TASKS_STOP = 1; - return I2C_ERROR_NO_SLAVE; - } - return 0; -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - int status, count, errorResult; - obj->i2c->ADDRESS = (address >> 1); - obj->i2c->SHORTS = 1; // to trigger suspend task when a byte is received - obj->i2c->EVENTS_RXDREADY = 0; - obj->i2c->TASKS_STARTRX = 1; - - // Read in all except last byte - for (count = 0; count < (length - 1); count++) { - status = i2c_do_read(obj, &data[count], 0); - if (status) { - errorResult = checkError(obj); - i2c_reset(obj); - if (errorResult<0) { - return errorResult; - } - return count; - } - } - - // read in last byte - status = i2c_do_read(obj, &data[length - 1], 1); - if (status) { - i2c_reset(obj); - return length - 1; - } - // If not repeated start, send stop. - if (stop) { - while (!obj->i2c->EVENTS_STOPPED) { - } - obj->i2c->EVENTS_STOPPED = 0; - } - return length; -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - int status, errorResult; - obj->i2c->ADDRESS = (address >> 1); - obj->i2c->SHORTS = 0; - obj->i2c->TASKS_STARTTX = 1; - - for (int i = 0; iaddress_set) { - obj->address_set = 1; - obj->i2c->ADDRESS = (data >> 1); - - if (data & 1) { - obj->i2c->EVENTS_RXDREADY = 0; - obj->i2c->SHORTS = 1; - obj->i2c->TASKS_STARTRX = 1; - } else { - obj->i2c->SHORTS = 0; - obj->i2c->TASKS_STARTTX = 1; - } - } else { - status = i2c_do_write(obj, data); - if (status) { - i2c_reset(obj); - } - } - return (1 - status); -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_testing; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_testing; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_testing; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_testing; -} - -#endif // #if DEVICE_I2C diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h deleted file mode 100755 index a87e1d7687..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/objects.h +++ /dev/null @@ -1,86 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define I2C_SPI_PERIPHERAL_FOR_I2C 1 -#define I2C_SPI_PERIPHERAL_FOR_SPI 2 - -typedef struct { - uint8_t usage; // I2C: 1, SPI: 2 - uint8_t sda_mosi; - uint8_t scl_miso; - uint8_t sclk; -} i2c_spi_peripheral_t; - -struct serial_s { - NRF_UART_Type *uart; - int index; -}; - -struct spi_s { - NRF_SPI_Type *spi; - NRF_SPIS_Type *spis; - uint8_t peripheral; -}; - -struct port_s { - __IO uint32_t *reg_cnf; - __IO uint32_t *reg_out; - __I uint32_t *reg_in; - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - PWMName pwm; - PinName pin; -}; - -struct i2c_s { - NRF_TWI_Type *i2c; - PinName sda; - PinName scl; - int freq; - uint8_t address_set; - uint8_t peripheral; -}; - -struct analogin_s { - ADCName adc; - uint8_t adc_pin; -}; - -struct gpio_irq_s { - uint32_t ch; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pinmap.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pinmap.c deleted file mode 100644 index 44ca32c039..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pinmap.c +++ /dev/null @@ -1,32 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pinmap.h" -#include "mbed_error.h" - -void pin_function(PinName pin, int function) -{ -} - -void pin_mode(PinName pin, PinMode mode) -{ - MBED_ASSERT(pin != (PinName)NC); - - uint32_t pin_number = (uint32_t)pin; - - NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk; - NRF_GPIO->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos); -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/port_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/port_api.c deleted file mode 100644 index 4168a7845c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/port_api.c +++ /dev/null @@ -1,84 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "port_api.h" -#include "pinmap.h" -#include "gpio_api.h" - -PinName port_pin(PortName port, int pin_n) -{ - return (PinName)(pin_n); -} - -void port_init(port_t *obj, PortName port, int mask, PinDirection dir) -{ - obj->port = port; - obj->mask = mask; - - obj->reg_out = &NRF_GPIO->OUT; - obj->reg_in = &NRF_GPIO->IN; - obj->reg_cnf = NRF_GPIO->PIN_CNF; - - port_dir(obj, dir); -} - -void port_mode(port_t *obj, PinMode mode) -{ - uint32_t i; - // The mode is set per pin: reuse pinmap logic - for (i = 0; i<31; i++) { - if (obj->mask & (1 << i)) { - pin_mode(port_pin(obj->port, i), mode); - } - } -} - -void port_dir(port_t *obj, PinDirection dir) -{ - int i; - switch (dir) { - case PIN_INPUT: - for (i = 0; i<31; i++) { - if (obj->mask & (1 << i)) { - obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - } - } - break; - case PIN_OUTPUT: - for (i = 0; i<31; i++) { - if (obj->mask & (1 << i)) { - obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - } - } - break; - } -} - -void port_write(port_t *obj, int value) -{ - *obj->reg_out = value; -} - -int port_read(port_t *obj) -{ - return (*obj->reg_in); -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c deleted file mode 100644 index f7b2be75e3..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/pwmout_api.c +++ /dev/null @@ -1,385 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define NO_PWMS 3 -#define TIMER_PRECISION 4 //4us ticks -#define TIMER_PRESCALER 6 //4us ticks = 16Mhz/(2**6) -static const PinMap PinMap_PWM[] = { - {P0_0, PWM_1, 1}, - {P0_1, PWM_1, 1}, - {P0_2, PWM_1, 1}, - {P0_3, PWM_1, 1}, - {P0_4, PWM_1, 1}, - {P0_5, PWM_1, 1}, - {P0_6, PWM_1, 1}, - {P0_7, PWM_1, 1}, - {P0_8, PWM_1, 1}, - {P0_9, PWM_1, 1}, - {P0_10, PWM_1, 1}, - {P0_11, PWM_1, 1}, - {P0_12, PWM_1, 1}, - {P0_13, PWM_1, 1}, - {P0_14, PWM_1, 1}, - {P0_15, PWM_1, 1}, - {P0_16, PWM_1, 1}, - {P0_17, PWM_1, 1}, - {P0_18, PWM_1, 1}, - {P0_19, PWM_1, 1}, - {P0_20, PWM_1, 1}, - {P0_21, PWM_1, 1}, - {P0_22, PWM_1, 1}, - {P0_23, PWM_1, 1}, - {P0_24, PWM_1, 1}, - {P0_25, PWM_1, 1}, - {P0_28, PWM_1, 1}, - {P0_29, PWM_1, 1}, - {P0_30, PWM_1, 1}, - {NC, NC, 0} -}; - -static NRF_TIMER_Type *Timers[1] = { - NRF_TIMER2 -}; - -uint16_t PERIOD = 20000 / TIMER_PRECISION; //20ms -uint8_t PWM_taken[NO_PWMS] = {0, 0, 0}; -uint16_t PULSE_WIDTH[NO_PWMS] = {1, 1, 1}; //set to 1 instead of 0 -uint16_t ACTUAL_PULSE[NO_PWMS] = {0, 0, 0}; - - -/** @brief Function for handling timer 2 peripheral interrupts. - */ -#ifdef __cplusplus -extern "C" { -#endif -void TIMER2_IRQHandler(void) -{ - NRF_TIMER2->EVENTS_COMPARE[3] = 0; - NRF_TIMER2->CC[3] = PERIOD; - - if (PWM_taken[0]) { - NRF_TIMER2->CC[0] = PULSE_WIDTH[0]; - } - if (PWM_taken[1]) { - NRF_TIMER2->CC[1] = PULSE_WIDTH[1]; - } - if (PWM_taken[2]) { - NRF_TIMER2->CC[2] = PULSE_WIDTH[2]; - } - - NRF_TIMER2->TASKS_START = 1; -} - -#ifdef __cplusplus -} -#endif -/** @brief Function for initializing the Timer peripherals. - */ -void timer_init(uint8_t pwmChoice) -{ - NRF_TIMER_Type *timer = Timers[0]; - timer->TASKS_STOP = 0; - - if (pwmChoice == 0) { - timer->POWER = 0; - timer->POWER = 1; - timer->MODE = TIMER_MODE_MODE_Timer; - timer->BITMODE = TIMER_BITMODE_BITMODE_16Bit << TIMER_BITMODE_BITMODE_Pos; - timer->PRESCALER = TIMER_PRESCALER; - timer->CC[3] = PERIOD; - } - - timer->CC[pwmChoice] = PULSE_WIDTH[pwmChoice]; - - //high priority application interrupt - NVIC_SetPriority(TIMER2_IRQn, 1); - NVIC_EnableIRQ(TIMER2_IRQn); - - timer->TASKS_START = 0x01; -} - -static void timer_free() -{ - NRF_TIMER_Type *timer = Timers[0]; - for(uint8_t i = 1; i < NO_PWMS; i++){ - if(PWM_taken[i]){ - break; - } - if((i == NO_PWMS - 1) && (!PWM_taken[i])) - timer->TASKS_STOP = 0x01; - } -} - - -/** @brief Function for initializing the GPIO Tasks/Events peripheral. - */ -void gpiote_init(PinName pin, uint8_t channel_number) -{ - // Connect GPIO input buffers and configure PWM_OUTPUT_PIN_NUMBER as an output. - NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - NRF_GPIO->OUTCLR = (1UL << pin); - // Configure GPIOTE channel 0 to toggle the PWM pin state - // @note Only one GPIOTE task can be connected to an output pin. - /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */ - NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) | - (31UL << GPIOTE_CONFIG_PSEL_Pos) | - (GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos); - /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */ - __NOP(); - __NOP(); - __NOP(); - /* Launch the task to take the GPIOTE channel output to the desired level */ - NRF_GPIOTE->TASKS_OUT[channel_number] = 1; - - /* Finally configure the channel as the caller expects. If OUTINIT works, the channel is configured properly. - If it does not, the channel output inheritance sets the proper level. */ - NRF_GPIOTE->CONFIG[channel_number] = (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) | - ((uint32_t)pin << GPIOTE_CONFIG_PSEL_Pos) | - ((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos) | - ((uint32_t)GPIOTE_CONFIG_OUTINIT_Low << GPIOTE_CONFIG_OUTINIT_Pos); // ((uint32_t)GPIOTE_CONFIG_OUTINIT_High << - // GPIOTE_CONFIG_OUTINIT_Pos);// - - /* Three NOPs are required to make sure configuration is written before setting tasks or getting events */ - __NOP(); - __NOP(); - __NOP(); -} - -static void gpiote_free(PinName pin,uint8_t channel_number) -{ - NRF_GPIOTE->TASKS_OUT[channel_number] = 0; - NRF_GPIOTE->CONFIG[channel_number] = 0; - NRF_GPIO->PIN_CNF[pin] = (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos); - -} - -/** @brief Function for initializing the Programmable Peripheral Interconnect peripheral. - */ -static void ppi_init(uint8_t pwm) -{ - //using ppi channels 0-7 (only 0-7 are available) - uint8_t channel_number = 2 * pwm; - NRF_TIMER_Type *timer = Timers[0]; - - // Configure PPI channel 0 to toggle ADVERTISING_LED_PIN_NO on every TIMER1 COMPARE[0] match - NRF_PPI->CH[channel_number].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm]; - NRF_PPI->CH[channel_number + 1].TEP = (uint32_t)&NRF_GPIOTE->TASKS_OUT[pwm]; - NRF_PPI->CH[channel_number].EEP = (uint32_t)&timer->EVENTS_COMPARE[pwm]; - NRF_PPI->CH[channel_number + 1].EEP = (uint32_t)&timer->EVENTS_COMPARE[3]; - - // Enable PPI channels. - NRF_PPI->CHEN |= (1 << channel_number) | - (1 << (channel_number + 1)); -} - -static void ppi_free(uint8_t pwm) -{ - //using ppi channels 0-7 (only 0-7 are available) - uint8_t channel_number = 2*pwm; - - // Disable PPI channels. - NRF_PPI->CHEN &= (~(1 << channel_number)) - & (~(1 << (channel_number+1))); -} - -void setModulation(pwmout_t *obj, uint8_t toggle, uint8_t high) -{ - if (high) { - NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos); - if (toggle) { - NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) | - ((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos); - } else { - NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos); - NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_LoToHi << GPIOTE_CONFIG_POLARITY_Pos); - } - } else { - NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_OUTINIT_High << GPIOTE_CONFIG_OUTINIT_Pos); - - if (toggle) { - NRF_GPIOTE->CONFIG[obj->pwm] |= (GPIOTE_CONFIG_MODE_Task << GPIOTE_CONFIG_MODE_Pos) | - ((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos); - } else { - NRF_GPIOTE->CONFIG[obj->pwm] &= ~((uint32_t)GPIOTE_CONFIG_POLARITY_Toggle << GPIOTE_CONFIG_POLARITY_Pos); - NRF_GPIOTE->CONFIG[obj->pwm] |= ((uint32_t)GPIOTE_CONFIG_POLARITY_HiToLo << GPIOTE_CONFIG_POLARITY_Pos); - } - } -} - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - // determine the channel - uint8_t pwmOutSuccess = 0; - PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); - - MBED_ASSERT(pwm != (PWMName)NC); - - if (PWM_taken[(uint8_t)pwm]) { - for (uint8_t i = 1; !pwmOutSuccess && (ipwm = pwm; - obj->pin = pin; - - gpiote_init(pin, (uint8_t)pwm); - ppi_init((uint8_t)pwm); - - if (pwm == 0) { - NRF_POWER->TASKS_CONSTLAT = 1; - } - - timer_init((uint8_t)pwm); - - //default to 20ms: standard for servos, and fine for e.g. brightness control - pwmout_period_ms(obj, 20); - pwmout_write (obj, 0); -} - -void pwmout_free(pwmout_t* obj) { - MBED_ASSERT(obj->pwm != (PWMName)NC); - pwmout_write(obj, 0); - PWM_taken[obj->pwm] = 0; - timer_free(); - ppi_free(obj->pwm); - gpiote_free(obj->pin,obj->pwm); -} - -void pwmout_write(pwmout_t *obj, float value) -{ - uint16_t oldPulseWidth; - - NRF_TIMER2->EVENTS_COMPARE[3] = 0; - NRF_TIMER2->TASKS_STOP = 1; - - if (value < 0.0f) { - value = 0.0; - } else if (value > 1.0f) { - value = 1.0; - } - - oldPulseWidth = ACTUAL_PULSE[obj->pwm]; - ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = value * PERIOD; - - if (PULSE_WIDTH[obj->pwm] == 0) { - PULSE_WIDTH[obj->pwm] = 1; - setModulation(obj, 0, 0); - } else if (PULSE_WIDTH[obj->pwm] == PERIOD) { - PULSE_WIDTH[obj->pwm] = PERIOD - 1; - setModulation(obj, 0, 1); - } else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) { - setModulation(obj, 1, oldPulseWidth == PERIOD); - } - - NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk; - NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk; - NRF_TIMER2->TASKS_START = 1; -} - -float pwmout_read(pwmout_t *obj) -{ - return ((float)PULSE_WIDTH[obj->pwm] / (float)PERIOD); -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -// Set the PWM period, keeping the duty cycle the same. -void pwmout_period_us(pwmout_t *obj, int us) -{ - uint32_t periodInTicks = us / TIMER_PRECISION; - - NRF_TIMER2->EVENTS_COMPARE[3] = 0; - NRF_TIMER2->TASKS_STOP = 1; - - if (periodInTicks>((1 << 16) - 1)) { - PERIOD = (1 << 16) - 1; //131ms - } else if (periodInTicks<5) { - PERIOD = 5; - } else { - PERIOD = periodInTicks; - } - NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk; - NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk; - NRF_TIMER2->TASKS_START = 1; -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - uint32_t pulseInTicks = us / TIMER_PRECISION; - uint16_t oldPulseWidth = ACTUAL_PULSE[obj->pwm]; - - NRF_TIMER2->EVENTS_COMPARE[3] = 0; - NRF_TIMER2->TASKS_STOP = 1; - - ACTUAL_PULSE[obj->pwm] = PULSE_WIDTH[obj->pwm] = pulseInTicks; - - if (PULSE_WIDTH[obj->pwm] == 0) { - PULSE_WIDTH[obj->pwm] = 1; - setModulation(obj, 0, 0); - } else if (PULSE_WIDTH[obj->pwm] == PERIOD) { - PULSE_WIDTH[obj->pwm] = PERIOD - 1; - setModulation(obj, 0, 1); - } else if ((oldPulseWidth == 0) || (oldPulseWidth == PERIOD)) { - setModulation(obj, 1, oldPulseWidth == PERIOD); - } - NRF_TIMER2->INTENSET = TIMER_INTENSET_COMPARE3_Msk; - NRF_TIMER2->SHORTS = TIMER_SHORTS_COMPARE3_CLEAR_Msk | TIMER_SHORTS_COMPARE3_STOP_Msk; - NRF_TIMER2->TASKS_START = 1; -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c deleted file mode 100755 index 5bd743cd6e..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/serial_api.c +++ /dev/null @@ -1,359 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -// math.h required for floating point operations for baud rate calculation -//#include -#include -#include "mbed_assert.h" - -#include "serial_api.h" -#include "cmsis.h" -#include "pinmap.h" - -/****************************************************************************** - * INITIALIZATION - ******************************************************************************/ -#define UART_NUM 1 - -static uint32_t serial_irq_ids[UART_NUM] = {0}; -static uart_irq_handler irq_handler; -static const int acceptedSpeeds[18][2] = { - {1200, UART_BAUDRATE_BAUDRATE_Baud1200}, - {2400, UART_BAUDRATE_BAUDRATE_Baud2400}, - {4800, UART_BAUDRATE_BAUDRATE_Baud4800}, - {9600, UART_BAUDRATE_BAUDRATE_Baud9600}, - {14400, UART_BAUDRATE_BAUDRATE_Baud14400}, - {19200, UART_BAUDRATE_BAUDRATE_Baud19200}, - {28800, UART_BAUDRATE_BAUDRATE_Baud28800}, - {31250, (0x00800000UL) /* 31250 baud */}, - {38400, UART_BAUDRATE_BAUDRATE_Baud38400}, - {56000, (0x00E51000UL) /* 56000 baud */}, - {57600, UART_BAUDRATE_BAUDRATE_Baud57600}, - {76800, UART_BAUDRATE_BAUDRATE_Baud76800}, - {115200, UART_BAUDRATE_BAUDRATE_Baud115200}, - {230400, UART_BAUDRATE_BAUDRATE_Baud230400}, - {250000, UART_BAUDRATE_BAUDRATE_Baud250000}, - {460800, UART_BAUDRATE_BAUDRATE_Baud460800}, - {921600, UART_BAUDRATE_BAUDRATE_Baud921600}, - {1000000, UART_BAUDRATE_BAUDRATE_Baud1M} -}; - -int stdio_uart_inited = 0; -serial_t stdio_uart; - -// Pinmap used for testing only -static const PinMap PinMap_UART_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - {P0_18, 0, 0}, - {P0_19, 0, 0}, - {P0_20, 0, 0}, - {P0_21, 0, 0}, - {P0_22, 0, 0}, - {P0_23, 0, 0}, - {P0_24, 0, 0}, - {P0_25, 0, 0}, - {P0_28, 0, 0}, - {P0_29, 0, 0}, - {P0_30, 0, 0}, - {NC, NC, 0} -}; - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - UARTName uart = UART_0; - obj->uart = (NRF_UART_Type *)uart; - - //pin configurations -- - NRF_GPIO->OUT |= (1 << tx); - NRF_GPIO->OUT |= (1 << RTS_PIN_NUMBER); - NRF_GPIO->DIR |= (1 << tx); //TX_PIN_NUMBER); - NRF_GPIO->DIR |= (1 << RTS_PIN_NUMBER); - - NRF_GPIO->DIR &= ~(1 << rx); //RX_PIN_NUMBER); - NRF_GPIO->DIR &= ~(1 << CTS_PIN_NUMBER); - - - // set default baud rate and format - serial_baud (obj, 9600); - serial_format(obj, 8, ParityNone, 1); - - obj->uart->ENABLE = (UART_ENABLE_ENABLE_Enabled << UART_ENABLE_ENABLE_Pos); - obj->uart->TASKS_STARTTX = 1; - obj->uart->TASKS_STARTRX = 1; - obj->uart->EVENTS_RXDRDY = 0; - // dummy write needed or TXDRDY trails write rather than leads write. - // pins are disconnected so nothing is physically transmitted on the wire - obj->uart->PSELTXD = 0xFFFFFFFF; - obj->uart->EVENTS_TXDRDY = 0; - obj->uart->TXD = 0; - while (obj->uart->EVENTS_TXDRDY != 1); - - obj->index = 0; - - obj->uart->PSELRTS = RTS_PIN_NUMBER; - obj->uart->PSELTXD = tx; //TX_PIN_NUMBER; - obj->uart->PSELCTS = CTS_PIN_NUMBER; - obj->uart->PSELRXD = rx; //RX_PIN_NUMBER; - - // set rx/tx pins in PullUp mode - if (tx != NC) { - pin_mode(tx, PullUp); - } - if (rx != NC) { - pin_mode(rx, PullUp); - } - - if (uart == STDIO_UART) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } -} - -void serial_free(serial_t *obj) -{ - serial_irq_ids[obj->index] = 0; -} - -// serial_baud -// set the baud rate, taking in to account the current SystemFrequency -void serial_baud(serial_t *obj, int baudrate) -{ - if (baudrate<=1200) { - obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200; - return; - } - - for (int i = 1; i<17; i++) { - if (baudrateuart->BAUDRATE = acceptedSpeeds[i - 1][1]; - return; - } - } - obj->uart->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M; -} - -void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) -{ - // 0: 1 stop bits, 1: 2 stop bits - // int parity_enable, parity_select; - switch (parity) { - case ParityNone: - obj->uart->CONFIG = 0; - break; - default: - obj->uart->CONFIG = (UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos); - return; - } - //no Flow Control -} - -//****************************************************************************** -// * INTERRUPT HANDLING -//****************************************************************************** -static inline void uart_irq(uint32_t iir, uint32_t index) -{ - SerialIrq irq_type; - switch (iir) { - case 1: - irq_type = TxIrq; - break; - case 2: - irq_type = RxIrq; - break; - - default: - return; - } - - if (serial_irq_ids[index] != 0) { - irq_handler(serial_irq_ids[index], irq_type); - } -} - -#ifdef __cplusplus -extern "C" { -#endif -void UART0_IRQHandler() -{ - uint32_t irtype = 0; - - if((NRF_UART0->INTENSET & 0x80) && NRF_UART0->EVENTS_TXDRDY) { - irtype = 1; - } else if((NRF_UART0->INTENSET & 0x04) && NRF_UART0->EVENTS_RXDRDY) { - irtype = 2; - } - uart_irq(irtype, 0); -} - -#ifdef __cplusplus -} -#endif -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - irq_handler = handler; - serial_irq_ids[obj->index] = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - IRQn_Type irq_n = (IRQn_Type)0; - - switch ((int)obj->uart) { - case UART_0: - irq_n = UART0_IRQn; - break; - } - - if (enable) { - switch (irq) { - case RxIrq: - obj->uart->INTENSET = (UART_INTENSET_RXDRDY_Msk); - break; - case TxIrq: - obj->uart->INTENSET = (UART_INTENSET_TXDRDY_Msk); - break; - } - NVIC_SetPriority(irq_n, 3); - NVIC_EnableIRQ(irq_n); - } else { // disable - // maseked writes to INTENSET dont disable and masked writes to - // INTENCLR seemed to clear the entire register, not bits. - // Added INTEN to memory map and seems to allow set and clearing of specific bits as desired - int all_disabled = 0; - switch (irq) { - case RxIrq: - obj->uart->INTENCLR = (UART_INTENCLR_RXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_TXDRDY_Msk)) == 0; - break; - case TxIrq: - obj->uart->INTENCLR = (UART_INTENCLR_TXDRDY_Msk); - all_disabled = (obj->uart->INTENCLR & (UART_INTENCLR_RXDRDY_Msk)) == 0; - break; - } - - if (all_disabled) { - NVIC_DisableIRQ(irq_n); - } - } -} - -//****************************************************************************** -//* READ/WRITE -//****************************************************************************** -int serial_getc(serial_t *obj) -{ - while (!serial_readable(obj)) { - } - - obj->uart->EVENTS_RXDRDY = 0; - - return (uint8_t)obj->uart->RXD; -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) { - } - - obj->uart->EVENTS_TXDRDY = 0; - obj->uart->TXD = (uint8_t)c; -} - -int serial_readable(serial_t *obj) -{ - return (obj->uart->EVENTS_RXDRDY == 1); -} - -int serial_writable(serial_t *obj) -{ - return (obj->uart->EVENTS_TXDRDY == 1); -} - -void serial_break_set(serial_t *obj) -{ - obj->uart->TASKS_SUSPEND = 1; -} - -void serial_break_clear(serial_t *obj) -{ - obj->uart->TASKS_STARTTX = 1; - obj->uart->TASKS_STARTRX = 1; -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) -{ - - if (type == FlowControlRTSCTS || type == FlowControlRTS) { - NRF_GPIO->DIR |= (1<uart->PSELRTS = rxflow; - - obj->uart->CONFIG |= 0x01; // Enable HWFC - } - - if (type == FlowControlRTSCTS || type == FlowControlCTS) { - NRF_GPIO->DIR &= ~(1<uart->PSELCTS = txflow; - - obj->uart->CONFIG |= 0x01; // Enable HWFC; - } - - if (type == FlowControlNone) { - obj->uart->PSELRTS = 0xFFFFFFFF; // Disable RTS - obj->uart->PSELCTS = 0xFFFFFFFF; // Disable CTS - - obj->uart->CONFIG &= ~0x01; // Enable HWFC; - } -} - -void serial_clear(serial_t *obj) { -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_testing; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c deleted file mode 100644 index d8d2d7e38d..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/sleep.c +++ /dev/null @@ -1,33 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "mbed_toolchain.h" - -MBED_WEAK void hal_sleep(void) -{ - // ensure debug is disconnected if semihost is enabled.... - NRF_POWER->TASKS_LOWPWR = 1; - // wait for interrupt - __WFE(); -} - -MBED_WEAK void hal_deepsleep(void) -{ - hal_sleep(); - // NRF_POWER->SYSTEMOFF=1; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c deleted file mode 100755 index fd817c0b4d..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/spi_api.c +++ /dev/null @@ -1,375 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -//#include -#include "mbed_assert.h" -#include "spi_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_error.h" - -#define SPIS_MESSAGE_SIZE 1 -volatile uint8_t m_tx_buf[SPIS_MESSAGE_SIZE] = {0}; -volatile uint8_t m_rx_buf[SPIS_MESSAGE_SIZE] = {0}; - -// nRF51822's I2C_0 and SPI_0 (I2C_1, SPI_1 and SPIS1) share the same address. -// They can't be used at the same time. So we use two global variable to track the usage. -// See nRF51822 address information at nRF51822_PS v2.0.pdf - Table 15 Peripheral instance reference -extern volatile i2c_spi_peripheral_t i2c0_spi0_peripheral; // from i2c_api.c -extern volatile i2c_spi_peripheral_t i2c1_spi1_peripheral; - -// Pinmap used for testing only -static const PinMap PinMap_SPI_testing[] = { - {P0_0, 0, 0}, - {P0_1, 0, 0}, - {P0_2, 0, 0}, - {P0_3, 0, 0}, - {P0_4, 0, 0}, - {P0_5, 0, 0}, - {P0_6, 0, 0}, - {P0_7, 0, 0}, - {P0_8, 0, 0}, - {P0_9, 0, 0}, - {P0_10, 0, 0}, - {P0_11, 0, 0}, - {P0_12, 0, 0}, - {P0_13, 0, 0}, - {P0_14, 0, 0}, - {P0_15, 0, 0}, - {P0_16, 0, 0}, - {P0_17, 0, 0}, - {P0_18, 0, 0}, - {P0_19, 0, 0}, - {P0_20, 0, 0}, - {P0_21, 0, 0}, - {P0_22, 0, 0}, - {P0_23, 0, 0}, - {P0_24, 0, 0}, - {P0_25, 0, 0}, - {P0_28, 0, 0}, - {P0_29, 0, 0}, - {P0_30, 0, 0}, - {NC, NC, 0} -}; - -void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - SPIName spi = SPI_0; - - if (ssel == NC && i2c0_spi0_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI && - i2c0_spi0_peripheral.sda_mosi == (uint8_t)mosi && - i2c0_spi0_peripheral.scl_miso == (uint8_t)miso && - i2c0_spi0_peripheral.sclk == (uint8_t)sclk) { - // The SPI with the same pins is already initialized - spi = SPI_0; - obj->peripheral = 0x1; - } else if (ssel == NC && i2c1_spi1_peripheral.usage == I2C_SPI_PERIPHERAL_FOR_SPI && - i2c1_spi1_peripheral.sda_mosi == (uint8_t)mosi && - i2c1_spi1_peripheral.scl_miso == (uint8_t)miso && - i2c1_spi1_peripheral.sclk == (uint8_t)sclk) { - // The SPI with the same pins is already initialized - spi = SPI_1; - obj->peripheral = 0x2; - } else if (i2c1_spi1_peripheral.usage == 0) { - i2c1_spi1_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI; - i2c1_spi1_peripheral.sda_mosi = (uint8_t)mosi; - i2c1_spi1_peripheral.scl_miso = (uint8_t)miso; - i2c1_spi1_peripheral.sclk = (uint8_t)sclk; - - spi = SPI_1; - obj->peripheral = 0x2; - } else if (i2c0_spi0_peripheral.usage == 0) { - i2c0_spi0_peripheral.usage = I2C_SPI_PERIPHERAL_FOR_SPI; - i2c0_spi0_peripheral.sda_mosi = (uint8_t)mosi; - i2c0_spi0_peripheral.scl_miso = (uint8_t)miso; - i2c0_spi0_peripheral.sclk = (uint8_t)sclk; - - spi = SPI_0; - obj->peripheral = 0x1; - } else { - // No available peripheral - error("No available SPI"); - } - - if (ssel==NC) { - obj->spi = (NRF_SPI_Type *)spi; - obj->spis = (NRF_SPIS_Type *)NC; - } else { - obj->spi = (NRF_SPI_Type *)NC; - obj->spis = (NRF_SPIS_Type *)spi; - } - - // pin out the spi pins - if (ssel != NC) { //slave - obj->spis->POWER = 0; - obj->spis->POWER = 1; - - NRF_GPIO->PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - NRF_GPIO->PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - NRF_GPIO->PIN_CNF[ssel] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - - obj->spis->PSELMOSI = mosi; - obj->spis->PSELMISO = miso; - obj->spis->PSELSCK = sclk; - obj->spis->PSELCSN = ssel; - - obj->spis->EVENTS_END = 0; - obj->spis->EVENTS_ACQUIRED = 0; - obj->spis->MAXRX = SPIS_MESSAGE_SIZE; - obj->spis->MAXTX = SPIS_MESSAGE_SIZE; - obj->spis->TXDPTR = (uint32_t)&m_tx_buf[0]; - obj->spis->RXDPTR = (uint32_t)&m_rx_buf[0]; - obj->spis->SHORTS = (SPIS_SHORTS_END_ACQUIRE_Enabled << SPIS_SHORTS_END_ACQUIRE_Pos); - - spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave - } else { //master - obj->spi->POWER = 0; - obj->spi->POWER = 1; - - //NRF_GPIO->DIR |= (1<PIN_CNF[mosi] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - obj->spi->PSELMOSI = mosi; - - NRF_GPIO->PIN_CNF[sclk] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - obj->spi->PSELSCK = sclk; - - //NRF_GPIO->DIR &= ~(1<PIN_CNF[miso] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) - | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos) - | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos) - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - - obj->spi->PSELMISO = miso; - - obj->spi->EVENTS_READY = 0U; - - spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master - spi_frequency(obj, 1000000); - } -} - -void spi_free(spi_t *obj) -{ -} - -static inline void spi_disable(spi_t *obj, int slave) -{ - if (slave) { - obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos); - } else { - obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos); - } -} - -static inline void spi_enable(spi_t *obj, int slave) -{ - if (slave) { - obj->spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos); - } else { - obj->spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos); - } -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - uint32_t config_mode = 0; - spi_disable(obj, slave); - - if (bits != 8) { - error("Only 8bits SPI supported"); - } - - switch (mode) { - case 0: - config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); - break; - case 1: - config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos); - break; - case 2: - config_mode = (SPI_CONFIG_CPHA_Leading << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos); - break; - case 3: - config_mode = (SPI_CONFIG_CPHA_Trailing << SPI_CONFIG_CPHA_Pos) | (SPI_CONFIG_CPOL_ActiveLow << SPI_CONFIG_CPOL_Pos); - break; - default: - error("SPI format error"); - break; - } - //default to msb first - if (slave) { - obj->spis->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); - } else { - obj->spi->CONFIG = (config_mode | (SPI_CONFIG_ORDER_MsbFirst << SPI_CONFIG_ORDER_Pos)); - } - - spi_enable(obj, slave); -} - -void spi_frequency(spi_t *obj, int hz) -{ - if ((int)obj->spi==NC) { - return; - } - spi_disable(obj, 0); - - if (hz<250000) { //125Kbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K125; - } else if (hz<500000) { //250Kbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K250; - } else if (hz<1000000) { //500Kbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_K500; - } else if (hz<2000000) { //1Mbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M1; - } else if (hz<4000000) { //2Mbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M2; - } else if (hz<8000000) { //4Mbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M4; - } else { //8Mbps - obj->spi->FREQUENCY = (uint32_t) SPI_FREQUENCY_FREQUENCY_M8; - } - - spi_enable(obj, 0); -} - -static inline int spi_readable(spi_t *obj) -{ - return (obj->spi->EVENTS_READY == 1); -} - -static inline int spi_writeable(spi_t *obj) -{ - return (obj->spi->EVENTS_READY == 0); -} - -static inline int spi_read(spi_t *obj) -{ - while (!spi_readable(obj)) { - } - - obj->spi->EVENTS_READY = 0; - return (int)obj->spi->RXD; -} - -int spi_master_write(spi_t *obj, int value) -{ - while (!spi_writeable(obj)) { - } - obj->spi->TXD = (uint32_t)value; - return spi_read(obj); -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -//static inline int spis_writeable(spi_t *obj) { -// return (obj->spis->EVENTS_ACQUIRED==1); -//} - -int spi_slave_receive(spi_t *obj) -{ - return obj->spis->EVENTS_END; -} - -int spi_slave_read(spi_t *obj) -{ - return m_rx_buf[0]; -} - -void spi_slave_write(spi_t *obj, int value) -{ - m_tx_buf[0] = value & 0xFF; - obj->spis->TASKS_RELEASE = 1; - obj->spis->EVENTS_ACQUIRED = 0; - obj->spis->EVENTS_END = 0; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_testing; -} diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_config.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_config.h deleted file mode 100755 index a5ad887d14..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_config.h +++ /dev/null @@ -1,20 +0,0 @@ -/* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ -#ifndef TWI_MASTER_CONFIG -#define TWI_MASTER_CONFIG - -#include "PinNames.h" - -#define TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER (I2C_SCL0) -#define TWI_MASTER_CONFIG_DATA_PIN_NUMBER (I2C_SDA0) - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.c deleted file mode 100755 index d7a02f0541..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.c +++ /dev/null @@ -1,304 +0,0 @@ -/* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#include "twi_master.h" -#include "twi_config.h" -#include -#include -#include "nrf.h" -#include "nrf_delay.h" - -/* Max cycles approximately to wait on RXDREADY and TXDREADY event, - * This is optimized way instead of using timers, this is not power aware. */ -#define MAX_TIMEOUT_LOOPS (20000UL) /**< MAX while loops to wait for RXD/TXD event */ - -static bool twi_master_write(uint8_t * data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi) -{ - uint32_t timeout = MAX_TIMEOUT_LOOPS; /* max loops to wait for EVENTS_TXDSENT event*/ - - if (data_length == 0) - { - /* Return false for requesting data of size 0 */ - return false; - } - - twi->TXD = *data++; - twi->TASKS_STARTTX = 1; - - /** @snippet [TWI HW master write] */ - while (true) - { - while (twi->EVENTS_TXDSENT == 0 && twi->EVENTS_ERROR == 0 && (--timeout)) - { - // Do nothing. - } - - if (timeout == 0 || NRF_TWI1->EVENTS_ERROR != 0) - { - // Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at - // Product Anomaly Notification document found at - // https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads - twi->EVENTS_ERROR = 0; - twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; - twi->POWER = 0; - nrf_delay_us(5); - twi->POWER = 1; - twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos; - - (void)twi_master_init_and_clear(twi); - - return false; - } - twi->EVENTS_TXDSENT = 0; - if (--data_length == 0) - { - break; - } - - twi->TXD = *data++; - } - /** @snippet [TWI HW master write] */ - - if (issue_stop_condition) - { - twi->EVENTS_STOPPED = 0; - twi->TASKS_STOP = 1; - /* Wait until stop sequence is sent */ - while(twi->EVENTS_STOPPED == 0) - { - // Do nothing. - } - } - return true; -} - - -/** @brief Function for read by twi_master. - */ -static bool twi_master_read(uint8_t * data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi) -{ - uint32_t timeout = MAX_TIMEOUT_LOOPS; /* max loops to wait for RXDREADY event*/ - - if (data_length == 0) - { - /* Return false for requesting data of size 0 */ - return false; - } - else if (data_length == 1) - { - NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_STOP; - } - else - { - NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_SUSPEND; - } - - NRF_PPI->CHENSET = PPI_CHENSET_CH0_Msk; - twi->EVENTS_RXDREADY = 0; - twi->TASKS_STARTRX = 1; - - /** @snippet [TWI HW master read] */ - while (true) - { - while (twi->EVENTS_RXDREADY == 0 && NRF_TWI1->EVENTS_ERROR == 0 && (--timeout)) - { - // Do nothing. - } - twi->EVENTS_RXDREADY = 0; - - if (timeout == 0 || twi->EVENTS_ERROR != 0) - { - // Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at - // Product Anomaly Notification document found at - // https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads - twi->EVENTS_ERROR = 0; - twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; - twi->POWER = 0; - nrf_delay_us(5); - twi->POWER = 1; - twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos; - - (void)twi_master_init_and_clear(twi); - - return false; - } - - *data++ = NRF_TWI1->RXD; - - /* Configure PPI to stop TWI master before we get last BB event */ - if (--data_length == 1) - { - NRF_PPI->CH[0].TEP = (uint32_t)&NRF_TWI1->TASKS_STOP; - } - - if (data_length == 0) - { - break; - } - - // Recover the peripheral as indicated by PAN 56: "TWI: TWI module lock-up." found at - // Product Anomaly Notification document found at - // https://www.nordicsemi.com/eng/Products/Bluetooth-R-low-energy/nRF51822/#Downloads - nrf_delay_us(20); - twi->TASKS_RESUME = 1; - } - /** @snippet [TWI HW master read] */ - - /* Wait until stop sequence is sent */ - while(twi->EVENTS_STOPPED == 0) - { - // Do nothing. - } - twi->EVENTS_STOPPED = 0; - - NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk; - return true; -} - - -/** - * @brief Function for detecting stuck slaves (SDA = 0 and SCL = 1) and tries to clear the bus. - * - * @return - * @retval false Bus is stuck. - * @retval true Bus is clear. - */ -static bool twi_master_clear_bus(NRF_TWI_Type* twi) -{ - uint32_t twi_state; - bool bus_clear; - uint32_t clk_pin_config; - uint32_t data_pin_config; - - // Save and disable TWI hardware so software can take control over the pins. - twi_state = twi->ENABLE; - twi->ENABLE = TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos; - - clk_pin_config = \ - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER]; - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \ - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - - data_pin_config = \ - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER]; - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \ - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos); - - TWI_SDA_HIGH(); - TWI_SCL_HIGH(); - TWI_DELAY(); - - if ((TWI_SDA_READ() == 1) && (TWI_SCL_READ() == 1)) - { - bus_clear = true; - } - else - { - uint_fast8_t i; - bus_clear = false; - - // Clock max 18 pulses worst case scenario(9 for master to send the rest of command and 9 - // for slave to respond) to SCL line and wait for SDA come high. - for (i=18; i--;) - { - TWI_SCL_LOW(); - TWI_DELAY(); - TWI_SCL_HIGH(); - TWI_DELAY(); - - if (TWI_SDA_READ() == 1) - { - bus_clear = true; - break; - } - } - } - - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = clk_pin_config; - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = data_pin_config; - - twi->ENABLE = twi_state; - - return bus_clear; -} - - -/** @brief Function for initializing the twi_master. - */ -bool twi_master_init_and_clear(NRF_TWI_Type* twi) -{ - /* To secure correct signal levels on the pins used by the TWI - master when the system is in OFF mode, and when the TWI master is - disabled, these pins must be configured in the GPIO peripheral. - */ - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER] = \ - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - - NRF_GPIO->PIN_CNF[TWI_MASTER_CONFIG_DATA_PIN_NUMBER] = \ - (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos) \ - | (GPIO_PIN_CNF_DRIVE_S0D1 << GPIO_PIN_CNF_DRIVE_Pos) \ - | (GPIO_PIN_CNF_PULL_Pullup << GPIO_PIN_CNF_PULL_Pos) \ - | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) \ - | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos); - - twi->EVENTS_RXDREADY = 0; - twi->EVENTS_TXDSENT = 0; - twi->PSELSCL = TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER; - twi->PSELSDA = TWI_MASTER_CONFIG_DATA_PIN_NUMBER; - twi->FREQUENCY = TWI_FREQUENCY_FREQUENCY_K100 << TWI_FREQUENCY_FREQUENCY_Pos; - NRF_PPI->CH[0].EEP = (uint32_t)&twi->EVENTS_BB; - NRF_PPI->CH[0].TEP = (uint32_t)&twi->TASKS_SUSPEND; - NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk; - twi->ENABLE = TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos; - - return twi_master_clear_bus(twi); -} - - -/** @brief Function for transfer by twi_master. - */ -bool twi_master_transfer(uint8_t address, - uint8_t * data, - uint8_t data_length, - bool issue_stop_condition, - NRF_TWI_Type* twi) -{ - bool transfer_succeeded = false; - if (data_length > 0 && twi_master_clear_bus(twi)) - { - twi->ADDRESS = (address >> 1); - - if ((address & TWI_READ_BIT)) - { - transfer_succeeded = twi_master_read(data, data_length, issue_stop_condition, twi); - } - else - { - transfer_succeeded = twi_master_write(data, data_length, issue_stop_condition, twi); - } - } - return transfer_succeeded; -} - -/*lint --flb "Leave library region" */ diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.h b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.h deleted file mode 100644 index 6a6593f87b..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/twi_master.h +++ /dev/null @@ -1,112 +0,0 @@ - /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. - * - * The information contained herein is property of Nordic Semiconductor ASA. - * Terms and conditions of usage are described in detail in NORDIC - * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. - * - * Licensees are granted free, non-transferable use of the information. NO - * WARRANTY of ANY KIND is provided. This heading must NOT be removed from - * the file. - * - */ - -#ifndef TWI_MASTER_H -#define TWI_MASTER_H - - -#ifdef __cplusplus -extern "C" { -#endif - -/*lint ++flb "Enter library region" */ - -#include -#include - -#include "nrf51.h" - -/** @file -* @brief Software controlled TWI Master driver. -* -* -* @defgroup lib_driver_twi_master Software controlled TWI Master driver -* @{ -* @ingroup nrf_drivers -* @brief Software controlled TWI Master driver. -* -* Supported features: -* - Repeated start -* - No multi-master -* - Only 7-bit addressing -* - Supports clock stretching (with optional SMBus style slave timeout) -* - Tries to handle slaves stuck in the middle of transfer -*/ - -#define TWI_READ_BIT (0x01) //!< If this bit is set in the address field, transfer direction is from slave to master. - -#define TWI_ISSUE_STOP ((bool)true) //!< Parameter for @ref twi_master_transfer -#define TWI_DONT_ISSUE_STOP ((bool)false) //!< Parameter for @ref twi_master_transfer - -/* These macros are needed to see if the slave is stuck and we as master send dummy clock cycles to end its wait */ -/*lint -e717 -save "Suppress do {} while (0) for these macros" */ -/*lint ++flb "Enter library region" */ -#define TWI_SCL_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line high */ -#define TWI_SCL_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Pulls SCL line low */ -#define TWI_SDA_HIGH() do { NRF_GPIO->OUTSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line high */ -#define TWI_SDA_LOW() do { NRF_GPIO->OUTCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Pulls SDA line low */ -#define TWI_SDA_INPUT() do { NRF_GPIO->DIRCLR = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as input */ -#define TWI_SDA_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_DATA_PIN_NUMBER); } while(0) /*!< Configures SDA pin as output */ -#define TWI_SCL_OUTPUT() do { NRF_GPIO->DIRSET = (1UL << TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER); } while(0) /*!< Configures SCL pin as output */ -/*lint -restore */ - -#define TWI_SDA_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_DATA_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SDA */ -#define TWI_SCL_READ() ((NRF_GPIO->IN >> TWI_MASTER_CONFIG_CLOCK_PIN_NUMBER) & 0x1UL) /*!< Reads current state of SCL */ - -#define TWI_DELAY() nrf_delay_us(4) /*!< Time to wait when pin states are changed. For fast-mode the delay can be zero and for standard-mode 4 us delay is sufficient. */ - - -/** - * @brief Function for initializing TWI bus IO pins and checks if the bus is operational. - * - * Both pins are configured as Standard-0, No-drive-1 (open drain). - * - * @param twi The TWI interface to use - either NRF_TWI0 or NRF_TWI1 - * @return - * @retval true TWI bus is clear for transfers. - * @retval false TWI bus is stuck. - */ -bool twi_master_init_and_clear(NRF_TWI_Type* twi); - -/** - * @brief Function for transferring data over TWI bus. - * - * If TWI master detects even one NACK from the slave or timeout occurs, STOP condition is issued - * and the function returns false. - * Bit 0 (@ref TWI_READ_BIT) in the address parameter controls transfer direction; - * - If 1, master reads data_length number of bytes from the slave - * - If 0, master writes data_length number of bytes to the slave. - * - * @note Make sure at least data_length number of bytes is allocated in data if TWI_READ_BIT is set. - * @note @ref TWI_ISSUE_STOP - * - * @param address Data transfer direction (LSB) / Slave address (7 MSBs). - * @param data Pointer to data. - * @param data_length Number of bytes to transfer. - * @param issue_stop_condition If @ref TWI_ISSUE_STOP, STOP condition is issued before exiting function. If @ref TWI_DONT_ISSUE_STOP, STOP condition is not issued before exiting function. If transfer failed for any reason, STOP condition will be issued in any case. - * @param twi The TWI interface to use - either NRF_TWI0 or NRF_TWI1 - * @return - * @retval true Data transfer succeeded without errors. - * @retval false Data transfer failed. - */ -bool twi_master_transfer(uint8_t address, uint8_t *data, uint8_t data_length, bool issue_stop_condition, NRF_TWI_Type* twi); - -/** - *@} - **/ - -#ifdef __cplusplus -} -#endif - -/*lint --flb "Leave library region" */ -#endif //TWI_MASTER_H diff --git a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c deleted file mode 100644 index eb916c0e8c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c +++ /dev/null @@ -1,618 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2013 Nordic Semiconductor - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#if DEVICE_USTICKER -#include -#include -#include "us_ticker_api.h" -#include "cmsis.h" -#include "PeripheralNames.h" -#include "nrf_delay.h" -#include "mbed_toolchain.h" -#include "mbed_critical.h" - -/* - * Note: The micro-second timer API on the nRF51 platform is implemented using - * the RTC counter run at 32kHz (sourced from an external oscillator). This is - * a trade-off between precision and power. Running a normal 32-bit MCU counter - * at high frequency causes the average power consumption to rise to a few - * hundred micro-amps, which is prohibitive for typical low-power BLE - * applications. - * A 32kHz clock doesn't offer the precision needed for keeping u-second time, - * but we're assuming that this will not be a problem for the average user. - */ - -#define MAX_RTC_COUNTER_VAL 0x00FFFFFF /**< Maximum value of the RTC counter. */ -#define RTC_CLOCK_FREQ (uint32_t)(32768) -#define RTC1_IRQ_PRI 3 /**< Priority of the RTC1 interrupt (used - * for checking for timeouts and executing - * timeout handlers). This must be the same - * as APP_IRQ_PRIORITY_LOW; taken from the - * Nordic SDK. */ -#define MAX_RTC_TASKS_DELAY 47 /**< Maximum delay until an RTC task is executed. */ - -#define FUZZY_RTC_TICKS 2 /* RTC COMPARE occurs when a CC register is N and the RTC - * COUNTER value transitions from N-1 to N. If we're trying to - * setup a callback for a time which will arrive very shortly, - * there are limits to how short the callback interval may be for us - * to rely upon the RTC Compare trigger. If the COUNTER is N, - * writing N+2 to a CC register is guaranteed to trigger a COMPARE - * event at N+2. */ - -#define RTC_UNITS_TO_MICROSECONDS(RTC_UNITS) (((RTC_UNITS) * (uint64_t)1000000) / RTC_CLOCK_FREQ) -#define MICROSECONDS_TO_RTC_UNITS(MICROS) ((((uint64_t)(MICROS) * RTC_CLOCK_FREQ) + 999999) / 1000000) - -#define US_TICKER_SW_IRQ_MASK 0x1 - -static bool us_ticker_inited = false; -static volatile uint32_t overflowCount; /**< The number of times the 24-bit RTC counter has overflowed. */ -static volatile bool us_ticker_callbackPending = false; -static uint32_t us_ticker_callbackTimestamp; -static bool os_tick_started = false; /**< flag indicating if the os_tick has started */ -/** - * The value previously set in the capture compare register of channel 1 - */ -static uint32_t previous_tick_cc_value = 0; - -// us ticker fire interrupt flag for IRQ handler -volatile uint8_t m_common_sw_irq_flag = 0; - -/* - RTX provide the following definitions which are used by the tick code: - * os_trv: The number (minus 1) of clock cycle between two tick. - * os_clockrate: Time duration between two ticks (in us). - * OS_Tick_Handler: The function which handle a tick event. - This function is special because it never returns. - Those definitions are used by the code which handle the os tick. - To allow compilation of us_ticker programs without RTOS, those symbols are - exported from this module as weak ones. - */ -MBED_WEAK uint32_t const os_trv; -MBED_WEAK uint32_t const os_clockrate; -MBED_WEAK void OS_Tick_Handler() { } - -static inline void rtc1_enableCompareInterrupt(void) -{ - NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; - NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE0_Msk; -} - -static inline void rtc1_disableCompareInterrupt(void) -{ - NRF_RTC1->INTENCLR = RTC_INTENSET_COMPARE0_Msk; - NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; -} - -static inline void rtc1_enableOverflowInterrupt(void) -{ - NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk; - NRF_RTC1->INTENSET = RTC_INTENSET_OVRFLW_Msk; -} - -static inline void rtc1_disableOverflowInterrupt(void) -{ - NRF_RTC1->INTENCLR = RTC_INTENSET_OVRFLW_Msk; - NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk; -} - -static inline void invokeCallback(void) -{ - us_ticker_callbackPending = false; - rtc1_disableCompareInterrupt(); - us_ticker_irq_handler(); -} - -/** - * @brief Function for starting the RTC1 timer. The RTC timer is expected to - * keep running--some interrupts may be disabled temporarily. - */ -static void rtc1_start() -{ - NRF_RTC1->PRESCALER = 0; /* for no pre-scaling. */ - - rtc1_enableOverflowInterrupt(); - - NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI); - NVIC_ClearPendingIRQ(RTC1_IRQn); - NVIC_EnableIRQ(RTC1_IRQn); - - NRF_RTC1->TASKS_START = 1; - nrf_delay_us(MAX_RTC_TASKS_DELAY); -} - -/** - * @brief Function for stopping the RTC1 timer. We don't expect to call this. - */ -void rtc1_stop(void) -{ - // If the os tick has been started, RTC1 shouldn't be stopped - // In that case, us ticker and overflow interrupt are disabled. - if (os_tick_started) { - rtc1_disableCompareInterrupt(); - rtc1_disableOverflowInterrupt(); - } else { - NVIC_DisableIRQ(RTC1_IRQn); - rtc1_disableCompareInterrupt(); - rtc1_disableOverflowInterrupt(); - - NRF_RTC1->TASKS_STOP = 1; - nrf_delay_us(MAX_RTC_TASKS_DELAY); - - NRF_RTC1->TASKS_CLEAR = 1; - nrf_delay_us(MAX_RTC_TASKS_DELAY); - } -} - -/** - * @brief Function for returning the current value of the RTC1 counter. - * - * @return Current RTC1 counter as a 64-bit value with 56-bit precision (even - * though the underlying counter is 24-bit) - */ -static inline uint64_t rtc1_getCounter64(void) -{ - if (NRF_RTC1->EVENTS_OVRFLW) { - overflowCount++; - NRF_RTC1->EVENTS_OVRFLW = 0; - NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk; - } - return ((uint64_t)overflowCount << 24) | NRF_RTC1->COUNTER; -} - -/** - * @brief Function for returning the current value of the RTC1 counter. - * - * @return Current RTC1 counter as a 32-bit value (even though the underlying counter is 24-bit) - */ -static inline uint32_t rtc1_getCounter(void) -{ - return rtc1_getCounter64(); -} - -/** - * @brief Function for handling the RTC1 interrupt for us ticker (capture compare channel 0 and overflow). - * - * @details Checks for timeouts, and executes timeout handlers for expired timers. - */ -void us_ticker_handler(void) -{ - if (m_common_sw_irq_flag & US_TICKER_SW_IRQ_MASK) { - m_common_sw_irq_flag &= ~US_TICKER_SW_IRQ_MASK; - us_ticker_irq_handler(); - } - - if (NRF_RTC1->EVENTS_OVRFLW) { - overflowCount++; - NRF_RTC1->EVENTS_OVRFLW = 0; - NRF_RTC1->EVTENCLR = RTC_EVTEN_OVRFLW_Msk; - } - if (NRF_RTC1->EVENTS_COMPARE[0]) { - NRF_RTC1->EVENTS_COMPARE[0] = 0; - NRF_RTC1->EVTENCLR = RTC_EVTEN_COMPARE0_Msk; - if (us_ticker_callbackPending && ((int)(us_ticker_callbackTimestamp - rtc1_getCounter()) <= 0)) - invokeCallback(); - } -} - -void us_ticker_init(void) -{ - if (us_ticker_inited) { - return; - } - - rtc1_start(); - us_ticker_inited = true; -} - -uint32_t us_ticker_read() -{ - if (!us_ticker_inited) { - us_ticker_init(); - } - - /* Return a pseudo microsecond counter value. This is only as precise as the - * 32khz low-freq clock source, but could be adequate.*/ - return RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64()); -} - -/** - * Setup the us_ticker callback interrupt to go at the given timestamp. - * - * @Note: Only one callback is pending at any time. - * - * @Note: If a callback is pending, and this function is called again, the new - * callback-time overrides the existing callback setting. It is the caller's - * responsibility to ensure that this function is called to setup a callback for - * the earliest timeout. - * - * @Note: If this function is used to setup an interrupt which is immediately - * pending--such as for 'now' or a time in the past,--then the callback is - * invoked a few ticks later. - */ -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - if (!us_ticker_inited) { - us_ticker_init(); - } - - /* - * The argument to this function is a 32-bit microsecond timestamp for when - * a callback should be invoked. On the nRF51, we use an RTC timer running - * at 32kHz to implement a low-power us-ticker. This results in a problem - * based on the fact that 1000000 is not a multiple of 32768. - * - * Going from a micro-second based timestamp to a 32kHz based RTC-time is a - * linear mapping; but this mapping doesn't preserve wraparounds--i.e. when - * the 32-bit micro-second timestamp wraps around unfortunately the - * underlying RTC counter doesn't. The result is that timestamp expiry - * checks on micro-second timestamps don't yield the same result when - * applied on the corresponding RTC timestamp values. - * - * One solution is to translate the incoming 32-bit timestamp into a virtual - * 64-bit timestamp based on the knowledge of system-uptime, and then use - * this wraparound-free 64-bit value to do a linear mapping to RTC time. - * System uptime on an nRF is maintained using the 24-bit RTC counter. We - * track the overflow count to extend the 24-bit hardware counter by an - * additional 32 bits. RTC_UNITS_TO_MICROSECONDS() converts this into - * microsecond units (in 64-bits). - */ - const uint64_t currentTime64 = RTC_UNITS_TO_MICROSECONDS(rtc1_getCounter64()); - uint64_t timestamp64 = (currentTime64 & ~(uint64_t)0xFFFFFFFFULL) + timestamp; - if (((uint32_t)currentTime64 > 0x80000000) && (timestamp < 0x80000000)) { - timestamp64 += (uint64_t)0x100000000ULL; - } - uint32_t newCallbackTime = MICROSECONDS_TO_RTC_UNITS(timestamp64); - - /* Check for repeat setup of an existing callback. This is actually not - * important; the following code should work even without this check. */ - if (us_ticker_callbackPending && (newCallbackTime == us_ticker_callbackTimestamp)) { - return; - } - - /* Check for callbacks which are immediately (or will *very* shortly become) pending. - * Even if they are immediately pending, they are scheduled to trigger a few - * ticks later. This keeps things simple by invoking the callback from an - * independent interrupt context. */ - if ((int)(newCallbackTime - rtc1_getCounter()) <= (int)FUZZY_RTC_TICKS) { - newCallbackTime = rtc1_getCounter() + FUZZY_RTC_TICKS; - } - - NRF_RTC1->CC[0] = newCallbackTime & MAX_RTC_COUNTER_VAL; - us_ticker_callbackTimestamp = newCallbackTime; - if (!us_ticker_callbackPending) { - us_ticker_callbackPending = true; - rtc1_enableCompareInterrupt(); - } -} - -void us_ticker_fire_interrupt(void) -{ - core_util_critical_section_enter(); - m_common_sw_irq_flag |= US_TICKER_SW_IRQ_MASK; - NVIC_SetPendingIRQ(RTC1_IRQn); - core_util_critical_section_exit(); -} - -void us_ticker_disable_interrupt(void) -{ - if (us_ticker_callbackPending) { - rtc1_disableCompareInterrupt(); - us_ticker_callbackPending = false; - } -} - -void us_ticker_clear_interrupt(void) -{ - NRF_RTC1->EVENTS_OVRFLW = 0; - NRF_RTC1->EVENTS_COMPARE[0] = 0; -} - -void us_ticker_free(void) -{ - -} - - -#if defined (__CC_ARM) /* ARMCC Compiler */ - -__asm void RTC1_IRQHandler(void) -{ - IMPORT OS_Tick_Handler - IMPORT us_ticker_handler - - /** - * Chanel 1 of RTC1 is used by RTX as a systick. - * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. - * Otherwise, just execute us_ticker_handler. - * This function has to be written in assembly and tagged as naked because OS_Tick_Handler - * will never return. - * A c function would put lr on the stack before calling OS_Tick_Handler and this value - * would never been dequeued. - * - * \code - * void RTC1_IRQHandler(void) { - if(NRF_RTC1->EVENTS_COMPARE[1]) { - // never return... - OS_Tick_Handler(); - } else { - us_ticker_handler(); - } - } - * \endcode - */ - ldr r0,=0x40011144 - ldr r1, [r0, #0] - cmp r1, #0 - beq US_TICKER_HANDLER - bl OS_Tick_Handler -US_TICKER_HANDLER - push {r3, lr} - bl us_ticker_handler - pop {r3, pc} - nop /* padding */ -} - -#elif defined (__GNUC__) /* GNU Compiler */ - -__attribute__((naked)) void RTC1_IRQHandler(void) -{ - /** - * Chanel 1 of RTC1 is used by RTX as a systick. - * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. - * Otherwise, just execute us_ticker_handler. - * This function has to be written in assembly and tagged as naked because OS_Tick_Handler - * will never return. - * A c function would put lr on the stack before calling OS_Tick_Handler and this value - * would never been dequeued. - * - * \code - * void RTC1_IRQHandler(void) { - if(NRF_RTC1->EVENTS_COMPARE[1]) { - // never return... - OS_Tick_Handler(); - } else { - us_ticker_handler(); - } - } - * \endcode - */ - __asm__ ( - "ldr r0,=0x40011144\n" - "ldr r1, [r0, #0]\n" - "cmp r1, #0\n" - "beq US_TICKER_HANDLER\n" - "bl OS_Tick_Handler\n" - "US_TICKER_HANDLER:\n" - "push {r3, lr}\n" - "bl us_ticker_handler\n" - "pop {r3, pc}\n" - "nop" - ); -} - -#else - -#error Compiler not supported. -#error Provide a definition of RTC1_IRQHandler. - -/* - * Chanel 1 of RTC1 is used by RTX as a systick. - * If the compare event on channel 1 is set, then branch to OS_Tick_Handler. - * Otherwise, just execute us_ticker_handler. - * This function has to be written in assembly and tagged as naked because OS_Tick_Handler - * will never return. - * A c function would put lr on the stack before calling OS_Tick_Handler and this value - * will never been dequeued. After a certain time a stack overflow will happen. - * - * \code - * void RTC1_IRQHandler(void) { - if(NRF_RTC1->EVENTS_COMPARE[1]) { - // never return... - OS_Tick_Handler(); - } else { - us_ticker_handler(); - } - } - * \endcode - */ - -#endif - -/** - * Return the next number of clock cycle needed for the next tick. - * @note This function has been carrefuly optimized for a systick occuring every 1000us. - */ -static uint32_t get_next_tick_cc_delta() { - uint32_t delta = 0; - - if (os_clockrate != 1000) { - // In RTX, by default SYSTICK is is used. - // A tick event is generated every os_trv + 1 clock cycles of the system timer. - delta = os_trv + 1; - } else { - // If the clockrate is set to 1000us then 1000 tick should happen every second. - // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31. - // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be - // generated in 32000 clock cycle instead of 32768 clock cycles. - // As a result, if a user schedule an OS timer to start in 100s, the timer will start - // instead after 97.656s - // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768 - // clock cycles. - // The strategy is simple, for 1000 ticks: - // * 768 ticks will occur 33 clock cycles after the previous tick - // * 232 ticks will occur 32 clock cycles after the previous tick - // By default every delta is equal to 33. - // Every five ticks (20%, 200 delta in one second), the delta is equal to 32 - // The remaining (32) deltas equal to 32 are distributed using primes numbers. - static uint32_t counter = 0; - if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) { - delta = 32; - } else { - delta = 33; - } - ++counter; - if (counter == 1000) { - counter = 0; - } - } - return delta; -} - -static inline void clear_tick_interrupt() { - NRF_RTC1->EVENTS_COMPARE[1] = 0; - NRF_RTC1->EVTENCLR = (1 << 17); -} - -/** - * Indicate if a value is included in a range which can be wrapped. - * @param begin start of the range - * @param end end of the range - * @param val value to check - * @return true if the value is included in the range and false otherwise. - */ -static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) { - // regular case, begin < end - // return true if begin <= val < end - if (begin < end) { - if (begin <= val && val < end) { - return true; - } else { - return false; - } - } else { - // In this case end < begin because it has wrap around the limits - // return false if end < val < begin - if (end < val && val < begin) { - return false; - } else { - return true; - } - } - -} - -/** - * Register the next tick. - */ -static void register_next_tick() { - previous_tick_cc_value = NRF_RTC1->CC[1]; - uint32_t delta = get_next_tick_cc_delta(); - uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL; - - // Disable irq directly for few cycles, - // Validation of the new CC value against the COUNTER, - // Setting the new CC value and enabling CC IRQ should be an atomic operation - // Otherwise, there is a possibility to set an invalid CC value because - // the RTC1 keeps running. - // This code is very short 20-38 cycles in the worst case, it shouldn't - // disturb softdevice. - __disable_irq(); - uint32_t current_counter = NRF_RTC1->COUNTER; - - // If an overflow occur, set the next tick in COUNTER + delta clock cycles - if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter) == false) { - new_compare_value = current_counter + delta; - } - NRF_RTC1->CC[1] = new_compare_value; - - // set the interrupt of CC channel 1 and reenable IRQs - NRF_RTC1->INTENSET = RTC_INTENSET_COMPARE1_Msk; - __enable_irq(); -} - -/** - * Initialize alternative hardware timer as RTX kernel timer - * This function is directly called by RTX. - * @note this function shouldn't be called directly. - * @return IRQ number of the alternative hardware timer - */ -int os_tick_init (void) -{ - // their is no need to start the LF clock, it is already started by SystemInit. - NVIC_SetPriority(RTC1_IRQn, RTC1_IRQ_PRI); - NVIC_ClearPendingIRQ(RTC1_IRQn); - NVIC_EnableIRQ(RTC1_IRQn); - - NRF_RTC1->TASKS_START = 1; - nrf_delay_us(MAX_RTC_TASKS_DELAY); - - NRF_RTC1->CC[1] = 0; - clear_tick_interrupt(); - register_next_tick(); - - os_tick_started = true; - - return RTC1_IRQn; -} - -/** - * Acknowledge the tick interrupt. - * This function is called by the function OS_Tick_Handler of RTX. - * @note this function shouldn't be called directly. - */ -void os_tick_irqack(void) -{ - clear_tick_interrupt(); - register_next_tick(); -} - -/** - * Returns the overflow flag of the alternative hardware timer. - * @note This function is exposed by RTX kernel. - * @return 1 if the timer has overflowed and 0 otherwise. - */ -uint32_t os_tick_ovf(void) { - uint32_t current_counter = NRF_RTC1->COUNTER; - uint32_t next_tick_cc_value = NRF_RTC1->CC[1]; - - return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1; -} - -/** - * Return the value of the alternative hardware timer. - * @note The documentation is not very clear about what is expected as a result, - * is it an ascending counter, a descending one ? - * None of this is specified. - * The default systick is a descending counter and this function return values in - * descending order, even if the internal counter used is an ascending one. - * @return the value of the alternative hardware timer. - */ -uint32_t os_tick_val(void) { - uint32_t current_counter = NRF_RTC1->COUNTER; - uint32_t next_tick_cc_value = NRF_RTC1->CC[1]; - - // do not use os_tick_ovf because its counter value can be different - if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) { - if (next_tick_cc_value > previous_tick_cc_value) { - return next_tick_cc_value - current_counter; - } else if(current_counter <= next_tick_cc_value) { - return next_tick_cc_value - current_counter; - } else { - return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter); - } - } else { - // use (os_trv + 1) has the base step, can be totally inacurate ... - uint32_t clock_cycles_by_tick = os_trv + 1; - - // if current counter has wrap arround, add the limit to it. - if (current_counter < next_tick_cc_value) { - current_counter = current_counter + MAX_RTC_COUNTER_VAL; - } - - return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick); - } -} -#endif // DEVICE_USTICKER diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h deleted file mode 100644 index 65cc930c8c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h +++ /dev/null @@ -1,81 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_PERIPHERALNAMES_H -#define MBED_PERIPHERALNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define STDIO_UART_TX TX_PIN_NUMBER -#define STDIO_UART_RX RX_PIN_NUMBER -#define STDIO_UART UART_0 - -typedef enum { - UART_0 = (int)NRF_UART0_BASE -} UARTName; - - -typedef enum { - SPI_0 = (int)NRF_SPI0_BASE, - SPI_1 = (int)NRF_SPI1_BASE, - SPIS = (int)NRF_SPIS1_BASE -} SPIName; - -typedef enum { - PWM_1 = 0, - PWM_2 -} PWMName; - -typedef enum { - I2C_0 = (int)NRF_TWI0_BASE, - I2C_1 = (int)NRF_TWI1_BASE -} I2CName; - -typedef enum { - ADC0_0 = (int)NRF_ADC_BASE -} ADCName; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PortNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PortNames.h deleted file mode 100644 index c63624639b..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/PortNames.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_PORTNAMES_H -#define MBED_PORTNAMES_H - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - Port0 = 0 //GPIO pins 0-31 -} PortName; - -#ifdef __cplusplus -} -#endif -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h deleted file mode 100644 index aca5d880f5..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h +++ /dev/null @@ -1,199 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_PINNAMES_H -#define MBED_PINNAMES_H - -#include "cmsis.h" - -#ifdef __cplusplus -extern "C" { -#endif - -typedef enum { - PIN_INPUT, - PIN_OUTPUT -} PinDirection; - -typedef enum { - p0 = 0, - p1 = 1, - p2 = 2, - p3 = 3, - p4 = 4, - p5 = 5, - p6 = 6, - p7 = 7, - p8 = 8, - p9 = 9, - p10 = 10, - p11 = 11, - p12 = 12, - p13 = 13, - p14 = 14, - p15 = 15, - p16 = 16, - p17 = 17, - p18 = 18, - p19 = 19, - p20 = 20, - p21 = 21, - p22 = 22, - p23 = 23, - p24 = 24, - p25 = 25, - p26 = 26, - p27 = 27, - p28 = 28, - p29 = 29, - p30 = 30, - - P0_0 = p0, - P0_1 = p1, - P0_2 = p2, - P0_3 = p3, - P0_4 = p4, - P0_5 = p5, - P0_6 = p6, - P0_7 = p7, - - P0_8 = p8, - P0_9 = p9, - P0_10 = p10, - P0_11 = p11, - P0_12 = p12, - P0_13 = p13, - P0_14 = p14, - P0_15 = p15, - - P0_16 = p16, - P0_17 = p17, - P0_18 = p18, - P0_19 = p19, - P0_20 = p20, - P0_21 = p21, - P0_22 = p22, - P0_23 = p23, - - P0_24 = p24, - P0_25 = p25, - P0_26 = p26, - P0_27 = p27, - P0_28 = p28, - P0_29 = p29, - P0_30 = p30, - - LED1 = p21, - LED2 = p22, - LED3 = p23, - LED4 = p24, - - BUTTON1 = p17, - BUTTON2 = p18, - BUTTON3 = p19, - BUTTON4 = p20, - - RX_PIN_NUMBER = p11, - TX_PIN_NUMBER = p9, - CTS_PIN_NUMBER = p10, - RTS_PIN_NUMBER = p8, - - // mBed interface Pins - USBTX = TX_PIN_NUMBER, - USBRX = RX_PIN_NUMBER, - - SPI_PSELMOSI0 = p25, - SPI_PSELMISO0 = p28, - SPI_PSELSS0 = p24, - SPI_PSELSCK0 = p29, - - SPI_PSELMOSI1 = p13, - SPI_PSELMISO1 = p14, - SPI_PSELSS1 = p12, - SPI_PSELSCK1 = p15, - - SPIS_PSELMOSI = p13, - SPIS_PSELMISO = p14, - SPIS_PSELSS = p12, - SPIS_PSELSCK = p15, - - I2C_SDA0 = p30, - I2C_SCL0 = p7, - - D0 = p12, - D1 = p13, - D2 = p14, - D3 = p15, - D4 = p16, - D5 = p17, - D6 = p18, - D7 = p19, - - D8 = p20, - D9 = p23, - D10 = p24, - D11 = p25, - D12 = p28, - D13 = p29, - - D14 = p30, - D15 = p7, - - A0 = p1, - A1 = p2, - A2 = p3, - A3 = p4, - A4 = p5, - A5 = p6, - - // Not connected - NC = (int)0xFFFFFFFF -} PinName; - -typedef enum { - PullNone = 0, - PullDown = 1, - PullUp = 3, - PullDefault = PullUp -} PinMode; - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h deleted file mode 100644 index 2427e752ea..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h +++ /dev/null @@ -1,38 +0,0 @@ -// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. -// Check the 'features' section of the target description in 'targets.json' for more details. -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#ifndef MBED_DEVICE_H -#define MBED_DEVICE_H - - - - - - - - - - - - - - - - -#include "objects.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c deleted file mode 100644 index f021ec9c10..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c +++ /dev/null @@ -1,94 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "analogin_api.h" -#include "cmsis.h" -#include "pinmap.h" -#include "nrf_drv_adc.h" - -#if DEVICE_ANALOGIN - - -#define ADC_10BIT_RANGE 0x3FF -#define ADC_RANGE ADC_10BIT_RANGE - -static const PinMap PinMap_ADC[] = { - {p1, ADC0_0, 4}, - {p2, ADC0_0, 8}, - {p3, ADC0_0, 16}, - {p4, ADC0_0, 32}, - {p5, ADC0_0, 64}, - {p6, ADC0_0, 128}, - {p26, ADC0_0, 1}, - {p27, ADC0_0, 2}, - {NC, NC, 0} -}; - -void ADC_IRQHandler(void); // export IRQ handler from nrf_drv_adc.c - -void analogin_init(analogin_t *obj, PinName pin) -{ - obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC); - MBED_ASSERT(obj->adc != (ADCName)NC); - - uint32_t pinFunc = pinmap_function(pin, PinMap_ADC); - MBED_ASSERT(pinFunc != (uint32_t)NC); - - obj->adc_pin = pinFunc; - - NVIC_SetVector(ADC_IRQn, (uint32_t)ADC_IRQHandler); - - ret_code_t ret_code; - // p_config, event_handler - ret_code = nrf_drv_adc_init(NULL , NULL); // select blocking mode - MBED_ASSERT((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE)); //NRF_ERROR_INVALID_STATE expected for multiple channels used. -} - -uint16_t analogin_read_u16(analogin_t *obj) -{ - nrf_adc_value_t adc_value; - - nrf_drv_adc_channel_t adc_channel; - - // initialization by assigment because IAR dosen't support variable initializer in declaration statement. - adc_channel.config.config.resolution = NRF_ADC_CONFIG_RES_10BIT; - adc_channel.config.config.input = NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD; - adc_channel.config.config.reference = NRF_ADC_CONFIG_REF_VBG; - adc_channel.config.config.ain = (obj->adc_pin); - adc_channel.p_next = NULL; - - - ret_code_t ret_code; - - ret_code = nrf_drv_adc_sample_convert( &adc_channel, &adc_value); - MBED_ASSERT(ret_code == NRF_SUCCESS); - - return adc_value; -} - -float analogin_read(analogin_t *obj) -{ - uint16_t value = analogin_read_u16(obj); - - return (float)value * (1.0f / (float)ADC_RANGE); -} - -const PinMap *analogin_pinmap() -{ - return PinMap_ADC; -} - -#endif // DEVICE_ANALOGIN diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S deleted file mode 100644 index 45a8a25549..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S +++ /dev/null @@ -1,189 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2013 Nordic Semiconductor. -;Licensed under the Apache License, Version 2.0 (the "License"); -;you may not use this file except in compliance with the License. -;You may obtain a copy of the License at -;http://www.apache.org/licenses/LICENSE-2.0 -;Unless required by applicable law or agreed to in writing, software -;distributed under the License is distributed on an "AS IS" BASIS, -;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;See the License for the specific language governing permissions and -;limitations under the License. - -; Description message - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler_v ;UART0 - DCD SPI0_TWI0_IRQHandler_v ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler_v ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler_v ;GPIOTE - DCD ADC_IRQHandler_v ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler_v ;TIMER1 - DCD TIMER2_IRQHandler_v ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler_v ;WDT - DCD RTC1_IRQHandler_v ;RTC1 - DCD QDEC_IRQHandler_v ;QDEC - DCD LPCOMP_IRQHandler_v ;LPCOMP_COMP - DCD SWI0_IRQHandler_v ;SWI0 - DCD SWI1_IRQHandler_v ;SWI1 - DCD SWI2_IRQHandler_v ;SWI2 - DCD SWI3_IRQHandler_v ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT nrf_reloc_vector_table - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk - ORRS R2, R2, R1 - STR R2, [R0] - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UART0_IRQHandler_v [WEAK] - EXPORT SPI0_TWI0_IRQHandler_v [WEAK] - EXPORT SPI1_TWI1_IRQHandler_v [WEAK] - EXPORT GPIOTE_IRQHandler_v [WEAK] - EXPORT ADC_IRQHandler_v [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler_v [WEAK] - EXPORT TIMER2_IRQHandler_v [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler_v [WEAK] - EXPORT RTC1_IRQHandler_v [WEAK] - EXPORT QDEC_IRQHandler_v [WEAK] - EXPORT LPCOMP_IRQHandler_v [WEAK] - EXPORT SWI0_IRQHandler_v [WEAK] - EXPORT SWI1_IRQHandler_v [WEAK] - EXPORT SWI2_IRQHandler_v [WEAK] - EXPORT SWI3_IRQHandler_v [WEAK] - EXPORT SWI4_IRQHandler [WEAK] - EXPORT SWI5_IRQHandler [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UART0_IRQHandler_v -SPI0_TWI0_IRQHandler_v -SPI1_TWI1_IRQHandler_v -GPIOTE_IRQHandler_v -ADC_IRQHandler_v -TIMER0_IRQHandler -TIMER1_IRQHandler_v -TIMER2_IRQHandler_v -RTC0_IRQHandler -TEMP_IRQHandler -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler_v -RTC1_IRQHandler_v -QDEC_IRQHandler_v -LPCOMP_IRQHandler_v -SWI0_IRQHandler_v -SWI1_IRQHandler_v -SWI2_IRQHandler_v -SWI3_IRQHandler_v -SWI4_IRQHandler -SWI5_IRQHandler - - B . - ENDP - ALIGN - END - diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct deleted file mode 100644 index c3ec0e86ff..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct +++ /dev/null @@ -1,33 +0,0 @@ -#! armcc -E - -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00008000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x1B000 0x0025000 { - ER_IROM1 0x1B000 0x0025000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section - *(*noinit) - } - RW_IRAM1 0x20002FB8 0x00005048 { - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20002FB8+0x00005048 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S deleted file mode 100644 index 0aa3da6bb4..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S +++ /dev/null @@ -1,198 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2013 Nordic Semiconductor. -;Licensed under the Apache License, Version 2.0 (the "License"); -;you may not use this file except in compliance with the License. -;You may obtain a copy of the License at -;http://www.apache.org/licenses/LICENSE-2.0 -;Unless required by applicable law or agreed to in writing, software -;distributed under the License is distributed on an "AS IS" BASIS, -;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;See the License for the specific language governing permissions and -;limitations under the License. - -; Description message - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler_v ;UART0 - DCD SPI0_TWI0_IRQHandler_v ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler_v ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler_v ;GPIOTE - DCD ADC_IRQHandler_v ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler_v ;TIMER1 - DCD TIMER2_IRQHandler_v ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler_v ;WDT - DCD RTC1_IRQHandler_v ;RTC1 - DCD QDEC_IRQHandler_v ;QDEC - DCD LPCOMP_IRQHandler_v ;LPCOMP_COMP - DCD SWI0_IRQHandler_v ;SWI0 - DCD SWI1_IRQHandler_v ;SWI1 - DCD SWI2_IRQHandler_v ;SWI2 - DCD SWI3_IRQHandler_v ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMONB_ADDRESS EQU 0x40000554 ; NRF_POWER->RAMONB address -NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU 0x3 ; All RAM blocks on in onmode bit mask - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT nrf_reloc_vector_table - - MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk - - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - ORRS R2, R2, R1 - STR R2, [R0] - - LDR R0, =NRF_POWER_RAMONB_ADDRESS - LDR R2, [R0] - ORRS R2, R2, R1 - STR R2, [R0] - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UART0_IRQHandler_v [WEAK] - EXPORT SPI0_TWI0_IRQHandler_v [WEAK] - EXPORT SPI1_TWI1_IRQHandler_v [WEAK] - EXPORT GPIOTE_IRQHandler_v [WEAK] - EXPORT ADC_IRQHandler_v [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler_v [WEAK] - EXPORT TIMER2_IRQHandler_v [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler_v [WEAK] - EXPORT RTC1_IRQHandler_v [WEAK] - EXPORT QDEC_IRQHandler_v [WEAK] - EXPORT LPCOMP_IRQHandler_v [WEAK] - EXPORT SWI0_IRQHandler_v [WEAK] - EXPORT SWI1_IRQHandler_v [WEAK] - EXPORT SWI2_IRQHandler_v [WEAK] - EXPORT SWI3_IRQHandler_v [WEAK] - EXPORT SWI4_IRQHandler [WEAK] - EXPORT SWI5_IRQHandler [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UART0_IRQHandler_v -SPI0_TWI0_IRQHandler_v -SPI1_TWI1_IRQHandler_v -GPIOTE_IRQHandler_v -ADC_IRQHandler_v -TIMER0_IRQHandler -TIMER1_IRQHandler_v -TIMER2_IRQHandler_v -RTC0_IRQHandler -TEMP_IRQHandler -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler_v -RTC1_IRQHandler_v -QDEC_IRQHandler_v -LPCOMP_IRQHandler_v -SWI0_IRQHandler_v -SWI1_IRQHandler_v -SWI2_IRQHandler_v -SWI3_IRQHandler_v -SWI4_IRQHandler -SWI5_IRQHandler - - B . - ENDP - ALIGN - END - diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct deleted file mode 100644 index 8da3f804c2..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct +++ /dev/null @@ -1,33 +0,0 @@ -#! armcc -E - -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00004000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x18000 0x0028000 { - ER_IROM1 0x18000 0x0028000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM0 0x20002000 UNINIT 0x000000c0 { ;no init section - *(*noinit) - } - RW_IRAM1 0x200020C0 0x00001F40 { - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x200020C0+0x00001F40 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct deleted file mode 100644 index 8311c162a1..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct +++ /dev/null @@ -1,33 +0,0 @@ -#! armcc -E - -;WITHOUT SOFTDEVICE: -;LR_IROM1 0x00000000 0x00040000 { -; ER_IROM1 0x00000000 0x00040000 { -; *.o (RESET, +First) -; *(InRoot$$Sections) -; .ANY (+RO) -; } -; RW_IRAM1 0x20000000 0x00004000 { -; .ANY (+RW +ZI) -; } -;} -; -;WITH SOFTDEVICE: - -#define Stack_Size MBED_BOOT_STACK_SIZE - -LR_IROM1 0x0001B000 0x0025000 { - ER_IROM1 0x0001B000 0x0025000 { - *.o (RESET, +First) - *(InRoot$$Sections) - .ANY (+RO) - } - RW_IRAM0 0x20002ef8 UNINIT 0x000000c0 { ;no init section - *(*noinit) - } - RW_IRAM1 0x20002FB8 0x00001048 { - .ANY (+RW +ZI) - } - ARM_LIB_STACK 0x20002FB8+0x00001048 EMPTY -Stack_Size { ; Stack region growing down - } -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld deleted file mode 100644 index 6d4f2b6f6b..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld +++ /dev/null @@ -1,171 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x800 -#endif - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000 - RAM (rwx) : ORIGIN = 0x20002ef8, LENGTH = 0x5108 -} - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__start_fs_data = .); - KEEP(*(.fs_data)) - PROVIDE(__stop_fs_data = .); - - *(.jcr) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - __edata = .; - - .noinit : - { - PROVIDE(__start_noinit = .); - KEEP(*(.noinit)) - PROVIDE(__stop_noinit = .); - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - __HeapBase = .; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld deleted file mode 100644 index 98c31c677f..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld +++ /dev/null @@ -1,157 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x800 -#endif - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000 - RAM (rwx) : ORIGIN = 0x20002000, LENGTH = 0x2000 -} - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - *(.jcr) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - __HeapBase = .; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld deleted file mode 100644 index e6f2352d54..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld +++ /dev/null @@ -1,169 +0,0 @@ -/* Linker script to configure memory regions. */ - -#if !defined(MBED_BOOT_STACK_SIZE) - #define MBED_BOOT_STACK_SIZE 0x800 -#endif - -MEMORY -{ - FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000 - RAM (rwx) : ORIGIN = 0x20002ef8, LENGTH = 0x1108 -} - -OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm") - -/* Linker script to place sections and symbol values. Should be used together - * with other linker script that defines memory regions FLASH and RAM. - * It references following symbols, which must be defined in code: - * Reset_Handler : Entry of reset handler - * - * It defines following symbols, which code can use without definition: - * __exidx_start - * __exidx_end - * __etext - * __data_start__ - * __preinit_array_start - * __preinit_array_end - * __init_array_start - * __init_array_end - * __fini_array_start - * __fini_array_end - * __data_end__ - * __bss_start__ - * __bss_end__ - * __end__ - * end - * __HeapLimit - * __StackLimit - * __StackTop - * __stack - */ -ENTRY(Reset_Handler) - -SECTIONS -{ - .text : - { - KEEP(*(.Vectors)) - *(.text*) - - KEEP(*(.init)) - KEEP(*(.fini)) - - /* .ctors */ - *crtbegin.o(.ctors) - *crtbegin?.o(.ctors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) - *(SORT(.ctors.*)) - *(.ctors) - - /* .dtors */ - *crtbegin.o(.dtors) - *crtbegin?.o(.dtors) - *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) - *(SORT(.dtors.*)) - *(.dtors) - - *(.rodata*) - - KEEP(*(.eh_frame*)) - } > FLASH - - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > FLASH - - __exidx_start = .; - .ARM.exidx : - { - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - } > FLASH - __exidx_end = .; - - __etext = .; - - .data : AT (__etext) - { - __data_start__ = .; - *(vtable) - *(.data*) - - . = ALIGN(8); - /* preinit data */ - PROVIDE_HIDDEN (__preinit_array_start = .); - KEEP(*(.preinit_array)) - PROVIDE_HIDDEN (__preinit_array_end = .); - - . = ALIGN(8); - /* init data */ - PROVIDE_HIDDEN (__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE_HIDDEN (__init_array_end = .); - - - . = ALIGN(8); - /* finit data */ - PROVIDE_HIDDEN (__fini_array_start = .); - KEEP(*(SORT(.fini_array.*))) - KEEP(*(.fini_array)) - PROVIDE_HIDDEN (__fini_array_end = .); - - . = ALIGN(8); - PROVIDE(__start_fs_data = .); - KEEP(*(.fs_data)) - PROVIDE(__stop_fs_data = .); - - *(.jcr) - . = ALIGN(8); - /* All data end */ - __data_end__ = .; - - } > RAM - - .noinit : - { - PROVIDE(__start_noinit = .); - KEEP(*(.noinit)) - PROVIDE(__stop_noinit = .); - } > RAM - - .bss : - { - . = ALIGN(8); - __bss_start__ = .; - *(.bss*) - *(COMMON) - . = ALIGN(8); - __bss_end__ = .; - } > RAM - - .heap (NOLOAD): - { - __end__ = .; - end = __end__; - __HeapBase = .; - *(.heap*) - . = ORIGIN(RAM) + LENGTH(RAM) - MBED_BOOT_STACK_SIZE; - __HeapLimit = .; - } > RAM - - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - *(.stack*) - } > RAM - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(RAM) + LENGTH(RAM); - __StackLimit = __StackTop - MBED_BOOT_STACK_SIZE; - PROVIDE(__stack = __StackTop); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack") -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S deleted file mode 100644 index baaec11d4c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_GCC_ARM/startup_NRF51822.S +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/* -NOTE: Template files (including this one) are application specific and therefore -expected to be copied into the application project folder prior to its use! -*/ - - .syntax unified - .arch armv6-m - - .section .stack - .align 3 - .globl __StackTop - .globl __StackLimit -__StackLimit: - .size __StackLimit, . - __StackLimit -__StackTop: - .size __StackTop, . - __StackTop - - .section .heap - .align 3 - .globl __HeapBase - .globl __HeapLimit - - .section .Vectors - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long POWER_CLOCK_IRQHandler /*POWER_CLOCK */ - .long RADIO_IRQHandler /*RADIO */ - .long UART0_IRQHandler_v /*UART0 */ - .long SPI0_TWI0_IRQHandler_v /*SPI0_TWI0 */ - .long SPI1_TWI1_IRQHandler_v /*SPI1_TWI1 */ - .long 0 /*Reserved */ - .long GPIOTE_IRQHandler_v /*GPIOTE */ - .long ADC_IRQHandler_v /*ADC */ - .long TIMER0_IRQHandler /*TIMER0 */ - .long TIMER1_IRQHandler_v /*TIMER1 */ - .long TIMER2_IRQHandler_v /*TIMER2 */ - .long RTC0_IRQHandler /*RTC0 */ - .long TEMP_IRQHandler /*TEMP */ - .long RNG_IRQHandler /*RNG */ - .long ECB_IRQHandler /*ECB */ - .long CCM_AAR_IRQHandler /*CCM_AAR */ - .long WDT_IRQHandler_v /*WDT */ - .long RTC1_IRQHandler_v /*RTC1 */ - .long QDEC_IRQHandler_v /*QDEC */ - .long LPCOMP_IRQHandler_v /*LPCOMP */ - .long SWI0_IRQHandler_v /*SWI0 */ - .long SWI1_IRQHandler_v /*SWI1 */ - .long SWI2_IRQHandler_v /*SWI2 */ - .long SWI3_IRQHandler_v /*SWI3 */ - .long SWI4_IRQHandler /*SWI4 */ - .long SWI5_IRQHandler /*SWI5 */ - - - .size __Vectors, . - __Vectors - -/* Reset Handler */ - - .equ NRF_POWER_RAMON_ADDRESS, 0x40000524 - .equ NRF_POWER_RAMONB_ADDRESS, 0x40000554 - .equ NRF_POWER_RAMONx_RAMxON_ONMODE_Msk, 0x3 - - .text - .thumb - .thumb_func - .align 1 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - .fnstart - - MOVS R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - ORRS R2, R1 - STR R2, [R0] - - LDR R0, =NRF_POWER_RAMONB_ADDRESS - LDR R2, [R0] - ORRS R2, R1 - STR R2, [R0] - -/* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .LC0 - -.LC1: - subs r3, 4 - ldr r0, [r1,r3] - str r0, [r2,r3] - bgt .LC1 -.LC0: - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =_start - BX R0 - - .pool - .cantunwind - .fnend - .size Reset_Handler,.-Reset_Handler - - .section ".text" - - -/* Dummy Exception Handlers (infinite loops which can be modified) */ - - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - B . - .size NMI_Handler, . - NMI_Handler - - - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - B . - .size HardFault_Handler, . - HardFault_Handler - - - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - B . - .size SVC_Handler, . - SVC_Handler - - - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - B . - .size PendSV_Handler, . - PendSV_Handler - - - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - B . - .size SysTick_Handler, . - SysTick_Handler - - -/* IRQ Handlers */ - - .globl Default_Handler - .type Default_Handler, %function -Default_Handler: - B . - .size Default_Handler, . - Default_Handler - - .macro IRQ handler - .weak \handler - .set \handler, Default_Handler - .endm - - IRQ POWER_CLOCK_IRQHandler /* restricted */ - IRQ RADIO_IRQHandler /* blocked */ - IRQ UART0_IRQHandler_v - IRQ SPI0_TWI0_IRQHandler_v - IRQ SPI1_TWI1_IRQHandler_v - IRQ GPIOTE_IRQHandler_v - IRQ ADC_IRQHandler_v - IRQ TIMER0_IRQHandler /* blocked */ - IRQ TIMER1_IRQHandler_v - IRQ TIMER2_IRQHandler_v - IRQ RTC0_IRQHandler /* blocked */ - IRQ TEMP_IRQHandler /* restricted */ - IRQ RNG_IRQHandler /* restricted */ - IRQ ECB_IRQHandler /* restricted */ - IRQ CCM_AAR_IRQHandler /* blocked */ - IRQ WDT_IRQHandler_v - IRQ RTC1_IRQHandler_v - IRQ QDEC_IRQHandler_v - IRQ LPCOMP_IRQHandler_v - IRQ SWI0_IRQHandler_v - IRQ SWI1_IRQHandler_v /* restricted for Radio Notification */ - IRQ SWI2_IRQHandler_v /* blocked for SoftDevice Event */ - IRQ SWI3_IRQHandler_v - IRQ SWI4_IRQHandler /* blocked */ - IRQ SWI5_IRQHandler /* blocked */ - - - .end diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf deleted file mode 100644 index 4d2fe9d568..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf +++ /dev/null @@ -1,48 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -define symbol __ICFEDIT_intvec_start__ = 0x0001b000; -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0001b0c0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8; -define symbol __ICFEDIT_region_RAM_end__ = 0x20003FFF; -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x900; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __code_start_soft_device__ = 0x0; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, - block CSTACK }; - -/*This is used for mbed applications build inside the Embedded workbench -Applications build with the python scritps use a hex merge so need to merge it -inside the linker. The linker can only use binary files so the hex merge is not possible -through the linker. That is why a binary is used instead of a hex image for the embedded project. -*/ -if(isdefinedsymbol(SOFT_DEVICE_BIN)) -{ - place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf deleted file mode 100644 index 22bc35e2de..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf +++ /dev/null @@ -1,48 +0,0 @@ -/*###ICF### Section handled by ICF editor, don't touch! ****/ -/*-Editor annotation file-*/ -/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */ -/*-Specials-*/ -if (!isdefinedsymbol(MBED_BOOT_STACK_SIZE)) { - define symbol MBED_BOOT_STACK_SIZE = 0x400; -} -define symbol __ICFEDIT_intvec_start__ = 0x0001b000; -/*-Memory Regions-*/ -define symbol __ICFEDIT_region_ROM_start__ = 0x0001b0c0; -define symbol __ICFEDIT_region_ROM_end__ = 0x0003FFFF; -define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8; -define symbol __ICFEDIT_region_RAM_end__ = 0x20007FFF; -export symbol __ICFEDIT_region_RAM_start__; -export symbol __ICFEDIT_region_RAM_end__; -/*-Sizes-*/ -define symbol __ICFEDIT_size_cstack__ = MBED_BOOT_STACK_SIZE; -define symbol __ICFEDIT_size_heap__ = 0x1800; -/**** End of ICF editor section. ###ICF###*/ - -define symbol __code_start_soft_device__ = 0x0; - -define memory mem with size = 4G; -define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__]; -define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__]; - -define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; -define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; - -initialize by copy { readwrite }; -do not initialize { section .noinit }; - -keep { section .intvec }; -place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; -place in ROM_region { readonly }; -place in RAM_region { readwrite, - block HEAP, - block CSTACK }; - -/*This is used for mbed applications build inside the Embedded workbench -Applications build with the python scritps use a hex merge so need to merge it -inside the linker. The linker can only use binary files so the hex merge is not possible -through the linker. That is why a binary is used instead of a hex image for the embedded project. -*/ -if(isdefinedsymbol(SOFT_DEVICE_BIN)) -{ - place at address mem:__code_start_soft_device__ { section .noinit_softdevice }; -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S deleted file mode 100644 index 4021495366..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/TOOLCHAIN_IAR/startup_NRF51822_IAR.S +++ /dev/null @@ -1,234 +0,0 @@ -;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved. -;; The information contained herein is confidential property of Nordic -;; Semiconductor ASA.Terms and conditions of usage are described in detail -;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT. -;; Licensees are granted free, non-transferable use of the information. NO -;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from -;; the file. - -;; Description message - - MODULE ?cstartup - - ;; Stack size default : 1024 - ;; Heap size default : 2048 - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN nrf_reloc_vector_table - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -;__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler ;POWER_CLOCK - DCD RADIO_IRQHandler ;RADIO - DCD UART0_IRQHandler_v ;UART0 - DCD SPI0_TWI0_IRQHandler_v ;SPI0_TWI0 - DCD SPI1_TWI1_IRQHandler_v ;SPI1_TWI1 - DCD 0 ;Reserved - DCD GPIOTE_IRQHandler_v ;GPIOTE - DCD ADC_IRQHandler_v ;ADC - DCD TIMER0_IRQHandler ;TIMER0 - DCD TIMER1_IRQHandler_v ;TIMER1 - DCD TIMER2_IRQHandler_v ;TIMER2 - DCD RTC0_IRQHandler ;RTC0 - DCD TEMP_IRQHandler ;TEMP - DCD RNG_IRQHandler ;RNG - DCD ECB_IRQHandler ;ECB - DCD CCM_AAR_IRQHandler ;CCM_AAR - DCD WDT_IRQHandler_v ;WDT - DCD RTC1_IRQHandler_v ;RTC1 - DCD QDEC_IRQHandler_v ;QDEC - DCD LPCOMP_IRQHandler_v ;LPCOMP_COMP - DCD SWI0_IRQHandler ;SWI0 - DCD SWI1_IRQHandler_v ;SWI1 - DCD SWI2_IRQHandler_v ;SWI2 - DCD SWI3_IRQHandler_v ;SWI3 - DCD SWI4_IRQHandler ;SWI4 - DCD SWI5_IRQHandler ;SWI5 - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors -NRF_POWER_RAMON_ADDRESS EQU 0x40000524 ; NRF_POWER->RAMON address -NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU 0xF ; All RAM blocks on in onmode bit mask - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =NRF_POWER_RAMON_ADDRESS - LDR R2, [R0] - MOVS R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk - ORRS R2, R2, R1 - STR R2, [R0] - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RADIO_IRQHandler - B . - PUBWEAK UART0_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_IRQHandler_v - B . - PUBWEAK SPI0_TWI0_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -SPI0_TWI0_IRQHandler_v - B . - PUBWEAK SPI1_TWI1_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_TWI1_IRQHandler_v - B . - PUBWEAK GPIOTE_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -GPIOTE_IRQHandler_v - B . - PUBWEAK ADC_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler_v - B . - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B . - PUBWEAK TIMER1_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler_v - B . - PUBWEAK TIMER2_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler_v - B . - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC0_IRQHandler - B . - PUBWEAK TEMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TEMP_IRQHandler - B . - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B . - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ECB_IRQHandler - B . - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CCM_AAR_IRQHandler - B . - PUBWEAK WDT_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -WDT_IRQHandler_v - B . - PUBWEAK RTC1_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -RTC1_IRQHandler_v - B . - PUBWEAK QDEC_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -QDEC_IRQHandler_v - B . - PUBWEAK LPCOMP_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -LPCOMP_IRQHandler_v - B . - PUBWEAK SWI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI0_IRQHandler - B . - PUBWEAK SWI1_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -SWI1_IRQHandler_v - B . - PUBWEAK SWI2_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -SWI2_IRQHandler_v - B . - PUBWEAK SWI3_IRQHandler_v - SECTION .text:CODE:REORDER:NOROOT(1) -SWI3_IRQHandler_v - B . - PUBWEAK SWI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI4_IRQHandler - B . - PUBWEAK SWI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SWI5_IRQHandler - B . - - - END \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis.h deleted file mode 100644 index b73fdadde8..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis.h +++ /dev/null @@ -1,13 +0,0 @@ -/* mbed Microcontroller Library - CMSIS - * Copyright (C) 2009-2011 ARM Limited. All rights reserved. - * - * A generic CMSIS include header, pulling in LPC407x_8x specifics - */ - -#ifndef MBED_CMSIS_H -#define MBED_CMSIS_H - -#include "nrf.h" -#include "cmsis_nvic.h" - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c deleted file mode 100644 index cdaa2042ee..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.c +++ /dev/null @@ -1,43 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ -#include "cmsis_nvic.h" - -extern uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS]; - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) -{ - nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET] = vector; -} - -uint32_t NVIC_GetVector(IRQn_Type IRQn) -{ - return nrf_dispatch_vector[IRQn + NVIC_USER_IRQ_OFFSET]; -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.h deleted file mode 100644 index ab365b2a79..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/cmsis_nvic.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * CMSIS-style functionality to support dynamic vectors - ******************************************************************************* - * Copyright (c) 2011 ARM Limited. All rights reserved. - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of ARM Limited nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - ******************************************************************************* - */ - -#ifndef MBED_CMSIS_NVIC_H -#define MBED_CMSIS_NVIC_H - -#define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals -#define NVIC_USER_IRQ_OFFSET 16 - -#include "nrf51.h" -#include "cmsis.h" - - -#ifdef __cplusplus -extern "C" { -#endif - -void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); -uint32_t NVIC_GetVector(IRQn_Type IRQn); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.c deleted file mode 100644 index 04f95209c8..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.c +++ /dev/null @@ -1,192 +0,0 @@ -/* - * Copyright (c) 2015 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/* NOTE: Template files (including this one) are application specific and therefore expected to - be copied into the application project folder prior to its use! */ - -#include -#include -#include "nrf.h" -#include "system_nrf51.h" -#include "nrf5x_lf_clk_helper.h" - -/*lint ++flb "Enter library region" */ - - -#define __SYSTEM_CLOCK (16000000UL) /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */ - -static bool is_manual_peripheral_setup_needed(void); -static bool is_disabled_in_debug_needed(void); -static bool is_peripheral_domain_setup_needed(void); - - -#if defined ( __CC_ARM ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#elif defined ( __ICCARM__ ) - __root uint32_t SystemCoreClock = __SYSTEM_CLOCK; -#elif defined ( __GNUC__ ) - uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK; -#endif - -void SystemCoreClockUpdate(void) -{ - SystemCoreClock = __SYSTEM_CLOCK; -} - -void SystemInit(void) -{ -#if defined(TARGET_NRF_32MHZ_XTAL) - /* For 32MHz HFCLK XTAL such as Taiyo Yuden - Physically, tiny footprint XTAL oscillate higher freq. To make BLE modules smaller, some modules - are using 32MHz XTAL. - This code wriging the value 0xFFFFFF00 to the UICR (User Information Configuration Register) - at address 0x10001008, to make nRF51 works with 32MHz system clock. This register will be overwritten - by SoftDevice to 0xFFFFFFFF, the default value. Each hex files built with mbed classic online compiler - contain SoftDevice, so that, this code run once just after the hex file will be flashed onto nRF51. - After changing the value, nRF51 need to reboot. */ - if (*(uint32_t *)0x10001008 == 0xFFFFFFFF) - { - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - *(uint32_t *)0x10001008 = 0xFFFFFF00; - NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos; - while (NRF_NVMC->READY == NVMC_READY_READY_Busy){} - NVIC_SystemReset(); - while (true){} - } -#endif - - /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register. - It can also be done in the application main() function. */ - - /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required - to enable the use of peripherals" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. The side effect of executing these instructions in the devices - that do not need it is that the new peripherals in the second generation devices (LPCOMP for - example) will not be available. */ - if (is_manual_peripheral_setup_needed()) - { - *(uint32_t volatile *)0x40000504 = 0xC007FFDF; - *(uint32_t volatile *)0x40006C18 = 0x00008000; - } - - /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG - register is incorrect" found at Product Anomaly document for your device found at - https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */ - if (is_disabled_in_debug_needed()) - { - NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos; - } - - /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices, - as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document - for your device found at https://www.nordicsemi.com/. */ - if (is_peripheral_domain_setup_needed()){ - if (*(uint32_t volatile *)0x4006EC00 != 1){ - *(uint32_t volatile *)0x4006EC00 = 0x9375; - while (*(uint32_t volatile *)0x4006EC00 != 1){ - } - } - *(uint32_t volatile *)0x4006EC14 = 0xC0; - } - - // Start the LF oscilator according to the mbed configuration (over the nrf5x_lf_clk_helper.h file) - NRF_CLOCK->LFCLKSRC = (CLOCK_LFCLKSRC_SRC_TO_USE << CLOCK_LFCLKSRC_SRC_Pos); - NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; - NRF_CLOCK->TASKS_LFCLKSTART = 1; - - // Wait for the external oscillator to start up. - while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) { - // Do nothing. - } -} - - -static bool is_manual_peripheral_setup_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} - -static bool is_disabled_in_debug_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} - -static bool is_peripheral_domain_setup_needed(void) -{ - if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0)) - { - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0)) - { - return true; - } - } - - return false; -} - -/*lint --flb "Leave library region" */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.h deleted file mode 100644 index 72398da0d7..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/device/system_nrf51.h +++ /dev/null @@ -1,78 +0,0 @@ -/* - * Copyright (c) 2015 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef SYSTEM_NRF51_H -#define SYSTEM_NRF51_H - -#ifdef __cplusplus -extern "C" { -#endif - -#include - - -extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ - -/** - * Initialize the system - * - * @param none - * @return none - * - * @brief Setup the microcontroller system. - * Initialize the System and update the SystemCoreClock variable. - */ -extern void SystemInit (void); - -/** - * Update SystemCoreClock variable - * - * @param none - * @return none - * - * @brief Updates the SystemCoreClock with current core Clock - * retrieved from cpu registers. - */ -extern void SystemCoreClockUpdate (void); - -#ifdef __cplusplus -} -#endif - -#endif /* SYSTEM_NRF51_H */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c deleted file mode 100644 index 75feeb4a89..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c +++ /dev/null @@ -1,299 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "mbed_assert.h" -#include "mbed_error.h" -#include "pwmout_api.h" -#include "cmsis.h" -#include "pinmap.h" - -#if DEVICE_PWMOUT - -#include "nrf.h" -#include "nrf_drv_timer.h" -#include "app_pwm.h" - -#define PWM_INSTANCE_COUNT 2 -#define PWM_CHANNELS_PER_INSTANCE 2 -#define PWM_DEFAULT_PERIOD_US 20000 -#define PWM_PERIOD_MIN 3 - -typedef struct -{ - const app_pwm_t * const instance; - NRF_TIMER_Type * const timer_reg; - uint8_t channels_allocated; - uint32_t pins[PWM_CHANNELS_PER_INSTANCE]; - uint16_t period_us; - uint16_t duty_ticks[PWM_CHANNELS_PER_INSTANCE]; -} pwm_t; - -// Pinmap used for testing only -static const PinMap PinMap_PWM_testing[] = { - {p0, 0, 0}, - {p1, 0, 0}, - {p2, 0, 0}, - {p3, 0, 0}, - {p4, 0, 0}, - {p5, 0, 0}, - {p6, 0, 0}, - {p7, 0, 0}, - {p8, 0, 0}, - {p9, 0, 0}, - {p10, 0, 0}, - {p11, 0, 0}, - {p12, 0, 0}, - {p13, 0, 0}, - {p14, 0, 0}, - {p15, 0, 0}, - {p16, 0, 0}, - {p17, 0, 0}, - {p18, 0, 0}, - {p19, 0, 0}, - {p20, 0, 0}, - {p21, 0, 0}, - {p22, 0, 0}, - {p23, 0, 0}, - {p24, 0, 0}, - {p25, 0, 0}, - - {p28, 0, 0}, - {p29, 0, 0}, - {p30, 0, 0}, - - {NC, NC, 0} -}; - -APP_PWM_INSTANCE(m_pwm_instance_0, 1); //PWM0: Timer 1 -APP_PWM_INSTANCE(m_pwm_instance_1, 2); //PWM1: Timer 2 - - -static pwm_t m_pwm[] = { - {.instance = &m_pwm_instance_0, .timer_reg = NRF_TIMER1, .channels_allocated = 0}, - {.instance = &m_pwm_instance_1, .timer_reg = NRF_TIMER2, .channels_allocated = 0} - }; - -static inline void pwm_ticks_set(pwm_t* pwm, uint8_t channel, uint16_t ticks) -{ - pwm->duty_ticks[channel] = ticks; - while (app_pwm_channel_duty_ticks_set(pwm->instance, channel, ticks) != NRF_SUCCESS); -} - -static void pwm_reinit(pwm_t * pwm) -{ - app_pwm_uninit(pwm->instance); - app_pwm_config_t pwm_cfg = APP_PWM_DEFAULT_CONFIG_2CH(pwm->period_us, - pwm->pins[0], - pwm->pins[1]); - app_pwm_init(pwm->instance, &pwm_cfg, NULL); - app_pwm_enable(pwm->instance); - - for (uint8_t channel = 0; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) { - if ((pwm->channels_allocated & (1 << channel)) && (pwm->pins[channel] != APP_PWM_NOPIN)) { - app_pwm_channel_duty_ticks_set(pwm->instance, channel, pwm->duty_ticks[channel]); - } - } -} - -void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c - -void TIMER1_IRQHandler(void); -void TIMER2_IRQHandler(void); - -static const peripheral_handler_desc_t timer_handlers[] = -{ - { - TIMER1_IRQn, - (uint32_t)TIMER1_IRQHandler - }, - { - TIMER2_IRQn, - (uint32_t)TIMER2_IRQHandler - } -}; - -void pwmout_init(pwmout_t *obj, PinName pin) -{ - if (pin == NC) { - error("PwmOut init failed. Invalid pin name."); - } - - // Check if pin is already initialized and find the next free channel. - uint8_t free_instance = 0xFF; - uint8_t free_channel = 0xFF; - - for (uint8_t inst = 0; inst < PWM_INSTANCE_COUNT; ++inst) { - if (m_pwm[inst].channels_allocated) { - for (uint8_t channel = 0; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) { - if (m_pwm[inst].channels_allocated & (1 << channel)) { - if (m_pwm[inst].pins[channel] == (uint32_t)pin) { - error("PwmOut init failed. Pin is already in use."); - return; - } - } - else { - if (free_instance == 0xFF) { - free_instance = inst; - free_channel = channel; - } - } - } - } - else { - if (free_instance == 0xFF) { - free_instance = inst; - free_channel = 0; - } - } - } - - if (free_instance == 0xFF) - { - error("PwmOut init failed. All available PWM channels are in use."); - return; - } - - // Init / reinit PWM instance. - m_pwm[free_instance].pins[free_channel] = (uint32_t) pin; - m_pwm[free_instance].duty_ticks[free_channel] = 0; - if (!m_pwm[free_instance].channels_allocated) { - - NVIC_SetVector(GPIOTE_IRQn, (uint32_t) GPIOTE_IRQHandler); - - NVIC_SetVector(timer_handlers[free_instance].IRQn, timer_handlers[free_instance].vector); - - m_pwm[free_instance].period_us = PWM_DEFAULT_PERIOD_US; - for (uint8_t channel = 1; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) { - m_pwm[free_instance].pins[channel] = APP_PWM_NOPIN; - m_pwm[free_instance].duty_ticks[channel] = 0; - } - app_pwm_config_t pwm_cfg = APP_PWM_DEFAULT_CONFIG_1CH(PWM_DEFAULT_PERIOD_US, pin); - app_pwm_init(m_pwm[free_instance].instance, &pwm_cfg, NULL); - app_pwm_enable(m_pwm[free_instance].instance); - } - else { - pwm_reinit(&m_pwm[free_instance]); - } - m_pwm[free_instance].channels_allocated |= (1 << free_channel); - - obj->pin = pin; - obj->pwm_struct = (void *) &m_pwm[free_instance]; - obj->pwm_channel = free_channel; -} - -void pwmout_free(pwmout_t *obj) -{ - MBED_ASSERT(obj->pwm_name != (PWMName)NC); - MBED_ASSERT(obj->pwm_channel < PWM_CHANNELS_PER_INSTANCE); - - pwm_t * pwm = (pwm_t *) obj->pwm_struct; - pwm->channels_allocated &= ~(1 << obj->pwm_channel); - pwm->pins[obj->pwm_channel] = APP_PWM_NOPIN; - pwm->duty_ticks[obj->pwm_channel] = 0; - - app_pwm_uninit(pwm->instance); - if (pwm->channels_allocated) { - pwm_reinit(pwm); - } - - obj->pwm_struct = NULL; -} - -void pwmout_write(pwmout_t *obj, float value) -{ - pwm_t * pwm = (pwm_t *) obj->pwm_struct; - if (value > 1.0f) { - value = 1.0f; - } - - app_pwm_channel_duty_set(pwm->instance, obj->pwm_channel, (app_pwm_duty_t)(value * 100.0f) ); -} - -float pwmout_read(pwmout_t *obj) -{ - pwm_t * pwm = (pwm_t *) obj->pwm_struct; - MBED_ASSERT(pwm != NULL); - return ((float)pwm->duty_ticks[obj->pwm_channel] / (float)app_pwm_cycle_ticks_get(pwm->instance)); -} - -void pwmout_period(pwmout_t *obj, float seconds) -{ - pwmout_period_us(obj, seconds * 1000000.0f); -} - -void pwmout_period_ms(pwmout_t *obj, int ms) -{ - pwmout_period_us(obj, ms * 1000); -} - -void pwmout_period_us(pwmout_t *obj, int us) -{ - pwm_t * pwm = (pwm_t *) obj->pwm_struct; - MBED_ASSERT(pwm != NULL); - if (us < PWM_PERIOD_MIN) { - us = PWM_PERIOD_MIN; - } - pwm->period_us = (uint32_t)us; - pwm_reinit(pwm); -} - -void pwmout_pulsewidth(pwmout_t *obj, float seconds) -{ - pwmout_pulsewidth_us(obj, seconds * 1000000.0f); -} - -void pwmout_pulsewidth_ms(pwmout_t *obj, int ms) -{ - pwmout_pulsewidth_us(obj, ms * 1000); -} - -void pwmout_pulsewidth_us(pwmout_t *obj, int us) -{ - pwm_t * pwm = (pwm_t *) obj->pwm_struct; - MBED_ASSERT(pwm); - - uint16_t ticks = nrf_timer_us_to_ticks((uint32_t)us, nrf_timer_frequency_get(pwm->timer_reg)); - pwm_ticks_set(pwm, obj->pwm_channel, ticks); -} - -const PinMap *pwmout_pinmap() -{ - return PinMap_PWM_testing; -} - -#endif // DEVICE_PWMOUT diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c deleted file mode 100644 index 0312297e12..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c +++ /dev/null @@ -1,281 +0,0 @@ -/* - * Copyright (c) 2015 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#include "nrf_drv_adc.h" -#include "nrf_drv_common.h" -#include "nrf_assert.h" -#include "app_util_platform.h" -#include "app_util.h" - -typedef struct -{ - nrf_drv_adc_event_handler_t event_handler; - nrf_drv_adc_channel_t * p_head; - nrf_drv_adc_channel_t * p_current_conv; - nrf_adc_value_t * p_buffer; - uint8_t size; - uint8_t idx; - nrf_drv_state_t state; -} adc_cb_t; - -static adc_cb_t m_cb; -static const nrf_drv_adc_config_t m_default_config = NRF_DRV_ADC_DEFAULT_CONFIG; - -ret_code_t nrf_drv_adc_init(nrf_drv_adc_config_t const * p_config, - nrf_drv_adc_event_handler_t event_handler) -{ - if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) - { - return NRF_ERROR_INVALID_STATE; - } - - nrf_adc_event_clear(NRF_ADC_EVENT_END); - if (event_handler) - { - if (!p_config) - { - p_config = (nrf_drv_adc_config_t *)&m_default_config; - } - nrf_drv_common_irq_enable(ADC_IRQn, p_config->interrupt_priority); - } - m_cb.event_handler = event_handler; - m_cb.state = NRF_DRV_STATE_INITIALIZED; - - return NRF_SUCCESS; -} - -void nrf_drv_adc_uninit(void) -{ - m_cb.p_head = NULL; - nrf_drv_common_irq_disable(ADC_IRQn); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_task_trigger(NRF_ADC_TASK_STOP); - - m_cb.state = NRF_DRV_STATE_UNINITIALIZED; -} - -void nrf_drv_adc_channel_enable(nrf_drv_adc_channel_t * const p_channel) -{ - ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED); - // This assert has been removed as it requires non-existent symbols from linker - //ASSERT(!is_address_from_stack(p_channel)); - - p_channel->p_next = NULL; - if (m_cb.p_head == NULL) - { - m_cb.p_head = p_channel; - } - else - { - nrf_drv_adc_channel_t * p_curr_channel = m_cb.p_head; - while (p_curr_channel->p_next != NULL) - { - ASSERT(p_channel != p_curr_channel); - p_curr_channel = p_curr_channel->p_next; - } - p_curr_channel->p_next = p_channel; - } -} - -void nrf_drv_adc_channel_disable(nrf_drv_adc_channel_t * const p_channel) -{ - ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED); - ASSERT(m_cb.p_head); - - nrf_drv_adc_channel_t * p_curr_channel = m_cb.p_head; - nrf_drv_adc_channel_t * p_prev_channel = NULL; - while(p_curr_channel != p_channel) - { - p_prev_channel = p_curr_channel; - p_curr_channel = p_curr_channel->p_next; - ASSERT(p_curr_channel == NULL); - } - if (p_prev_channel) - { - p_prev_channel->p_next = p_curr_channel->p_next; - } - else - { - m_cb.p_head = p_curr_channel->p_next; - } -} - -void nrf_drv_adc_sample(void) -{ - ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); - ASSERT(!nrf_adc_is_busy()); - nrf_adc_start(); -} - -ret_code_t nrf_drv_adc_sample_convert(nrf_drv_adc_channel_t const * const p_channel, - nrf_adc_value_t * p_value) -{ - ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); - if(m_cb.state == NRF_DRV_STATE_POWERED_ON) - { - return NRF_ERROR_BUSY; - } - else - { - m_cb.state = NRF_DRV_STATE_POWERED_ON; - - nrf_adc_config_set(p_channel->config.data); - nrf_adc_enable(); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_start(); - if (p_value) - { - while(!nrf_adc_event_check(NRF_ADC_EVENT_END)) {} - nrf_adc_event_clear(NRF_ADC_EVENT_END); - *p_value = (nrf_adc_value_t)nrf_adc_result_get(); - nrf_adc_disable(); - - m_cb.state = NRF_DRV_STATE_INITIALIZED; - } - else - { - ASSERT(m_cb.event_handler); - m_cb.p_buffer = NULL; - nrf_adc_int_enable(NRF_ADC_INT_END_MASK); - } - return NRF_SUCCESS; - } -} - -static bool adc_sample_process() -{ - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_disable(); - m_cb.p_buffer[m_cb.idx] = (nrf_adc_value_t)nrf_adc_result_get(); - m_cb.idx++; - if (m_cb.idx < m_cb.size) - { - bool task_trigger = false; - if (m_cb.p_current_conv->p_next == NULL) - { - m_cb.p_current_conv = m_cb.p_head; - } - else - { - m_cb.p_current_conv = m_cb.p_current_conv->p_next; - task_trigger = true; - } - nrf_adc_config_set(m_cb.p_current_conv->config.data); - nrf_adc_enable(); - if (task_trigger) - { - //nrf_adc_start(); - nrf_adc_task_trigger(NRF_ADC_TASK_START); - } - return false; - } - else - { - return true; - } -} - -ret_code_t nrf_drv_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size) -{ - ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); - if(m_cb.state == NRF_DRV_STATE_POWERED_ON) - { - return NRF_ERROR_BUSY; - } - else - { - m_cb.state = NRF_DRV_STATE_POWERED_ON; - m_cb.p_current_conv = m_cb.p_head; - m_cb.size = size; - m_cb.idx = 0; - m_cb.p_buffer = buffer; - nrf_adc_config_set(m_cb.p_current_conv->config.data); - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_enable(); - if (m_cb.event_handler) - { - nrf_adc_int_enable(NRF_ADC_INT_END_MASK); - } - else - { - while(1) - { - while(!nrf_adc_event_check(NRF_ADC_EVENT_END)){} - - if (adc_sample_process()) - { - m_cb.state = NRF_DRV_STATE_INITIALIZED; - break; - } - } - } - return NRF_SUCCESS; - } -} - -bool nrf_drv_adc_is_busy(void) -{ - ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED); - return (m_cb.state == NRF_DRV_STATE_POWERED_ON) ? true : false; -} - -void ADC_IRQHandler(void) -{ - if (m_cb.p_buffer == NULL) - { - nrf_adc_event_clear(NRF_ADC_EVENT_END); - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_adc_disable(); - nrf_drv_adc_evt_t evt; - evt.type = NRF_DRV_ADC_EVT_SAMPLE; - evt.data.sample.sample = (nrf_adc_value_t)nrf_adc_result_get(); - m_cb.state = NRF_DRV_STATE_INITIALIZED; - m_cb.event_handler(&evt); - } - else if (adc_sample_process()) - { - nrf_adc_int_disable(NRF_ADC_INT_END_MASK); - nrf_drv_adc_evt_t evt; - evt.type = NRF_DRV_ADC_EVT_DONE; - evt.data.done.p_buffer = m_cb.p_buffer; - evt.data.done.size = m_cb.size; - m_cb.state = NRF_DRV_STATE_INITIALIZED; - m_cb.event_handler(&evt); - } -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h deleted file mode 100644 index 832d4d9941..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h +++ /dev/null @@ -1,324 +0,0 @@ -/* - * Copyright (c) 2015 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#include "nrf_adc.h" -#include "nrf_drv_config.h" -#include "sdk_errors.h" -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @addtogroup nrf_adc ADC HAL and driver - * @ingroup nrf_drivers - * @brief Analog-to-digital converter (ADC) APIs. - * @details The ADC HAL provides basic APIs for accessing the registers of the analog-to-digital converter. - * The ADC driver provides APIs on a higher level. - * - * @defgroup nrf_adc_drv ADC driver - * @{ - * @ingroup nrf_adc - * @brief Analog-to-digital converter (ADC) driver. - */ - - -/** - * @brief Driver event types. - */ -typedef enum -{ - NRF_DRV_ADC_EVT_DONE, ///< Event generated when the buffer is filled with samples. - NRF_DRV_ADC_EVT_SAMPLE, ///< Event generated when the requested channel is sampled. -} nrf_drv_adc_evt_type_t; - -typedef int16_t nrf_adc_value_t; - -/** - * @brief Analog-to-digital converter driver DONE event. - */ -typedef struct -{ - nrf_adc_value_t * p_buffer; ///< Pointer to buffer with converted samples. - uint16_t size; ///< Number of samples in the buffer. -} nrf_drv_adc_done_evt_t; - -/** - * @brief Analog-to-digital converter driver SAMPLE event. - */ -typedef struct -{ - nrf_adc_value_t sample; ///< Converted sample. -} nrf_drv_adc_sample_evt_t; - -/** - * @brief Analog-to-digital converter driver event. - */ -typedef struct -{ - nrf_drv_adc_evt_type_t type; ///< Event type. - union - { - nrf_drv_adc_done_evt_t done; ///< Data for DONE event. - nrf_drv_adc_sample_evt_t sample; ///< Data for SAMPLE event. - } data; -} nrf_drv_adc_evt_t; - -/**@brief Macro for initializing the ADC channel with the default configuration. */ -#define NRF_DRV_ADC_DEFAULT_CHANNEL(analog_input) \ - {{{ \ - .resolution = NRF_ADC_CONFIG_RES_10BIT, \ - .input = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE, \ - .reference = NRF_ADC_CONFIG_REF_VBG, \ - .ain = (analog_input) \ - }}, NULL} - -/** - * @brief ADC channel configuration. - * - * @note The bit fields reflect bit fields in the ADC CONFIG register. - */ -typedef struct -{ - uint32_t resolution :2; ///< 8-10 bit resolution. - uint32_t input :3; ///< Input selection and scaling. - uint32_t reference :2; ///< Reference source. - uint32_t reserved :1; ///< Unused bit fields. - uint32_t ain :8; ///< Analog input. - uint32_t external_reference:2; ///< Eternal reference source. -}nrf_drv_adc_channel_config_t; - -// Forward declaration of the nrf_drv_adc_channel_t type. -typedef struct nrf_drv_adc_channel_s nrf_drv_adc_channel_t; - -/** - * @brief ADC channel. - * - * This structure is defined by the user and used by the driver. Therefore, it should - * not be defined on the stack as a local variable. - */ -struct nrf_drv_adc_channel_s -{ - union - { - nrf_drv_adc_channel_config_t config; ///< Channel configuration. - uint32_t data; ///< Raw value. - } config; - nrf_drv_adc_channel_t * p_next; ///< Pointer to the next enabled channel (for internal use). -}; - -/** - * @brief ADC configuration. - */ -typedef struct -{ - uint8_t interrupt_priority; ///< Priority of ADC interrupt. -} nrf_drv_adc_config_t; - -/** @brief ADC default configuration. */ -#define NRF_DRV_ADC_DEFAULT_CONFIG \ -{ \ - .interrupt_priority = ADC_CONFIG_IRQ_PRIORITY \ -} - -/** - * @brief User event handler prototype. - * - * This function is called when the requested number of samples has been processed. - * - * @param p_event Event. - */ -typedef void (*nrf_drv_adc_event_handler_t)(nrf_drv_adc_evt_t const * p_event); - -/** - * @brief Function for initializing the ADC. - * - * If a valid event handler is provided, the driver is initialized in non-blocking mode. - * If event_handler is NULL, the driver works in blocking mode. - * - * @param[in] p_config Driver configuration. - * @param[in] event_handler Event handler provided by the user. - * - * @retval NRF_SUCCESS If initialization was successful. - * @retval NRF_ERROR_INVALID_STATE If the driver is already initialized. - */ -ret_code_t nrf_drv_adc_init(nrf_drv_adc_config_t const * p_config, - nrf_drv_adc_event_handler_t event_handler); - -/** - * @brief Function for uninitializing the ADC. - * - * This function stops all ongoing conversions and disables all channels. - */ -void nrf_drv_adc_uninit(void); - -/** - * @brief Function for enabling an ADC channel. - * - * This function configures and enables the channel. When @ref nrf_drv_adc_buffer_convert is - * called, all channels that have been enabled with this function are sampled. - * - * @note The channel instance variable @p p_channel is used by the driver as an item - * in a list. Therefore, it cannot be an automatic variable, and an assertion fails if it is - * an automatic variable (if asserts are enabled). - */ -void nrf_drv_adc_channel_enable(nrf_drv_adc_channel_t * const p_channel); - -/** - * @brief Function for disabling an ADC channel. - */ -void nrf_drv_adc_channel_disable(nrf_drv_adc_channel_t * const p_channel); - -/** - * @brief Function for starting ADC sampling. - * - * This function triggers single ADC sampling. If more than one channel is enabled, the driver - * emulates scanning and all channels are sampled in the order they were enabled. - */ -void nrf_drv_adc_sample(void); - -/** - * @brief Function for executing a single ADC conversion. - * - * This function selects the desired input and starts a single conversion. If a valid pointer - * is provided for the result, the function blocks until the conversion is completed. Otherwise, the - * function returns when the conversion is started, and the result is provided in an event (driver - * must be initialized in non-blocking mode otherwise an assertion will fail). The function will fail if - * ADC is busy. The channel does not need to be enabled to perform a single conversion. - * - * @param[in] p_channel Channel. - * @param[out] p_value Pointer to the location where the result should be placed. Unless NULL is - * provided, the function is blocking. - * - * @retval NRF_SUCCESS If conversion was successful. - * @retval NRF_ERROR_BUSY If the ADC driver is busy. - */ -ret_code_t nrf_drv_adc_sample_convert(nrf_drv_adc_channel_t const * const p_channel, - nrf_adc_value_t * p_value); - -/** - * @brief Function for converting data to the buffer. - * - * If the driver is initialized in non-blocking mode, this function returns when the first conversion - * is set up. When the buffer is filled, the application is notified by the event handler. If the - * driver is initialized in blocking mode, the function returns when the buffer is filled. - * - * Conversion is done on all enabled channels, but it is not triggered by this - * function. This function will prepare the ADC for sampling and then - * wait for the SAMPLE task. Sampling can be triggered manually by the @ref - * nrf_drv_adc_sample function or by PPI using the @ref NRF_ADC_TASK_START task. - * - * @note If more than one channel is enabled, the function emulates scanning, and - * a single START task will trigger conversion on all enabled channels. For example: - * If 3 channels are enabled and the user requests 6 samples, the completion event - * handler will be called after 2 START tasks. - * @note The application must adjust the sampling frequency. The maximum frequency - * depends on the sampling timer and the maximum latency of the ADC interrupt. If - * an interrupt is not handled before the next sampling is triggered, the sample - * will be lost. - * - * @param[in] buffer Result buffer. - * @param[in] size Buffer size in samples. - * - * @retval NRF_SUCCESS If conversion was successful. - * @retval NRF_ERROR_BUSY If the driver is busy. - */ -ret_code_t nrf_drv_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size); - -/** - * @brief Function for retrieving the ADC state. - * - * @retval true If the ADC is busy. - * @retval false If the ADC is ready. - */ -bool nrf_drv_adc_is_busy(void); - -/** - * @brief Function for getting the address of the ADC START task. - * - * This function is used to get the address of the START task, which can be used to trigger ADC - * conversion. - * - * @return Start task address. - */ -__STATIC_INLINE uint32_t nrf_drv_adc_start_task_get(void); - -/** - * @brief Function for converting a GPIO pin number to an analog input pin mask to be used in - * the ADC channel configuration. - * - * @param[in] pin GPIO pin. - * - * @return Analog input pin mask. The function returns @ref NRF_ADC_CONFIG_INPUT_DISABLED - * if the specified pin is not an analog input. - */ -__STATIC_INLINE nrf_adc_config_input_t nrf_drv_adc_gpio_to_ain(uint32_t pin); - -#ifndef SUPPRESS_INLINE_IMPLEMENTATION - -__STATIC_INLINE uint32_t nrf_drv_adc_start_task_get(void) -{ - return nrf_adc_task_address_get(NRF_ADC_TASK_START); -} - -__STATIC_INLINE nrf_adc_config_input_t nrf_drv_adc_gpio_to_ain(uint32_t pin) -{ - // AIN2 - AIN7 - if (pin >= 1 && pin <= 6) - { - return (nrf_adc_config_input_t)(1 << (pin+1)); - } - // AIN0 - AIN1 - else if (pin >= 26 && pin <= 27) - { - return (nrf_adc_config_input_t)(1 <<(pin - 26)); - } - else - { - return NRF_ADC_CONFIG_INPUT_DISABLED; - } -} - -#ifdef __cplusplus -} -#endif - -#endif -/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h deleted file mode 100644 index cbf187048d..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright (c) 2015 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef NRF_DRV_CONFIG_H -#define NRF_DRV_CONFIG_H - -/** - * Provide a non-zero value here in applications that need to use several - * peripherals with the same ID that are sharing certain resources - * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used - * simultaneously. Therefore, this definition allows to initialize the driver - * for another peripheral from a given group only after the previously used one - * is uninitialized. Normally, this is not possible, because interrupt handlers - * are implemented in individual drivers. - * This functionality requires a more complicated interrupt handling and driver - * initialization, hence it is not always desirable to use it. - */ -#define PERIPHERAL_RESOURCE_SHARING_ENABLED 1 - -/* CLOCK */ -#define CLOCK_ENABLED 1 - -#if (CLOCK_ENABLED == 1) -#define CLOCK_CONFIG_XTAL_FREQ NRF_CLOCK_XTALFREQ_Default -#define CLOCK_CONFIG_LF_SRC NRF_CLOCK_LFCLK_Xtal -#define CLOCK_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* GPIOTE */ -#define GPIOTE_ENABLED 1 - -#if (GPIOTE_ENABLED == 1) -#define GPIOTE_CONFIG_USE_SWI_EGU false -#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8 -#endif - -/* TIMER */ -#ifdef SOFTDEVICE_PRESENT -#define TIMER0_ENABLED 0 -#else -#define TIMER0_ENABLED 1 -#endif - -#if (TIMER0_ENABLED == 1) -#define TIMER0_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER0_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER0_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_32Bit -#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER0_INSTANCE_INDEX 0 -#endif - -#define TIMER1_ENABLED 1 - -#if (TIMER1_ENABLED == 1) -#define TIMER1_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER1_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER1_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER1_INSTANCE_INDEX (TIMER0_ENABLED) -#endif - -#define TIMER2_ENABLED 1 - -#if (TIMER2_ENABLED == 1) -#define TIMER2_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER2_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER2_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER2_INSTANCE_INDEX (TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER3_ENABLED 0 - -#if (TIMER3_ENABLED == 1) -#define TIMER3_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER3_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER3_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER3_INSTANCE_INDEX (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - -#define TIMER4_ENABLED 0 - -#if (TIMER4_ENABLED == 1) -#define TIMER4_CONFIG_FREQUENCY NRF_TIMER_FREQ_16MHz -#define TIMER4_CONFIG_MODE TIMER_MODE_MODE_Timer -#define TIMER4_CONFIG_BIT_WIDTH TIMER_BITMODE_BITMODE_16Bit -#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TIMER4_INSTANCE_INDEX (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED) -#endif - - -#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED) - -/* RTC */ -#define RTC0_ENABLED 0 - -#if (RTC0_ENABLED == 1) -#define RTC0_CONFIG_FREQUENCY 32678 -#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC0_CONFIG_RELIABLE false - -#define RTC0_INSTANCE_INDEX 0 -#endif - -#define RTC1_ENABLED 0 - -#if (RTC1_ENABLED == 1) -#define RTC1_CONFIG_FREQUENCY 32768 -#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC1_CONFIG_RELIABLE false - -#define RTC1_INSTANCE_INDEX (RTC0_ENABLED) -#endif - -#define RTC2_ENABLED 0 - -#if (RTC2_ENABLED == 1) -#define RTC2_CONFIG_FREQUENCY 32768 -#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define RTC2_CONFIG_RELIABLE false - -#define RTC2_INSTANCE_INDEX (RTC0_ENABLED+RTC1_ENABLED) -#endif - - -#define RTC_COUNT (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED) - -#define NRF_MAXIMUM_LATENCY_US 2000 - -/* RNG */ -#define RNG_ENABLED 0 - -#if (RNG_ENABLED == 1) -#define RNG_CONFIG_ERROR_CORRECTION true -#define RNG_CONFIG_POOL_SIZE 8 -#define RNG_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PWM */ - -#define PWM0_ENABLED 0 - -#if (PWM0_ENABLED == 1) -#define PWM0_CONFIG_OUT0_PIN 2 -#define PWM0_CONFIG_OUT1_PIN 3 -#define PWM0_CONFIG_OUT2_PIN 4 -#define PWM0_CONFIG_OUT3_PIN 5 -#define PWM0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM0_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM0_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM0_CONFIG_TOP_VALUE 1000 -#define PWM0_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM0_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM0_INSTANCE_INDEX 0 -#endif - -#define PWM1_ENABLED 0 - -#if (PWM1_ENABLED == 1) -#define PWM1_CONFIG_OUT0_PIN 2 -#define PWM1_CONFIG_OUT1_PIN 3 -#define PWM1_CONFIG_OUT2_PIN 4 -#define PWM1_CONFIG_OUT3_PIN 5 -#define PWM1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM1_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM1_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM1_CONFIG_TOP_VALUE 1000 -#define PWM1_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM1_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM1_INSTANCE_INDEX (PWM0_ENABLED) -#endif - -#define PWM2_ENABLED 0 - -#if (PWM2_ENABLED == 1) -#define PWM2_CONFIG_OUT0_PIN 2 -#define PWM2_CONFIG_OUT1_PIN 3 -#define PWM2_CONFIG_OUT2_PIN 4 -#define PWM2_CONFIG_OUT3_PIN 5 -#define PWM2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define PWM2_CONFIG_BASE_CLOCK NRF_PWM_CLK_1MHz -#define PWM2_CONFIG_COUNT_MODE NRF_PWM_MODE_UP -#define PWM2_CONFIG_TOP_VALUE 1000 -#define PWM2_CONFIG_LOAD_MODE NRF_PWM_LOAD_COMMON -#define PWM2_CONFIG_STEP_MODE NRF_PWM_STEP_AUTO - -#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED) -#endif - -#define PWM_COUNT (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED) - -/* SPI */ -#define SPI0_ENABLED 0 - -#if (SPI0_ENABLED == 1) -#define SPI0_USE_EASY_DMA 0 - -#define SPI0_CONFIG_SCK_PIN 2 -#define SPI0_CONFIG_MOSI_PIN 3 -#define SPI0_CONFIG_MISO_PIN 4 -#define SPI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI0_INSTANCE_INDEX 0 -#endif - -#define SPI1_ENABLED 1 - -#if (SPI1_ENABLED == 1) -#define SPI1_USE_EASY_DMA 0 - -#define SPI1_CONFIG_SCK_PIN 2 -#define SPI1_CONFIG_MOSI_PIN 3 -#define SPI1_CONFIG_MISO_PIN 4 -#define SPI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI1_INSTANCE_INDEX (SPI0_ENABLED) -#endif - -#define SPI2_ENABLED 0 - -#if (SPI2_ENABLED == 1) -#define SPI2_USE_EASY_DMA 0 - -#define SPI2_CONFIG_SCK_PIN 2 -#define SPI2_CONFIG_MOSI_PIN 3 -#define SPI2_CONFIG_MISO_PIN 4 -#define SPI2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED) -#endif - -#define SPI_COUNT (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED) - -/* SPIS */ -#define SPIS0_ENABLED 0 - -#if (SPIS0_ENABLED == 1) -#define SPIS0_CONFIG_SCK_PIN 2 -#define SPIS0_CONFIG_MOSI_PIN 3 -#define SPIS0_CONFIG_MISO_PIN 4 -#define SPIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS0_INSTANCE_INDEX 0 -#endif - -#define SPIS1_ENABLED 1 - -#if (SPIS1_ENABLED == 1) -#define SPIS1_CONFIG_SCK_PIN 2 -#define SPIS1_CONFIG_MOSI_PIN 3 -#define SPIS1_CONFIG_MISO_PIN 4 -#define SPIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED -#endif - -#define SPIS2_ENABLED 0 - -#if (SPIS2_ENABLED == 1) -#define SPIS2_CONFIG_SCK_PIN 2 -#define SPIS2_CONFIG_MOSI_PIN 3 -#define SPIS2_CONFIG_MISO_PIN 4 -#define SPIS2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED) -#endif - -#define SPIS_COUNT (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED) - -/* UART */ -#define UART0_ENABLED 1 - -#if (UART0_ENABLED == 1) -#define UART0_CONFIG_HWFC NRF_UART_HWFC_ENABLED -#define UART0_CONFIG_PARITY NRF_UART_PARITY_EXCLUDED -#define UART0_CONFIG_BAUDRATE NRF_UART_BAUDRATE_9600 -#define UART0_CONFIG_PSEL_TXD 9 -#define UART0_CONFIG_PSEL_RXD 11 -#define UART0_CONFIG_PSEL_CTS 10 -#define UART0_CONFIG_PSEL_RTS 8 -#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#ifdef NRF52 -#define UART0_CONFIG_USE_EASY_DMA false -//Compile time flag -#define UART_EASY_DMA_SUPPORT 1 -#define UART_LEGACY_SUPPORT 1 -#endif //NRF52 -#endif - -#define TWI0_ENABLED 1 - -#if (TWI0_ENABLED == 1) -#define TWI0_USE_EASY_DMA 0 - -#define TWI0_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI0_CONFIG_SCL 0 -#define TWI0_CONFIG_SDA 1 -#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI0_INSTANCE_INDEX 0 -#endif - -#define TWI1_ENABLED 1 - -#if (TWI1_ENABLED == 1) -#define TWI1_USE_EASY_DMA 0 - -#define TWI1_CONFIG_FREQUENCY NRF_TWI_FREQ_100K -#define TWI1_CONFIG_SCL 0 -#define TWI1_CONFIG_SDA 1 -#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - -#define TWI1_INSTANCE_INDEX (TWI0_ENABLED) -#endif - -#define TWI_COUNT (TWI0_ENABLED + TWI1_ENABLED) - -/* TWIS */ -#define TWIS0_ENABLED 0 - -#if (TWIS0_ENABLED == 1) - #define TWIS0_CONFIG_ADDR0 0 - #define TWIS0_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS0_CONFIG_SCL 0 - #define TWIS0_CONFIG_SDA 1 - #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS0_INSTANCE_INDEX 0 -#endif - -#define TWIS1_ENABLED 0 - -#if (TWIS1_ENABLED == 1) - #define TWIS1_CONFIG_ADDR0 0 - #define TWIS1_CONFIG_ADDR1 0 /* 0: Disabled */ - #define TWIS1_CONFIG_SCL 0 - #define TWIS1_CONFIG_SDA 1 - #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW - - #define TWIS1_INSTANCE_INDEX (TWIS0_ENABLED) -#endif - -#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED) -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0 -/* For more documentation see nrf_drv_twis.h file */ -#define TWIS_NO_SYNC_MODE 0 - -/* QDEC */ -#define QDEC_ENABLED 0 - -#if (QDEC_ENABLED == 1) -#define QDEC_CONFIG_REPORTPER NRF_QDEC_REPORTPER_10 -#define QDEC_CONFIG_SAMPLEPER NRF_QDEC_SAMPLEPER_16384us -#define QDEC_CONFIG_PIO_A 1 -#define QDEC_CONFIG_PIO_B 2 -#define QDEC_CONFIG_PIO_LED 3 -#define QDEC_CONFIG_LEDPRE 511 -#define QDEC_CONFIG_LEDPOL NRF_QDEC_LEPOL_ACTIVE_HIGH -#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define QDEC_CONFIG_DBFEN false -#define QDEC_CONFIG_SAMPLE_INTEN false -#endif - -/* ADC */ -#define ADC_ENABLED 1 - -#if (ADC_ENABLED == 1) -#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - - -/* SAADC */ -#define SAADC_ENABLED 0 - -#if (SAADC_ENABLED == 1) -#define SAADC_CONFIG_RESOLUTION NRF_SAADC_RESOLUTION_10BIT -#define SAADC_CONFIG_OVERSAMPLE NRF_SAADC_OVERSAMPLE_DISABLED -#define SAADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* PDM */ -#define PDM_ENABLED 0 - -#if (PDM_ENABLED == 1) -#define PDM_CONFIG_MODE NRF_PDM_MODE_MONO -#define PDM_CONFIG_EDGE NRF_PDM_EDGE_LEFTFALLING -#define PDM_CONFIG_CLOCK_FREQ NRF_PDM_FREQ_1032K -#define PDM_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#endif - -/* COMP */ -#define COMP_ENABLED 0 - -#if (COMP_ENABLED == 1) -#define COMP_CONFIG_REF NRF_COMP_REF_Int1V8 -#define COMP_CONFIG_MAIN_MODE NRF_COMP_MAIN_MODE_SE -#define COMP_CONFIG_SPEED_MODE NRF_COMP_SP_MODE_High -#define COMP_CONFIG_HYST NRF_COMP_HYST_NoHyst -#define COMP_CONFIG_ISOURCE NRF_COMP_ISOURCE_Off -#define COMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define COMP_CONFIG_INPUT NRF_COMP_INPUT_0 -#endif - -/* LPCOMP */ -#define LPCOMP_ENABLED 0 - -#if (LPCOMP_ENABLED == 1) -#define LPCOMP_CONFIG_REFERENCE NRF_LPCOMP_REF_SUPPLY_4_8 -#define LPCOMP_CONFIG_DETECTION NRF_LPCOMP_DETECT_DOWN -#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#define LPCOMP_CONFIG_INPUT NRF_LPCOMP_INPUT_0 -#endif - -/* WDT */ -#define WDT_ENABLED 0 - -#if (WDT_ENABLED == 1) -#define WDT_CONFIG_BEHAVIOUR NRF_WDT_BEHAVIOUR_RUN_SLEEP -#define WDT_CONFIG_RELOAD_VALUE 2000 -#define WDT_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#endif - -/* SWI EGU */ -#ifdef NRF52 - #define EGU_ENABLED 0 -#endif - -/* I2S */ -#define I2S_ENABLED 0 - -#if (I2S_ENABLED == 1) -#define I2S_CONFIG_SCK_PIN 22 -#define I2S_CONFIG_LRCK_PIN 23 -#define I2S_CONFIG_MCK_PIN NRF_DRV_I2S_PIN_NOT_USED -#define I2S_CONFIG_SDOUT_PIN 24 -#define I2S_CONFIG_SDIN_PIN 25 -#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH -#define I2S_CONFIG_MASTER NRF_I2S_MODE_MASTER -#define I2S_CONFIG_FORMAT NRF_I2S_FORMAT_I2S -#define I2S_CONFIG_ALIGN NRF_I2S_ALIGN_LEFT -#define I2S_CONFIG_SWIDTH NRF_I2S_SWIDTH_16BIT -#define I2S_CONFIG_CHANNELS NRF_I2S_CHANNELS_STEREO -#define I2S_CONFIG_MCK_SETUP NRF_I2S_MCK_32MDIV8 -#define I2S_CONFIG_RATIO NRF_I2S_RATIO_256X -#endif - -#include "nrf_drv_config_validation.h" - -#endif // NRF_DRV_CONFIG_H diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h deleted file mode 100644 index 09a00582dd..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h +++ /dev/null @@ -1,202 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - @defgroup nrf_mbr_api Master Boot Record API - @{ - - @brief APIs for updating SoftDevice and BootLoader - -*/ - -/* Header guard */ -#ifndef NRF_MBR_H__ -#define NRF_MBR_H__ - -#include "nrf_svc.h" -#include - -#ifndef NRF51 -#error "This header file shall only be included for nRF51 projects" -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup NRF_MBR_DEFINES Defines - * @{ */ - -/**@brief MBR SVC Base number. */ -#define MBR_SVC_BASE (0x18) - -/**@brief Page size in words. */ -#define PAGE_SIZE_IN_WORDS 256 -/** @} */ - -/** @brief The size that must be reserved for the MBR when a softdevice is written to flash. -This is the offset where the first byte of the softdevice hex file is written.*/ -#define MBR_SIZE (0x1000) - -/** @addtogroup NRF_MBR_ENUMS Enumerations - * @{ */ - -/**@brief nRF Master Boot Record API SVC numbers. */ -enum NRF_MBR_SVCS -{ - SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */ -}; - -/**@brief Possible values for ::sd_mbr_command_t.command */ -enum NRF_MBR_COMMANDS -{ - SD_MBR_COMMAND_COPY_BL, /**< Copy a new BootLoader. @see sd_mbr_command_copy_bl_t */ - SD_MBR_COMMAND_COPY_SD, /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/ - SD_MBR_COMMAND_INIT_SD, /**< Init forwarding interrupts to SD, and run reset function in SD*/ - SD_MBR_COMMAND_COMPARE, /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/ - SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Start forwarding all exception to this address @see ::sd_mbr_command_vector_table_base_set_t*/ -}; - -/** @} */ - -/** @addtogroup NRF_MBR_TYPES Types - * @{ */ - -/**@brief This command copies part of a new SoftDevice - * The destination area is erased before copying. - * If dst is in the middle of a flash page, that whole flash page will be erased. - * If (dst+len) is in the middle of a flash page, that whole flash page will be erased. - * - * The user of this function is responsible for setting the PROTENSET registers. - * - * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly. - * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying. - */ -typedef struct -{ - uint32_t *src; /**< Pointer to the source of data to be copied.*/ - uint32_t *dst; /**< Pointer to the destination where the content is to be copied.*/ - uint32_t len; /**< Number of 32 bit words to copy. Must be a multiple of @ref PAGE_SIZE_IN_WORDS words.*/ -} sd_mbr_command_copy_sd_t; - - -/**@brief This command works like memcmp, but takes the length in words. - * - * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal. - * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal. - */ -typedef struct -{ - uint32_t *ptr1; /**< Pointer to block of memory. */ - uint32_t *ptr2; /**< Pointer to block of memory. */ - uint32_t len; /**< Number of 32 bit words to compare.*/ -} sd_mbr_command_compare_t; - - -/**@brief This command copies a new BootLoader. - * With this command, destination of BootLoader is always the address written in NRF_UICR->BOOTADDR. - * - * Destination is erased by this function. - * If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased. - * - * This function will use PROTENSET to protect the flash that is not intended to be written. - * - * On Success, this function will not return. It will start the new BootLoader from reset-vector as normal. - * - * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen. - * @retval ::NRF_ERROR_FORBIDDEN if NRF_UICR->BOOTADDR is not set. - * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area. - */ -typedef struct -{ - uint32_t *bl_src; /**< Pointer to the source of the Bootloader to be be copied.*/ - uint32_t bl_len; /**< Number of 32 bit words to copy for BootLoader. */ -} sd_mbr_command_copy_bl_t; - -/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR - * - * Once this function has been called, this address is where the MBR will start to forward interrupts to after a reset. - * - * To restore default forwarding this function should be called with @param address set to 0. - * The MBR will then start forwarding to interrupts to the address in NFR_UICR->BOOTADDR or to the SoftDevice if the BOOTADDR is not set. - * - * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen. - * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size. - */ -typedef struct -{ - uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/ -} sd_mbr_command_vector_table_base_set_t; - -typedef struct -{ - uint32_t command; /**< type of command to be issued see @ref NRF_MBR_COMMANDS. */ - union - { - sd_mbr_command_copy_sd_t copy_sd; /**< Parameters for copy SoftDevice.*/ - sd_mbr_command_copy_bl_t copy_bl; /**< Parameters for copy BootLoader.*/ - sd_mbr_command_compare_t compare; /**< Parameters for verify.*/ - sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set.*/ - } params; -} sd_mbr_command_t; - -/** @} */ - -/** @addtogroup NRF_MBR_FUNCTIONS Functions - * @{ */ - -/**@brief Issue Master Boot Record commands - * - * Commands used when updating a SoftDevice and bootloader. - * - * @param[in] param Pointer to a struct describing the command. - * - *@note for retvals see ::sd_mbr_command_copy_sd_t ::sd_mbr_command_copy_bl_t ::sd_mbr_command_compare_t - -*/ -SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param)); - -/** @} */ -#ifdef __cplusplus -} -#endif -#endif // NRF_MBR_H__ - -/** - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h deleted file mode 100644 index 71e3984776..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h +++ /dev/null @@ -1,635 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_COMMON BLE SoftDevice Common - @{ - @defgroup ble_api Events, type definitions and API calls - @{ - - @brief Module independent events, type definitions and API calls for the BLE SoftDevice. - - */ - -#ifndef NRF_BLE_H__ -#define NRF_BLE_H__ - -#include "nrf_ble_ranges.h" -#include "nrf_ble_types.h" -#include "nrf_ble_gap.h" -#include "nrf_ble_l2cap.h" -#include "nrf_ble_gatt.h" -#include "nrf_ble_gattc.h" -#include "nrf_ble_gatts.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations - * @{ */ - -/** - * @brief Common API SVC numbers. - */ -enum BLE_COMMON_SVCS -{ - SD_BLE_ENABLE = BLE_SVC_BASE, /**< Enable and initialize the BLE stack */ - SD_BLE_EVT_GET, /**< Get an event from the pending events queue. */ - SD_BLE_TX_PACKET_COUNT_GET, /**< Get the total number of available application transmission packets for a particular connection. */ - SD_BLE_UUID_VS_ADD, /**< Add a Vendor Specific UUID. */ - SD_BLE_UUID_DECODE, /**< Decode UUID bytes. */ - SD_BLE_UUID_ENCODE, /**< Encode UUID bytes. */ - SD_BLE_VERSION_GET, /**< Get the local version information (company id, Link Layer Version, Link Layer Subversion). */ - SD_BLE_USER_MEM_REPLY, /**< User Memory Reply. */ - SD_BLE_OPT_SET, /**< Set a BLE option. */ - SD_BLE_OPT_GET, /**< Get a BLE option. */ -}; - - /** - * @brief BLE Module Independent Event IDs. - */ -enum BLE_COMMON_EVTS -{ - BLE_EVT_TX_COMPLETE = BLE_EVT_BASE, /**< Transmission Complete. @ref ble_evt_tx_complete_t */ - BLE_EVT_USER_MEM_REQUEST, /**< User Memory request. @ref ble_evt_user_mem_request_t */ - BLE_EVT_USER_MEM_RELEASE /**< User Memory release. @ref ble_evt_user_mem_release_t */ -}; - -/**@brief BLE connection bandwidth types. - * Bandwidth types supported by the SoftDevice in packets per connection interval. - */ -enum BLE_CONN_BWS -{ - BLE_CONN_BW_NONE = 0, - BLE_CONN_BW_LOW, - BLE_CONN_BW_MID, - BLE_CONN_BW_HIGH -}; - -/**@brief Common Option IDs. - * IDs that uniquely identify a common option. - */ -enum BLE_COMMON_OPTS -{ - BLE_COMMON_OPT_CONN_BW = BLE_OPT_BASE, /**< Bandwidth configuration @ref ble_common_opt_conn_bw_t */ - BLE_COMMON_OPT_PA_LNA /**< PA and LNA options */ -}; - -/** @} */ - -/** @addtogroup BLE_COMMON_DEFINES Defines - * @{ */ - -/** @brief Required pointer alignment for BLE Events. -*/ -#define BLE_EVTS_PTR_ALIGNMENT 4 - -/** @defgroup BLE_USER_MEM_TYPES User Memory Types - * @{ */ -#define BLE_USER_MEM_TYPE_INVALID 0x00 /**< Invalid User Memory Types. */ -#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES 0x01 /**< User Memory for GATTS queued writes. */ -/** @} */ - -/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific UUID counts - * @{ - */ -#define BLE_UUID_VS_COUNT_MIN 1 /**< Minimum VS UUID count. */ -#define BLE_UUID_VS_COUNT_DEFAULT 0 /**< Use the default VS UUID count (10 for this version of the SoftDevice). */ -/** @} */ - -/** @} */ - -/** @addtogroup BLE_COMMON_STRUCTURES Structures - * @{ */ - -/**@brief User Memory Block. */ -typedef struct -{ - uint8_t *p_mem; /**< Pointer to the start of the user memory block. */ - uint16_t len; /**< Length in bytes of the user memory block. */ -} ble_user_mem_block_t; - -/** - * @brief Event structure for @ref BLE_EVT_TX_COMPLETE. - */ -typedef struct -{ - uint8_t count; /**< Number of packets transmitted. */ -} ble_evt_tx_complete_t; - -/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */ -typedef struct -{ - uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ -} ble_evt_user_mem_request_t; - -/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */ -typedef struct -{ - uint8_t type; /**< User memory type, see @ref BLE_USER_MEM_TYPES. */ - ble_user_mem_block_t mem_block; /**< User memory block */ -} ble_evt_user_mem_release_t; - - -/**@brief Event structure for events not associated with a specific function module. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which this event occurred. */ - union - { - ble_evt_tx_complete_t tx_complete; /**< Transmission Complete. */ - ble_evt_user_mem_request_t user_mem_request; /**< User Memory Request Event Parameters. */ - ble_evt_user_mem_release_t user_mem_release; /**< User Memory Release Event Parameters. */ - } params; -} ble_common_evt_t; - -/**@brief BLE Event header. */ -typedef struct -{ - uint16_t evt_id; /**< Value from a BLE__EVT series. */ - uint16_t evt_len; /**< Length in octets including this header. */ -} ble_evt_hdr_t; - -/**@brief Common BLE Event type, wrapping the module specific event reports. */ -typedef struct -{ - ble_evt_hdr_t header; /**< Event header. */ - union - { - ble_common_evt_t common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */ - ble_gap_evt_t gap_evt; /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */ - ble_l2cap_evt_t l2cap_evt; /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */ - ble_gattc_evt_t gattc_evt; /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */ - ble_gatts_evt_t gatts_evt; /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */ - } evt; -} ble_evt_t; - - -/** - * @brief Version Information. - */ -typedef struct -{ - uint8_t version_number; /**< Link Layer Version number for BT 4.1 spec is 7 (https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer). */ - uint16_t company_id; /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */ - uint16_t subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */ -} ble_version_t; - -/* @brief: Configuration parameters for the PA and LNA. */ -typedef struct -{ - uint8_t enable :1; /**< Enable toggling for this amplifier */ - uint8_t active_high :1; /**< Set the pin to be active high */ - uint8_t gpio_pin :6; /**< The GPIO pin to toggle for this amplifier */ -} ble_pa_lna_cfg_t; - -/* - * @brief PA & LNA GPIO toggle configuration - * - * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or - * a low noise amplifier. - * - * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided - * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled. - * - * @note @ref sd_ble_opt_get is not supported for this option. - * @note This feature is only supported for nRF52, on nRF51 @ref NRF_ERROR_NOT_SUPPORTED will always be returned. - * @note Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences - * and must be avoided by the application. - * - */ -typedef struct -{ - ble_pa_lna_cfg_t pa_cfg; /**< Power Amplifier configuration */ - ble_pa_lna_cfg_t lna_cfg; /**< Low Noise Amplifier configuration */ - - uint8_t ppi_ch_id_set; /**< PPI channel used for radio pin setting */ - uint8_t ppi_ch_id_clr; /**< PPI channel used for radio pin clearing */ - uint8_t gpiote_ch_id; /**< GPIOTE channel used for radio pin toggling */ -} ble_common_opt_pa_lna_t; - -/** - * @brief BLE connection bandwidth configuration parameters - */ -typedef struct -{ - uint8_t conn_bw_tx; /**< Connection bandwidth configuration for transmission, see @ref BLE_CONN_BWS.*/ - uint8_t conn_bw_rx; /**< Connection bandwidth configuration for reception, see @ref BLE_CONN_BWS.*/ -} ble_conn_bw_t; - -/**@brief BLE connection specific bandwidth configuration parameters. - * - * This can be used with @ref sd_ble_opt_set to set the bandwidth configuration to be used when creating connections. - * - * Call @ref sd_ble_opt_set with this option prior to calling @ref sd_ble_gap_adv_start or @ref sd_ble_gap_connect. - * - * The bandwidth configurations set via @ref sd_ble_opt_set are maintained separately for central and peripheral - * connections. The given configurations are used for all future connections of the role indicated in this structure - * unless they are changed by subsequent @ref sd_ble_opt_set calls. - * - * @note When this option is not used, the SoftDevice will use the default options: - * - @ref BLE_CONN_BW_HIGH for @ref BLE_GAP_ROLE_PERIPH connections (both transmission and reception). - * - @ref BLE_CONN_BW_MID for @ref BLE_GAP_ROLE_CENTRAL connections (both transmisison and reception). - * This option allows the application to selectively override these defaults for each role. - * - * @note The global memory pool configuration can be set with the @ref ble_conn_bw_counts_t configuration parameter, which - * is provided to @ref sd_ble_enable. - * - * @note Please refer to SoftDevice Specification for more information on bandwidth configuration. - * - * @mscs - * @mmsc{@ref BLE_COMMON_CONF_BW} - * @endmscs - * - * @retval ::NRF_SUCCESS Set successfully. - * @retval ::BLE_ERROR_INVALID_ROLE The role is invalid. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid bandwidth configuration parameters. - * @retval ::NRF_ERROR_NOT_SUPPORTED If the combination of role and bandwidth configuration is not supported. - */ -typedef struct -{ - uint8_t role; /**< BLE role of the connection, see @ref BLE_GAP_ROLES. */ - ble_conn_bw_t conn_bw; /**< Bandwidth configuration parameters. */ -} ble_common_opt_conn_bw_t; - -/**@brief Option structure for common options. */ -typedef union -{ - ble_common_opt_conn_bw_t conn_bw; /**< Parameters for the connection bandwidth option. */ - ble_common_opt_pa_lna_t pa_lna; /**< Parameters for controlling PA and LNA pin toggling. */ -} ble_common_opt_t; - -/**@brief Common BLE Option type, wrapping the module specific options. */ -typedef union -{ - ble_common_opt_t common_opt; /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */ - ble_gap_opt_t gap_opt; /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */ -} ble_opt_t; - -/** - * @brief BLE bandwidth count parameters - * - * These parameters are used to configure the memory pools allocated within the SoftDevice for application packets - * (both transmission and reception) for all connections. - * - * @note The sum of all three counts must add up to the sum of @ref ble_gap_enable_params_t::central_conn_count and - * @ref ble_gap_enable_params_t::periph_conn_count in @ref ble_gap_enable_params_t. - */ -typedef struct { - uint8_t high_count; /**< Total number of high bandwidth TX or RX memory pools available to the application at runtime for all active connections. */ - uint8_t mid_count; /**< Total number of medium bandwidth TX or RX memory pools available to the application at runtime for all active connections. */ - uint8_t low_count; /**< Total number of low bandwidth TX or RX memory pools available to the application at runtime for all active connections. */ -} ble_conn_bw_count_t; - -/** - * @brief BLE bandwidth global memory pool configuration parameters - * - * These configuration parameters are used to set the amount of memory dedicated to application packets for - * all connections. The application should specify the most demanding configuration for the intended use. - * - * Please refer to the SoftDevice Specification for more information on bandwidth configuration. - * - * @note Each connection created at runtime requires both a TX and an RX memory pool. By the use of these configuration - * parameters, the application can decide the size and total number of the global memory pools that will be later - * available for connection creation. - * - * @mscs - * @mmsc{@ref BLE_COMMON_CONF_BW} - * @endmscs - * - */ -typedef struct { - ble_conn_bw_count_t tx_counts; /**< Global memory pool configuration for transmission.*/ - ble_conn_bw_count_t rx_counts; /**< Global memory pool configuration for reception.*/ -} ble_conn_bw_counts_t; - -/** - * @brief BLE Common Initialization parameters. - * - * @note If @ref p_conn_bw_counts is NULL the SoftDevice will assume default bandwidth configuration for all connections. - * To fit a custom bandwidth configuration requirement, the application developer may have to specify a custom memory - * pool configuration here. See @ref ble_common_opt_conn_bw_t for bandwidth configuration of individual connections. - * Please refer to the SoftDevice Specification for more information on bandwidth configuration. - */ -typedef struct -{ - uint16_t vs_uuid_count; /**< Maximum number of 128-bit, Vendor Specific UUID bases to allocate. */ - ble_conn_bw_counts_t *p_conn_bw_counts; /**< Bandwidth configuration parameters or NULL for defaults. */ -} ble_common_enable_params_t; - -/** - * @brief BLE Initialization parameters. - */ -typedef struct -{ - ble_common_enable_params_t common_enable_params; /**< Common init parameters @ref ble_common_enable_params_t. */ - ble_gap_enable_params_t gap_enable_params; /**< GAP init parameters @ref ble_gap_enable_params_t. */ - ble_gatts_enable_params_t gatts_enable_params; /**< GATTS init parameters @ref ble_gatts_enable_params_t. */ -} ble_enable_params_t; - -/** @} */ - -/** @addtogroup BLE_COMMON_FUNCTIONS Functions - * @{ */ - -/**@brief Enable the BLE stack - * - * @param[in, out] p_ble_enable_params Pointer to ble_enable_params_t - * @param[in, out] p_app_ram_base Pointer to a variable containing the start address of the application RAM region - * (APP_RAM_BASE). On return, this will contain the minimum start address of the application RAM region required by the - * SoftDevice for this configuration. Calling @ref sd_ble_enable() with *p_app_ram_base set to 0 can be used during - * development to find out how much memory a specific configuration will need. - * - * @note The memory requirement for a specific configuration will not increase between SoftDevices with the same major - * version number. - * - * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located between 0x20000000 and - * APP_RAM_BASE-1 and the application's RAM region is located between APP_RAM_BASE and the start of the call stack. - * - * @details This call initializes the BLE stack, no other BLE related function can be called before this one. - * - * @mscs - * @mmsc{@ref BLE_COMMON_ENABLE} - * @endmscs - * - * @retval ::NRF_SUCCESS The BLE stack has been initialized successfully. - * @retval ::NRF_ERROR_INVALID_STATE The BLE stack had already been initialized and cannot be reinitialized. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. - * @retval ::NRF_ERROR_INVALID_LENGTH The specified Attribute Table size is either too small or not a multiple of 4. - * The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN. - * @retval ::NRF_ERROR_INVALID_PARAM Incorrectly configured VS UUID count or connection count parameters. - * @retval ::NRF_ERROR_NO_MEM The amount of memory assigned to the SoftDevice by *p_app_ram_base is not - * large enough to fit this configuration's memory requirement. Check *p_app_ram_base - * and set the start address of the application RAM region accordingly. - * @retval ::NRF_ERROR_CONN_COUNT The requested number of connections exceeds the maximum supported by the SoftDevice. - * Please refer to the SoftDevice Specification for more information on role configuration. - */ -SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(ble_enable_params_t * p_ble_enable_params, uint32_t * p_app_ram_base)); - -/**@brief Get an event from the pending events queue. - * - * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length. - * This buffer must be 4-byte aligned in memory. - * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length. - * - * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that - * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt. - * The application is free to choose whether to call this function from thread mode (main context) or directly from the - * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher - * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned) - * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so - * could potentially leave events in the internal queue without the application being aware of this fact. Sizing the - * p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to - * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event, - * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size. - * Please note that because of the variable length nature of some events, sizeof(ble_evt_t) will not always be large - * enough to fit certain events, and so it is the application's responsibility to provide an amount of memory large - * enough so that the relevant event is copied in full. The application may "peek" the event length by providing p_dest - * as a NULL pointer and inspecting the value of *p_len upon return: - * - * \code - * uint16_t len; - * errcode = sd_ble_evt_get(NULL, &len); - * \endcode - * - * @note The pointer supplied must be aligned to the extend defined by @ref BLE_EVTS_PTR_ALIGNMENT - * - * @mscs - * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC} - * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC} - * @endmscs - * - * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied. - * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled. - * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer. - */ -SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len)); - - -/**@brief Get the total number of available guaranteed application transmission packets for a particular connection. - * - * @details This call allows the application to obtain the total number of guaranteed application transmission packets - * available for a connection. Please note that this does not return the number of free packets, but rather the total - * amount of them for that particular connection. The application has two options to handle transmitting application packets: - * - Use a simple arithmetic calculation: after connection creation time the application should use this function to - * find out the total amount of guaranteed packets available to it and store it in a variable. - * Every time a packet is successfully queued for a transmission on this connection using any of the exposed functions in - * this BLE API, the application should decrement that variable. Conversely, whenever a @ref BLE_EVT_TX_COMPLETE event - * with the conn_handle matching the particular connection is received by the application, it should retrieve the count - * field in such event and add that number to the same variable storing the number of available guaranteed packets. This - * mechanism allows the application to be aware at any time of the number of guaranteed application packets available for - * each of the active connections, and therefore it can know with certainty whether it is possible to send more data or - * it has to wait for a @ref BLE_EVT_TX_COMPLETE event before it proceeds. - * The application can still pursue transmissions when the number of guaranteed application packets available is smaller - * than or equal to zero, but successful queuing of the tranmsission is not guaranteed. - * - Choose to simply not keep track of available packets at all, and instead handle the @ref BLE_ERROR_NO_TX_PACKETS error - * by queueing the packet to be transmitted and try again as soon as a @ref BLE_EVT_TX_COMPLETE event arrives. - * - * The API functions that may consume an application packet depending on the parameters supplied to them can be found below: - * - @ref sd_ble_gattc_write (write without response only) - * - @ref sd_ble_gatts_hvx (notifications only) - * - @ref sd_ble_l2cap_tx (all packets) - * - * @param[in] conn_handle Connection handle. - * @param[out] p_count Pointer to a uint8_t which will contain the number of application transmission packets upon - * successful return. - * @mscs - * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC} - * @endmscs - * - * @retval ::NRF_SUCCESS Number of application transmission packets retrieved successfully. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_TX_PACKET_COUNT_GET, uint32_t, sd_ble_tx_packet_count_get(uint16_t conn_handle, uint8_t *p_count)); - - -/**@brief Add a Vendor Specific UUID. - * - * @details This call enables the application to add a vendor specific UUID to the BLE stack's table, for later use - * all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t format - * when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code paths. - * The way that this is accomplished is by extending the grouping mechanism that the Bluetooth SIG standard base - * UUID uses for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to - * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the uuid field - * in the same structure contains the 2 bytes at indices 12 and 13. The number of possible 128-bit UUIDs available to - * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536, - * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array. - * - * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by - * the 16-bit uuid field in @ref ble_uuid_t. - * - * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in - * p_uuid_type along with an NRF_SUCCESS error code. - * - * @param[in] p_vs_uuid Pointer to a 16-octet (128-bit) little endian Vendor Specific UUID disregarding - * bytes 12 and 13. - * @param[out] p_uuid_type Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored. - * - * @retval ::NRF_SUCCESS Successfully added the Vendor Specific UUID. - * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid. - * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs. - */ -SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type)); - - -/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure. - * - * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared - * to the corresponding ones in each entry of the table of vendor specific UUIDs populated with @ref sd_ble_uuid_vs_add - * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index - * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type. - * - * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE. - * - * @param[in] uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes). - * @param[in] p_uuid_le Pointer pointing to little endian raw UUID bytes. - * @param[out] p_uuid Pointer to a @ref ble_uuid_t structure to be filled in. - * - * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length. - * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs. - */ -SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid)); - - -/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit). - * - * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed. - * - * @param[in] p_uuid Pointer to a @ref ble_uuid_t structure that will be encoded into bytes. - * @param[out] p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes). - * @param[out] p_uuid_le Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored. - * - * @retval ::NRF_SUCCESS Successfully encoded into the buffer. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type. - */ -SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le)); - - -/**@brief Get Version Information. - * - * @details This call allows the application to get the BLE stack version information. - * - * @param[out] p_version Pointer to a ble_version_t structure to be filled in. - * - * @retval ::NRF_SUCCESS Version information stored successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure). - */ -SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version)); - - -/**@brief Provide a user memory block. - * - * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application. - * - * @param[in] conn_handle Connection handle. - * @param[in,out] p_block Pointer to a user memory block structure. - * - * @mscs - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} - * @endmscs - * - * @retval ::NRF_SUCCESS Successfully queued a response to the peer. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no execute write request pending. - * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time. - */ -SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block)); - -/**@brief Set a BLE option. - * - * @details This call allows the application to set the value of an option. - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} - * @mmsc{@ref BLE_COMMON_CONF_BW} - * @endmscs - * - * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. - * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value. - * - * @retval ::NRF_SUCCESS Option set successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. - * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time. - * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. - */ -SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt)); - - -/**@brief Get a BLE option. - * - * @details This call allows the application to retrieve the value of an option. - * - * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS. - * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in. - * - * @retval ::NRF_SUCCESS Option retrieved successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. - * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time. - * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed. - * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported. - * - */ -SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt)); - -/** @} */ -#ifdef __cplusplus -} -#endif -#endif /* NRF_BLE_H__ */ - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h deleted file mode 100644 index 7eaf23d125..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h +++ /dev/null @@ -1,93 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_COMMON - @{ - @addtogroup nrf_error - @{ - @ingroup BLE_COMMON - @} - - @defgroup ble_err General error codes - @{ - - @brief General error code definitions for the BLE API. - - @ingroup BLE_COMMON -*/ -#ifndef NRF_BLE_ERR_H__ -#define NRF_BLE_ERR_H__ - -#include "nrf_error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/* @defgroup BLE_ERRORS Error Codes - * @{ */ -#define BLE_ERROR_NOT_ENABLED (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */ -#define BLE_ERROR_INVALID_CONN_HANDLE (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */ -#define BLE_ERROR_INVALID_ATTR_HANDLE (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */ -#define BLE_ERROR_NO_TX_PACKETS (NRF_ERROR_STK_BASE_NUM+0x004) /**< Not enough application packets available on this connection. */ -#define BLE_ERROR_INVALID_ROLE (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */ -/** @} */ - - -/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges - * @brief Assignment of subranges for module specific error codes. - * @note For specific error codes, see ble_.h or ble_error_.h. - * @{ */ -#define NRF_L2CAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */ -#define NRF_GAP_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */ -#define NRF_GATTC_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */ -#define NRF_GATTS_ERR_BASE (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */ -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif - - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h deleted file mode 100644 index 926714ed36..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h +++ /dev/null @@ -1,1745 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_GAP Generic Access Profile (GAP) - @{ - @brief Definitions and prototypes for the GAP interface. - */ - -#ifndef NRF_BLE_GAP_H__ -#define NRF_BLE_GAP_H__ - -#include "nrf_ble_types.h" -#include "nrf_ble_ranges.h" -#include "nrf_svc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations - * @{ */ - -/**@brief GAP API SVC numbers. - */ -enum BLE_GAP_SVCS -{ - SD_BLE_GAP_ADDRESS_SET = BLE_GAP_SVC_BASE, /**< Set own Bluetooth Address. */ - SD_BLE_GAP_ADDRESS_GET, /**< Get own Bluetooth Address. */ - SD_BLE_GAP_ADV_DATA_SET, /**< Set Advertising Data. */ - SD_BLE_GAP_ADV_START, /**< Start Advertising. */ - SD_BLE_GAP_ADV_STOP, /**< Stop Advertising. */ - SD_BLE_GAP_CONN_PARAM_UPDATE, /**< Connection Parameter Update. */ - SD_BLE_GAP_DISCONNECT, /**< Disconnect. */ - SD_BLE_GAP_TX_POWER_SET, /**< Set TX Power. */ - SD_BLE_GAP_APPEARANCE_SET, /**< Set Appearance. */ - SD_BLE_GAP_APPEARANCE_GET, /**< Get Appearance. */ - SD_BLE_GAP_PPCP_SET, /**< Set PPCP. */ - SD_BLE_GAP_PPCP_GET, /**< Get PPCP. */ - SD_BLE_GAP_DEVICE_NAME_SET, /**< Set Device Name. */ - SD_BLE_GAP_DEVICE_NAME_GET, /**< Get Device Name. */ - SD_BLE_GAP_AUTHENTICATE, /**< Initiate Pairing/Bonding. */ - SD_BLE_GAP_SEC_PARAMS_REPLY, /**< Reply with Security Parameters. */ - SD_BLE_GAP_AUTH_KEY_REPLY, /**< Reply with an authentication key. */ - SD_BLE_GAP_LESC_DHKEY_REPLY, /**< Reply with an LE Secure Connections DHKey. */ - SD_BLE_GAP_KEYPRESS_NOTIFY, /**< Notify of a keypress during an authentication procedure. */ - SD_BLE_GAP_LESC_OOB_DATA_GET, /**< Get the local LE Secure Connections OOB data. */ - SD_BLE_GAP_LESC_OOB_DATA_SET, /**< Set the remote LE Secure Connections OOB data. */ - SD_BLE_GAP_ENCRYPT, /**< Initiate encryption procedure. */ - SD_BLE_GAP_SEC_INFO_REPLY, /**< Reply with Security Information. */ - SD_BLE_GAP_CONN_SEC_GET, /**< Obtain connection security level. */ - SD_BLE_GAP_RSSI_START, /**< Start reporting of changes in RSSI. */ - SD_BLE_GAP_RSSI_STOP, /**< Stop reporting of changes in RSSI. */ - SD_BLE_GAP_SCAN_START, /**< Start Scanning. */ - SD_BLE_GAP_SCAN_STOP, /**< Stop Scanning. */ - SD_BLE_GAP_CONNECT, /**< Connect. */ - SD_BLE_GAP_CONNECT_CANCEL, /**< Cancel ongoing connection procedure. */ - SD_BLE_GAP_RSSI_GET, /**< Get the last RSSI sample. */ -}; - -/**@brief GAP Event IDs. - * IDs that uniquely identify an event coming from the stack to the application. - */ -enum BLE_GAP_EVTS -{ - BLE_GAP_EVT_CONNECTED = BLE_GAP_EVT_BASE, /**< Connection established. \n See @ref ble_gap_evt_connected_t. */ - BLE_GAP_EVT_DISCONNECTED, /**< Disconnected from peer. \n See @ref ble_gap_evt_disconnected_t. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE, /**< Connection Parameters updated. \n See @ref ble_gap_evt_conn_param_update_t. */ - BLE_GAP_EVT_SEC_PARAMS_REQUEST, /**< Request to provide security parameters. \n Reply with @ref sd_ble_gap_sec_params_reply. \n See @ref ble_gap_evt_sec_params_request_t. */ - BLE_GAP_EVT_SEC_INFO_REQUEST, /**< Request to provide security information. \n Reply with @ref sd_ble_gap_sec_info_reply. \n See @ref ble_gap_evt_sec_info_request_t. */ - BLE_GAP_EVT_PASSKEY_DISPLAY, /**< Request to display a passkey to the user. \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */ - BLE_GAP_EVT_KEY_PRESSED, /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t */ - BLE_GAP_EVT_AUTH_KEY_REQUEST, /**< Request to provide an authentication key. \n Reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_auth_key_request_t. */ - BLE_GAP_EVT_LESC_DHKEY_REQUEST, /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply. \n See @ref ble_gap_evt_lesc_dhkey_request_t */ - BLE_GAP_EVT_AUTH_STATUS, /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t. */ - BLE_GAP_EVT_CONN_SEC_UPDATE, /**< Connection security updated. \n See @ref ble_gap_evt_conn_sec_update_t. */ - BLE_GAP_EVT_TIMEOUT, /**< Timeout expired. \n See @ref ble_gap_evt_timeout_t. */ - BLE_GAP_EVT_RSSI_CHANGED, /**< RSSI report. \n See @ref ble_gap_evt_rssi_changed_t. */ - BLE_GAP_EVT_ADV_REPORT, /**< Advertising report. \n See @ref ble_gap_evt_adv_report_t. */ - BLE_GAP_EVT_SEC_REQUEST, /**< Security Request. \n See @ref ble_gap_evt_sec_request_t. */ - BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, /**< Connection Parameter Update Request. \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */ - BLE_GAP_EVT_SCAN_REQ_REPORT, /**< Scan request report. \n See @ref ble_gap_evt_scan_req_report_t. */ -}; - -/**@brief GAP Option IDs. - * IDs that uniquely identify a GAP option. - */ -enum BLE_GAP_OPTS -{ - BLE_GAP_OPT_CH_MAP = BLE_GAP_OPT_BASE, /**< Channel Map. @ref ble_gap_opt_ch_map_t */ - BLE_GAP_OPT_LOCAL_CONN_LATENCY, /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */ - BLE_GAP_OPT_PASSKEY, /**< Set passkey. @ref ble_gap_opt_passkey_t */ - BLE_GAP_OPT_PRIVACY, /**< Custom privacy. @ref ble_gap_opt_privacy_t */ - BLE_GAP_OPT_SCAN_REQ_REPORT, /**< Scan request report. @ref ble_gap_opt_scan_req_report_t */ - BLE_GAP_OPT_COMPAT_MODE /**< Compatibility mode. @ref ble_gap_opt_compat_mode_t */ -}; - -/** @} */ - -/**@addtogroup BLE_GAP_DEFINES Defines - * @{ */ - -/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP - * @{ */ -#define BLE_ERROR_GAP_UUID_LIST_MISMATCH (NRF_GAP_ERR_BASE + 0x000) /**< UUID list does not contain an integral number of UUIDs. */ -#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST (NRF_GAP_ERR_BASE + 0x001) /**< Use of Whitelist not permitted with discoverable advertising. */ -#define BLE_ERROR_GAP_INVALID_BLE_ADDR (NRF_GAP_ERR_BASE + 0x002) /**< The upper two bits of the address do not correspond to the specified address type. */ -#define BLE_ERROR_GAP_WHITELIST_IN_USE (NRF_GAP_ERR_BASE + 0x003) /**< Attempt to overwrite the whitelist while already in use by another operation. */ -/**@} */ - - -/**@defgroup BLE_GAP_ROLES GAP Roles - * @note Not explicitly used in peripheral API, but will be relevant for central API. - * @{ */ -#define BLE_GAP_ROLE_INVALID 0x0 /**< Invalid Role. */ -#define BLE_GAP_ROLE_PERIPH 0x1 /**< Peripheral Role. */ -#define BLE_GAP_ROLE_CENTRAL 0x2 /**< Central Role. */ -/**@} */ - - -/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources - * @{ */ -#define BLE_GAP_TIMEOUT_SRC_ADVERTISING 0x00 /**< Advertising timeout. */ -#define BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST 0x01 /**< Security request timeout. */ -#define BLE_GAP_TIMEOUT_SRC_SCAN 0x02 /**< Scanning timeout. */ -#define BLE_GAP_TIMEOUT_SRC_CONN 0x03 /**< Connection timeout. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types - * @{ */ -#define BLE_GAP_ADDR_TYPE_PUBLIC 0x00 /**< Public address. */ -#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC 0x01 /**< Random Static address. */ -#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE 0x02 /**< Private Resolvable address. */ -#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Private Non-Resolvable address. */ -/**@} */ - -/**@defgroup BLE_GAP_ADDR_CYCLE_MODES GAP Address cycle modes - * @{ */ -#define BLE_GAP_ADDR_CYCLE_MODE_NONE 0x00 /**< Set addresses directly, no automatic address cycling. */ -#define BLE_GAP_ADDR_CYCLE_MODE_AUTO 0x01 /**< Automatically generate and update private addresses. */ -/** @} */ - -/**@brief The default interval in seconds at which a private address is refreshed when address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO. */ -#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (60 * 15) - -/** @brief BLE address length. */ -#define BLE_GAP_ADDR_LEN 6 - - -/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format - * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm - * @{ */ -#define BLE_GAP_AD_TYPE_FLAGS 0x01 /**< Flags for discoverability. */ -#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE 0x02 /**< Partial list of 16 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE 0x03 /**< Complete list of 16 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE 0x04 /**< Partial list of 32 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE 0x05 /**< Complete list of 32 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE 0x06 /**< Partial list of 128 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE 0x07 /**< Complete list of 128 bit service UUIDs. */ -#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME 0x08 /**< Short local device name. */ -#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME 0x09 /**< Complete local device name. */ -#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL 0x0A /**< Transmit power level. */ -#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE 0x0D /**< Class of device. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C 0x0E /**< Simple Pairing Hash C. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R 0x0F /**< Simple Pairing Randomizer R. */ -#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE 0x10 /**< Security Manager TK Value. */ -#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS 0x11 /**< Security Manager Out Of Band Flags. */ -#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE 0x12 /**< Slave Connection Interval Range. */ -#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT 0x14 /**< List of 16-bit Service Solicitation UUIDs. */ -#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT 0x15 /**< List of 128-bit Service Solicitation UUIDs. */ -#define BLE_GAP_AD_TYPE_SERVICE_DATA 0x16 /**< Service Data - 16-bit UUID. */ -#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS 0x17 /**< Public Target Address. */ -#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS 0x18 /**< Random Target Address. */ -#define BLE_GAP_AD_TYPE_APPEARANCE 0x19 /**< Appearance. */ -#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL 0x1A /**< Advertising Interval. */ -#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS 0x1B /**< LE Bluetooth Device Address. */ -#define BLE_GAP_AD_TYPE_LE_ROLE 0x1C /**< LE Role. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256 0x1D /**< Simple Pairing Hash C-256. */ -#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256 0x1E /**< Simple Pairing Randomizer R-256. */ -#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID 0x20 /**< Service Data - 32-bit UUID. */ -#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID 0x21 /**< Service Data - 128-bit UUID. */ -#define BLE_GAP_AD_TYPE_URI 0x24 /**< URI */ -#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA 0x3D /**< 3D Information Data. */ -#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA 0xFF /**< Manufacturer Specific Data. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags - * @{ */ -#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE (0x01) /**< LE Limited Discoverable Mode. */ -#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE (0x02) /**< LE General Discoverable Mode. */ -#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED (0x04) /**< BR/EDR not supported. */ -#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER (0x08) /**< Simultaneous LE and BR/EDR, Controller. */ -#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST (0x10) /**< Simultaneous LE and BR/EDR, Host. */ -#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE Limited Discoverable Mode, BR/EDR not supported. */ -#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) /**< LE General Discoverable Mode, BR/EDR not supported. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min - * @{ */ -#define BLE_GAP_ADV_INTERVAL_MIN 0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */ -#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */ -#define BLE_GAP_ADV_INTERVAL_MAX 0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */ - /**@} */ - - -/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min - * @{ */ -#define BLE_GAP_SCAN_INTERVAL_MIN 0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */ -#define BLE_GAP_SCAN_INTERVAL_MAX 0x4000 /**< Maximum Scan interval in 625 us units, i.e. 10.24 s. */ - /** @} */ - - -/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min - * @{ */ -#define BLE_GAP_SCAN_WINDOW_MIN 0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */ -#define BLE_GAP_SCAN_WINDOW_MAX 0x4000 /**< Maximum Scan window in 625 us units, i.e. 10.24 s. */ - /** @} */ - - -/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min - * @{ */ -#define BLE_GAP_SCAN_TIMEOUT_MIN 0x0001 /**< Minimum Scan timeout in seconds. */ -#define BLE_GAP_SCAN_TIMEOUT_MAX 0xFFFF /**< Maximum Scan timeout in seconds. */ - /** @} */ - - -/**@brief Maximum size of advertising data in octets. */ -#define BLE_GAP_ADV_MAX_SIZE 31 - - -/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types - * @{ */ -#define BLE_GAP_ADV_TYPE_ADV_IND 0x00 /**< Connectable undirected. */ -#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND 0x01 /**< Connectable directed. */ -#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND 0x02 /**< Scannable undirected. */ -#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND 0x03 /**< Non connectable undirected. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies - * @{ */ -#define BLE_GAP_ADV_FP_ANY 0x00 /**< Allow scan requests and connect requests from any device. */ -#define BLE_GAP_ADV_FP_FILTER_SCANREQ 0x01 /**< Filter scan requests with whitelist. */ -#define BLE_GAP_ADV_FP_FILTER_CONNREQ 0x02 /**< Filter connect requests with whitelist. */ -#define BLE_GAP_ADV_FP_FILTER_BOTH 0x03 /**< Filter both scan and connect requests with whitelist. */ -/**@} */ - - -/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values - * @{ */ -#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX 180 /**< Maximum advertising time in limited discoverable mode (TGAP(lim_adv_timeout) = 180s). */ -#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED 0 /**< Unlimited advertising in general discoverable mode. */ -/**@} */ - - -/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes - * @{ */ -#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE 0x00 /**< Not discoverable discovery Mode. */ -#define BLE_GAP_DISC_MODE_LIMITED 0x01 /**< Limited Discovery Mode. */ -#define BLE_GAP_DISC_MODE_GENERAL 0x02 /**< General Discovery Mode. */ -/**@} */ - -/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities - * @{ */ -#define BLE_GAP_IO_CAPS_DISPLAY_ONLY 0x00 /**< Display Only. */ -#define BLE_GAP_IO_CAPS_DISPLAY_YESNO 0x01 /**< Display and Yes/No entry. */ -#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY 0x02 /**< Keyboard Only. */ -#define BLE_GAP_IO_CAPS_NONE 0x03 /**< No I/O capabilities. */ -#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY 0x04 /**< Keyboard and Display. */ -/**@} */ - -/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types - * @{ */ -#define BLE_GAP_AUTH_KEY_TYPE_NONE 0x00 /**< No key (may be used to reject). */ -#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY 0x01 /**< 6-digit Passkey. */ -#define BLE_GAP_AUTH_KEY_TYPE_OOB 0x02 /**< Out Of Band data. */ -/**@} */ - -/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types - * @{ */ -#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START 0x00 /**< Passkey entry started. */ -#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN 0x01 /**< Passkey digit entered. */ -#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT 0x02 /**< Passkey digit erased. */ -#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR 0x03 /**< Passkey cleared. */ -#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END 0x04 /**< Passkey entry completed. */ -/**@} */ - -/**@defgroup BLE_GAP_SEC_STATUS GAP Security status - * @{ */ -#define BLE_GAP_SEC_STATUS_SUCCESS 0x00 /**< Procedure completed with success. */ -#define BLE_GAP_SEC_STATUS_TIMEOUT 0x01 /**< Procedure timed out. */ -#define BLE_GAP_SEC_STATUS_PDU_INVALID 0x02 /**< Invalid PDU received. */ -#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN 0x03 /**< Reserved for Future Use range #1 begin. */ -#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END 0x80 /**< Reserved for Future Use range #1 end. */ -#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED 0x81 /**< Passkey entry failed (user cancelled or other). */ -#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE 0x82 /**< Out of Band Key not available. */ -#define BLE_GAP_SEC_STATUS_AUTH_REQ 0x83 /**< Authentication requirements not met. */ -#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE 0x84 /**< Confirm value failed. */ -#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP 0x85 /**< Pairing not supported. */ -#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE 0x86 /**< Encryption key size. */ -#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED 0x87 /**< Unsupported SMP command. */ -#define BLE_GAP_SEC_STATUS_UNSPECIFIED 0x88 /**< Unspecified reason. */ -#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS 0x89 /**< Too little time elapsed since last attempt. */ -#define BLE_GAP_SEC_STATUS_INVALID_PARAMS 0x8A /**< Invalid parameters. */ -#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE 0x8B /**< DHKey check failure. */ -#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE 0x8C /**< Numeric Comparison failure. */ -#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG 0x8D /**< BR/EDR pairing in progress. */ -#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E /**< BR/EDR Link Key cannot be used for LE keys. */ -#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN 0x8F /**< Reserved for Future Use range #2 begin. */ -#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END 0xFF /**< Reserved for Future Use range #2 end. */ -/**@} */ - -/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources - * @{ */ -#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL 0x00 /**< Local failure. */ -#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE 0x01 /**< Remote failure. */ -/**@} */ - -/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits - * @{ */ -#define BLE_GAP_CP_MIN_CONN_INTVL_NONE 0xFFFF /**< No new minimum connection interval specified in connect parameters. */ -#define BLE_GAP_CP_MIN_CONN_INTVL_MIN 0x0006 /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ -#define BLE_GAP_CP_MIN_CONN_INTVL_MAX 0x0C80 /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ -#define BLE_GAP_CP_MAX_CONN_INTVL_NONE 0xFFFF /**< No new maximum connection interval specified in connect parameters. */ -#define BLE_GAP_CP_MAX_CONN_INTVL_MIN 0x0006 /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */ -#define BLE_GAP_CP_MAX_CONN_INTVL_MAX 0x0C80 /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */ -#define BLE_GAP_CP_SLAVE_LATENCY_MAX 0x01F3 /**< Highest slave latency permitted, in connection events. */ -#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE 0xFFFF /**< No new supervision timeout specified in connect parameters. */ -#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN 0x000A /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */ -#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX 0x0C80 /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */ -/**@} */ - - -/**@brief GAP device name maximum length. */ -#define BLE_GAP_DEVNAME_MAX_LEN 31 - -/**@brief Disable RSSI events for connections */ -#define BLE_GAP_RSSI_THRESHOLD_INVALID 0xFF - -/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters - * - * See @ref ble_gap_conn_sec_mode_t. - * @{ */ -/**@brief Set sec_mode pointed to by ptr to have no access rights.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr) do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0) -/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr) do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0) -/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0) -/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0) -/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0) -/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0) -/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/ -#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr) do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0) -/**@} */ - - -/**@brief GAP Security Random Number Length. */ -#define BLE_GAP_SEC_RAND_LEN 8 - -/**@brief GAP Security Key Length. */ -#define BLE_GAP_SEC_KEY_LEN 16 - -/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */ -#define BLE_GAP_LESC_P256_PK_LEN 64 - -/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */ -#define BLE_GAP_LESC_DHKEY_LEN 32 - -/**@brief GAP Passkey Length. */ -#define BLE_GAP_PASSKEY_LEN 6 - -/**@brief Maximum amount of addresses in a whitelist. */ -#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8) - -/**@brief Maximum amount of IRKs in a whitelist. - * @note The number of IRKs is limited to 8, even if the hardware supports more. - */ -#define BLE_GAP_WHITELIST_IRK_MAX_COUNT (8) - -/**@defgroup GAP_SEC_MODES GAP Security Modes - * @{ */ -#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */ -/**@} */ -/** @} */ - -/**@addtogroup BLE_GAP_STRUCTURES Structures - * @{ */ - -/** - * @brief BLE GAP initialization parameters. - */ -typedef struct -{ - uint8_t periph_conn_count; /**< Number of connections acting as a peripheral */ - uint8_t central_conn_count; /**< Number of connections acting as a central */ - uint8_t central_sec_count; /**< Number of SMP instances for all connections acting as a central. */ -} ble_gap_enable_params_t; - -/**@brief Bluetooth Low Energy address. */ -typedef struct -{ - uint8_t addr_type; /**< See @ref BLE_GAP_ADDR_TYPES. */ - uint8_t addr[BLE_GAP_ADDR_LEN]; /**< 48-bit address, LSB format. */ -} ble_gap_addr_t; - - -/**@brief GAP connection parameters. - * - * @note When ble_conn_params_t is received in an event, both min_conn_interval and - * max_conn_interval will be equal to the connection interval set by the central. - * - * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies: - * conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval - * that corresponds to the following Bluetooth Spec requirement: - * The Supervision_Timeout in milliseconds shall be larger than - * (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds. - */ -typedef struct -{ - uint16_t min_conn_interval; /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t max_conn_interval; /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t slave_latency; /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/ - uint16_t conn_sup_timeout; /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/ -} ble_gap_conn_params_t; - - -/**@brief GAP connection security modes. - * - * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n - * Security Mode 1 Level 1: No security is needed (aka open link).\n - * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n - * Security Mode 1 Level 3: MITM protected encrypted link required.\n - * Security Mode 1 Level 4: LESC MITM protected encrypted link required.\n - * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n - * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n - */ -typedef struct -{ - uint8_t sm : 4; /**< Security Mode (1 or 2), 0 for no permissions at all. */ - uint8_t lv : 4; /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */ - -} ble_gap_conn_sec_mode_t; - - -/**@brief GAP connection security status.*/ -typedef struct -{ - ble_gap_conn_sec_mode_t sec_mode; /**< Currently active security mode for this connection.*/ - uint8_t encr_key_size; /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */ -} ble_gap_conn_sec_t; - - -/**@brief Identity Resolving Key. */ -typedef struct -{ - uint8_t irk[BLE_GAP_SEC_KEY_LEN]; /**< Array containing IRK. */ -} ble_gap_irk_t; - - -/**@brief Whitelist structure. */ -typedef struct -{ - ble_gap_addr_t **pp_addrs; /**< Pointer to an array of device address pointers, pointing to addresses to be used in whitelist. NULL if none are given. */ - uint8_t addr_count; /**< Count of device addresses in array, up to @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. */ - ble_gap_irk_t **pp_irks; /**< Pointer to an array of Identity Resolving Key (IRK) pointers, each pointing to an IRK in the whitelist. NULL if none are given. */ - uint8_t irk_count; /**< Count of IRKs in array, up to @ref BLE_GAP_WHITELIST_IRK_MAX_COUNT. */ -} ble_gap_whitelist_t; - -/**@brief Channel mask for RF channels used in advertising. */ -typedef struct -{ - uint8_t ch_37_off : 1; /**< Setting this bit to 1 will turn off advertising on channel 37 */ - uint8_t ch_38_off : 1; /**< Setting this bit to 1 will turn off advertising on channel 38 */ - uint8_t ch_39_off : 1; /**< Setting this bit to 1 will turn off advertising on channel 39 */ -} ble_gap_adv_ch_mask_t; - -/**@brief GAP advertising parameters.*/ -typedef struct -{ - uint8_t type; /**< See @ref BLE_GAP_ADV_TYPES. */ - ble_gap_addr_t *p_peer_addr; /**< For @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND mode only, known peer address. */ - uint8_t fp; /**< Filter Policy, see @ref BLE_GAP_ADV_FILTER_POLICIES. */ - ble_gap_whitelist_t *p_whitelist; /**< Pointer to whitelist, NULL if no whitelist or the current active whitelist is to be used. */ - uint16_t interval; /**< Advertising interval between 0x0020 and 0x4000 in 0.625 ms units (20ms to 10.24s), see @ref BLE_GAP_ADV_INTERVALS. - - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for high duty cycle directed advertising. - - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, set @ref BLE_GAP_ADV_INTERVAL_MIN <= interval <= @ref BLE_GAP_ADV_INTERVAL_MAX for low duty cycle advertising.*/ - uint16_t timeout; /**< Advertising timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. See also @ref BLE_GAP_ADV_TIMEOUT_VALUES. If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for High duty cycle directed advertising. */ - ble_gap_adv_ch_mask_t channel_mask; /**< Advertising channel mask. See @ref ble_gap_adv_ch_mask_t. */ -} ble_gap_adv_params_t; - - -/**@brief GAP scanning parameters. */ -typedef struct -{ - uint8_t active : 1; /**< If 1, perform active scanning (scan requests). */ - uint8_t selective : 1; /**< If 1, ignore unknown devices (non whitelisted). */ - ble_gap_whitelist_t * p_whitelist; /**< Pointer to whitelist, NULL if no whitelist or the current active whitelist is to be used. */ - uint16_t interval; /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */ - uint16_t window; /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */ - uint16_t timeout; /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */ -} ble_gap_scan_params_t; - - -/** @brief Keys that can be exchanged during a bonding procedure. */ -typedef struct -{ - uint8_t enc : 1; /**< Long Term Key and Master Identification. */ - uint8_t id : 1; /**< Identity Resolving Key and Identity Address Information. */ - uint8_t sign : 1; /**< Connection Signature Resolving Key. */ - uint8_t link : 1; /**< Derive the Link Key from the LTK. */ -} ble_gap_sec_kdist_t; - - -/**@brief GAP security parameters. */ -typedef struct -{ - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Enable Man In The Middle protection. */ - uint8_t lesc : 1; /**< Enable LE Secure Connection pairing. */ - uint8_t keypress : 1; /**< Enable generation of keypress notifications. */ - uint8_t io_caps : 3; /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */ - uint8_t oob : 1; /**< Out Of Band data available. */ - uint8_t min_key_size; /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */ - uint8_t max_key_size; /**< Maximum encryption key size in octets between min_key_size and 16. */ - ble_gap_sec_kdist_t kdist_own; /**< Key distribution bitmap: keys that the local device will distribute. */ - ble_gap_sec_kdist_t kdist_peer; /**< Key distribution bitmap: keys that the remote device will distribute. */ -} ble_gap_sec_params_t; - - -/**@brief GAP Encryption Information. */ -typedef struct -{ - uint8_t ltk[BLE_GAP_SEC_KEY_LEN]; /**< Long Term Key. */ - uint8_t lesc : 1; /**< Key generated using LE Secure Connections. */ - uint8_t auth : 1; /**< Authenticated Key. */ - uint8_t ltk_len : 6; /**< LTK length in octets. */ -} ble_gap_enc_info_t; - - -/**@brief GAP Master Identification. */ -typedef struct -{ - uint16_t ediv; /**< Encrypted Diversifier. */ - uint8_t rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */ -} ble_gap_master_id_t; - - -/**@brief GAP Signing Information. */ -typedef struct -{ - uint8_t csrk[BLE_GAP_SEC_KEY_LEN]; /**< Connection Signature Resolving Key. */ -} ble_gap_sign_info_t; - -/**@brief GAP LE Secure Connections P-256 Public Key. */ -typedef struct -{ - uint8_t pk[BLE_GAP_LESC_P256_PK_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */ -} ble_gap_lesc_p256_pk_t; - -/**@brief GAP LE Secure Connections DHKey. */ -typedef struct -{ - uint8_t key[BLE_GAP_LESC_DHKEY_LEN]; /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */ -} ble_gap_lesc_dhkey_t; - -/**@brief GAP LE Secure Connections OOB data. */ -typedef struct -{ - ble_gap_addr_t addr; /**< Bluetooth address of the device. */ - uint8_t r[BLE_GAP_SEC_KEY_LEN]; /**< Random Number. */ - uint8_t c[BLE_GAP_SEC_KEY_LEN]; /**< Confirm Value. */ -} ble_gap_lesc_oob_data_t; - -/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */ -typedef struct -{ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - ble_gap_addr_t own_addr; /**< Bluetooth address of the local device used during connection setup. */ - uint8_t role; /**< BLE role for this connection, see @ref BLE_GAP_ROLES */ - uint8_t irk_match :1; /**< If 1, peer device's address resolved using an IRK. */ - uint8_t irk_match_idx :7; /**< Index in IRK list where the address was matched. */ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ -} ble_gap_evt_connected_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */ -typedef struct -{ - uint8_t reason; /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */ -} ble_gap_evt_disconnected_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */ -typedef struct -{ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ -} ble_gap_evt_conn_param_update_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */ -typedef struct -{ - ble_gap_sec_params_t peer_params; /**< Initiator Security Parameters. */ -} ble_gap_evt_sec_params_request_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */ -typedef struct -{ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - ble_gap_master_id_t master_id; /**< Master Identification for LTK lookup. */ - uint8_t enc_info : 1; /**< If 1, Encryption Information required. */ - uint8_t id_info : 1; /**< If 1, Identity Information required. */ - uint8_t sign_info : 1; /**< If 1, Signing Information required. */ -} ble_gap_evt_sec_info_request_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */ -typedef struct -{ - uint8_t passkey[BLE_GAP_PASSKEY_LEN]; /**< 6-digit passkey in ASCII ('0'-'9' digits only). */ - uint8_t match_request : 1; /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply - with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or - @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */ -} ble_gap_evt_passkey_display_t; - -/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */ -typedef struct -{ - uint8_t kp_not; /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */ -} ble_gap_evt_key_pressed_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */ -typedef struct -{ - uint8_t key_type; /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */ -} ble_gap_evt_auth_key_request_t; - -/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */ -typedef struct -{ - ble_gap_lesc_p256_pk_t *p_pk_peer; /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory - inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */ - uint8_t oobd_req :1; /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */ -} ble_gap_evt_lesc_dhkey_request_t; - - -/**@brief Security levels supported. - * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1. -*/ -typedef struct -{ - uint8_t lv1 : 1; /**< If 1: Level 1 is supported. */ - uint8_t lv2 : 1; /**< If 1: Level 2 is supported. */ - uint8_t lv3 : 1; /**< If 1: Level 3 is supported. */ - uint8_t lv4 : 1; /**< If 1: Level 4 is supported. */ -} ble_gap_sec_levels_t; - - -/**@brief Encryption Key. */ -typedef struct -{ - ble_gap_enc_info_t enc_info; /**< Encryption Information. */ - ble_gap_master_id_t master_id; /**< Master Identification. */ -} ble_gap_enc_key_t; - - -/**@brief Identity Key. */ -typedef struct -{ - ble_gap_irk_t id_info; /**< Identity Information. */ - ble_gap_addr_t id_addr_info; /**< Identity Address Information. */ -} ble_gap_id_key_t; - - -/**@brief Security Keys. */ -typedef struct -{ - ble_gap_enc_key_t *p_enc_key; /**< Encryption Key, or NULL. */ - ble_gap_id_key_t *p_id_key; /**< Identity Key, or NULL. */ - ble_gap_sign_info_t *p_sign_key; /**< Signing Key, or NULL. */ - ble_gap_lesc_p256_pk_t *p_pk; /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined - in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */ -} ble_gap_sec_keys_t; - - -/**@brief Security key set for both local and peer keys. */ -typedef struct -{ - ble_gap_sec_keys_t keys_own; /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */ - ble_gap_sec_keys_t keys_peer; /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */ -} ble_gap_sec_keyset_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */ -typedef struct -{ - uint8_t auth_status; /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */ - uint8_t error_src : 2; /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */ - uint8_t bonded : 1; /**< Procedure resulted in a bond. */ - ble_gap_sec_levels_t sm1_levels; /**< Levels supported in Security Mode 1. */ - ble_gap_sec_levels_t sm2_levels; /**< Levels supported in Security Mode 2. */ - ble_gap_sec_kdist_t kdist_own; /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */ - ble_gap_sec_kdist_t kdist_peer; /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */ -} ble_gap_evt_auth_status_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */ -typedef struct -{ - ble_gap_conn_sec_t conn_sec; /**< Connection security level. */ -} ble_gap_evt_conn_sec_update_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */ -typedef struct -{ - uint8_t src; /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */ -} ble_gap_evt_timeout_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */ -typedef struct -{ - int8_t rssi; /**< Received Signal Strength Indication in dBm. */ -} ble_gap_evt_rssi_changed_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. */ -typedef struct -{ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ - int8_t rssi; /**< Received Signal Strength Indication in dBm. */ - uint8_t scan_rsp : 1; /**< If 1, the report corresponds to a scan response and the type field may be ignored. */ - uint8_t type : 2; /**< See @ref BLE_GAP_ADV_TYPES. Only valid if the scan_rsp field is 0. */ - uint8_t dlen : 5; /**< Advertising or scan response data length. */ - uint8_t data[BLE_GAP_ADV_MAX_SIZE]; /**< Advertising or scan response data. */ -} ble_gap_evt_adv_report_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */ -typedef struct -{ - uint8_t bond : 1; /**< Perform bonding. */ - uint8_t mitm : 1; /**< Man In The Middle protection requested. */ - uint8_t lesc : 1; /**< LE Secure Connections requested. */ - uint8_t keypress : 1; /**< Generation of keypress notifications requested. */ -} ble_gap_evt_sec_request_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */ -typedef struct -{ - ble_gap_conn_params_t conn_params; /**< GAP Connection Parameters. */ -} ble_gap_evt_conn_param_update_request_t; - - -/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */ -typedef struct -{ - int8_t rssi; /**< Received Signal Strength Indication in dBm. */ - ble_gap_addr_t peer_addr; /**< Bluetooth address of the peer device. */ -} ble_gap_evt_scan_req_report_t; - - - -/**@brief GAP event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occurred. */ - union /**< union alternative identified by evt_id in enclosing struct. */ - { - ble_gap_evt_connected_t connected; /**< Connected Event Parameters. */ - ble_gap_evt_disconnected_t disconnected; /**< Disconnected Event Parameters. */ - ble_gap_evt_conn_param_update_t conn_param_update; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_sec_params_request_t sec_params_request; /**< Security Parameters Request Event Parameters. */ - ble_gap_evt_sec_info_request_t sec_info_request; /**< Security Information Request Event Parameters. */ - ble_gap_evt_passkey_display_t passkey_display; /**< Passkey Display Event Parameters. */ - ble_gap_evt_key_pressed_t key_pressed; /**< Key Pressed Event Parameters. */ - ble_gap_evt_auth_key_request_t auth_key_request; /**< Authentication Key Request Event Parameters. */ - ble_gap_evt_lesc_dhkey_request_t lesc_dhkey_request; /**< LE Secure Connections DHKey calculation request. */ - ble_gap_evt_auth_status_t auth_status; /**< Authentication Status Event Parameters. */ - ble_gap_evt_conn_sec_update_t conn_sec_update; /**< Connection Security Update Event Parameters. */ - ble_gap_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gap_evt_rssi_changed_t rssi_changed; /**< RSSI Event parameters. */ - ble_gap_evt_adv_report_t adv_report; /**< Advertising Report Event Parameters. */ - ble_gap_evt_sec_request_t sec_request; /**< Security Request Event Parameters. */ - ble_gap_evt_conn_param_update_request_t conn_param_update_request; /**< Connection Parameter Update Parameters. */ - ble_gap_evt_scan_req_report_t scan_req_report; /**< Scan Request Report parameters. */ - } params; /**< Event Parameters. */ - -} ble_gap_evt_t; - - -/**@brief Channel Map option. - * Used with @ref sd_ble_opt_get to get the current channel map - * or @ref sd_ble_opt_set to set a new channel map. When setting the - * channel map, it applies to all current and future connections. When getting the - * current channel map, it applies to a single connection and the connection handle - * must be supplied. - * - * @note Setting the channel map may take some time, depending on connection parameters. - * The time taken may be different for each connection and the get operation will - * return the previous channel map until the new one has taken effect. - * - * @note After setting the channel map, by spec it can not be set again until at least 1 s has passed. - * See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46. - * - * @retval ::NRF_SUCCESS Get or set successful. - * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get. - * @retval ::NRF_ERROR_NOT_SUPPORTED Returned by sd_ble_opt_set in peripheral-only SoftDevices. - * - */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle (only applicable for get) */ - uint8_t ch_map[5]; /**< Channel Map (37-bit). */ -} ble_gap_opt_ch_map_t; - - -/**@brief Local connection latency option. - * - * Local connection latency is a feature which enables the slave to improve - * current consumption by ignoring the slave latency set by the peer. The - * local connection latency can only be set to a multiple of the slave latency, - * and cannot be longer than half of the supervision timeout. - * - * Used with @ref sd_ble_opt_set to set the local connection latency. The - * @ref sd_ble_opt_get is not supported for this option, but the actual - * local connection latency (unless set to NULL) is set as a return parameter - * when setting the option. - * - * @note The latency set will be truncated down to the closest slave latency event - * multiple, or the nearest multiple before half of the supervision timeout. - * - * @note The local connection latency is disabled by default, and needs to be enabled for new - * connections and whenever the connection is updated. - * - * @retval ::NRF_SUCCESS Set successfully. - * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter. - */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle */ - uint16_t requested_latency; /**< Requested local connection latency. */ - uint16_t * p_actual_latency; /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */ -} ble_gap_opt_local_conn_latency_t; - - -/**@brief Passkey Option. - * - * Structure containing the passkey to be used during pairing. This can be used with @ref - * sd_ble_opt_set to make the SoftDevice use a pre-programmed passkey for authentication - * instead of generating a random one. - * - * @note @ref sd_ble_opt_get is not supported for this option. - * - */ -typedef struct -{ - uint8_t * p_passkey; /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/ -} ble_gap_opt_passkey_t; - - -/**@brief Custom Privacy Option. - * - * This structure is used with both @ref sd_ble_opt_set (as input) and with - * @ref sd_ble_opt_get (as output). - * - * Structure containing: - * - A pointer to an IRK to set (if input), or a place to store a read IRK (if output). - * - A private address refresh cycle. - * - * @note The specified address cycle interval is used when the address cycle mode is - * @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO. If 0 is given, the address will not be automatically - * refreshed at all. The default interval is @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S. - * - * @note If the current address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address will immediately be - * refreshed when a custom privacy option is set. A new address can be generated manually by calling - * @ref sd_ble_gap_address_set with the same type again. - * - * @note If the IRK is updated, the new IRK becomes the one to be distributed in all - * bonding procedures performed after @ref sd_ble_opt_set returns. - * - * @retval ::NRF_SUCCESS Set or read successfully. - * @retval ::NRF_ERROR_INVALID_ADDR The pointer to IRK storage is invalid. - */ -typedef struct -{ - ble_gap_irk_t * p_irk; /**< When input: Pointer to custom IRK, or NULL to use/reset to the device's default IRK. When output: Pointer to where the current IRK is to be stored, or NULL to not read out the IRK. */ - uint16_t interval_s; /**< When input: Custom private address cycle interval in seconds. When output: The current private address cycle interval. */ -} ble_gap_opt_privacy_t; - - -/**@brief Scan request report option. - * - * This can be used with @ref sd_ble_opt_set to make the SoftDevice send - * @ref BLE_GAP_EVT_SCAN_REQ_REPORT events. - * - * @note Due to the limited space reserved for scan request report events, - * not all received scan requests will be reported. - * - * @note If whitelisting is used, only whitelisted requests are reported. - * - * @retval ::NRF_SUCCESS Set successfully. - * @retval ::NRF_ERROR_INVALID_STATE When advertising is ongoing while the option is set. - */ -typedef struct -{ - uint8_t enable : 1; /**< Enable scan request reports. */ -} ble_gap_opt_scan_req_report_t; - -/**@brief Compatibility mode option. - * - * This can be used with @ref sd_ble_opt_set to enable and disable - * compatibility modes. Compatibility modes are disabled by default. - * - * @note Compatibility mode 1 enables interoperability with devices that do not support - * a value of 0 for the WinOffset parameter in the Link Layer CONNECT_REQ packet. - * - * @retval ::NRF_SUCCESS Set successfully. - * @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set. - */ -typedef struct -{ - uint8_t mode_1_enable : 1; /**< Enable compatibility mode 1.*/ -} ble_gap_opt_compat_mode_t; - -/**@brief Option structure for GAP options. */ -typedef union -{ - ble_gap_opt_ch_map_t ch_map; /**< Parameters for the Channel Map option. */ - ble_gap_opt_local_conn_latency_t local_conn_latency; /**< Parameters for the Local connection latency option */ - ble_gap_opt_passkey_t passkey; /**< Parameters for the Passkey option.*/ - ble_gap_opt_privacy_t privacy; /**< Parameters for the Custom privacy option. */ - ble_gap_opt_scan_req_report_t scan_req_report; /**< Parameters for the scan request report option.*/ - ble_gap_opt_compat_mode_t compat_mode; /**< Parameters for the compatibility mode option.*/ -} ble_gap_opt_t; -/**@} */ - - -/**@addtogroup BLE_GAP_FUNCTIONS Functions - * @{ */ - -/**@brief Set local Bluetooth address. - * - * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address type is required to - * be @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or - * @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. The given address is ignored and the - * SoftDevice will generate a new private address automatically every - * @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S seconds. If this API - * call is used again with the same parameters, the SoftDevice will immediately - * generate a new private address to replace the current address. - * - * @note If the application wishes to use a @ref BLE_GAP_ADDR_TYPE_PUBLIC or - * @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC address, the cycle mode must be - * @ref BLE_GAP_ADDR_CYCLE_MODE_NONE. - * - * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being - * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged - * for the lifetime of each IC. - * - * @note If this API function is called while advertising or scanning, the softdevice will immediately update the - * advertising or scanning address without the need to stop the procedure in the following cases: - * - If the previously set address is of type @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address - * is also of type @ref BLE_GAP_ADDR_TYPE_PUBLIC - * - If the previously set address is not @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address is - * also not @ref BLE_GAP_ADDR_TYPE_PUBLIC. - * If the address is changed from a @ref BLE_GAP_ADDR_TYPE_PUBLIC address to another type or from - * another type to a @ref BLE_GAP_ADDR_TYPE_PUBLIC address, the change will take effect the next - * time an advertising or scanning procedure is started. - * - * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_NONE and the application is - * using privacy, the application must take care to generate and set new private addresses - * periodically to comply with the Privacy specification in Bluetooth Core Spec. - * - * @mscs - * @mmsc{@ref BLE_GAP_ADV_MSC} - * @endmscs - * - * @param[in] addr_cycle_mode Address cycle mode, see @ref BLE_GAP_ADDR_CYCLE_MODES. - * @param[in] p_addr Pointer to address structure. - * - * @retval ::NRF_SUCCESS Address successfully set. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters. - * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address. - * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - */ -SVCALL(SD_BLE_GAP_ADDRESS_SET, uint32_t, sd_ble_gap_address_set(uint8_t addr_cycle_mode, ble_gap_addr_t const *p_addr)); - - -/**@brief Get local Bluetooth address. - * - * @param[out] p_addr Pointer to address structure to be filled in. - * - * @retval ::NRF_SUCCESS Address successfully retrieved. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GAP_ADDRESS_GET, uint32_t, sd_ble_gap_address_get(ble_gap_addr_t *p_addr)); - - -/**@brief Set, clear or update advertising and scan response data. - * - * @note The format of the advertising data will be checked by this call to ensure interoperability. - * Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and - * duplicating the local name in the advertising data and scan response data. - * - * @note To clear the advertising data and set it to a 0-length packet, simply provide a valid pointer (p_data/p_sr_data) with its corresponding - * length (dlen/srdlen) set to 0. - * - * @note The call will fail if p_data and p_sr_data are both NULL since this would have no effect. - * - * @mscs - * @mmsc{@ref BLE_GAP_ADV_MSC} - * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} - * @endmscs - * - * @param[in] p_data Raw data to be placed in advertising packet. If NULL, no changes are made to the current advertising packet data. - * @param[in] dlen Data length for p_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_data is NULL, can be 0 if p_data is not NULL. - * @param[in] p_sr_data Raw data to be placed in scan response packet. If NULL, no changes are made to the current scan response packet data. - * @param[in] srdlen Data length for p_sr_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_sr_data is NULL, can be 0 if p_data is not NULL. - * - * @retval ::NRF_SUCCESS Advertising data successfully updated or cleared. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, both p_data and p_sr_data cannot be NULL. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied. - * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied, check the advertising data format specification. - * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied. - * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data type. - * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied. - */ -SVCALL(SD_BLE_GAP_ADV_DATA_SET, uint32_t, sd_ble_gap_adv_data_set(uint8_t const *p_data, uint8_t dlen, uint8_t const *p_sr_data, uint8_t srdlen)); - - -/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). - * - * @note An application can start an advertising procedure for broadcasting purposes while a connection - * is active. After a @ref BLE_GAP_EVT_CONNECTED event is received, this function may therefore - * be called to start a broadcast advertising procedure. The advertising procedure - * cannot however be connectable (it must be of type @ref BLE_GAP_ADV_TYPE_ADV_SCAN_IND or - * @ref BLE_GAP_ADV_TYPE_ADV_NONCONN_IND). @note Only one advertiser may be active at any time. - * - * @note To use the currently active whitelist set p_adv_params->p_whitelist to NULL. - * - * @events - * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.} - * @event{@ref BLE_GAP_EVT_TIMEOUT, Advertisement has timed out.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_ADV_MSC} - * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} - * @endmscs - * - * @param[in] p_adv_params Pointer to advertising parameters structure. - * - * @retval ::NRF_SUCCESS The BLE stack has started advertising. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started. - * @retval ::NRF_ERROR_NO_MEM The configured memory pools (see @ref ble_conn_bw_counts_t) are not large enough for the - * bandwidth selected for this connection. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check the accepted ranges and limits. - * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Bluetooth address supplied. - * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible. - * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. - * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it. - * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. - * Stop one or more currently active roles (Central, Peripheral or Observer) and try again - */ -SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(ble_gap_adv_params_t const *p_adv_params)); - - -/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure). - * - * @mscs - * @mmsc{@ref BLE_GAP_ADV_MSC} - * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} - * @endmscs - * - * @retval ::NRF_SUCCESS The BLE stack has stopped advertising. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in advertising state). - */ -SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(void)); - - -/**@brief Update connection parameters. - * - * @details In the central role this will initiate a Link Layer connection parameter update procedure, - * otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for - * the central to perform the procedure. In both cases, and regardless of success or failure, the application - * will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event. - * - * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested. - * - * @events - * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_CPU_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} - * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC} - * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_conn_params Pointer to desired connection parameters. If NULL is provided on a peripheral role, - * the parameters in the PPCP characteristic of the GAP service will be used instead. - * If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected - * - * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, process pending events and wait for pending procedures to complete and retry. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params)); - - -/**@brief Disconnect (GAP Link Termination). - * - * @details This call initiates the disconnection procedure, and its completion will be communicated to the application - * with a @ref BLE_GAP_EVT_DISCONNECTED event. - * - * @events - * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_CONN_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE). - * - * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (disconnection is already in progress). - */ -SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code)); - - -/**@brief Set the radio's transmit power. - * - * @param[in] tx_power Radio transmit power in dBm (accepted values are -40, -30, -20, -16, -12, -8, -4, 0, and 4 dBm). - * - * @note The -30dBm setting is only available on nRF51 series ICs. - * @note The -40dBm setting is only available on nRF52 series ICs. - * - * @retval ::NRF_SUCCESS Successfully changed the transmit power. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - */ -SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(int8_t tx_power)); - - -/**@brief Set GAP Appearance value. - * - * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES. - * - * @retval ::NRF_SUCCESS Appearance value set successfully. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - */ -SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance)); - - -/**@brief Get GAP Appearance value. - * - * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES. - * - * @retval ::NRF_SUCCESS Appearance value retrieved successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance)); - - -/**@brief Set GAP Peripheral Preferred Connection Parameters. - * - * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters. - * - * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - */ -SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params)); - - -/**@brief Get GAP Peripheral Preferred Connection Parameters. - * - * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored. - * - * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params)); - - -/**@brief Set GAP device name. - * - * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t. - * @param[in] p_dev_name Pointer to a UTF-8 encoded, non NULL-terminated string. - * @param[in] len Length of the UTF-8, non NULL-terminated string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN). - * - * @retval ::NRF_SUCCESS GAP device name and permissions set successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - */ -SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len)); - - -/**@brief Get GAP device name. - * - * @note If the device name is longer than the size of the supplied buffer, - * p_len will return the complete device name length, - * and not the number of bytes actually returned in p_dev_name. - * The application may use this information to allocate a suitable buffer size. - * - * @param[out] p_dev_name Pointer to an empty buffer where the UTF-8 non NULL-terminated string will be placed. Set to NULL to obtain the complete device name length. - * @param[in,out] p_len Length of the buffer pointed by p_dev_name, complete device name length on output. - * - * @retval ::NRF_SUCCESS GAP device name retrieved successfully. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - */ -SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len)); - - -/**@brief Initiate the GAP Authentication procedure. - * - * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected), - * otherwise in the peripheral role, an SMP Security Request will be sent. - * - * @events - * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:} - * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST} - * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST} - * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY} - * @event{@ref BLE_GAP_EVT_KEY_PRESSED} - * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST} - * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST} - * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE} - * @event{@ref BLE_GAP_EVT_AUTH_STATUS} - * @event{@ref BLE_GAP_EVT_TIMEOUT} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure. - * In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used. - * In the central role, this pointer may be NULL to reject a Security Request. - * - * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. - * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. - * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited. - */ -SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params)); - - -/**@brief Reply with GAP security parameters. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * - * @events - * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS. - * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have - * already been provided during a previous call to @ref sd_ble_gap_authenticate. - * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure - * will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application - * upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event. - * Note that the SoftDevice expects the application to provide memory for storing the - * peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key - * can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the - * @ref BLE_GAP_EVT_AUTH_STATUS event. - * - * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported. - */ -SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset)); - - -/**@brief Reply with an authentication key. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * - * @events - * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES. - * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL. - * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination) - * or NULL when confirming LE Secure Connections Numeric Comparison. - * If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in Little Endian format. - * - * @retval ::NRF_SUCCESS Authentication key successfully set. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key)); - -/**@brief Reply with an LE Secure connections DHKey. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * - * @events - * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_dhkey LE Secure Connections DHKey. - * - * @retval ::NRF_SUCCESS DHKey successfully set. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey)); - -/**@brief Notify the peer of a local keypress. - * - * @details This function can only be used when an authentication procedure using LE Secure Connection is in progress. Calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE. - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES. - * - * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either not entering a passkey or keypresses have not been enabled by both peers. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time. - */ -SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not)); - -/**@brief Generate a set of OOB data to send to a peer out of band. - * - * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established, - * the one used during connection setup). The application may manually overwrite it with an updated value. - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. Can be BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet. - * @param[in] p_pk_own LE Secure Connections local P-256 Public Key. - * @param[out] p_oobd_own The OOB data to be sent out of band to a peer. - * - * @retval ::NRF_SUCCESS OOB data successfully generated. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own)); - -/**@brief Provide the OOB data sent/received out of band. - * - * @note At least one of the 2 pointers provided must be different from NULL. - * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function. - * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function. - * - * @events - * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if none sent. - * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received. - * - * @retval ::NRF_SUCCESS OOB data accepted. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer)); - -/**@brief Initiate GAP Encryption procedure. - * - * @details In the central role, this function will initiate the encryption procedure using the encryption information provided. - * - * @events - * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC} - * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure. - * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. - * - * @retval ::NRF_SUCCESS Successfully initiated authentication procedure. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role. - * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry. - */ -SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info)); - - -/**@brief Reply with GAP security information. - * - * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE. - * @note If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters. - * @note Data signing is not yet supported, and p_sign_info must therefore be NULL. - * - * @mscs - * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available. - * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available. - * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available. - * - * @retval ::NRF_SUCCESS Successfully accepted security information. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info)); - - -/**@brief Get the current connection security. - * - * @param[in] conn_handle Connection handle. - * @param[out] p_conn_sec Pointer to a @ref ble_gap_conn_sec_t structure to be filled in. - * - * @retval ::NRF_SUCCESS Current connection security successfully retrieved. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec)); - - -/**@brief Start reporting the received signal strength to the application. - * - * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called. - * - * @events - * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is - dependent on the settings of the threshold_dbm - and skip_count input parameters.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} - * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] threshold_dbm Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID. - * @param[in] skip_count Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event. - * - * @retval ::NRF_SUCCESS Successfully activated RSSI reporting. - * @retval ::NRF_ERROR_INVALID_STATE Disconnection in progress. Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count)); - - -/**@brief Stop reporting the received signal strength. - * - * @note An RSSI change detected before the call but not yet received by the application - * may be reported after @ref sd_ble_gap_rssi_stop has been called. - * - * @mscs - * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} - * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * - * @retval ::NRF_SUCCESS Successfully deactivated RSSI reporting. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - */ -SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle)); - - -/**@brief Get the received signal strength for the last connection event. - * - * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND - * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start. - * - * @mscs - * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[out] p_rssi Pointer to the location where the RSSI measurement shall be stored. - * - * @retval ::NRF_SUCCESS Successfully read the RSSI. - * @retval ::NRF_ERROR_NOT_FOUND No sample is available. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::NRF_ERROR_INVALID_STATE RSSI reporting is not ongoing, or disconnection in progress. - */ -SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi)); - - -/**@brief Start scanning (GAP Discovery procedure, Observer Procedure). - * - * @note To use the currently active whitelist set p_scan_params->p_whitelist to NULL. - * - * @events - * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.} - * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GAP_SCAN_MSC} - * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} - * @endmscs - * - * @param[in] p_scan_params Pointer to scan parameters structure. - * - * @retval ::NRF_SUCCESS Successfully initiated scanning procedure. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. - * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it. - * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. - * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again - */ -SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params)); - - -/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure). - * - * @mscs - * @mmsc{@ref BLE_GAP_SCAN_MSC} - * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} - * @endmscs - * - * @retval ::NRF_SUCCESS Successfully stopped scanning procedure. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in scanning state). - */ -SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void)); - - -/**@brief Create a connection (GAP Link Establishment). - * - * @note To use the currently active whitelist set p_scan_params->p_whitelist to NULL. - * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function. - * - * @mscs - * @mmsc{@ref BLE_GAP_WL_SHARE_MSC} - * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} - * @endmscs - * - * @param[in] p_peer_addr Pointer to peer address. If the selective bit is set in @ref ble_gap_scan_params_t, then this must be NULL. - * @param[in] p_scan_params Pointer to scan parameters structure. - * @param[in] p_conn_params Pointer to desired connection parameters. - * - * @retval ::NRF_SUCCESS Successfully initiated connection procedure. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address. - * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached. - * @retval ::NRF_ERROR_NO_MEM The configured memory pool (see @ref ble_conn_bw_counts_t) is not large enough for the - * bandwidth selected for this connection. - * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. If another connection is being established - * wait for the corresponding @ref BLE_GAP_EVT_CONNECTED event before calling again. - * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it. - * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available. - * Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again - */ -SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params)); - - -/**@brief Cancel a connection establishment. - * - * @mscs - * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC} - * @endmscs - * - * @retval ::NRF_SUCCESS Successfully cancelled an ongoing connection procedure. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - */ -SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void)); - -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif // NRF_BLE_GAP_H__ - -/** - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatt.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatt.h deleted file mode 100644 index c7023502bd..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatt.h +++ /dev/null @@ -1,215 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common - @{ - @brief Common definitions and prototypes for the GATT interfaces. - */ - -#ifndef NRF_BLE_GATT_H__ -#define NRF_BLE_GATT_H__ - -#include "nrf_ble_types.h" -#include "nrf_ble_ranges.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup BLE_GATT_DEFINES Defines - * @{ */ - -/** @brief Default MTU size. */ -#define GATT_MTU_SIZE_DEFAULT 23 - -/** @brief Only the default MTU size of 23 is currently supported. */ -#define GATT_RX_MTU 23 - - -/**@brief Invalid Attribute Handle. */ -#define BLE_GATT_HANDLE_INVALID 0x0000 - -/**@brief First Attribute Handle. */ -#define BLE_GATT_HANDLE_START 0x0001 - -/**@brief Last Attribute Handle. */ -#define BLE_GATT_HANDLE_END 0xFFFF - -/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources - * @{ */ -#define BLE_GATT_TIMEOUT_SRC_PROTOCOL 0x00 /**< ATT Protocol timeout. */ -/** @} */ - -/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations - * @{ */ -#define BLE_GATT_OP_INVALID 0x00 /**< Invalid Operation. */ -#define BLE_GATT_OP_WRITE_REQ 0x01 /**< Write Request. */ -#define BLE_GATT_OP_WRITE_CMD 0x02 /**< Write Command. */ -#define BLE_GATT_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ -#define BLE_GATT_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ -#define BLE_GATT_OP_EXEC_WRITE_REQ 0x05 /**< Execute Write Request. */ -/** @} */ - -/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags - * @{ */ -#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00 -#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE 0x01 -/** @} */ - -/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations - * @{ */ -#define BLE_GATT_HVX_INVALID 0x00 /**< Invalid Operation. */ -#define BLE_GATT_HVX_NOTIFICATION 0x01 /**< Handle Value Notification. */ -#define BLE_GATT_HVX_INDICATION 0x02 /**< Handle Value Indication. */ -/** @} */ - -/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes - * @{ */ -#define BLE_GATT_STATUS_SUCCESS 0x0000 /**< Success. */ -#define BLE_GATT_STATUS_UNKNOWN 0x0001 /**< Unknown or not applicable status. */ -#define BLE_GATT_STATUS_ATTERR_INVALID 0x0100 /**< ATT Error: Invalid Error Code. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE 0x0101 /**< ATT Error: Invalid Attribute Handle. */ -#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED 0x0102 /**< ATT Error: Read not permitted. */ -#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED 0x0103 /**< ATT Error: Write not permitted. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_PDU 0x0104 /**< ATT Error: Used in ATT as Invalid PDU. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION 0x0105 /**< ATT Error: Authenticated link required. */ -#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED 0x0106 /**< ATT Error: Used in ATT as Request Not Supported. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET 0x0107 /**< ATT Error: Offset specified was past the end of the attribute. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION 0x0108 /**< ATT Error: Used in ATT as Insufficient Authorisation. */ -#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL 0x0109 /**< ATT Error: Used in ATT as Prepare Queue Full. */ -#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND 0x010A /**< ATT Error: Used in ATT as Attribute not found. */ -#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG 0x010B /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE 0x010C /**< ATT Error: Encryption key size used is insufficient. */ -#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH 0x010D /**< ATT Error: Invalid value size. */ -#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR 0x010E /**< ATT Error: Very unlikely error. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION 0x010F /**< ATT Error: Encrypted link required. */ -#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE 0x0110 /**< ATT Error: Attribute type is not a supported grouping attribute. */ -#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES 0x0111 /**< ATT Error: Encrypted link required. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN 0x0112 /**< ATT Error: Reserved for Future Use range #1 begin. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END 0x017F /**< ATT Error: Reserved for Future Use range #1 end. */ -#define BLE_GATT_STATUS_ATTERR_APP_BEGIN 0x0180 /**< ATT Error: Application range begin. */ -#define BLE_GATT_STATUS_ATTERR_APP_END 0x019F /**< ATT Error: Application range end. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN 0x01A0 /**< ATT Error: Reserved for Future Use range #2 begin. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END 0x01DF /**< ATT Error: Reserved for Future Use range #2 end. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN 0x01E0 /**< ATT Error: Reserved for Future Use range #3 begin. */ -#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END 0x01FC /**< ATT Error: Reserved for Future Use range #3 end. */ -#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR 0x01FD /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */ -#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG 0x01FE /**< ATT Common Profile and Service Error: Procedure Already in Progress. */ -#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE 0x01FF /**< ATT Common Profile and Service Error: Out Of Range. */ -/** @} */ - - -/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats - * @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml - * @{ */ -#define BLE_GATT_CPF_FORMAT_RFU 0x00 /**< Reserved For Future Use. */ -#define BLE_GATT_CPF_FORMAT_BOOLEAN 0x01 /**< Boolean. */ -#define BLE_GATT_CPF_FORMAT_2BIT 0x02 /**< Unsigned 2-bit integer. */ -#define BLE_GATT_CPF_FORMAT_NIBBLE 0x03 /**< Unsigned 4-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT8 0x04 /**< Unsigned 8-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT12 0x05 /**< Unsigned 12-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT16 0x06 /**< Unsigned 16-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT24 0x07 /**< Unsigned 24-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT32 0x08 /**< Unsigned 32-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT48 0x09 /**< Unsigned 48-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT64 0x0A /**< Unsigned 64-bit integer. */ -#define BLE_GATT_CPF_FORMAT_UINT128 0x0B /**< Unsigned 128-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT8 0x0C /**< Signed 2-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT12 0x0D /**< Signed 12-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT16 0x0E /**< Signed 16-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT24 0x0F /**< Signed 24-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT32 0x10 /**< Signed 32-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT48 0x11 /**< Signed 48-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT64 0x12 /**< Signed 64-bit integer. */ -#define BLE_GATT_CPF_FORMAT_SINT128 0x13 /**< Signed 128-bit integer. */ -#define BLE_GATT_CPF_FORMAT_FLOAT32 0x14 /**< IEEE-754 32-bit floating point. */ -#define BLE_GATT_CPF_FORMAT_FLOAT64 0x15 /**< IEEE-754 64-bit floating point. */ -#define BLE_GATT_CPF_FORMAT_SFLOAT 0x16 /**< IEEE-11073 16-bit SFLOAT. */ -#define BLE_GATT_CPF_FORMAT_FLOAT 0x17 /**< IEEE-11073 32-bit FLOAT. */ -#define BLE_GATT_CPF_FORMAT_DUINT16 0x18 /**< IEEE-20601 format. */ -#define BLE_GATT_CPF_FORMAT_UTF8S 0x19 /**< UTF-8 string. */ -#define BLE_GATT_CPF_FORMAT_UTF16S 0x1A /**< UTF-16 string. */ -#define BLE_GATT_CPF_FORMAT_STRUCT 0x1B /**< Opaque Structure. */ -/** @} */ - -/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces - * @{ - */ -#define BLE_GATT_CPF_NAMESPACE_BTSIG 0x01 /**< Bluetooth SIG defined Namespace. */ -#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */ -/** @} */ - -/** @} */ - -/** @addtogroup BLE_GATT_STRUCTURES Structures - * @{ */ - -/**@brief GATT Characteristic Properties. */ -typedef struct -{ - /* Standard properties */ - uint8_t broadcast :1; /**< Broadcasting of the value permitted. */ - uint8_t read :1; /**< Reading the value permitted. */ - uint8_t write_wo_resp :1; /**< Writing the value with Write Command permitted. */ - uint8_t write :1; /**< Writing the value with Write Request permitted. */ - uint8_t notify :1; /**< Notications of the value permitted. */ - uint8_t indicate :1; /**< Indications of the value permitted. */ - uint8_t auth_signed_wr :1; /**< Writing the value with Signed Write Command permitted. */ -} ble_gatt_char_props_t; - -/**@brief GATT Characteristic Extended Properties. */ -typedef struct -{ - /* Extended properties */ - uint8_t reliable_wr :1; /**< Writing the value with Queued Write operations permitted. */ - uint8_t wr_aux :1; /**< Writing the Characteristic User Description descriptor permitted. */ -} ble_gatt_char_ext_props_t; - -#ifdef __cplusplus -} -#endif -#endif // NRF_BLE_GATT_H__ - -/** @} */ - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h deleted file mode 100644 index 5aa20fe430..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h +++ /dev/null @@ -1,572 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client - @{ - @brief Definitions and prototypes for the GATT Client interface. - */ - -#ifndef NRF_BLE_GATTC_H__ -#define NRF_BLE_GATTC_H__ - -#include "nrf_ble_gatt.h" -#include "nrf_ble_types.h" -#include "nrf_ble_ranges.h" -#include "nrf_svc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations - * @{ */ - -/**@brief GATTC API SVC numbers. */ -enum BLE_GATTC_SVCS -{ - SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */ - SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, /**< Relationship Discovery. */ - SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, /**< Characteristic Discovery. */ - SD_BLE_GATTC_DESCRIPTORS_DISCOVER, /**< Characteristic Descriptor Discovery. */ - SD_BLE_GATTC_ATTR_INFO_DISCOVER, /**< Attribute Information Discovery. */ - SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, /**< Read Characteristic Value by UUID. */ - SD_BLE_GATTC_READ, /**< Generic read. */ - SD_BLE_GATTC_CHAR_VALUES_READ, /**< Read multiple Characteristic Values. */ - SD_BLE_GATTC_WRITE, /**< Generic write. */ - SD_BLE_GATTC_HV_CONFIRM, /**< Handle Value Confirmation. */ -}; - -/** - * @brief GATT Client Event IDs. - */ -enum BLE_GATTC_EVTS -{ - BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE, /**< Primary Service Discovery Response event. \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t. */ - BLE_GATTC_EVT_REL_DISC_RSP, /**< Relationship Discovery Response event. \n See @ref ble_gattc_evt_rel_disc_rsp_t. */ - BLE_GATTC_EVT_CHAR_DISC_RSP, /**< Characteristic Discovery Response event. \n See @ref ble_gattc_evt_char_disc_rsp_t. */ - BLE_GATTC_EVT_DESC_DISC_RSP, /**< Descriptor Discovery Response event. \n See @ref ble_gattc_evt_desc_disc_rsp_t. */ - BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, /**< Attribute Information Response event. \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */ - BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP, /**< Read By UUID Response event. \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t. */ - BLE_GATTC_EVT_READ_RSP, /**< Read Response event. \n See @ref ble_gattc_evt_read_rsp_t. */ - BLE_GATTC_EVT_CHAR_VALS_READ_RSP, /**< Read multiple Response event. \n See @ref ble_gattc_evt_char_vals_read_rsp_t. */ - BLE_GATTC_EVT_WRITE_RSP, /**< Write Response event. \n See @ref ble_gattc_evt_write_rsp_t. */ - BLE_GATTC_EVT_HVX, /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm. \n See @ref ble_gattc_evt_hvx_t. */ - BLE_GATTC_EVT_TIMEOUT /**< Timeout event. \n See @ref ble_gattc_evt_timeout_t. */ -}; - -/** @} */ - -/** @addtogroup BLE_GATTC_DEFINES Defines - * @{ */ - -/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC - * @{ */ -#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */ -/** @} */ - -/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats - * @{ */ -#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT 1 /**< 16-bit Attribute Information Format. */ -#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT 2 /**< 128-bit Attribute Information Format. */ -/** @} */ - -/** @} */ - -/** @addtogroup BLE_GATTC_STRUCTURES Structures - * @{ */ - -/**@brief Operation Handle Range. */ -typedef struct -{ - uint16_t start_handle; /**< Start Handle. */ - uint16_t end_handle; /**< End Handle. */ -} ble_gattc_handle_range_t; - - -/**@brief GATT service. */ -typedef struct -{ - ble_uuid_t uuid; /**< Service UUID. */ - ble_gattc_handle_range_t handle_range; /**< Service Handle Range. */ -} ble_gattc_service_t; - - -/**@brief GATT include. */ -typedef struct -{ - uint16_t handle; /**< Include Handle. */ - ble_gattc_service_t included_srvc; /**< Handle of the included service. */ -} ble_gattc_include_t; - - -/**@brief GATT characteristic. */ -typedef struct -{ - ble_uuid_t uuid; /**< Characteristic UUID. */ - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - uint8_t char_ext_props : 1; /**< Extended properties present. */ - uint16_t handle_decl; /**< Handle of the Characteristic Declaration. */ - uint16_t handle_value; /**< Handle of the Characteristic Value. */ -} ble_gattc_char_t; - - -/**@brief GATT descriptor. */ -typedef struct -{ - uint16_t handle; /**< Descriptor Handle. */ - ble_uuid_t uuid; /**< Descriptor UUID. */ -} ble_gattc_desc_t; - - -/**@brief Write Parameters. */ -typedef struct -{ - uint8_t write_op; /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */ - uint8_t flags; /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */ - uint16_t handle; /**< Handle to the attribute to be written. */ - uint16_t offset; /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */ - uint16_t len; /**< Length of data in bytes. */ - uint8_t *p_value; /**< Pointer to the value data. */ -} ble_gattc_write_params_t; - -/**@brief Attribute Information. */ -typedef struct -{ - uint16_t handle; /**< Attribute handle. */ - union { - ble_uuid_t uuid16; /**< 16-bit Attribute UUID. */ - ble_uuid128_t uuid128; /**< 128-bit Attribute UUID. */ - } info; -} ble_gattc_attr_info_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Service count. */ - ble_gattc_service_t services[1]; /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_prim_srvc_disc_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Include count. */ - ble_gattc_include_t includes[1]; /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_rel_disc_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Characteristic count. */ - ble_gattc_char_t chars[1]; /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_char_disc_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Descriptor count. */ - ble_gattc_desc_t descs[1]; /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_desc_disc_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */ -typedef struct -{ - uint16_t count; /**< Attribute count. */ - uint8_t format; /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */ - ble_gattc_attr_info_t attr_info[1]; /**< Attribute information. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_attr_info_disc_rsp_t; - -/**@brief GATT read by UUID handle value pair. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint8_t *p_value; /**< Pointer to value, variable length (length available as value_len in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t). - Please note that this pointer is absolute to the memory provided by the user when retrieving the event, - so it will effectively point to a location inside the handle_value array. */ -} ble_gattc_handle_value_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */ -typedef struct -{ - uint16_t count; /**< Handle-Value Pair Count. */ - uint16_t value_len; /**< Length of the value in Handle-Value(s) list. */ - ble_gattc_handle_value_t handle_value[1]; /**< Handle-Value(s) list. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_char_val_by_uuid_read_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint16_t offset; /**< Offset of the attribute data. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_read_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */ -typedef struct -{ - uint16_t len; /**< Concatenated Attribute values length. */ - uint8_t values[1]; /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_char_vals_read_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - uint8_t write_op; /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */ - uint16_t offset; /**< Data offset. */ - uint16_t len; /**< Data length. */ - uint8_t data[1]; /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_write_rsp_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */ -typedef struct -{ - uint16_t handle; /**< Handle to which the HVx operation applies. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t len; /**< Attribute data length. */ - uint8_t data[1]; /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gattc_evt_hvx_t; - -/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */ -typedef struct -{ - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ -} ble_gattc_evt_timeout_t; - -/**@brief GATTC event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occured. */ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint16_t error_handle; /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */ - union - { - ble_gattc_evt_prim_srvc_disc_rsp_t prim_srvc_disc_rsp; /**< Primary Service Discovery Response Event Parameters. */ - ble_gattc_evt_rel_disc_rsp_t rel_disc_rsp; /**< Relationship Discovery Response Event Parameters. */ - ble_gattc_evt_char_disc_rsp_t char_disc_rsp; /**< Characteristic Discovery Response Event Parameters. */ - ble_gattc_evt_desc_disc_rsp_t desc_disc_rsp; /**< Descriptor Discovery Response Event Parameters. */ - ble_gattc_evt_char_val_by_uuid_read_rsp_t char_val_by_uuid_read_rsp; /**< Characteristic Value Read by UUID Response Event Parameters. */ - ble_gattc_evt_read_rsp_t read_rsp; /**< Read Response Event Parameters. */ - ble_gattc_evt_char_vals_read_rsp_t char_vals_read_rsp; /**< Characteristic Values Read Response Event Parameters. */ - ble_gattc_evt_write_rsp_t write_rsp; /**< Write Response Event Parameters. */ - ble_gattc_evt_hvx_t hvx; /**< Handle Value Notification/Indication Event Parameters. */ - ble_gattc_evt_timeout_t timeout; /**< Timeout Event Parameters. */ - ble_gattc_evt_attr_info_disc_rsp_t attr_info_disc_rsp; /**< Attribute Information Discovery Event Parameters. */ - } params; /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */ -} ble_gattc_evt_t; -/** @} */ - -/** @addtogroup BLE_GATTC_FUNCTIONS Functions - * @{ */ - -/**@brief Initiate or continue a GATT Primary Service Discovery procedure. - * - * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle. - * If the last service has not been reached, this function must be called again with an updated start handle value to continue the search. - * - * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with - * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. - * - * @events - * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] start_handle Handle to start searching from. - * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned. - * - * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid)); - - -/**@brief Initiate or continue a GATT Relationship Discovery procedure. - * - * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached, - * this must be called again with an updated handle range to continue the search. - * - * @events - * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_REL_DISC_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. - * - * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); - - -/**@brief Initiate or continue a GATT Characteristic Discovery procedure. - * - * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached, - * this must be called again with an updated handle range to continue the discovery. - * - * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with - * type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event. - * - * @events - * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on. - * - * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); - - -/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure. - * - * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached, - * this must be called again with an updated handle range to continue the discovery. - * - * @events - * @event{BLE_GATTC_EVT_DESC_DISC_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on. - * - * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range)); - - -/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure. - * - * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached, - * this must be called again with an updated handle range to continue the discovery. - * - * @events - * @event{BLE_GATTC_EVT_DESC_DISC_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_READ_UUID_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_uuid Pointer to a Characteristic value UUID to read. - * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on. - * - * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range)); - - -/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure. - * - * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor - * to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the - * complete value. - * - * @events - * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] handle The handle of the attribute to be read. - * @param[in] offset Offset into the attribute value to be read. - * - * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset)); - - -/**@brief Initiate a GATT Read Multiple Characteristic Values procedure. - * - * @details This function initiates a GATT Read Multiple Characteristic Values procedure. - * - * @events - * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_READ_MULT_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read. - * @param[in] handle_count The number of handles in p_handles. - * - * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count)); - - -/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure. - * - * @details This function can perform all write procedures described in GATT. - * - * @note It is important to note that a write without response will consume an application buffer, and will therefore - * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. A write (with response) on the other hand will use the - * standard client internal buffer and thus will only generate a @ref BLE_GATTC_EVT_WRITE_RSP event as soon as the write response - * has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details. - * - * @events - * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Generated when using write request or queued writes.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC} - * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC} - * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC} - * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_write_params A pointer to a write parameters structure. - * - * @retval ::NRF_SUCCESS Successfully started the Write procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - * @retval ::NRF_ERROR_BUSY Procedure already in progress. - * @retval ::BLE_ERROR_NO_TX_PACKETS No available application packets for this connection. - */ -SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params)); - - -/**@brief Send a Handle Value Confirmation to the GATT Server. - * - * @mscs - * @mmsc{@ref BLE_GATTC_HVI_MSC} - * @endmscs - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] handle The handle of the attribute in the indication. - * - * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed. - * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle. - */ -SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle)); - -/**@brief Discovers information about a range of attributes on a GATT server. - * - * @events - * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.} - * @endevents - * - * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on. - * @param[in] p_handle_range The range of handles to request information about. - * - * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_BUSY Client procedure already in progress. - */ -SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range)); - -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif /* NRF_BLE_GATTC_H__ */ - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatts.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatts.h deleted file mode 100644 index 147d1a8fbf..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatts.h +++ /dev/null @@ -1,725 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server - @{ - @brief Definitions and prototypes for the GATTS interface. - */ - -#ifndef NRF_BLE_GATTS_H__ -#define NRF_BLE_GATTS_H__ - -#include "nrf_ble_types.h" -#include "nrf_ble_ranges.h" -#include "nrf_ble_l2cap.h" -#include "nrf_ble_gap.h" -#include "nrf_ble_gatt.h" -#include "nrf_svc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations - * @{ */ - -/** - * @brief GATTS API SVC numbers. - */ -enum BLE_GATTS_SVCS -{ - SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */ - SD_BLE_GATTS_INCLUDE_ADD, /**< Add an included service. */ - SD_BLE_GATTS_CHARACTERISTIC_ADD, /**< Add a characteristic. */ - SD_BLE_GATTS_DESCRIPTOR_ADD, /**< Add a generic attribute. */ - SD_BLE_GATTS_VALUE_SET, /**< Set an attribute value. */ - SD_BLE_GATTS_VALUE_GET, /**< Get an attribute value. */ - SD_BLE_GATTS_HVX, /**< Handle Value Notification or Indication. */ - SD_BLE_GATTS_SERVICE_CHANGED, /**< Perform a Service Changed Indication to one or more peers. */ - SD_BLE_GATTS_RW_AUTHORIZE_REPLY, /**< Reply to an authorization request for a read or write operation on one or more attributes. */ - SD_BLE_GATTS_SYS_ATTR_SET, /**< Set the persistent system attributes for a connection. */ - SD_BLE_GATTS_SYS_ATTR_GET, /**< Retrieve the persistent system attributes. */ - SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, /**< Retrieve the first valid user handle. */ - SD_BLE_GATTS_ATTR_GET /**< Retrieve the UUID and/or metadata of an attribute. */ -}; - -/** - * @brief GATT Server Event IDs. - */ -enum BLE_GATTS_EVTS -{ - BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE, /**< Write operation performed. \n See @ref ble_gatts_evt_write_t. */ - BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST, /**< Read/Write Authorization request. \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */ - BLE_GATTS_EVT_SYS_ATTR_MISSING, /**< A persistent system attribute access is pending. \n Respond with @ref sd_ble_gatts_sys_attr_set. \n See @ref ble_gatts_evt_sys_attr_missing_t. */ - BLE_GATTS_EVT_HVC, /**< Handle Value Confirmation. \n See @ref ble_gatts_evt_hvc_t. */ - BLE_GATTS_EVT_SC_CONFIRM, /**< Service Changed Confirmation. No additional event structure applies. */ - BLE_GATTS_EVT_TIMEOUT /**< Peer failed to resonpond to an ATT request in time. \n See @ref ble_gatts_evt_timeout_t. */ -}; -/** @} */ - -/** @addtogroup BLE_GATTS_DEFINES Defines - * @{ */ - -/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS - * @{ */ -#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */ -#define BLE_ERROR_GATTS_SYS_ATTR_MISSING (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */ -/** @} */ - -/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths - * @{ */ -#define BLE_GATTS_FIX_ATTR_LEN_MAX (510) /**< Maximum length for fixed length Attribute Values. */ -#define BLE_GATTS_VAR_ATTR_LEN_MAX (512) /**< Maximum length for variable length Attribute Values. */ -/** @} */ - -/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types - * @{ */ -#define BLE_GATTS_SRVC_TYPE_INVALID 0x00 /**< Invalid Service Type. */ -#define BLE_GATTS_SRVC_TYPE_PRIMARY 0x01 /**< Primary Service. */ -#define BLE_GATTS_SRVC_TYPE_SECONDARY 0x02 /**< Secondary Type. */ -/** @} */ - - -/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types - * @{ */ -#define BLE_GATTS_ATTR_TYPE_INVALID 0x00 /**< Invalid Attribute Type. */ -#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL 0x01 /**< Primary Service Declaration. */ -#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL 0x02 /**< Secondary Service Declaration. */ -#define BLE_GATTS_ATTR_TYPE_INC_DECL 0x03 /**< Include Declaration. */ -#define BLE_GATTS_ATTR_TYPE_CHAR_DECL 0x04 /**< Characteristic Declaration. */ -#define BLE_GATTS_ATTR_TYPE_CHAR_VAL 0x05 /**< Characteristic Value. */ -#define BLE_GATTS_ATTR_TYPE_DESC 0x06 /**< Descriptor. */ -#define BLE_GATTS_ATTR_TYPE_OTHER 0x07 /**< Other, non-GATT specific type. */ -/** @} */ - - -/** @defgroup BLE_GATTS_OPS GATT Server Operations - * @{ */ -#define BLE_GATTS_OP_INVALID 0x00 /**< Invalid Operation. */ -#define BLE_GATTS_OP_WRITE_REQ 0x01 /**< Write Request. */ -#define BLE_GATTS_OP_WRITE_CMD 0x02 /**< Write Command. */ -#define BLE_GATTS_OP_SIGN_WRITE_CMD 0x03 /**< Signed Write Command. */ -#define BLE_GATTS_OP_PREP_WRITE_REQ 0x04 /**< Prepare Write Request. */ -#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL 0x05 /**< Execute Write Request: Cancel all prepared writes. */ -#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW 0x06 /**< Execute Write Request: Immediately execute all prepared writes. */ -/** @} */ - -/** @defgroup BLE_GATTS_VLOCS GATT Value Locations - * @{ */ -#define BLE_GATTS_VLOC_INVALID 0x00 /**< Invalid Location. */ -#define BLE_GATTS_VLOC_STACK 0x01 /**< Attribute Value is located in stack memory, no user memory is required. */ -#define BLE_GATTS_VLOC_USER 0x02 /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack - will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */ -/** @} */ - -/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types - * @{ */ -#define BLE_GATTS_AUTHORIZE_TYPE_INVALID 0x00 /**< Invalid Type. */ -#define BLE_GATTS_AUTHORIZE_TYPE_READ 0x01 /**< Authorize a Read Operation. */ -#define BLE_GATTS_AUTHORIZE_TYPE_WRITE 0x02 /**< Authorize a Write Request Operation. */ -/** @} */ - -/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags - * @{ */ -#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0) /**< Restrict system attributes to system services only. */ -#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1) /**< Restrict system attributes to user services only. */ -/** @} */ - -/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size - * @{ - */ -#define BLE_GATTS_ATTR_TAB_SIZE_MIN 216 /**< Minimum Attribute Table size */ -#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT 0x0000 /**< Default Attribute Table size (0x580 bytes for this version of the SoftDevice). */ -/** @} */ - -/** @} */ - -/** @addtogroup BLE_GATTS_STRUCTURES Structures - * @{ */ - -/** - * @brief BLE GATTS initialization parameters. - */ -typedef struct -{ - uint8_t service_changed:1; /**< Include the Service Changed characteristic in the Attribute Table. */ - uint32_t attr_tab_size; /**< Attribute Table size in bytes. The size must be a multiple of 4. @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT is used to set the default size. */ -} ble_gatts_enable_params_t; - -/**@brief Attribute metadata. */ -typedef struct -{ - ble_gap_conn_sec_mode_t read_perm; /**< Read permissions. */ - ble_gap_conn_sec_mode_t write_perm; /**< Write permissions. */ - uint8_t vlen :1; /**< Variable length attribute. */ - uint8_t vloc :2; /**< Value location, see @ref BLE_GATTS_VLOCS.*/ - uint8_t rd_auth :1; /**< Read authorization and value will be requested from the application on every read operation. */ - uint8_t wr_auth :1; /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */ -} ble_gatts_attr_md_t; - - -/**@brief GATT Attribute. */ -typedef struct -{ - ble_uuid_t *p_uuid; /**< Pointer to the attribute UUID. */ - ble_gatts_attr_md_t *p_attr_md; /**< Pointer to the attribute metadata structure. */ - uint16_t init_len; /**< Initial attribute value length in bytes. */ - uint16_t init_offs; /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */ - uint16_t max_len; /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */ - uint8_t* p_value; /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer - that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location. - The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/ -} ble_gatts_attr_t; - -/**@brief GATT Attribute Value. */ -typedef struct -{ - uint16_t len; /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/ - uint16_t offset; /**< Attribute value offset. */ - uint8_t *p_value; /**< Pointer to where value is stored or will be stored. - If value is stored in user memory, only the attribute length is updated when p_value == NULL. - Set to NULL when reading to obtain the complete length of the attribute value */ -} ble_gatts_value_t; - - -/**@brief GATT Characteristic Presentation Format. */ -typedef struct -{ - uint8_t format; /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */ - int8_t exponent; /**< Exponent for integer data types. */ - uint16_t unit; /**< Unit from Bluetooth Assigned Numbers. */ - uint8_t name_space; /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ - uint16_t desc; /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */ -} ble_gatts_char_pf_t; - - -/**@brief GATT Characteristic metadata. */ -typedef struct -{ - ble_gatt_char_props_t char_props; /**< Characteristic Properties. */ - ble_gatt_char_ext_props_t char_ext_props; /**< Characteristic Extended Properties. */ - uint8_t *p_char_user_desc; /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */ - uint16_t char_user_desc_max_size; /**< The maximum size in bytes of the user description descriptor. */ - uint16_t char_user_desc_size; /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */ - ble_gatts_char_pf_t* p_char_pf; /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */ - ble_gatts_attr_md_t* p_user_desc_md; /**< Attribute metadata for the User Description descriptor, or NULL for default values. */ - ble_gatts_attr_md_t* p_cccd_md; /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */ - ble_gatts_attr_md_t* p_sccd_md; /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */ -} ble_gatts_char_md_t; - - -/**@brief GATT Characteristic Definition Handles. */ -typedef struct -{ - uint16_t value_handle; /**< Handle to the characteristic value. */ - uint16_t user_desc_handle; /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t cccd_handle; /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ - uint16_t sccd_handle; /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */ -} ble_gatts_char_handles_t; - - -/**@brief GATT HVx parameters. */ -typedef struct -{ - uint16_t handle; /**< Characteristic Value Handle. */ - uint8_t type; /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */ - uint16_t offset; /**< Offset within the attribute value. */ - uint16_t *p_len; /**< Length in bytes to be written, length in bytes written after successful return. */ - uint8_t *p_data; /**< Actual data content, use NULL to use the current attribute value. */ -} ble_gatts_hvx_params_t; - -/**@brief GATT Authorization parameters. */ -typedef struct -{ - uint16_t gatt_status; /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */ - uint8_t update : 1; /**< If set, data supplied in p_data will be used to update the attribute value. - Please note that for @ref BLE_GATTS_OP_WRITE_REQ operations this bit must always be set, - as the data to be written needs to be stored and later provided by the application. */ - uint16_t offset; /**< Offset of the attribute value being updated. */ - uint16_t len; /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */ - const uint8_t *p_data; /**< Pointer to new value used to update the attribute value. */ -} ble_gatts_authorize_params_t; - -/**@brief GATT Read or Write Authorize Reply parameters. */ -typedef struct -{ - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_authorize_params_t read; /**< Read authorization parameters. */ - ble_gatts_authorize_params_t write; /**< Write authorization parameters. */ - } params; /**< Reply Parameters. */ -} ble_gatts_rw_authorize_reply_params_t; - - - -/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - ble_uuid_t uuid; /**< Attribute UUID. */ - uint8_t op; /**< Type of write operation, see @ref BLE_GATTS_OPS. */ - uint8_t auth_required; /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalise the writing operation. */ - uint16_t offset; /**< Offset for the write operation. */ - uint16_t len; /**< Length of the received data. */ - uint8_t data[1]; /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_gatts_evt_write_t; - -/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ - ble_uuid_t uuid; /**< Attribute UUID. */ - uint16_t offset; /**< Offset for the read operation. */ -} ble_gatts_evt_read_t; - -/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */ -typedef struct -{ - uint8_t type; /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */ - union { - ble_gatts_evt_read_t read; /**< Attribute Read Parameters. */ - ble_gatts_evt_write_t write; /**< Attribute Write Parameters. */ - } request; /**< Request Parameters. */ -} ble_gatts_evt_rw_authorize_request_t; - -/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */ -typedef struct -{ - uint8_t hint; /**< Hint (currently unused). */ -} ble_gatts_evt_sys_attr_missing_t; - - -/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */ -typedef struct -{ - uint16_t handle; /**< Attribute Handle. */ -} ble_gatts_evt_hvc_t; - -/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */ -typedef struct -{ - uint8_t src; /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */ -} ble_gatts_evt_timeout_t; - - -/**@brief GATT Server event callback event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which the event occurred. */ - union - { - ble_gatts_evt_write_t write; /**< Write Event Parameters. */ - ble_gatts_evt_rw_authorize_request_t authorize_request; /**< Read or Write Authorize Request Parameters. */ - ble_gatts_evt_sys_attr_missing_t sys_attr_missing; /**< System attributes missing. */ - ble_gatts_evt_hvc_t hvc; /**< Handle Value Confirmation Event Parameters. */ - ble_gatts_evt_timeout_t timeout; /**< Timeout Event. */ - } params; /**< Event Parameters. */ -} ble_gatts_evt_t; - -/** @} */ - -/** @addtogroup BLE_GATTS_FUNCTIONS Functions - * @{ */ - -/**@brief Add a service declaration to the Attribute Table. - * - * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to - * add a secondary service declaration that is not referenced by another service later in the Attribute Table. - * - * @mscs - * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} - * @endmscs - * - * @param[in] type Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES. - * @param[in] p_uuid Pointer to service UUID. - * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. - * - * @retval ::NRF_SUCCESS Successfully added a service declaration. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table. - * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle)); - - -/**@brief Add an include declaration to the Attribute Table. - * - * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time). - * - * @note The included service must already be present in the Attribute Table prior to this call. - * - * @mscs - * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} - * @endmscs - * - * @param[in] service_handle Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. - * @param[in] inc_srvc_handle Handle of the included service. - * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored. - * - * @retval ::NRF_SUCCESS Successfully added an include declaration. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. - * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. - */ -SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle)); - - -/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table. - * - * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time). - * - * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writeable auxiliaries bits, - * readable (no security) and writeable (selectable) CCCDs and SCCDs and valid presentation format values. - * - * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions. - * - * @mscs - * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} - * @endmscs - * - * @param[in] service_handle Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. - * @param[in] p_char_md Characteristic metadata. - * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value. - * @param[out] p_handles Pointer to the structure where the assigned handles will be stored. - * - * @retval ::NRF_SUCCESS Successfully added a characteristic. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required. - * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. - */ -SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles)); - - -/**@brief Add a descriptor to the Attribute Table. - * - * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time). - * - * @mscs - * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC} - * @endmscs - * - * @param[in] char_handle Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially. - * @param[in] p_attr Pointer to the attribute structure. - * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored. - * - * @retval ::NRF_SUCCESS Successfully added a descriptor. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints. - * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required. - * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. - */ -SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle)); - -/**@brief Set the value of a given attribute. - * - * @note Values other than system attributes can be set at any time, regardless of wheter any active connections exist. - * - * @mscs - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. If the value does not belong to a system attribute then @ref BLE_CONN_HANDLE_INVALID can be used. - * @param[in] handle Attribute handle. - * @param[in,out] p_value Attribute value information. - * - * @retval ::NRF_SUCCESS Successfully set the value of the attribute. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. - * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE @ref BLE_CONN_HANDLE_INVALID supplied on a system attribute. - */ -SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); - -/**@brief Get the value of a given attribute. - * - * @note If the attribute value is longer than the size of the supplied buffer, - * p_len will return the total attribute value length (excluding offset), - * and not the number of bytes actually returned in p_data. - * The application may use this information to allocate a suitable buffer size. - * - * @note When retrieving system attribute values with this function, the connection handle - * may refer to an already disconnected connection. Refer to the documentation of - * @ref sd_ble_gatts_sys_attr_get for further information. - * - * @param[in] conn_handle Connection handle. If the value does not belong to a system attribute then @ref BLE_CONN_HANDLE_INVALID can be used. - * @param[in] handle Attribute handle. - * @param[in,out] p_value Attribute value information. - * - * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied. - * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE @ref BLE_CONN_HANDLE_INVALID supplied on a system attribute. - */ -SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value)); - -/**@brief Notify or Indicate an attribute value. - * - * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation - * (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that - * the application can atomically perform a value update and a server initiated transaction with a single API call. - * If the application chooses to indicate an attribute value, a @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from - * the peer. - * - * @note The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution. - * When receiveing the error codes @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and - * @ref BLE_ERROR_NO_TX_PACKETS the Attribute Table has been updated. - * The caller can check whether the value has been updated by looking at the contents of *(p_hvx_params->p_len). - * - * @note It is important to note that a notification will consume an application buffer, and will therefore - * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. An indication on the other hand will use the - * standard server internal buffer and thus will only generate a @ref BLE_GATTS_EVT_HVC event as soon as the confirmation - * has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details. - * - * @events - * @event{@ref BLE_EVT_TX_COMPLETE, Transmission complete.} - * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from peer.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} - * @mmsc{@ref BLE_GATTS_HVN_MSC} - * @mmsc{@ref BLE_GATTS_HVI_MSC} - * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC} - * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_hvx_params Pointer to an HVx parameters structure. If the p_data member contains a non-NULL pointer the attribute value will be updated with - * the contents pointed by it before sending the notification or indication. - * - * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or notifications and/or indications not enabled in the CCCD. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate. - * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated. - * @retval ::NRF_ERROR_NOT_FOUND Attribute not found. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied. - * @retval ::NRF_ERROR_BUSY Procedure already in progress. - * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. - * @retval ::BLE_ERROR_NO_TX_PACKETS No available application packets for this connection, applies only to notifications. - */ -SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params)); - -/**@brief Indicate the Service Changed attribute value. - * - * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute - * Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will - * be issued. - * - * @note Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here. - * - * @events - * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_GATTS_SC_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] start_handle Start of affected attribute handle range. - * @param[in] end_handle End of affected attribute handle range. - * - * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref sd_ble_enable and @ref ble_gatts_enable_params_t. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or notifications and/or indications not enabled in the CCCD. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application. - * @retval ::NRF_ERROR_BUSY Procedure already in progress. - * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value. - */ -SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle)); - -/**@brief Respond to a Read/Write authorization request. - * - * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application. - * - * @mscs - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC} - * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC} - * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC} - * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application. - * - * @retval ::NRF_SUCCESS Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no authorization request pending. - * @retval ::NRF_ERROR_INVALID_PARAM Authorization op invalid, - * handle supplied does not match requested handle, - * or invalid data to be written provided by the application. - * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time. - */ -SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params)); - - -/**@brief Update persistent system attribute information. - * - * @details Supply information about persistent system attributes to the stack, - * previously obtained using @ref sd_ble_gatts_sys_attr_get. - * This call is only allowed for active connections, and is usually - * made immediately after a connection is established with an known bonded device, - * often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. - * - * p_sysattrs may point directly to the application's stored copy of the system attributes - * obtained using @ref sd_ble_gatts_sys_attr_get. - * If the pointer is NULL, the system attribute info is initialized, assuming that - * the application does not have any previously saved system attribute data for this device. - * - * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration. - * - * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially. - * This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or - * reset the SoftDevice to return to a known state. - * - * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified. - * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified. - * - * @mscs - * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC} - * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC} - * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle. - * @param[in] p_sys_attr_data Pointer to a saved copy of system attributes supplied to the stack, or NULL. - * @param[in] len Size of data pointed by p_sys_attr_data, in octets. - * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS - * - * @retval ::NRF_SUCCESS Successfully set the system attribute information. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State. - * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time. - */ -SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags)); - - -/**@brief Retrieve persistent system attribute information from the stack. - * - * @details This call is used to retrieve information about values to be stored perisistently by the application - * during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device, - * the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set. - * If retrieved after disconnection, the data should be read before a new connection established. The connection handle for - * the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it. - * Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes - * may be written to at any time by the peer during a connection's lifetime. - * - * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned. - * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned. - * - * @mscs - * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC} - * @endmscs - * - * @param[in] conn_handle Connection handle of the recently terminated connection. - * @param[out] p_sys_attr_data Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described - * in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data. - * @param[in,out] p_len Size of application buffer if p_sys_attr_data is not NULL. Unconditially updated to actual length of system attribute data. - * @param[in] flags Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS - * - * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information. - * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer. - * @retval ::NRF_ERROR_NOT_FOUND No system attributes found. - */ -SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags)); - - -/**@brief Retrieve the first valid user attribute handle. - * - * @param[out] p_handle Pointer to an integer where the handle will be stored. - * - * @retval ::NRF_SUCCESS Successfully retrieved the handle. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - */ -SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle)); - -/**@brief Retrieve the attribute UUID and/or metadata. - * - * @param[in] handle Attribute handle - * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field. - * @param[out] p_md Metadata of the attribute. Use NULL to omit this field. - * - * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata, - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL. - * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found. - */ -SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md)); - -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif // NRF_BLE_GATTS_H__ - -/** - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_hci.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_hci.h deleted file mode 100644 index a709c0a60f..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_hci.h +++ /dev/null @@ -1,134 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_COMMON - @{ -*/ - - -#ifndef NRF_BLE_HCI_H__ -#define NRF_BLE_HCI_H__ -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes - * @{ */ - -#define BLE_HCI_STATUS_CODE_SUCCESS 0x00 /**< Success. */ -#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND 0x01 /**< Unknown BLE Command. */ -#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER 0x02 /**< Unknown Connection Identifier. */ -/*0x03 Hardware Failure -0x04 Page Timeout -*/ -#define BLE_HCI_AUTHENTICATION_FAILURE 0x05 /**< Authentication Failure. */ -#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING 0x06 /**< Pin or Key missing. */ -#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED 0x07 /**< Memory Capacity Exceeded. */ -#define BLE_HCI_CONNECTION_TIMEOUT 0x08 /**< Connection Timeout. */ -/*0x09 Connection Limit Exceeded -0x0A Synchronous Connection Limit To A Device Exceeded -0x0B ACL Connection Already Exists*/ -#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED 0x0C /**< Command Disallowed. */ -/*0x0D Connection Rejected due to Limited Resources -0x0E Connection Rejected Due To Security Reasons -0x0F Connection Rejected due to Unacceptable BD_ADDR -0x10 Connection Accept Timeout Exceeded -0x11 Unsupported Feature or Parameter Value*/ -#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12 /**< Invalid BLE Command Parameters. */ -#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION 0x13 /**< Remote User Terminated Connection. */ -#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14 /**< Remote Device Terminated Connection due to low resources.*/ -#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF 0x15 /**< Remote Device Terminated Connection due to power off. */ -#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION 0x16 /**< Local Host Terminated Connection. */ -/* -0x17 Repeated Attempts -0x18 Pairing Not Allowed -0x19 Unknown LMP PDU -*/ -#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A /**< Unsupported Remote Feature. */ -/* -0x1B SCO Offset Rejected -0x1C SCO Interval Rejected -0x1D SCO Air Mode Rejected*/ -#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS 0x1E /**< Invalid LMP Parameters. */ -#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR 0x1F /**< Unspecified Error. */ -/*0x20 Unsupported LMP Parameter Value -0x21 Role Change Not Allowed -*/ -#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT 0x22 /**< LMP Response Timeout. */ -/*0x23 LMP Error Transaction Collision*/ -#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED 0x24 /**< LMP PDU Not Allowed. */ -/*0x25 Encryption Mode Not Acceptable -0x26 Link Key Can Not be Changed -0x27 Requested QoS Not Supported -*/ -#define BLE_HCI_INSTANT_PASSED 0x28 /**< Instant Passed. */ -#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED 0x29 /**< Pairing with Unit Key Unsupported. */ -#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION 0x2A /**< Different Transaction Collision. */ -/* -0x2B Reserved -0x2C QoS Unacceptable Parameter -0x2D QoS Rejected -0x2E Channel Classification Not Supported -0x2F Insufficient Security -0x30 Parameter Out Of Mandatory Range -0x31 Reserved -0x32 Role Switch Pending -0x33 Reserved -0x34 Reserved Slot Violation -0x35 Role Switch Failed -0x36 Extended Inquiry Response Too Large -0x37 Secure Simple Pairing Not Supported By Host. -0x38 Host Busy - Pairing -0x39 Connection Rejected due to No Suitable Channel Found*/ -#define BLE_HCI_CONTROLLER_BUSY 0x3A /**< Controller Busy. */ -#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE 0x3B /**< Connection Interval Unacceptable. */ -#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT 0x3C /**< Directed Adverisement Timeout. */ -#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE 0x3D /**< Connection Terminated due to MIC Failure. */ -#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED 0x3E /**< Connection Failed to be Established. */ - -/** @} */ - - -#ifdef __cplusplus -} -#endif -#endif // NRF_BLE_HCI_H__ - -/** @} */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h deleted file mode 100644 index 57d3592969..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h +++ /dev/null @@ -1,205 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP) - @{ - @brief Definitions and prototypes for the L2CAP interface. - */ - -#ifndef NRF_BLE_L2CAP_H__ -#define NRF_BLE_L2CAP_H__ - -#include "nrf_ble_types.h" -#include "nrf_ble_ranges.h" -#include "nrf_ble_err.h" -#include "nrf_svc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations - * @{ */ - -/**@brief L2CAP API SVC numbers. */ -enum BLE_L2CAP_SVCS -{ - SD_BLE_L2CAP_CID_REGISTER = BLE_L2CAP_SVC_BASE, /**< Register a CID. */ - SD_BLE_L2CAP_CID_UNREGISTER, /**< Unregister a CID. */ - SD_BLE_L2CAP_TX /**< Transmit a packet. */ -}; - -/**@brief L2CAP Event IDs. */ -enum BLE_L2CAP_EVTS -{ - BLE_L2CAP_EVT_RX = BLE_L2CAP_EVT_BASE /**< L2CAP packet received. */ -}; - -/** @} */ - -/**@addtogroup BLE_L2CAP_DEFINES Defines - * @{ */ - -/**@defgroup BLE_ERRORS_L2CAP SVC return values specific to L2CAP - * @{ */ -#define BLE_ERROR_L2CAP_CID_IN_USE (NRF_L2CAP_ERR_BASE + 0x000) /**< CID already in use. */ -/** @} */ - -/**@brief Default L2CAP MTU. */ -#define BLE_L2CAP_MTU_DEF (23) - -/**@brief Invalid Channel Identifier. */ -#define BLE_L2CAP_CID_INVALID (0x0000) - -/**@brief Dynamic Channel Identifier base. */ -#define BLE_L2CAP_CID_DYN_BASE (0x0040) - -/**@brief Maximum amount of dynamic CIDs. */ -#define BLE_L2CAP_CID_DYN_MAX (8) - -/** @} */ - -/**@addtogroup BLE_L2CAP_STRUCTURES Structures - * @{ */ - -/**@brief Packet header format for L2CAP transmission. */ -typedef struct -{ - uint16_t len; /**< Length of valid info in data member. */ - uint16_t cid; /**< Channel ID on which packet is transmitted. */ -} ble_l2cap_header_t; - - -/**@brief L2CAP Received packet event report. */ -typedef struct -{ - ble_l2cap_header_t header; /**< L2CAP packet header. */ - uint8_t data[1]; /**< Packet data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation. - See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */ -} ble_l2cap_evt_rx_t; - - -/**@brief L2CAP event callback event structure. */ -typedef struct -{ - uint16_t conn_handle; /**< Connection Handle on which event occured. */ - union - { - ble_l2cap_evt_rx_t rx; /**< RX Event parameters. */ - } params; /**< Event Parameters. */ -} ble_l2cap_evt_t; - -/** @} */ - -/**@addtogroup BLE_L2CAP_FUNCTIONS Functions - * @{ */ - -/**@brief Register a CID with L2CAP. - * - * @details This registers a higher protocol layer with the L2CAP multiplexer, and is requried prior to all operations on the CID. - * - * @mscs - * @mmsc{@ref BLE_L2CAP_API_MSC} - * @endmscs - * - * @param[in] cid L2CAP CID. - * - * @retval ::NRF_SUCCESS Successfully registered a CID with the L2CAP layer. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CID must be above @ref BLE_L2CAP_CID_DYN_BASE. - * @retval ::BLE_ERROR_L2CAP_CID_IN_USE L2CAP CID already in use. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - */ -SVCALL(SD_BLE_L2CAP_CID_REGISTER, uint32_t, sd_ble_l2cap_cid_register(uint16_t cid)); - -/**@brief Unregister a CID with L2CAP. - * - * @details This unregisters a previously registerd higher protocol layer with the L2CAP multiplexer. - * - * @mscs - * @mmsc{@ref BLE_L2CAP_API_MSC} - * @endmscs - * - * @param[in] cid L2CAP CID. - * - * @retval ::NRF_SUCCESS Successfully unregistered the CID. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied. - * @retval ::NRF_ERROR_NOT_FOUND CID not previously registered. - */ -SVCALL(SD_BLE_L2CAP_CID_UNREGISTER, uint32_t, sd_ble_l2cap_cid_unregister(uint16_t cid)); - -/**@brief Transmit an L2CAP packet. - * - * @note It is important to note that a call to this function will consume an application packet, and will therefore - * generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. - * Please see the documentation of @ref sd_ble_tx_packet_count_get for more details. - * - * @events - * @event{@ref BLE_EVT_TX_COMPLETE} - * @event{@ref BLE_L2CAP_EVT_RX} - * @endevents - * - * @mscs - * @mmsc{@ref BLE_L2CAP_API_MSC} - * @endmscs - * - * @param[in] conn_handle Connection Handle. - * @param[in] p_header Pointer to a packet header containing length and CID. - * @param[in] p_data Pointer to the data to be transmitted. - * - * @retval ::NRF_SUCCESS Successfully queued an L2CAP packet for transmission. - * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied. - * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CIDs must be registered beforehand with @ref sd_ble_l2cap_cid_register. - * @retval ::NRF_ERROR_NOT_FOUND CID not found. - * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation. - * @retval ::BLE_ERROR_NO_TX_PACKETS Not enough application packets available. - * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, see @ref BLE_L2CAP_MTU_DEF. - */ -SVCALL(SD_BLE_L2CAP_TX, uint32_t, sd_ble_l2cap_tx(uint16_t conn_handle, ble_l2cap_header_t const *p_header, uint8_t const *p_data)); - -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif // NRF_BLE_L2CAP_H__ - -/** - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_ranges.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_ranges.h deleted file mode 100644 index 7476d488c0..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_ranges.h +++ /dev/null @@ -1,129 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_COMMON - @{ - @defgroup ble_ranges Module specific SVC, event and option number subranges - @{ - - @brief Definition of SVC, event and option number subranges for each API module. - - @note - SVCs, event and option numbers are split into subranges for each API module. - Each module receives its entire allocated range of SVC calls, whether implemented or not, - but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range. - - Note that the symbols BLE__SVC_LAST is the end of the allocated SVC range, - rather than the last SVC function call actually defined and implemented. - - Specific SVC, event and option values are defined in each module's ble_.h file, - which defines names of each individual SVC code based on the range start value. -*/ - -#ifndef NRF_BLE_RANGES_H__ -#define NRF_BLE_RANGES_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#define BLE_SVC_BASE 0x60 /**< Common BLE SVC base. */ -#define BLE_SVC_LAST 0x6B /**< Total: 12. */ - -#define BLE_RESERVED_SVC_BASE 0x6C /**< Reserved BLE SVC base. */ -#define BLE_RESERVED_SVC_LAST 0x6F /**< Total: 4. */ - -#define BLE_GAP_SVC_BASE 0x70 /**< GAP BLE SVC base. */ -#define BLE_GAP_SVC_LAST 0x8F /**< Total: 32. */ - -#define BLE_GATTC_SVC_BASE 0x90 /**< GATTC BLE SVC base. */ -#define BLE_GATTC_SVC_LAST 0x9F /**< Total: 32. */ - -#define BLE_GATTS_SVC_BASE 0xA0 /**< GATTS BLE SVC base. */ -#define BLE_GATTS_SVC_LAST 0xAF /**< Total: 16. */ - -#define BLE_L2CAP_SVC_BASE 0xB0 /**< L2CAP BLE SVC base. */ -#define BLE_L2CAP_SVC_LAST 0xBF /**< Total: 16. */ - - -#define BLE_EVT_INVALID 0x00 /**< Invalid BLE Event. */ - -#define BLE_EVT_BASE 0x01 /**< Common BLE Event base. */ -#define BLE_EVT_LAST 0x0F /**< Total: 15. */ - -#define BLE_GAP_EVT_BASE 0x10 /**< GAP BLE Event base. */ -#define BLE_GAP_EVT_LAST 0x2F /**< Total: 32. */ - -#define BLE_GATTC_EVT_BASE 0x30 /**< GATTC BLE Event base. */ -#define BLE_GATTC_EVT_LAST 0x4F /**< Total: 32. */ - -#define BLE_GATTS_EVT_BASE 0x50 /**< GATTS BLE Event base. */ -#define BLE_GATTS_EVT_LAST 0x6F /**< Total: 32. */ - -#define BLE_L2CAP_EVT_BASE 0x70 /**< L2CAP BLE Event base. */ -#define BLE_L2CAP_EVT_LAST 0x8F /**< Total: 32. */ - - -#define BLE_OPT_INVALID 0x00 /**< Invalid BLE Option. */ - -#define BLE_OPT_BASE 0x01 /**< Common BLE Option base. */ -#define BLE_OPT_LAST 0x1F /**< Total: 31. */ - -#define BLE_GAP_OPT_BASE 0x20 /**< GAP BLE Option base. */ -#define BLE_GAP_OPT_LAST 0x3F /**< Total: 32. */ - -#define BLE_GATTC_OPT_BASE 0x40 /**< GATTC BLE Option base. */ -#define BLE_GATTC_OPT_LAST 0x5F /**< Total: 32. */ - -#define BLE_GATTS_OPT_BASE 0x60 /**< GATTS BLE Option base. */ -#define BLE_GATTS_OPT_LAST 0x7F /**< Total: 32. */ - -#define BLE_L2CAP_OPT_BASE 0x80 /**< L2CAP BLE Option base. */ -#define BLE_L2CAP_OPT_LAST 0x9F /**< Total: 32. */ - -#ifdef __cplusplus -} -#endif -#endif /* NRF_BLE_RANGES_H__ */ - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_types.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_types.h deleted file mode 100644 index 0ef31dd83a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_types.h +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -/** - @addtogroup BLE_COMMON - @{ - @defgroup ble_types Common types and macro definitions - @{ - - @brief Common types and macro definitions for the BLE SoftDevice. - */ - -#ifndef NRF_BLE_TYPES_H__ -#define NRF_BLE_TYPES_H__ - -#include - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup BLE_TYPES_DEFINES Defines - * @{ */ - -/** @defgroup BLE_CONN_HANDLES BLE Connection Handles - * @{ */ -#define BLE_CONN_HANDLE_INVALID 0xFFFF /**< Invalid Connection Handle. */ -#define BLE_CONN_HANDLE_ALL 0xFFFE /**< Applies to all Connection Handles. */ -/** @} */ - - -/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs - * @{ */ -/* Generic UUIDs, applicable to all services */ -#define BLE_UUID_UNKNOWN 0x0000 /**< Reserved UUID. */ -#define BLE_UUID_SERVICE_PRIMARY 0x2800 /**< Primary Service. */ -#define BLE_UUID_SERVICE_SECONDARY 0x2801 /**< Secondary Service. */ -#define BLE_UUID_SERVICE_INCLUDE 0x2802 /**< Include. */ -#define BLE_UUID_CHARACTERISTIC 0x2803 /**< Characteristic. */ -#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP 0x2900 /**< Characteristic Extended Properties Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC 0x2901 /**< Characteristic User Description Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG 0x2902 /**< Client Characteristic Configuration Descriptor. */ -#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG 0x2903 /**< Server Characteristic Configuration Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT 0x2904 /**< Characteristic Presentation Format Descriptor. */ -#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT 0x2905 /**< Characteristic Aggregate Format Descriptor. */ -/* GATT specific UUIDs */ -#define BLE_UUID_GATT 0x1801 /**< Generic Attribute Profile. */ -#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED 0x2A05 /**< Service Changed Characteristic. */ -/* GAP specific UUIDs */ -#define BLE_UUID_GAP 0x1800 /**< Generic Access Profile. */ -#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME 0x2A00 /**< Device Name Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE 0x2A01 /**< Appearance Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_PPF 0x2A02 /**< Peripheral Privacy Flag Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR 0x2A03 /**< Reconnection Address Characteristic. */ -#define BLE_UUID_GAP_CHARACTERISTIC_PPCP 0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */ -/** @} */ - - -/** @defgroup BLE_UUID_TYPES Types of UUID - * @{ */ -#define BLE_UUID_TYPE_UNKNOWN 0x00 /**< Invalid UUID type. */ -#define BLE_UUID_TYPE_BLE 0x01 /**< Bluetooth SIG UUID (16-bit). */ -#define BLE_UUID_TYPE_VENDOR_BEGIN 0x02 /**< Vendor UUID types start at this index (128-bit). */ -/** @} */ - - -/** @defgroup BLE_APPEARANCES Bluetooth Appearance values - * @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml - * @{ */ -#define BLE_APPEARANCE_UNKNOWN 0 /**< Unknown. */ -#define BLE_APPEARANCE_GENERIC_PHONE 64 /**< Generic Phone. */ -#define BLE_APPEARANCE_GENERIC_COMPUTER 128 /**< Generic Computer. */ -#define BLE_APPEARANCE_GENERIC_WATCH 192 /**< Generic Watch. */ -#define BLE_APPEARANCE_WATCH_SPORTS_WATCH 193 /**< Watch: Sports Watch. */ -#define BLE_APPEARANCE_GENERIC_CLOCK 256 /**< Generic Clock. */ -#define BLE_APPEARANCE_GENERIC_DISPLAY 320 /**< Generic Display. */ -#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL 384 /**< Generic Remote Control. */ -#define BLE_APPEARANCE_GENERIC_EYE_GLASSES 448 /**< Generic Eye-glasses. */ -#define BLE_APPEARANCE_GENERIC_TAG 512 /**< Generic Tag. */ -#define BLE_APPEARANCE_GENERIC_KEYRING 576 /**< Generic Keyring. */ -#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER 640 /**< Generic Media Player. */ -#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER 704 /**< Generic Barcode Scanner. */ -#define BLE_APPEARANCE_GENERIC_THERMOMETER 768 /**< Generic Thermometer. */ -#define BLE_APPEARANCE_THERMOMETER_EAR 769 /**< Thermometer: Ear. */ -#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR 832 /**< Generic Heart rate Sensor. */ -#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT 833 /**< Heart Rate Sensor: Heart Rate Belt. */ -#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE 896 /**< Generic Blood Pressure. */ -#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM 897 /**< Blood Pressure: Arm. */ -#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST 898 /**< Blood Pressure: Wrist. */ -#define BLE_APPEARANCE_GENERIC_HID 960 /**< Human Interface Device (HID). */ -#define BLE_APPEARANCE_HID_KEYBOARD 961 /**< Keyboard (HID Subtype). */ -#define BLE_APPEARANCE_HID_MOUSE 962 /**< Mouse (HID Subtype). */ -#define BLE_APPEARANCE_HID_JOYSTICK 963 /**< Joystiq (HID Subtype). */ -#define BLE_APPEARANCE_HID_GAMEPAD 964 /**< Gamepad (HID Subtype). */ -#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE 965 /**< Digitizer Tablet (HID Subtype). */ -#define BLE_APPEARANCE_HID_CARD_READER 966 /**< Card Reader (HID Subtype). */ -#define BLE_APPEARANCE_HID_DIGITAL_PEN 967 /**< Digital Pen (HID Subtype). */ -#define BLE_APPEARANCE_HID_BARCODE 968 /**< Barcode Scanner (HID Subtype). */ -#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER 1024 /**< Generic Glucose Meter. */ -#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR 1088 /**< Generic Running Walking Sensor. */ -#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE 1089 /**< Running Walking Sensor: In-Shoe. */ -#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE 1090 /**< Running Walking Sensor: On-Shoe. */ -#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP 1091 /**< Running Walking Sensor: On-Hip. */ -#define BLE_APPEARANCE_GENERIC_CYCLING 1152 /**< Generic Cycling. */ -#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER 1153 /**< Cycling: Cycling Computer. */ -#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR 1154 /**< Cycling: Speed Sensor. */ -#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR 1155 /**< Cycling: Cadence Sensor. */ -#define BLE_APPEARANCE_CYCLING_POWER_SENSOR 1156 /**< Cycling: Power Sensor. */ -#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR 1157 /**< Cycling: Speed and Cadence Sensor. */ -#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER 3136 /**< Generic Pulse Oximeter. */ -#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP 3137 /**< Fingertip (Pulse Oximeter subtype). */ -#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN 3138 /**< Wrist Worn(Pulse Oximeter subtype). */ -#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE 3200 /**< Generic Weight Scale. */ -#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT 5184 /**< Generic Outdoor Sports Activity. */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP 5185 /**< Location Display Device (Outdoor Sports Activity subtype). */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD 5187 /**< Location Pod (Outdoor Sports Activity subtype). */ -#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD 5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */ -/** @} */ - -/** @brief Set .type and .uuid fields of ble_uuid_struct to specified uuid value. */ -#define BLE_UUID_BLE_ASSIGN(instance, value) do {\ - instance.type = BLE_UUID_TYPE_BLE; \ - instance.uuid = value;} while(0) - -/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */ -#define BLE_UUID_COPY_PTR(dst, src) do {\ - (dst)->type = (src)->type; \ - (dst)->uuid = (src)->uuid;} while(0) - -/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */ -#define BLE_UUID_COPY_INST(dst, src) do {\ - (dst).type = (src).type; \ - (dst).uuid = (src).uuid;} while(0) - -/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ -#define BLE_UUID_EQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid)) - -/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */ -#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \ - (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid)) - -/** @} */ - -/** @addtogroup BLE_TYPES_STRUCTURES Structures - * @{ */ - -/** @brief 128 bit UUID values. */ -typedef struct -{ - uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */ -} ble_uuid128_t; - -/** @brief Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */ -typedef struct -{ - uint16_t uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */ - uint8_t type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */ -} ble_uuid_t; - -/** @} */ -#ifdef __cplusplus -} -#endif - -#endif /* NRF_BLE_TYPES_H__ */ - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h deleted file mode 100644 index e4f90fd54c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h +++ /dev/null @@ -1,90 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /** - @defgroup nrf_error SoftDevice Global Error Codes - @{ - - @brief Global Error definitions -*/ - -/* Header guard */ -#ifndef NRF_ERROR_H__ -#define NRF_ERROR_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions - * @{ */ -#define NRF_ERROR_BASE_NUM (0x0) ///< Global error base -#define NRF_ERROR_SDM_BASE_NUM (0x1000) ///< SDM error base -#define NRF_ERROR_SOC_BASE_NUM (0x2000) ///< SoC error base -#define NRF_ERROR_STK_BASE_NUM (0x3000) ///< STK error base -/** @} */ - -#define NRF_SUCCESS (NRF_ERROR_BASE_NUM + 0) ///< Successful command -#define NRF_ERROR_SVC_HANDLER_MISSING (NRF_ERROR_BASE_NUM + 1) ///< SVC handler is missing -#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED (NRF_ERROR_BASE_NUM + 2) ///< SoftDevice has not been enabled -#define NRF_ERROR_INTERNAL (NRF_ERROR_BASE_NUM + 3) ///< Internal Error -#define NRF_ERROR_NO_MEM (NRF_ERROR_BASE_NUM + 4) ///< No Memory for operation -#define NRF_ERROR_NOT_FOUND (NRF_ERROR_BASE_NUM + 5) ///< Not found -#define NRF_ERROR_NOT_SUPPORTED (NRF_ERROR_BASE_NUM + 6) ///< Not supported -#define NRF_ERROR_INVALID_PARAM (NRF_ERROR_BASE_NUM + 7) ///< Invalid Parameter -#define NRF_ERROR_INVALID_STATE (NRF_ERROR_BASE_NUM + 8) ///< Invalid state, operation disallowed in this state -#define NRF_ERROR_INVALID_LENGTH (NRF_ERROR_BASE_NUM + 9) ///< Invalid Length -#define NRF_ERROR_INVALID_FLAGS (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags -#define NRF_ERROR_INVALID_DATA (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data -#define NRF_ERROR_DATA_SIZE (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size -#define NRF_ERROR_TIMEOUT (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out -#define NRF_ERROR_NULL (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer -#define NRF_ERROR_FORBIDDEN (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation -#define NRF_ERROR_INVALID_ADDR (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address -#define NRF_ERROR_BUSY (NRF_ERROR_BASE_NUM + 17) ///< Busy -#define NRF_ERROR_CONN_COUNT (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded. -#define NRF_ERROR_RESOURCES (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation - -#ifdef __cplusplus -} -#endif -#endif // NRF_ERROR_H__ - -/** - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h deleted file mode 100644 index 575829c7f9..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - /** - @addtogroup nrf_sdm_api - @{ - @defgroup nrf_sdm_error SoftDevice Manager Error Codes - @{ - - @brief Error definitions for the SDM API -*/ - -/* Header guard */ -#ifndef NRF_ERROR_SDM_H__ -#define NRF_ERROR_SDM_H__ - -#include "nrf_error.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN (NRF_ERROR_SDM_BASE_NUM + 0) ///< Unknown lfclk source. -#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1) ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts). -#define NRF_ERROR_SDM_INCORRECT_CLENR0 (NRF_ERROR_SDM_BASE_NUM + 2) ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing). - -#ifdef __cplusplus -} -#endif -#endif // NRF_ERROR_SDM_H__ - -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h deleted file mode 100644 index 28989ee4e1..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - @addtogroup nrf_soc_api - @{ - @defgroup nrf_soc_error SoC Library Error Codes - @{ - - @brief Error definitions for the SoC library - -*/ - -/* Header guard */ -#ifndef NRF_ERROR_SOC_H__ -#define NRF_ERROR_SOC_H__ - -#include "nrf_error.h" -#ifdef __cplusplus -extern "C" { -#endif - -/* Mutex Errors */ -#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN (NRF_ERROR_SOC_BASE_NUM + 0) ///< Mutex already taken - -/* NVIC errors */ -#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE (NRF_ERROR_SOC_BASE_NUM + 1) ///< NVIC interrupt not available -#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2) ///< NVIC interrupt priority not allowed -#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 3) ///< NVIC should not return - -/* Power errors */ -#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 4) ///< Power mode unknown -#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN (NRF_ERROR_SOC_BASE_NUM + 5) ///< Power POF threshold unknown -#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN (NRF_ERROR_SOC_BASE_NUM + 6) ///< Power off should not return - -/* Rand errors */ -#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES (NRF_ERROR_SOC_BASE_NUM + 7) ///< RAND not enough values - -/* PPI errors */ -#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL (NRF_ERROR_SOC_BASE_NUM + 8) ///< Invalid PPI Channel -#define NRF_ERROR_SOC_PPI_INVALID_GROUP (NRF_ERROR_SOC_BASE_NUM + 9) ///< Invalid PPI Group - -#ifdef __cplusplus -} -#endif -#endif // NRF_ERROR_SOC_H__ -/** - @} - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h deleted file mode 100644 index 8b49061c72..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h +++ /dev/null @@ -1,486 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - * @defgroup nrf_nvic_api SoftDevice NVIC API - * @{ - * - * @note In order to use this module, the following code has to be added to a .c file: - * \code - * nrf_nvic_state_t nrf_nvic_state; - * \endcode - * - * @note Definitions and declarations starting with __ (double underscore) in this header file are - * not intended for direct use by the application. - * - * @brief APIs for the accessing NVIC when using a SoftDevice. - * - */ - -#ifndef NRF_NVIC_H__ -#define NRF_NVIC_H__ - -#include -#include "nrf.h" - -#include "nrf_error_soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@addtogroup NRF_NVIC_DEFINES Defines - * @{ */ - -/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions - * @{ */ - -#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */ - -#ifdef NRF51 - #define __NRF_NVIC_ISER_COUNT (1) /**< The number of ISER/ICER registers in the NVIC that are used. */ - - /**@brief Interrupts used by the SoftDevice. */ - #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ - (1U << POWER_CLOCK_IRQn) \ - | (1U << RADIO_IRQn) \ - | (1U << RTC0_IRQn) \ - | (1U << TIMER0_IRQn) \ - | (1U << RNG_IRQn) \ - | (1U << ECB_IRQn) \ - | (1U << CCM_AAR_IRQn) \ - | (1U << TEMP_IRQn) \ - | (1U << __NRF_NVIC_NVMC_IRQn) \ - | (1U << (uint32_t)SWI4_IRQn) \ - | (1U << (uint32_t)SWI5_IRQn) \ - )) - - /**@brief Interrupts available for to application. */ - #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0) -#endif - -#ifdef NRF52 - #define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */ - - /**@brief Interrupts used by the SoftDevice. */ - #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \ - (1U << POWER_CLOCK_IRQn) \ - | (1U << RADIO_IRQn) \ - | (1U << RTC0_IRQn) \ - | (1U << TIMER0_IRQn) \ - | (1U << RNG_IRQn) \ - | (1U << ECB_IRQn) \ - | (1U << CCM_AAR_IRQn) \ - | (1U << TEMP_IRQn) \ - | (1U << __NRF_NVIC_NVMC_IRQn) \ - | (1U << (uint32_t)SWI4_EGU4_IRQn) \ - | (1U << (uint32_t)SWI5_EGU5_IRQn) \ - )) - #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0) - - /**@brief Interrupts available for to application. */ - #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0) - #define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1) -#endif -/**@} */ - -/**@} */ - -/**@addtogroup NRF_NVIC_VARIABLES Variables - * @{ */ - -/**@brief Type representing the state struct for the SoftDevice NVIC module. */ -typedef struct -{ - uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */ - uint32_t volatile __cr_flag; /**< Non-zero if already in a critical region */ -} nrf_nvic_state_t; - -/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an - * application source file. */ -extern nrf_nvic_state_t nrf_nvic_state; - -/**@} */ - -/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions - * @{ */ - -/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts. - * - * @retval The value of PRIMASK prior to disabling the interrupts. - */ -static inline int __sd_nvic_irq_disable(void) -{ - int pm = __get_PRIMASK(); - __disable_irq(); - return pm; -} - -/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts. - */ -static inline void __sd_nvic_irq_enable(void) -{ - __enable_irq(); -} - -/**@brief Checks if IRQn is available to application - * @param[in] IRQn irq to check - * - * @retval 1 (true) if the irq to check is available to the application - */ -static inline uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn) -{ - if (IRQn < 32) - { - return ((1UL<= (1 << __NVIC_PRIO_BITS)) - { - return 0; - } -#ifdef NRF51 - if( priority == 0 - || priority == 2 - ) - { - return 0; - } -#endif -#ifdef NRF52 - if( priority == 0 - || priority == 1 - || priority == 4 - || priority == 5 - ) - { - return 0; - } -#endif - return 1; -} - -/**@} */ - -/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions - * @{ */ - -/**@brief Enable External Interrupt. - * @note Corresponds to NVIC_EnableIRQ in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt was enabled. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application. - */ -static inline uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn))) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; - } - - if (nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); - } - else - { - NVIC_EnableIRQ(IRQn); - } - return NRF_SUCCESS; -} - -/**@brief Disable External Interrupt. - * @note Corresponds to NVIC_DisableIRQ in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt was disabled. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application. - */ -static inline uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - - if (nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F)); - } - else - { - NVIC_DisableIRQ(IRQn); - } - - return NRF_SUCCESS; -} - -/**@brief Get Pending Interrupt. - * @note Corresponds to NVIC_GetPendingIRQ in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_GetPendingIRQ documentation in CMSIS. - * @param[out] p_pending_irq Return value from NVIC_GetPendingIRQ. - * - * @retval ::NRF_SUCCESS The interrupt is available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - */ -static inline uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - *p_pending_irq = NVIC_GetPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } -} - -/**@brief Set Pending Interrupt. - * @note Corresponds to NVIC_SetPendingIRQ in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt is set pending. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - */ -static inline uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - NVIC_SetPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } -} - -/**@brief Clear Pending Interrupt. - * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS. - * - * @retval ::NRF_SUCCESS The interrupt pending flag is cleared. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - */ -static inline uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - NVIC_ClearPendingIRQ(IRQn); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } -} - -/**@brief Set Interrupt Priority. - * @note Corresponds to NVIC_SetPriority in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * @pre Priority is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_SetPriority documentation in CMSIS. - * @param[in] priority A valid IRQ priority for use by the application. - * - * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application. - */ -static inline uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority) -{ - if (!__sd_nvic_app_accessible_irq(IRQn)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } - - if (!__sd_nvic_is_app_accessible_priority(priority)) - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED; - } - - NVIC_SetPriority(IRQn, (uint32_t)priority); - return NRF_SUCCESS; -} - -/**@brief Get Interrupt Priority. - * @note Corresponds to NVIC_GetPriority in CMSIS. - * - * @pre IRQn is valid and not reserved by the stack. - * - * @param[in] IRQn See the NVIC_GetPriority documentation in CMSIS. - * @param[out] p_priority Return value from NVIC_GetPriority. - * - * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority. - * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application. - */ -static inline uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority) -{ - if (__sd_nvic_app_accessible_irq(IRQn)) - { - *p_priority = (NVIC_GetPriority(IRQn) & 0xFF); - return NRF_SUCCESS; - } - else - { - return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE; - } -} - -/**@brief System Reset. - * @note Corresponds to NVIC_SystemReset in CMSIS. - * - * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN - */ -static inline uint32_t sd_nvic_SystemReset(void) -{ - NVIC_SystemReset(); - return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN; -} - -/**@brief Enters critical region. - * - * @post Application interrupts will be disabled. - * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each - * execution context - * @sa sd_nvic_critical_region_exit - * - * @retval ::NRF_SUCCESS - */ -static inline uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region) -{ - int was_masked = __sd_nvic_irq_disable(); - if (!nrf_nvic_state.__cr_flag) - { - nrf_nvic_state.__cr_flag = 1; - nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); - NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; - #ifdef NRF52 - nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); - NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; - #endif - *p_is_nested_critical_region = 0; - } - else - { - *p_is_nested_critical_region = 1; - } - if (!was_masked) - { - __sd_nvic_irq_enable(); - } - return NRF_SUCCESS; -} - -/**@brief Exit critical region. - * - * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter. - * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called. - * - * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter. - * - * @retval ::NRF_SUCCESS - */ -static inline uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region) -{ - if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0)) - { - int was_masked = __sd_nvic_irq_disable(); - NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; - #ifdef NRF52 - NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; - #endif - nrf_nvic_state.__cr_flag = 0; - if (!was_masked) - { - __sd_nvic_irq_enable(); - } - } - - return NRF_SUCCESS; -} -/**@} */ - -#ifdef __cplusplus -} -#endif - -#endif // NRF_NVIC_H__ - -/**@} */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h deleted file mode 100644 index 20aef49626..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2015 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef NRF_SD_DEF_H__ -#define NRF_SD_DEF_H__ - -#include - -#define SD_PPI_CHANNELS_USED 0xFFF0C000uL /**< PPI channels utilized by SotfDevice (not available to the application). */ -#define SD_PPI_GROUPS_USED 0x0000000CuL /**< PPI groups utilized by SoftDevice (not available to the application). */ -#define SD_TIMERS_USED 0x00000001uL /**< Timers used by SoftDevice. */ -#define SD_SWI_USED 0x0000003CuL /**< Software interrupts used by SoftDevice */ - -#endif /* NRF_SD_DEF_H__ */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h deleted file mode 100644 index bb370abffe..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - @defgroup nrf_sdm_api SoftDevice Manager API - @{ - - @brief APIs for SoftDevice management. - -*/ - -/* Header guard */ -#ifndef NRF_SDM_H__ -#define NRF_SDM_H__ - -#include "nrf_svc.h" -#include "nrf.h" -#include "nrf_soc.h" -#include "nrf_error_sdm.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup NRF_SDM_DEFINES Defines - * @{ */ -#ifdef NRFSOC_DOXYGEN -//Stuff defined elsewere, to satisfy doxygen -#define MBR_SIZE 0 -#warning test -#endif - -/** @brief SoftDevice Manager SVC Base number. */ -#define SDM_SVC_BASE 0x10 - -/** @brief Defines the SoftDevice Information Structure location (address) as an offset from -the start of the softdevice (without MBR)*/ -#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000) - -/** @brief Defines the absolute Softdevice information structure location (address)*/ -#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE) - -/** @brief Defines the offset for Softdevice size value relative to Softdevice base address*/ -#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08) - -/** @brief Defines the offset for FWID value relative to Softdevice base address*/ -#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C) - -/** @brief Defines a macro for retreiving the actual Softdevice size value from a given base address - use @ref MBR_SIZE when Softdevice is installed just above the MBR (the usual case)*/ -#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET))) - -/** @brief Defines a macro for retreiving the actual FWID value from a given base address - use @ref MBR_SIZE when Softdevice is installed just above the MBR (the usual case)*/ -#define SD_FWID_GET(baseaddr) ((*((uint32_t *) ((baseaddr) + SD_FWID_OFFSET))) & 0xFFFF) - -/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges - * @{ */ -#define NRF_FAULT_ID_SD_RANGE_START 0x00000000 /**< SoftDevice ID range start. */ -#define NRF_FAULT_ID_APP_RANGE_START 0x00001000 /**< Application ID range start. */ -/**@} */ - -/**@defgroup NRF_FAULT_IDS Fault ID types - * @{ */ -#define NRF_FAULT_ID_SD_ASSERT (NRF_FAULT_ID_SD_RANGE_START + 1) /**< SoftDevice assertion. The info parameter will be set to 0x00000000. */ -#define NRF_FAULT_ID_APP_MEMACC (NRF_FAULT_ID_APP_RANGE_START + 1) /**< Application invalid memory access. The info parameter will contain the address in memory that was accessed. */ -/**@} */ - -/** @} */ - -/** @addtogroup NRF_SDM_ENUMS Enumerations - * @{ */ - -/**@brief nRF SoftDevice Manager API SVC numbers. */ -enum NRF_SD_SVCS -{ - SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */ - SD_SOFTDEVICE_DISABLE, /**< ::sd_softdevice_disable */ - SD_SOFTDEVICE_IS_ENABLED, /**< ::sd_softdevice_is_enabled */ - SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */ - SVC_SDM_LAST /**< Placeholder for last SDM SVC */ -}; - -/** @} */ - -/** @addtogroup NRF_SDM_DEFINES Defines - * @{ */ - -/**@defgroup NRF_CLOCK_LF_XTAL_ACCURACY Clock accuracy * @{ */ - -#define NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM (0) /* Default */ -#define NRF_CLOCK_LF_XTAL_ACCURACY_500_PPM (1) -#define NRF_CLOCK_LF_XTAL_ACCURACY_150_PPM (2) -#define NRF_CLOCK_LF_XTAL_ACCURACY_100_PPM (3) -#define NRF_CLOCK_LF_XTAL_ACCURACY_75_PPM (4) -#define NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM (5) -#define NRF_CLOCK_LF_XTAL_ACCURACY_30_PPM (6) -#define NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM (7) - -/** @} */ - -/**@defgroup NRF_CLOCK_LF_SRC Possible lfclk oscillator sources * @{ */ - -#define NRF_CLOCK_LF_SRC_RC (0) /**< LFCLK RC oscillator. */ -#define NRF_CLOCK_LF_SRC_XTAL (1) /**< LFCLK crystal oscillator. */ -#define NRF_CLOCK_LF_SRC_SYNTH (2) /**< LFCLK Synthesized from HFCLK. */ - -/** @} */ -/** @} */ - -/** @addtogroup NRF_SDM_TYPES Types - * @{ */ - -/**@brief Type representing lfclk oscillator source. */ -typedef struct -{ - uint8_t source; /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */ - uint8_t rc_ctiv; /**< Only for NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second - units (nRF51: 1-64, nRF52: 1-32). - @note To avoid excessive clock drift, 0.5 degrees Celsius is the - maximum temperature change allowed in one calibration timer - interval. The interval should be selected to ensure this. - - @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. */ - uint8_t rc_temp_ctiv; /**< Only for NRF_CLOCK_LF_SRC_RC: How often (in number of calibration - intervals) the RC oscillator shall be calibrated if the temperature - hasn't changed. - 0: Always calibrate even if the temperature hasn't changed. - 1: Only calibrate if the temperature has changed (nRF51 only). - 2-33: Check the temperature and only calibrate if it has changed, - however calibration will take place every rc_temp_ctiv - intervals in any case. - - @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC. - - @note For nRF52, the application must ensure calibration at least once - every 8 seconds to ensure +/-250ppm clock stability. The - recommended configuration for NRF_CLOCK_LF_SRC_RC on nRF52 is - rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at - least once every 8 seconds and for temperature changes of 0.5 - degrees Celsius every 4 seconds. See the Product Specification - for the nRF52 device being used for more information.*/ - uint8_t xtal_accuracy; /**< External crystal clock accuracy used in the LL to compute timing windows. - - @note For the NRF_CLOCK_LF_SRC_RC clock source this parameter is ignored. */ -} nrf_clock_lf_cfg_t; - -/**@brief Fault Handler type. - * - * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back. - * The protocol stack will be in an undefined state when this happens and the only way to recover will be to - * perform a reset, using e.g. CMSIS NVIC_SystemReset(). - * - * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback. - * - * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS. - * @param[in] pc The program counter of the instruction that triggered the fault. - * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details. - */ -typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info); - -/** @} */ - -/** @addtogroup NRF_SDM_FUNCTIONS Functions - * @{ */ - -/**@brief Enables the SoftDevice and by extension the protocol stack. - * - * @note Some care must be taken if a low frequency clock source is already running when calling this function: - * If the LF clock has a different source then the one currently running, it will be stopped. Then, the new - * clock source will be started. - * - * @note This function has no effect when returning with an error. - * - * @post If return code is ::NRF_SUCCESS - * - SoC library and protocol stack APIs are made available. - * - A portion of RAM will be unavailable (see relevant SDS documentation). - * - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation). - * - Interrupts will not arrive from protected peripherals or interrupts. - * - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice. - * - Interrupt latency may be affected by the SoftDevice (see relevant SDS documentation). - * - Chosen low frequency clock source will be running. - * - * @param p_clock_lf_cfg Low frequency clock source and accuracy. - If NULL the clock will be configured as an rc source with rc_ctiv = 16 and .rc_temp_ctiv = 2 - In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock. - * @param fault_handler Callback to be invoked in case of fault. - * - * @retval ::NRF_SUCCESS - * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated. - * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level. - * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected. - */ -SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler)); - - -/**@brief Disables the SoftDevice and by extension the protocol stack. - * - * Idempotent function to disable the SoftDevice. - * - * @post SoC library and protocol stack APIs are made unavailable. - * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest). - * @post All peripherals used by the SoftDevice will be reset to default values. - * @post All of RAM become available. - * @post All interrupts are forwarded to the application. - * @post LFCLK source chosen in ::sd_softdevice_enable will be left running. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void)); - -/**@brief Check if the SoftDevice is enabled. - * - * @param[out] p_softdevice_enabled If the SoftDevice is enabled: 1 else 0. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled)); - -/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice - * - * This function is only intended to be called when a bootloader is enabled. - * - * @param[in] address The base address of the interrupt vector table for forwarded interrupts. - - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address)); - -/** @} */ - -#ifdef __cplusplus -} -#endif -#endif // NRF_SDM_H__ - -/** - @} -*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h deleted file mode 100644 index e1fbb2236a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h +++ /dev/null @@ -1,911 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - * @defgroup nrf_soc_api SoC Library API - * @{ - * - * @brief APIs for the SoC library. - * - */ - -#ifndef NRF_SOC_H__ -#define NRF_SOC_H__ - -#include -#include -#include "nrf_svc.h" -#include "nrf.h" - -#include "nrf_error_soc.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/**@addtogroup NRF_SOC_DEFINES Defines - * @{ */ - -/**@brief The number of the lowest SVC number reserved for the SoC library. */ -#define SOC_SVC_BASE (0x20) -#define SOC_SVC_BASE_NOT_AVAILABLE (0x2B) - -/**@brief Guranteed time for application to process radio inactive notification. */ -#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US (62) - -/**@brief The minimum allowed timeslot extension time. */ -#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200) - -#define SOC_ECB_KEY_LENGTH (16) /**< ECB key length. */ -#define SOC_ECB_CLEARTEXT_LENGTH (16) /**< ECB cleartext length. */ -#define SOC_ECB_CIPHERTEXT_LENGTH (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */ - -#ifdef NRF51 -#define SD_EVT_IRQn (SWI2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ -#define SD_EVT_IRQHandler (SWI2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */ -#define RADIO_NOTIFICATION_IRQn (SWI1_IRQn) /**< The radio notification IRQ number. */ -#define RADIO_NOTIFICATION_IRQHandler (SWI1_IRQHandler) /**< The radio notification IRQ handler. */ -#endif -#ifdef NRF52 -#define SD_EVT_IRQn (SWI2_EGU2_IRQn) /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */ -#define SD_EVT_IRQHandler (SWI2_EGU2_IRQHandler) /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */ -#define RADIO_NOTIFICATION_IRQn (SWI1_EGU1_IRQn) /**< The radio notification IRQ number. */ -#define RADIO_NOTIFICATION_IRQHandler (SWI1_EGU1_IRQHandler) /**< The radio notification IRQ handler. */ -#endif - -#define NRF_RADIO_LENGTH_MIN_US (100) /**< The shortest allowed radio timeslot, in microseconds. */ -#define NRF_RADIO_LENGTH_MAX_US (100000) /**< The longest allowed radio timeslot, in microseconds. */ - -#define NRF_RADIO_DISTANCE_MAX_US (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */ - -#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */ - -#define NRF_RADIO_START_JITTER_US (2) /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */ - -/**@} */ - -/**@addtogroup NRF_SOC_ENUMS Enumerations - * @{ */ - -/**@brief The SVC numbers used by the SVC functions in the SoC library. */ -enum NRF_SOC_SVCS -{ - SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE, - SD_PPI_CHANNEL_ENABLE_SET, - SD_PPI_CHANNEL_ENABLE_CLR, - SD_PPI_CHANNEL_ASSIGN, - SD_PPI_GROUP_TASK_ENABLE, - SD_PPI_GROUP_TASK_DISABLE, - SD_PPI_GROUP_ASSIGN, - SD_PPI_GROUP_GET, - SD_FLASH_PAGE_ERASE, - SD_FLASH_WRITE, - SD_FLASH_PROTECT, - SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE, - SD_MUTEX_ACQUIRE, - SD_MUTEX_RELEASE, - SD_RFU_1, - SD_RFU_2, - SD_RFU_3, - SD_RFU_4, - SD_RFU_5, - SD_RFU_6, - SD_RFU_7, - SD_RFU_8, - SD_RFU_9, - SD_RFU_10, - SD_RAND_APPLICATION_POOL_CAPACITY_GET, - SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, - SD_RAND_APPLICATION_VECTOR_GET, - SD_POWER_MODE_SET, - SD_POWER_SYSTEM_OFF, - SD_POWER_RESET_REASON_GET, - SD_POWER_RESET_REASON_CLR, - SD_POWER_POF_ENABLE, - SD_POWER_POF_THRESHOLD_SET, - SD_POWER_RAMON_SET, - SD_POWER_RAMON_CLR, - SD_POWER_RAMON_GET, - SD_POWER_GPREGRET_SET, - SD_POWER_GPREGRET_CLR, - SD_POWER_GPREGRET_GET, - SD_POWER_DCDC_MODE_SET, - SD_APP_EVT_WAIT, - SD_CLOCK_HFCLK_REQUEST, - SD_CLOCK_HFCLK_RELEASE, - SD_CLOCK_HFCLK_IS_RUNNING, - SD_RADIO_NOTIFICATION_CFG_SET, - SD_ECB_BLOCK_ENCRYPT, - SD_ECB_BLOCKS_ENCRYPT, - SD_RADIO_SESSION_OPEN, - SD_RADIO_SESSION_CLOSE, - SD_RADIO_REQUEST, - SD_EVT_GET, - SD_TEMP_GET, - SVC_SOC_LAST -}; - -/**@brief Possible values of a ::nrf_mutex_t. */ -enum NRF_MUTEX_VALUES -{ - NRF_MUTEX_FREE, - NRF_MUTEX_TAKEN -}; - -/**@brief Power modes. */ -enum NRF_POWER_MODES -{ - NRF_POWER_MODE_CONSTLAT, /**< Constant latency mode. See power management in the reference manual. */ - NRF_POWER_MODE_LOWPWR /**< Low power mode. See power management in the reference manual. */ -}; - - -/**@brief Power failure thresholds */ -enum NRF_POWER_THRESHOLDS -{ - NRF_POWER_THRESHOLD_V21, /**< 2.1 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V23, /**< 2.3 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V25, /**< 2.5 Volts power failure threshold. */ - NRF_POWER_THRESHOLD_V27 /**< 2.7 Volts power failure threshold. */ -}; - - -/**@brief DC/DC converter modes. */ -enum NRF_POWER_DCDC_MODES -{ - NRF_POWER_DCDC_DISABLE, /**< The DCDC is disabled. */ - NRF_POWER_DCDC_ENABLE /**< The DCDC is enabled. */ -}; - -/**@brief Radio notification distances. */ -enum NRF_RADIO_NOTIFICATION_DISTANCES -{ - NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */ - NRF_RADIO_NOTIFICATION_DISTANCE_800US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_1740US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_2680US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_3620US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_4560US, /**< The distance from the active notification to start of radio activity. */ - NRF_RADIO_NOTIFICATION_DISTANCE_5500US /**< The distance from the active notification to start of radio activity. */ -}; - - -/**@brief Radio notification types. */ -enum NRF_RADIO_NOTIFICATION_TYPES -{ - NRF_RADIO_NOTIFICATION_TYPE_NONE = 0, /**< The event does not have a radio notification signal. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE, /**< Using interrupt for notification when the radio will be enabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */ - NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, /**< Using interrupt for notification both when the radio will be enabled and disabled. */ -}; - -/**@brief The Radio signal callback types. */ -enum NRF_RADIO_CALLBACK_SIGNAL_TYPE -{ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_START, /**< This signal indicates the start of the radio timeslot. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0, /**< This signal indicates the NRF_TIMER0 interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO, /**< This signal indicates the NRF_RADIO interrupt. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED, /**< This signal indicates extend action failed. */ - NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED /**< This signal indicates extend action succeeded. */ -}; - -/**@brief The actions requested by the signal callback. - * - * This code gives the SOC instructions about what action to take when the signal callback has - * returned. - */ -enum NRF_RADIO_SIGNAL_CALLBACK_ACTION -{ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE, /**< Return without action. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND, /**< Request an extension of the current timeslot (maximum execution time for this action is when the extension succeeded). */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_END, /**< End the current radio timeslot. */ - NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END /**< Request a new radio timeslot and end the current timeslot. */ -}; - -/**@brief Radio timeslot high frequency clock source configuration. */ -enum NRF_RADIO_HFCLK_CFG -{ - NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the - external crystal for the whole duration of the timeslot. This should be the - preferred option for events that use the radio or require high timing accuracy. */ - NRF_RADIO_HFCLK_CFG_NO_GUARANTEE /**< This configuration allows for earlier and tighter scheduling of timeslots. - The RC oscillator may be the clock source in part or for the whole duration of the timeslot. - The RC oscillator's accuracy must therefore be taken into consideration. - @note If the application will use the radio peripheral in timeslots with this configuration, - it must make sure that the crystal is running and stable before starting the radio. */ -}; - -/**@brief Radio timeslot priorities. */ -enum NRF_RADIO_PRIORITY -{ - NRF_RADIO_PRIORITY_HIGH, /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */ - NRF_RADIO_PRIORITY_NORMAL, /**< Normal (equal priority as the priority of secondary activites of the SoftDevice stack(s)). */ -}; - -/**@brief Radio timeslot request type. */ -enum NRF_RADIO_REQUEST_TYPE -{ - NRF_RADIO_REQ_TYPE_EARLIEST, /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */ - NRF_RADIO_REQ_TYPE_NORMAL /**< Normal radio timeslot request. */ -}; - -/**@brief SoC Events. */ -enum NRF_SOC_EVTS -{ - NRF_EVT_HFCLKSTARTED, /**< Event indicating that the HFCLK has started. */ - NRF_EVT_POWER_FAILURE_WARNING, /**< Event indicating that a power failure warning has occurred. */ - NRF_EVT_FLASH_OPERATION_SUCCESS, /**< Event indicating that the ongoing flash operation has completed successfully. */ - NRF_EVT_FLASH_OPERATION_ERROR, /**< Event indicating that the ongoing flash operation has timed out with an error. */ - NRF_EVT_RADIO_BLOCKED, /**< Event indicating that a radio timeslot was blocked. */ - NRF_EVT_RADIO_CANCELED, /**< Event indicating that a radio timeslot was canceled by SoftDevice. */ - NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */ - NRF_EVT_RADIO_SESSION_IDLE, /**< Event indicating that a radio timeslot session is idle. */ - NRF_EVT_RADIO_SESSION_CLOSED, /**< Event indicating that a radio timeslot session is closed. */ - NRF_EVT_NUMBER_OF_EVTS -}; - -/**@} */ - - -/**@addtogroup NRF_SOC_STRUCTURES Structures - * @{ */ - -/**@brief Represents a mutex for use with the nrf_mutex functions. - * @note Accessing the value directly is not safe, use the mutex functions! - */ -typedef volatile uint8_t nrf_mutex_t; - -/**@brief Parameters for a request for a timeslot as early as possible. */ -typedef struct -{ - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t length_us; /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */ - uint32_t timeout_us; /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */ -} nrf_radio_request_earliest_t; - -/**@brief Parameters for a normal radio timeslot request. */ -typedef struct -{ - uint8_t hfclk; /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */ - uint8_t priority; /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */ - uint32_t distance_us; /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */ - uint32_t length_us; /**< The radio timeslot length (in the range [100..100,000] microseconds). */ -} nrf_radio_request_normal_t; - -/**@brief Radio timeslot request parameters. */ -typedef struct -{ - uint8_t request_type; /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */ - union - { - nrf_radio_request_earliest_t earliest; /**< Parameters for requesting a radio timeslot as early as possible. */ - nrf_radio_request_normal_t normal; /**< Parameters for requesting a normal radio timeslot. */ - } params; -} nrf_radio_request_t; - -/**@brief Return parameters of the radio timeslot signal callback. */ -typedef struct -{ - uint8_t callback_action; /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */ - union - { - struct - { - nrf_radio_request_t * p_next; /**< The request parameters for the next radio timeslot. */ - } request; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */ - struct - { - uint32_t length_us; /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */ - } extend; /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */ - } params; -} nrf_radio_signal_callback_return_param_t; - -/**@brief The radio timeslot signal callback type. - * - * @note In case of invalid return parameters, the radio timeslot will automatically end - * immediately after returning from the signal callback and the - * @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent. - * @note The returned struct pointer must remain valid after the signal callback - * function returns. For instance, this means that it must not point to a stack variable. - * - * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE. - * - * @return Pointer to structure containing action requested by the application. - */ -typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type); - -/**@brief AES ECB parameter typedefs */ -typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH]; -typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH]; -typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH]; - -/**@brief AES ECB data structure */ -typedef struct -{ - soc_ecb_key_t key; /**< Encryption key. */ - soc_ecb_cleartext_t cleartext; /**< Cleartext data. */ - soc_ecb_ciphertext_t ciphertext; /**< Ciphertext data. */ -} nrf_ecb_hal_data_t; - -/**@brief AES ECB block. Used to provide multiple blocks in a single call - to @ref sd_ecb_blocks_encrypt.*/ -typedef struct -{ - soc_ecb_key_t* p_key; /**< Pointer to the Encryption key. */ - soc_ecb_cleartext_t* p_cleartext; /**< Pointer to the Cleartext data. */ - soc_ecb_ciphertext_t* p_ciphertext; /**< Pointer to the Ciphertext data. */ -} nrf_ecb_hal_data_block_t; - -/**@} */ - -/**@addtogroup NRF_SOC_FUNCTIONS Functions - * @{ */ - -/**@brief Initialize a mutex. - * - * @param[in] p_mutex Pointer to the mutex to initialize. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex)); - -/**@brief Attempt to acquire a mutex. - * - * @param[in] p_mutex Pointer to the mutex to acquire. - * - * @retval ::NRF_SUCCESS The mutex was successfully acquired. - * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired. - */ -SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex)); - -/**@brief Release a mutex. - * - * @param[in] p_mutex Pointer to the mutex to release. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex)); - -/**@brief Query the capacity of the application random pool. - * - * @param[out] p_pool_capacity The capacity of the pool. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity)); - -/**@brief Get number of random bytes available to the application. - * - * @param[out] p_bytes_available The number of bytes currently available in the pool. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available)); - -/**@brief Get random bytes from the application pool. - * - * @param[out] p_buff Pointer to unit8_t buffer for storing the bytes. - * @param[in] length Number of bytes to take from pool and place in p_buff. - * - * @retval ::NRF_SUCCESS The requested bytes were written to p_buff. - * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available. -*/ -SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length)); - -/**@brief Gets the reset reason register. - * - * @param[out] p_reset_reason Contents of the NRF_POWER->RESETREAS register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason)); - -/**@brief Clears the bits of the reset reason register. - * - * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk)); - -/**@brief Sets the power mode when in CPU sleep. - * - * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait - * - * @retval ::NRF_SUCCESS The power mode was set. - * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown. - */ -SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode)); - -/**@brief Puts the chip in System OFF mode. - * - * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN - */ -SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void)); - -/**@brief Enables or disables the power-fail comparator. - * - * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs. - * The event can be retrieved with sd_evt_get(); - * - * @param[in] pof_enable True if the power-fail comparator should be enabled, false if it should be disabled. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable)); - -/**@brief Sets the power-fail threshold value. - * - * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS. - * - * @retval ::NRF_SUCCESS The power failure threshold was set. - * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown. - */ -SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold)); - -/**@brief Sets bits in the NRF_POWER->RAMON register. - * - * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon)); - -/**@brief Clears bits in the NRF_POWER->RAMON register. - * - * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon)); - -/**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks. - * - * @param[out] p_ramon Content of NRF_POWER->RAMON register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon)); - -/**@brief Set bits in the NRF_POWER->GPREGRET register. - * - * @param[in] gpregret_msk Bits to be set in the GPREGRET register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk)); - -/**@brief Clear bits in the NRF_POWER->GPREGRET register. - * - * @param[in] gpregret_msk Bits to be clear in the GPREGRET register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk)); - -/**@brief Get contents of the NRF_POWER->GPREGRET register. - * - * @param[out] p_gpregret Contents of the GPREGRET register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret)); - -/**@brief Sets the DCDC mode. - * - * Enable or disable the DCDC peripheral. - * - * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES. - * - * @retval ::NRF_SUCCESS - * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid. - */ -SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode)); - -/**@brief Request the high frequency crystal oscillator. - * - * Will start the high frequency crystal oscillator, the startup time of the crystal varies - * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started. - * - * @see sd_clock_hfclk_is_running - * @see sd_clock_hfclk_release - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void)); - -/**@brief Releases the high frequency crystal oscillator. - * - * Will stop the high frequency crystal oscillator, this happens immediately. - * - * @see sd_clock_hfclk_is_running - * @see sd_clock_hfclk_request - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void)); - -/**@brief Checks if the high frequency crystal oscillator is running. - * - * @see sd_clock_hfclk_request - * @see sd_clock_hfclk_release - * - * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running)); - -/**@brief Waits for an application event. - * - * An application event is either an application interrupt or a pended interrupt when the - * interrupt is disabled. When the interrupt is enabled it will be taken immediately since - * this function will wait in thread mode, then the execution will return in the application's - * main thread. When an interrupt is disabled and gets pended it will return to the application's - * thread main. The application must ensure that the pended flag is cleared using - * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for - * disabled interrupts, as the interrupt handler will clear the pending flag automatically for - * enabled interrupts. - * - * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0 - * System Control Register (SCR). @sa CMSIS_SCB - * - * @note If an application interrupt has happened since the last time sd_app_evt_wait was - * called this function will return immediately and not go to sleep. This is to avoid race - * conditions that can occur when a flag is updated in the interrupt handler and processed - * in the main loop. - * - * @post An application interrupt has happened or a interrupt pending flag is set. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void)); - -/**@brief Get PPI channel enable register contents. - * - * @param[out] p_channel_enable The contents of the PPI CHEN register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable)); - -/**@brief Set PPI channel enable register. - * - * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk)); - -/**@brief Clear PPI channel enable register. - * - * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk)); - -/**@brief Assign endpoints to a PPI channel. - * - * @param[in] channel_num Number of the PPI channel to assign. - * @param[in] evt_endpoint Event endpoint of the PPI channel. - * @param[in] task_endpoint Task endpoint of the PPI channel. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint)); - -/**@brief Task to enable a channel group. - * - * @param[in] group_num Number of the channel group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num)); - -/**@brief Task to disable a channel group. - * - * @param[in] group_num Number of the PPI group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num)); - -/**@brief Assign PPI channels to a channel group. - * - * @param[in] group_num Number of the channel group. - * @param[in] channel_msk Mask of the channels to assign to the group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk)); - -/**@brief Gets the PPI channels of a channel group. - * - * @param[in] group_num Number of the channel group. - * @param[out] p_channel_msk Mask of the channels assigned to the group. - * - * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk)); - -/**@brief Configures the Radio Notification signal. - * - * @note - * - The notification signal latency depends on the interrupt priority settings of SWI used - * for notification signal. - * - To ensure that the radio notification signal behaves in a consistent way, always - * configure radio notifications when there is no protocol stack or other SoftDevice - * activity in progress. It is recommended that the radio notification signal is - * configured directly after the SoftDevice has been enabled. - * - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice - * will interrupt the application to do Radio Event preparation. - * - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have - * to shorten the connection events to have time for the Radio Notification signals. - * - * @param[in] type Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES. - * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio - * notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is - * recommended (but not required) to be used with - * @ref NRF_RADIO_NOTIFICATION_TYPE_NONE. - * - * @param[in] distance Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES. - * This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or - * @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. - * - * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid. - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance)); - -/**@brief Encrypts a block according to the specified parameters. - * - * 128-bit AES encryption. - * - * @note: - * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while - * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application - * main or low interrupt level. - * - * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input - * parameters and one output parameter). - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data)); - -/**@brief Encrypts multiple data blocks provided as an array of data block structures. - * - * @details: Performs 128-bit AES encryption on multiple data blocks - * - * @note: - * - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while - * the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application - * main or low interrupt level. - * - * @param[in] block_count Count of blocks in the p_data_blocks array. - * @param[in,out] p_data_blocks Pointer to the first entry in a contiguous array of - * @ref nrf_ecb_hal_data_block_t structures. - * - * @retval ::NRF_SUCCESS - */ -SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks)); - -/**@brief Gets any pending events generated by the SoC API. - * - * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned. - * - * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending. - * - * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter. - * @retval ::NRF_ERROR_NOT_FOUND No pending events. - */ -SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id)); - -/**@brief Get the temperature measured on the chip - * - * This function will block until the temperature measurement is done. - * It takes around 50us from call to return. - * - * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius. - * - * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp - */ -SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp)); - -/**@brief Flash Write -* -* Commands to write a buffer to flash -* -* If the SoftDevice is enabled: -* This call initiates the flash access command, and its completion will be communicated to the -* application with exactly one of the following events: -* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. -* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. -* -* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the - * write has been completed -* -* @note -* - This call takes control over the radio and the CPU during flash erase and write to make sure that -* they will not interfere with the flash access. This means that all interrupts will be blocked -* for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual -* and the command parameters). -* -* -* @param[in] p_dst Pointer to start of flash location to be written. -* @param[in] p_src Pointer to buffer with data to be written. -* @param[in] size Number of 32-bit words to write. Maximum size is 256 32-bit words for nRF51 and 1024 for nRF52. -* -* @retval ::NRF_ERROR_INVALID_ADDR Tried to write to a non existing flash address, or p_dst or p_src was unaligned. -* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. -* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size. -* @retval ::NRF_ERROR_FORBIDDEN Tried to write to or read from protected location. -* @retval ::NRF_SUCCESS The command was accepted. -*/ -SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size)); - - -/**@brief Flash Erase page -* -* Commands to erase a flash page -* If the SoftDevice is enabled: -* This call initiates the flash access command, and its completion will be communicated to the -* application with exactly one of the following events: -* - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed. -* - @ref NRF_EVT_FLASH_OPERATION_ERROR - The command could not be started. -* -* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the -* erase has been completed -* -* @note -* - This call takes control over the radio and the CPU during flash erase and write to make sure that -* they will not interfere with the flash access. This means that all interrupts will be blocked -* for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual -* and the command parameters). -* -* -* @param[in] page_number Pagenumber of the page to erase -* @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. -* @retval ::NRF_ERROR_INVALID_ADDR Tried to erase to a non existing flash page. -* @retval ::NRF_ERROR_BUSY The previous command has not yet completed. -* @retval ::NRF_ERROR_FORBIDDEN Tried to erase a protected page. -* @retval ::NRF_SUCCESS The command was accepted. -*/ -SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number)); - - -/**@brief Flash Protection set - * - * Commands to set the flash protection configuration registers. - On nRF51 this sets the PROTENSETx registers of the MPU peripheral. - On nRF52 this sets the CONFIGx registers of the BPROT peripheral. - * - * @note To read the values read them directly. They are only write-protected. - * - * @param[in] block_cfg0 Value to be written to the configuration register. - * @param[in] block_cfg1 Value to be written to the configuration register. - * @param[in] block_cfg2 Value to be written to the configuration register (ignored on nRF51). - * @param[in] block_cfg3 Value to be written to the configuration register (ignored on nRF51). - * - * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice. - * @retval ::NRF_SUCCESS Values successfully written to configuration registers. - */ -SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t block_cfg0, uint32_t block_cfg1, uint32_t block_cfg2, uint32_t block_cfg3)); - -/**@brief Opens a session for radio timeslot requests. - * - * @note Only one session can be open at a time. - * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot - * starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed - * by the application. - * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0 - * interrupt occurs. - * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO - * interrupt occurs. - * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This - * implies that none of the sd_* API calls can be used from p_radio_signal_callback(). - * - * @param[in] p_radio_signal_callback The signal callback. - * - * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer. - * @retval ::NRF_ERROR_BUSY If session cannot be opened. - * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error. - * @retval ::NRF_SUCCESS Otherwise. - */ - SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback)); - -/**@brief Closes a session for radio timeslot requests. - * - * @note Any current radio timeslot will be finished before the session is closed. - * @note If a radio timeslot is scheduled when the session is closed, it will be canceled. - * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED - * event is received. - * - * @retval ::NRF_ERROR_FORBIDDEN If session not opened. - * @retval ::NRF_ERROR_BUSY If session is currently being closed. - * @retval ::NRF_SUCCESS Otherwise. - */ - SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void)); - -/**@brief Requests a radio timeslot. - * - * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST - * and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST. - * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by - * p_request->distance_us and is given relative to the start of the previous timeslot. - * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event. - * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event. - * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths. - * @note If an opportunity for the first radio timeslot is not found before 100ms after the call to this - * function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent. - * The application may then try to schedule the first radio timeslot again. - * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START). - * Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS. - * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us. - * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the - * specified radio timeslot start, but this does not affect the actual start time of the timeslot. - * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency - * (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is - * guaranteed to be clocked from the external crystal. - * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral - * during the radio timeslot. - * - * @param[in] p_request Pointer to the request parameters. - * - * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE. - * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid. - * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid. - * @retval ::NRF_SUCCESS Otherwise. - */ - SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t * p_request )); - -/**@} */ - -#ifdef __cplusplus -} -#endif -#endif // NRF_SOC_H__ - -/**@} */ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h deleted file mode 100644 index aa91e5d35e..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2000 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#ifndef NRF_SVC__ -#define NRF_SVC__ - -#include "stdint.h" - -#ifdef __cplusplus -extern "C" { -#endif - -#ifdef SVCALL_AS_NORMAL_FUNCTION -#define SVCALL(number, return_type, signature) return_type signature -#else - -#ifndef SVCALL -#if defined (__CC_ARM) -#define SVCALL(number, return_type, signature) return_type __svc(number) signature -#elif defined (__GNUC__) -#ifdef __cplusplus -#define GCC_CAST_CPP (uint16_t) -#else -#define GCC_CAST_CPP -#endif -#define SVCALL(number, return_type, signature) \ - _Pragma("GCC diagnostic push") \ - _Pragma("GCC diagnostic ignored \"-Wreturn-type\"") \ - __attribute__((naked)) \ - __attribute__((unused)) \ - static return_type signature \ - { \ - __asm( \ - "svc %0\n" \ - "bx r14" : : "I" (GCC_CAST_CPP number) : "r0" \ - ); \ - } \ - _Pragma("GCC diagnostic pop") - -#elif defined (__ICCARM__) -#define PRAGMA(x) _Pragma(#x) -#define SVCALL(number, return_type, signature) \ -PRAGMA(swi_number = (number)) \ - __swi return_type signature; -#else -#define SVCALL(number, return_type, signature) return_type signature -#endif -#endif // SVCALL - -#endif // SVCALL_AS_NORMAL_FUNCTION - -#ifdef __cplusplus -} -#endif -#endif // NRF_SVC__ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex deleted file mode 100644 index 4cfda4eec1..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex +++ /dev/null @@ -1,6783 +0,0 @@ -:020000040000FA -:10000000C0070000D1060000D1000000B1060000CA -:1000100000000000000000000000000000000000E0 -:100020000000000000000000000000005107000078 -:100030000000000000000000DB000000E500000000 -:10004000EF000000F9000000030100000D010000B6 -:1000500017010000210100002B0100003501000004 -:100060003F01000049010000530100005D01000054 -:1000700067010000710100007B01000085010000A4 -:100080008F01000099010000A3010000AD010000F4 -:10009000B7010000C1010000CB010000D501000044 -:1000A000DF010000E9010000F3010000FD01000094 -:1000B00007020000110200001B02000025020000E0 -:1000C0001FB5C046C04600F0EFFA04B00FB41FBD24 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/dev/null @@ -1,17 +0,0 @@ -#ifndef _SDK_CONFIG_H_ -#define _SDK_CONFIG_H_ - -#include "nrf_drv_config.h" - -#define UART_DEFAULT_CONFIG_BAUDRATE UART0_CONFIG_BAUDRATE -#define UART_DEFAULT_CONFIG_PARITY UART0_CONFIG_PARITY -#define UART_DEFAULT_CONFIG_HWFC UART0_CONFIG_HWFC - -#define SPIS_DEFAULT_ORC NRF_DRV_SPIS_DEFAULT_ORC -#define SPIS_DEFAULT_CONFIG_IRQ_PRIORITY SPIS1_CONFIG_IRQ_PRIORITY; -#define SPIS_DEFAULT_ORC NRF_DRV_SPIS_DEFAULT_ORC -#define SPIS_DEFAULT_DEF NRF_DRV_SPIS_DEFAULT_DEF - -#define SPI_DEFAULT_CONFIG_IRQ_PRIORITY SPI1_CONFIG_IRQ_PRIORITY - -#endif \ No newline at end of file diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.c deleted file mode 100644 index 126c33f208..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "us_ticker_api.h" -#include "common_rtc.h" -#include "app_util.h" -#include "nrf_drv_common.h" -#include "lp_ticker_api.h" -#include "mbed_critical.h" - -#if defined(NRF52_PAN_20) -/* Macro for testing if the SoftDevice is active, regardless of whether the - * application is build with the SoftDevice or not. - */ -#if defined(SOFTDEVICE_PRESENT) -#include "nrf_sdh.h" -#define NRF_HAL_SD_IS_ENABLED() nrf_sdh_is_enabled() -#else -#define NRF_HAL_SD_IS_ENABLED() 0 -#endif -#endif - - -//------------------------------------------------------------------------------ -// Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h"). -// -#include "app_util_platform.h" - -bool m_common_rtc_enabled = false; -uint32_t volatile m_common_rtc_overflows = 0; -bool volatile lp_ticker_interrupt_fire = false; - -__STATIC_INLINE void rtc_ovf_event_check(void) -{ - if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) { - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); - /* Don't disable this event. It shall occur periodically. - * It is needed for RTC. */ - - ++m_common_rtc_overflows; - } -} - -#if defined(TARGET_MCU_NRF51822) -void common_rtc_irq_handler(void) -#else -void COMMON_RTC_IRQ_HANDLER(void) -#endif -{ - rtc_ovf_event_check(); - -#if DEVICE_LPTICKER - if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT) || - lp_ticker_interrupt_fire) { - - if (lp_ticker_interrupt_fire) { - lp_ticker_interrupt_fire = false; - } - - lp_ticker_irq_handler(); - } -#endif -} - -/* Function for fix errata 20: RTC Register values are invalid. */ -__STATIC_INLINE void errata_20(void) -{ -#if defined(NRF52_PAN_20) - if (!NRF_HAL_SD_IS_ENABLED()) - { - NRF_CLOCK->EVENTS_LFCLKSTARTED = 0; - NRF_CLOCK->TASKS_LFCLKSTART = 1; - - while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) - { - } - } - NRF_RTC1->TASKS_STOP = 0; -#endif -} - -void RTC1_IRQHandler(void); - -void common_rtc_init(void) -{ - if (m_common_rtc_enabled) { -#if DEVICE_LPTICKER - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); - nrf_rtc_int_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK); -#endif - return; - } - - errata_20(); - - nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_STOP); - - NVIC_SetVector(RTC1_IRQn, (uint32_t)RTC1_IRQHandler); - - /* RTC is driven by the low frequency (32.768 kHz) clock, a proper request - * must be made to have it running. - * Currently this clock is started in 'SystemInit' (see "system_nrf51.c" - * or "system_nrf52.c", respectively). - */ - - nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0); - - /* Clear all RTC events. */ -#if defined(TARGET_MCU_NRF51822) - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT); -#endif -#if DEVICE_LPTICKER - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); -#endif - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW); - - /* Disable all RTC events (According to NRF_51 Reference Manual - * RTC events can not be used to control RTC interrupts). - * IRQ signal to NVIC is provided if interrupt is enabled. - */ - - nrf_rtc_event_disable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK -#if defined(TARGET_MCU_NRF51822) - | OS_TICK_INT_MASK -#endif -#if DEVICE_LPTICKER - | LP_TICKER_INT_MASK -#endif - ); - - /* This interrupt is enabled permanently, since overflow indications are needed - * continuously. - */ - nrf_rtc_int_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK); - - /* Disable LP ticker interrupt for now. */ -#if DEVICE_LPTICKER - nrf_rtc_int_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK); -#endif - - nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE), APP_IRQ_PRIORITY_HIGH); - - nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START); - - m_common_rtc_enabled = true; -} - -void common_rtc_free() -{ - nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_STOP); - nrf_rtc_int_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK); - NVIC_DisableIRQ(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE)); - - m_common_rtc_enabled = false; -} - -void common_rtc_set_interrupt(uint32_t ticks_count, uint32_t cc_channel, - uint32_t int_mask) -{ - /* Set ticks value when interrupt should be fired. - * Interrupt scheduling is performed in upper layers. */ - - core_util_critical_section_enter(); - - /* Wrap ticks_count before comparisons. */ - ticks_count = RTC_WRAP(ticks_count); - - /* COMPARE occurs when a CC register is N and the COUNTER value transitions from N-1 to N. - * If the COUNTER is N, writing N+2 to a CC register is guaranteed to trigger a - * COMPARE event at N+2. - */ - const uint32_t now = nrf_rtc_counter_get(COMMON_RTC_INSTANCE); - - if (now == ticks_count || - RTC_WRAP(now + 1) == ticks_count) { - ticks_count = RTC_WRAP(ticks_count + 2); - } - - nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, ticks_count); - - if (!nrf_rtc_int_is_enabled(COMMON_RTC_INSTANCE, int_mask)) { - nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT); - nrf_rtc_int_enable(COMMON_RTC_INSTANCE, int_mask); - } - - core_util_critical_section_exit(); -} - -/* Since there is no SysTick on NRF51, the RTC1 channel 0 is used as an - * alternative source of RTOS ticks. - */ -#if defined(TARGET_MCU_NRF51822) - -#include "mbed_toolchain.h" - - -#define MAX_RTC_COUNTER_VAL ((1uL << RTC_COUNTER_BITS) - 1) - -#ifndef RTC1_CONFIG_FREQUENCY - #define RTC1_CONFIG_FREQUENCY 32678 // [Hz] -#endif - - - -void COMMON_RTC_IRQ_HANDLER(void) -{ - if(!nrf_rtc_event_pending(COMMON_RTC_INSTANCE, OS_TICK_EVENT)) { - common_rtc_irq_handler(); - } -} - -IRQn_Type mbed_get_m0_tick_irqn() -{ - return SWI3_IRQn; -} - - -#endif // defined(TARGET_MCU_NRF51822) diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.h deleted file mode 100644 index dae27b263c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/common_rtc.h +++ /dev/null @@ -1,53 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2015 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef COMMON_RTC_H -#define COMMON_RTC_H - -#include "nrf_rtc.h" - -#define RTC_COUNTER_BITS 24u -#define RTC_FREQ 32768u - -// Instance 0 is reserved for SoftDevice. -// Instance 1 is used as a common one for lp_ticker and (in case -// of NRF51) as an alternative tick source for RTOS. -#define COMMON_RTC_INSTANCE NRF_RTC1 -#define COMMON_RTC_IRQ_HANDLER RTC1_IRQHandler -#define OS_TICK_CC_CHANNEL 0 -#define LP_TICKER_CC_CHANNEL 1 - -#define COMMON_RTC_EVENT_COMPARE(channel) \ - CONCAT_2(NRF_RTC_EVENT_COMPARE_, channel) -#define COMMON_RTC_INT_COMPARE_MASK(channel) \ - CONCAT_3(NRF_RTC_INT_COMPARE, channel, _MASK) - -#define OS_TICK_EVENT COMMON_RTC_EVENT_COMPARE(OS_TICK_CC_CHANNEL) -#define OS_TICK_INT_MASK COMMON_RTC_INT_COMPARE_MASK(OS_TICK_CC_CHANNEL) -#define LP_TICKER_EVENT COMMON_RTC_EVENT_COMPARE(LP_TICKER_CC_CHANNEL) -#define LP_TICKER_INT_MASK COMMON_RTC_INT_COMPARE_MASK(LP_TICKER_CC_CHANNEL) - -extern bool m_common_rtc_enabled; -extern uint32_t volatile m_common_rtc_overflows; -extern bool volatile lp_ticker_interrupt_fire; - -void common_rtc_init(void); -uint32_t common_rtc_32bit_ticks_get(void); -uint64_t common_rtc_64bit_us_get(void); -void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel, - uint32_t int_mask); - -#endif // COMMON_RTC_H diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c deleted file mode 100644 index 0d9cfff2c4..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/flash_api.c +++ /dev/null @@ -1,207 +0,0 @@ -/* - * Copyright (c) 2017 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#if DEVICE_FLASH && DEVICE_LPTICKER - -#include "hal/flash_api.h" -#include "hal/lp_ticker_api.h" - -#include "nrf_drv_common.h" -#include "nrf_nvmc.h" -#include "nrf_soc.h" - -#define WORD_WRITE_TIMEOUT_US (1 * 1000) // Max. value from datasheet: 338 us -#define PAGE_ERASE_TIMEOUT_US (200 * 1000) // Max. value from datasheet: 89.7 ms - -/* Macro for testing if the SoftDevice is active, regardless of whether the - * application is build with the SoftDevice or not. - */ -#if defined(SOFTDEVICE_PRESENT) -#include "nrf_sdm.h" -static uint8_t wrapper(void) { - uint8_t softdevice_is_enabled; - ret_code_t result = sd_softdevice_is_enabled(&softdevice_is_enabled); - return ((result == NRF_SUCCESS) && (softdevice_is_enabled == 1)); -} -#define NRF_HAL_SD_IS_ENABLED() wrapper() -#else -#define NRF_HAL_SD_IS_ENABLED() 0 -#endif - -int32_t flash_init(flash_t *obj) -{ - (void)(obj); - - /* Initialize low power ticker. Used for timeouts. */ - static bool first_init = true; - - if (first_init) { - first_init = false; - } - - return 0; -} - -int32_t flash_free(flash_t *obj) -{ - (void)(obj); - - return 0; -} - -int32_t flash_erase_sector(flash_t *obj, uint32_t address) -{ - (void)(obj); - - /* Return value defaults to error. */ - uint32_t result = NRF_ERROR_BUSY; - - if (NRF_HAL_SD_IS_ENABLED()) { - - /* Convert address to page number. */ - uint32_t page_number = address / NRF_FICR->CODEPAGESIZE; - - /* Setup stop watch for timeout. */ - uint32_t start_us = lp_ticker_read(); - uint32_t now_us = start_us; - - /* Retry if flash is busy until timeout is reached. */ - while (((now_us - start_us) < PAGE_ERASE_TIMEOUT_US) && - (result == NRF_ERROR_BUSY)) { - - result = sd_flash_page_erase(page_number); - - /* Read timeout timer. */ - now_us = lp_ticker_read(); - } - - } else { - - /* Raw API doesn't return error code, assume success. */ - nrf_nvmc_page_erase(address); - result = NRF_SUCCESS; - } - - /* Convert Nordic error code to mbed HAL error code. */ - return (result == NRF_SUCCESS) ? 0 : -1; -} - -int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size) -{ - (void)(obj); - - /* Return value defaults to error. */ - uint32_t result = NRF_ERROR_BUSY; - - /* Convert size to words. */ - uint32_t words = size / sizeof(uint32_t); - - if (NRF_HAL_SD_IS_ENABLED()) { - - /* Setup stop watch for timeout. */ - uint32_t start_us = lp_ticker_read(); - uint32_t now_us = start_us; - - /* Retry if flash is busy until timeout is reached. */ - while (((now_us - start_us) < (words * WORD_WRITE_TIMEOUT_US)) && - (result == NRF_ERROR_BUSY)) { - - result = sd_flash_write((uint32_t *) address, (const uint32_t *) data, words); - - /* Read timeout timer. */ - now_us = lp_ticker_read(); - } - - } else { - /* We will use *_words function to speed up flashing code. Word means 32bit -> 4B - * or sizeof(uint32_t). - */ - nrf_nvmc_write_words(address, (const uint32_t *) data, words); - result = NRF_SUCCESS; - } - - /* Convert Nordic error code to mbed HAL error code. */ - return (result == NRF_SUCCESS) ? 0 : -1; -} - -uint32_t flash_get_size(const flash_t *obj) -{ - (void)(obj); - - /* Just count flash size. */ - return NRF_FICR->CODESIZE * NRF_FICR->CODEPAGESIZE; -} - -uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address) -{ - (void)(obj); - - /* Test if passed address is in flash space. */ - if (address < flash_get_size(obj)) { - return NRF_FICR->CODEPAGESIZE; - } - - /* Something goes wrong, return invalid size error code. */ - return MBED_FLASH_INVALID_SIZE; -} - -uint32_t flash_get_page_size(const flash_t *obj) -{ - (void)(obj); - - /* Return minimum writeable size. Note that this is different from the erase page size. */ - return 4; -} - -uint32_t flash_get_start_address(const flash_t *obj) -{ - (void)(obj); - - return 0; -} - -uint8_t flash_get_erase_value(const flash_t *obj) -{ - (void)obj; - - return 0xFF; -} - -#endif - -/** @}*/ diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/gpio_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/gpio_api.c deleted file mode 100644 index 9407684f4a..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/gpio_api.c +++ /dev/null @@ -1,271 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "mbed_assert.h" -#include "gpio_api.h" -#include "gpio_irq_api.h" -#include "pinmap.h" -#include "nrf_drv_gpiote.h" - - -#if defined(TARGET_MCU_NRF51822) -#define GPIO_PIN_COUNT 31 -#elif defined(TARGET_MCU_NRF52832) -#define GPIO_PIN_COUNT 32 -#elif defined(TARGET_MCU_NRF52840) -#define GPIO_PIN_COUNT 48 -#else -#error not recognized gpio count for mcu -#endif - -typedef struct { - bool used_as_gpio : 1; - PinDirection direction : 1; - PinMode pull : 2; - bool used_as_irq : 1; - bool irq_fall : 1; - bool irq_rise : 1; -} gpio_cfg_t; - -#if GPIO_PIN_COUNT > 32 -typedef uint64_t gpio_mask_t; -#else -typedef uint32_t gpio_mask_t; -#endif - -static gpio_mask_t m_gpio_initialized; -static gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT]; - - -/*********** - GPIO IRQ -***********/ - -static gpio_irq_handler m_irq_handler; -static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0}; -static gpio_mask_t m_gpio_irq_enabled; - - -static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action) -{ - nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin); - gpio_irq_event event = (sense == NRF_GPIO_PIN_SENSE_LOW) ? IRQ_RISE : IRQ_FALL; - - if (m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) { - if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise) - || ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall)) { - m_irq_handler(m_channel_ids[pin], event); - } - } -} - -void GPIOTE_IRQHandler(void);// exported from nrf_drv_gpiote.c - -void gpio_init(gpio_t *obj, PinName pin) -{ - obj->pin = pin; - if (pin == (PinName)NC) { - return; - } - MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT); - - NVIC_SetVector(GPIOTE_IRQn, (uint32_t) GPIOTE_IRQHandler); - - (void) nrf_drv_gpiote_init(); - - m_gpio_cfg[obj->pin].used_as_gpio = true; -} - -#ifdef TARGET_SDK_11 -// implement polyfill of gpio hal for the nRF5 SDK v11 -__STATIC_INLINE uint32_t nrf_gpio_pin_out_read(uint32_t pin) -{ - return (NRF_GPIO->OUTSET & (1UL << (pin))); -} -#endif - -int gpio_read(gpio_t *obj) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT) { - return (nrf_gpio_pin_out_read(obj->pin) ? 1 : 0); - } else { - return nrf_gpio_pin_read(obj->pin); - } -} - -static void gpiote_pin_uninit(uint8_t pin) -{ - if (m_gpio_initialized & ((gpio_mask_t)1UL << pin)) { - if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq)) { - nrf_drv_gpiote_out_uninit(pin); - } else if (m_gpio_cfg[pin].used_as_irq) { - nrf_drv_gpiote_in_uninit(pin); - } - } -} - -static void gpio_apply_config(uint8_t pin) -{ - if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq) { - if ((m_gpio_cfg[pin].direction == PIN_INPUT) - || (m_gpio_cfg[pin].used_as_irq)) { - //Configure as input. - nrf_drv_gpiote_in_config_t cfg; - - cfg.hi_accuracy = false; - cfg.is_watcher = false; - cfg.sense = NRF_GPIOTE_POLARITY_TOGGLE; - switch (m_gpio_cfg[pin].pull) { - case PullUp: - cfg.pull = NRF_GPIO_PIN_PULLUP; - break; - case PullDown: - cfg.pull = NRF_GPIO_PIN_PULLDOWN; - break; - default: - cfg.pull = NRF_GPIO_PIN_NOPULL; - break; - } - if (m_gpio_cfg[pin].used_as_irq) { - nrf_drv_gpiote_in_init(pin, &cfg, gpiote_irq_handler); - if ((m_gpio_irq_enabled & ((gpio_mask_t)1 << pin)) - && (m_gpio_cfg[pin].irq_rise || m_gpio_cfg[pin].irq_fall)) { - nrf_drv_gpiote_in_event_enable(pin, true); - } - } else { - nrf_gpio_cfg_input(pin, cfg.pull); - } - } else { - // Configure as output. - nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(nrf_gpio_pin_out_read(pin)); - nrf_drv_gpiote_out_init(pin, &cfg); - } - m_gpio_initialized |= ((gpio_mask_t)1UL << pin); - } else { - m_gpio_initialized &= ~((gpio_mask_t)1UL << pin); - } -} - -uint32_t gpio_set(PinName pin) -{ - MBED_ASSERT(pin != (PinName)NC); - m_gpio_cfg[pin].used_as_gpio = true; - m_gpio_cfg[pin].direction = PIN_INPUT; - m_gpio_cfg[pin].pull = PullNone; - m_gpio_cfg[pin].used_as_irq = false; - m_gpio_cfg[pin].irq_fall = false; - m_gpio_cfg[pin].irq_rise = false; - - return (uint32_t)(1UL << pin); -} - -void gpio_mode(gpio_t *obj, PinMode mode) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - - gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change. - - m_gpio_cfg[obj->pin].pull = mode; - gpio_apply_config(obj->pin); -} - - -void gpio_dir(gpio_t *obj, PinDirection direction) -{ - MBED_ASSERT(obj->pin != (PinName)NC); - - gpiote_pin_uninit(obj->pin); // try to uninitialize gpio before a change. - - m_gpio_cfg[obj->pin].direction = direction; - gpio_apply_config(obj->pin); -} - - -/*********** - GPIO IRQ -***********/ - -int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) -{ - if (pin == NC) { - return -1; - } - MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT); - (void) nrf_drv_gpiote_init(); - - gpiote_pin_uninit(pin); // try to uninitialize gpio before a change. - - m_gpio_cfg[pin].used_as_irq = true; - m_gpio_cfg[pin].pull = PullNone; - m_channel_ids[pin] = id; - obj->ch = pin; - m_irq_handler = handler; - m_channel_ids[pin] = id; - - gpio_apply_config(pin); - return 0; -} - - -void gpio_irq_free(gpio_irq_t *obj) -{ - nrf_drv_gpiote_in_uninit(obj->ch); - m_gpio_cfg[obj->ch].used_as_irq = false; - m_channel_ids[obj->ch] = 0; - - gpio_apply_config(obj->ch); -} - - -void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) -{ - gpio_cfg_t *cfg = &m_gpio_cfg[obj->ch]; - bool irq_enabled_before = - (m_gpio_irq_enabled & ((gpio_mask_t)1 << obj->ch)) && - (cfg->irq_rise || cfg->irq_fall); - - if (event == IRQ_RISE) { - cfg->irq_rise = enable ? true : false; - } else if (event == IRQ_FALL) { - cfg->irq_fall = enable ? true : false; - } - - bool irq_enabled_after = cfg->irq_rise || cfg->irq_fall; - - if (irq_enabled_before != irq_enabled_after) { - if (irq_enabled_after) { - gpio_irq_enable(obj); - } else { - gpio_irq_disable(obj); - } - } -} - - -void gpio_irq_enable(gpio_irq_t *obj) -{ - m_gpio_irq_enabled |= ((gpio_mask_t)1 << obj->ch); - if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall) { - nrf_drv_gpiote_in_event_enable(obj->ch, true); - } -} - - -void gpio_irq_disable(gpio_irq_t *obj) -{ - m_gpio_irq_enabled &= ~((gpio_mask_t)1 << obj->ch); - nrf_drv_gpiote_in_event_disable(obj->ch); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/i2c_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/i2c_api.c deleted file mode 100644 index 9d0740f018..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/i2c_api.c +++ /dev/null @@ -1,776 +0,0 @@ -/* - * Copyright (c) 2017 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#include "i2c_api.h" - -#if DEVICE_I2C && DEVICE_LPTICKER - -#include "mbed_assert.h" -#include "mbed_error.h" -#include "nrf_twi.h" -#include "nrf_drv_common.h" -#include "sdk_config.h" -#include "app_util_platform.h" -#include "nrf_gpio.h" -#include "nrf_delay.h" - -#include "us_ticker_api.h" - -// An arbitrary value used as the timeout in loops waiting for given event -// (e.g. STOPPED), needed to avoid infinite loops. -// This value might be defined externally. -#ifndef I2C_TIMEOUT_VALUE_US - #define I2C_TIMEOUT_VALUE_US 1000000 -#endif - -#if DEVICE_I2C_ASYNCH - #define TWI_IDX(obj) ((obj)->i2c.twi_idx) -#else - #define TWI_IDX(obj) ((obj)->twi_idx) -#endif -#define TWI_INFO(obj) (&m_twi_info[TWI_IDX(obj)]) - -#ifdef TARGET_SDK13 - #define TWI0_INSTANCE_INDEX 0 - #define TWI1_INSTANCE_INDEX TWI0_INSTANCE_INDEX+TWI0_ENABLED -#endif - -typedef struct { - bool initialized; - uint32_t pselsda; - uint32_t pselscl; - nrf_twi_frequency_t frequency; - bool start_twi; - -#if DEVICE_I2C_ASYNCH - volatile bool active; - uint8_t const *tx; - size_t tx_length; - uint8_t *rx; - size_t rx_length; - bool stop; - - volatile uint32_t events; - void (*handler)(void); - uint32_t evt_mask; -#endif // DEVICE_I2C_ASYNCH -} twi_info_t; -static twi_info_t m_twi_info[TWI_COUNT]; - -static NRF_TWI_Type * const m_twi_instances[TWI_COUNT] = { -#if TWI0_ENABLED - NRF_TWI0, -#endif -#if TWI1_ENABLED - NRF_TWI1, -#endif -}; - -// Pinmap used for testing only -static const PinMap PinMap_I2C_testing[] = { - {p0, 0, 0}, - {p1, 0, 0}, - {p2, 0, 0}, - {p3, 0, 0}, - {p4, 0, 0}, - {p5, 0, 0}, - {p6, 0, 0}, - {p7, 0, 0}, - {p8, 0, 0}, - {p9, 0, 0}, - {p10, 0, 0}, - {p11, 0, 0}, - {p12, 0, 0}, - {p13, 0, 0}, - {p14, 0, 0}, - {p15, 0, 0}, - {p16, 0, 0}, - {p17, 0, 0}, - {p18, 0, 0}, - {p19, 0, 0}, - {p20, 0, 0}, - {p21, 0, 0}, - {p22, 0, 0}, - {p23, 0, 0}, - {p24, 0, 0}, - {p25, 0, 0}, - - {p28, 0, 0}, - {p29, 0, 0}, - {p30, 0, 0}, - - {NC, NC, 0} -}; - -void SPI0_TWI0_IRQHandler(void); -void SPI1_TWI1_IRQHandler(void); - -static const peripheral_handler_desc_t twi_handlers[TWI_COUNT] = -{ -#if TWI0_ENABLED - { - SPI0_TWI0_IRQn, - (uint32_t) SPI0_TWI0_IRQHandler - }, -#endif -#if TWI1_ENABLED - { - SPI1_TWI1_IRQn, - (uint32_t) SPI1_TWI1_IRQHandler - } -#endif -}; -#ifdef NRF51 - #define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) || defined(NRF52840_XXAA) - #define TWI_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST -#endif - - -#if DEVICE_I2C_ASYNCH -static void start_asynch_rx(twi_info_t *twi_info, NRF_TWI_Type *twi) -{ - if (twi_info->rx_length == 1 && twi_info->stop) { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); - } else { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK); - } - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX); -} - -static void twi_irq_handler(uint8_t instance_idx) -{ - twi_info_t *twi_info = &m_twi_info[instance_idx]; - - NRF_TWI_Type *twi = m_twi_instances[instance_idx]; - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - - // In case of an error, force STOP. - // The current transfer may be suspended (if it is RX), so it must be - // resumed before the STOP task is triggered. - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); - twi_info->events |= I2C_EVENT_ERROR; - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) { - twi_info->events |= I2C_EVENT_ERROR_NO_SLAVE; - } - if (errorsrc & NRF_TWI_ERROR_DATA_NACK) { - twi_info->events |= I2C_EVENT_TRANSFER_EARLY_NACK; - } - } - - bool finished = false; - - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - - MBED_ASSERT(twi_info->tx_length > 0); - --(twi_info->tx_length); - // Send next byte if there is still something to be sent. - if (twi_info->tx_length > 0) { - nrf_twi_txd_set(twi, *(twi_info->tx)); - ++(twi_info->tx); - // It TX is done, start RX if requested. - } else if (twi_info->rx_length > 0) { - start_asynch_rx(twi_info, twi); - // If there is nothing more to do, finalize the transfer. - } else { - if (twi_info->stop) { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - } else { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); - finished = true; - } - twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE; - } - } - - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - - MBED_ASSERT(twi_info->rx_length > 0); - *(twi_info->rx) = nrf_twi_rxd_get(twi); - ++(twi_info->rx); - --(twi_info->rx_length); - - if (twi_info->rx_length > 0) { - // If more bytes should be received, resume the transfer - // (in case the stop condition should be generated after the next - // byte, change the shortcuts configuration first). - if (twi_info->rx_length == 1 && twi_info->stop) { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - } else { - // If all requested bytes were received, finalize the transfer. - finished = true; - twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE; - } - } - - if (finished || - nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED) || - (nrf_twi_int_enable_check(twi, NRF_TWI_INT_SUSPENDED_MASK) && - nrf_twi_event_check(twi, NRF_TWI_EVENT_SUSPENDED))) { - // There is no need to clear the STOPPED and SUSPENDED events here, - // they will no longer generate the interrupt - see below. - - nrf_twi_shorts_set(twi, 0); - // Disable all interrupt sources. - nrf_twi_int_disable(twi, UINT32_MAX); - twi_info->active = false; - - if (twi_info->handler) { - twi_info->handler(); - } - } -} - -#if TWI0_ENABLED -static void irq_handler_twi0(void) -{ - twi_irq_handler(TWI0_INSTANCE_INDEX); -} -#endif -#if TWI1_ENABLED -static void irq_handler_twi1(void) -{ - twi_irq_handler(TWI1_INSTANCE_INDEX); -} -#endif -static nrf_drv_irq_handler_t const m_twi_irq_handlers[TWI_COUNT] = -{ -#if TWI0_ENABLED - irq_handler_twi0, -#endif -#if TWI1_ENABLED - irq_handler_twi1, -#endif -}; -#endif // DEVICE_I2C_ASYNCH - - -static void configure_twi_pin(uint32_t pin, nrf_gpio_pin_dir_t dir) -{ - nrf_gpio_cfg(pin, - dir, - NRF_GPIO_PIN_INPUT_CONNECT, - NRF_GPIO_PIN_PULLUP, - NRF_GPIO_PIN_S0D1, - NRF_GPIO_PIN_NOSENSE); -} - -static void twi_clear_bus(twi_info_t *twi_info) -{ - // Try to set SDA high, and check if no slave tries to drive it low. - nrf_gpio_pin_set(twi_info->pselsda); - configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_OUTPUT); - // In case SDA is low, make up to 9 cycles on SCL line to help the slave - // that pulls SDA low release it. - if (!nrf_gpio_pin_read(twi_info->pselsda)) { - nrf_gpio_pin_set(twi_info->pselscl); - configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_OUTPUT); - nrf_delay_us(4); - - for (int i = 0; i < 9; i++) { - if (nrf_gpio_pin_read(twi_info->pselsda)) { - break; - } - nrf_gpio_pin_clear(twi_info->pselscl); - nrf_delay_us(4); - nrf_gpio_pin_set(twi_info->pselscl); - nrf_delay_us(4); - } - - // Finally, generate STOP condition to put the bus into initial state. - nrf_gpio_pin_clear(twi_info->pselsda); - nrf_delay_us(4); - nrf_gpio_pin_set(twi_info->pselsda); - } -} - -void i2c_init(i2c_t *obj, PinName sda, PinName scl) -{ - ret_code_t ret; - int i; - - for (i = 0; i < TWI_COUNT; ++i) { - if (m_twi_info[i].initialized && - m_twi_info[i].pselsda == (uint32_t)sda && - m_twi_info[i].pselscl == (uint32_t)scl) { - TWI_IDX(obj) = i; - TWI_INFO(obj)->frequency = NRF_TWI_FREQ_100K; - i2c_reset(obj); - return; - } - } - - for (i = 0; i < TWI_COUNT; ++i) { - if (!m_twi_info[i].initialized) { - ret = nrf_drv_common_per_res_acquire(m_twi_instances[i], - m_twi_irq_handlers[i]); - - if (ret != NRF_SUCCESS) { - continue; /* the hw resource is busy - test another one */ - } - - TWI_IDX(obj) = i; - - twi_info_t *twi_info = TWI_INFO(obj); - twi_info->initialized = true; - twi_info->pselsda = (uint32_t)sda; - twi_info->pselscl = (uint32_t)scl; - twi_info->frequency = NRF_TWI_FREQ_100K; - twi_info->start_twi = false; -#if DEVICE_I2C_ASYNCH - twi_info->active = false; -#endif - - twi_clear_bus(twi_info); - - configure_twi_pin(twi_info->pselsda, NRF_GPIO_PIN_DIR_INPUT); - configure_twi_pin(twi_info->pselscl, NRF_GPIO_PIN_DIR_INPUT); - - i2c_reset(obj); - -#if DEVICE_I2C_ASYNCH - NVIC_SetVector(twi_handlers[i].IRQn, twi_handlers[i].vector); - nrf_drv_common_irq_enable(twi_handlers[i].IRQn, TWI_IRQ_PRIORITY); -#endif - - return; - } - } - - error("No available I2C peripheral\r\n"); -} - -void i2c_reset(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - nrf_twi_disable(twi); - nrf_twi_pins_set(twi, twi_info->pselscl, twi_info->pselsda); - nrf_twi_frequency_set(twi, twi_info->frequency); - nrf_twi_enable(twi); -} - -int i2c_start(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); -#if DEVICE_I2C_ASYNCH - if (twi_info->active) { - return I2C_ERROR_BUS_BUSY; - } -#endif - twi_info->start_twi = true; - - return 0; -} - -int i2c_stop(i2c_t *obj) -{ - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - uint32_t t0; - - // The current transfer may be suspended (if it is RX), so it must be - // resumed before the STOP task is triggered. - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - - t0 = ticker_read(get_us_ticker_data()); - - do { - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_STOPPED)) { - return 0; - } - } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US); - - return 1; -} - -void i2c_frequency(i2c_t *obj, int hz) -{ - twi_info_t *twi_info = TWI_INFO(obj); - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - if (hz < 250000) { - twi_info->frequency = NRF_TWI_FREQ_100K; - } else if (hz < 400000) { - twi_info->frequency = NRF_TWI_FREQ_250K; - } else { - twi_info->frequency = NRF_TWI_FREQ_400K; - } - nrf_twi_frequency_set(twi, twi_info->frequency); -} - -static uint8_t twi_address(int i2c_address) -{ - // The TWI peripheral requires 7-bit slave address (without R/W bit). - return (i2c_address >> 1); -} - -static void start_twi_read(NRF_TWI_Type *twi, int address) -{ - nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - (void)nrf_twi_errorsrc_get_and_clear(twi); - - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_SUSPEND_MASK); - - nrf_twi_address_set(twi, twi_address(address)); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTRX); -} - -int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) -{ - // Zero-length RX transfers are not supported. Such transfers cannot - // be easily achieved with TWI peripheral (some dirty tricks would be - // required for this), and they are actually useless (TX can be used - // to check if the address is acknowledged by a slave). - MBED_ASSERT(length > 0); - - twi_info_t *twi_info = TWI_INFO(obj); -#if DEVICE_I2C_ASYNCH - if (twi_info->active) { - return I2C_ERROR_BUS_BUSY; - } -#endif - twi_info->start_twi = false; - - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - start_twi_read(twi, address); - - int result = length; - while (length > 0) { - int byte_read_result = i2c_byte_read(obj, (stop && length == 1)); - if (byte_read_result < 0) { - // When an error occurs, return the number of bytes that have been - // received successfully. - result -= length; - // Force STOP condition. - stop = 1; - break; - } - *data++ = (uint8_t)byte_read_result; - --length; - } - - if (stop) { - (void)i2c_stop(obj); - } - - return result; -} - -static uint8_t twi_byte_write(NRF_TWI_Type *twi, uint8_t data) -{ - uint32_t t0; - - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - - nrf_twi_txd_set(twi, data); - - t0 = ticker_read(get_us_ticker_data()); - - do { - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_TXDSENT)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - return 1; // ACK received - } - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - return 0; // some error occurred - } - } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US); - - return 2; // timeout; -} - -static void start_twi_write(NRF_TWI_Type *twi, int address) -{ - nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - (void)nrf_twi_errorsrc_get_and_clear(twi); - - nrf_twi_shorts_set(twi, 0); - - nrf_twi_address_set(twi, twi_address(address)); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX); -} - -int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) -{ - twi_info_t *twi_info = TWI_INFO(obj); - bool timeout = false; - uint32_t t0, t1; - -#if DEVICE_I2C_ASYNCH - if (twi_info->active) { - return I2C_ERROR_BUS_BUSY; - } -#endif - twi_info->start_twi = false; - - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - start_twi_write(twi, address); - - // Special case - transaction with no data. - // It can be used to check if a slave acknowledges the address. - if (length == 0) { - nrf_twi_event_t event; - if (stop) { - event = NRF_TWI_EVENT_STOPPED; - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - } else { - event = NRF_TWI_EVENT_SUSPENDED; - nrf_twi_event_clear(twi, event); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); - } - - t0 = ticker_read(get_us_ticker_data()); - - do { - if (nrf_twi_event_check(twi, event)) { - break; - } - t1 = ticker_read(get_us_ticker_data()); - timeout = (t1 - t0) >= I2C_TIMEOUT_VALUE_US; - } while (!timeout); - - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) { - if (!stop) { - i2c_stop(obj); - } - return I2C_ERROR_NO_SLAVE; - } - - return (timeout ? I2C_ERROR_BUS_BUSY : 0); - } - - int result = length; - do { - uint8_t byte_write_result = twi_byte_write(twi, (uint8_t)*data++); - if (byte_write_result != 1) { - if (byte_write_result == 0) { - // Check what kind of error has been signaled by TWI. - uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(twi); - if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK) { - result = I2C_ERROR_NO_SLAVE; - } else { - // Some other error - return the number of bytes that - // have been sent successfully. - result -= length; - } - } else { - result = I2C_ERROR_BUS_BUSY; - } - // Force STOP condition. - stop = 1; - break; - } - --length; - } while (length > 0); - - if (stop) { - (void)i2c_stop(obj); - } - - return result; -} - -int i2c_byte_read(i2c_t *obj, int last) -{ - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - uint32_t t0; - - if (last) { - nrf_twi_shorts_set(twi, NRF_TWI_SHORT_BB_STOP_MASK); - } - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - - t0 = ticker_read(get_us_ticker_data()); - - do { - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_RXDREADY)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - return nrf_twi_rxd_get(twi); - } - if (nrf_twi_event_check(twi, NRF_TWI_EVENT_ERROR)) { - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - return I2C_ERROR_NO_SLAVE; - } - } while (((uint32_t)ticker_read(get_us_ticker_data()) - t0) < I2C_TIMEOUT_VALUE_US); - - return I2C_ERROR_BUS_BUSY; -} - -int i2c_byte_write(i2c_t *obj, int data) -{ - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - twi_info_t *twi_info = TWI_INFO(obj); - if (twi_info->start_twi) { - twi_info->start_twi = false; - - if (data & 1) { - start_twi_read(twi, data); - } else { - start_twi_write(twi, data); - } - return 1; - } else { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - // 0 - TWI signaled error (NAK is the only possibility here) - // 1 - ACK received - // 2 - timeout (clock stretched for too long?) - return twi_byte_write(twi, (uint8_t)data); - } -} - -const PinMap *i2c_master_sda_pinmap() -{ - return PinMap_I2C_testing; -} - -const PinMap *i2c_master_scl_pinmap() -{ - return PinMap_I2C_testing; -} - -const PinMap *i2c_slave_sda_pinmap() -{ - return PinMap_I2C_testing; -} - -const PinMap *i2c_slave_scl_pinmap() -{ - return PinMap_I2C_testing; -} - - -#if DEVICE_I2C_ASYNCH -void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, - void *rx, size_t rx_length, uint32_t address, - uint32_t stop, uint32_t handler, - uint32_t event, DMAUsage hint) -{ - (void)hint; - - twi_info_t *twi_info = TWI_INFO(obj); - if (twi_info->active) { - return; - } - twi_info->active = true; - twi_info->events = 0; - twi_info->handler = (void (*)(void))handler; - twi_info->evt_mask = event; - twi_info->tx_length = tx_length; - twi_info->tx = tx; - twi_info->rx_length = rx_length; - twi_info->rx = rx; - twi_info->stop = stop; - - NRF_TWI_Type *twi = m_twi_instances[TWI_IDX(obj)]; - - nrf_twi_event_clear(twi, NRF_TWI_EVENT_TXDSENT); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_RXDREADY); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_STOPPED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_SUSPENDED); - nrf_twi_event_clear(twi, NRF_TWI_EVENT_ERROR); - (void)nrf_twi_errorsrc_get_and_clear(twi); - - nrf_twi_address_set(twi, twi_address(address)); - nrf_twi_task_trigger(twi, NRF_TWI_TASK_RESUME); - // TX only, or TX + RX (after a repeated start). - if (tx_length > 0) { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX); - nrf_twi_txd_set(twi, *(twi_info->tx)); - ++(twi_info->tx); - // RX only. - } else if (rx_length > 0) { - start_asynch_rx(twi_info, twi); - // Both 'tx_length' and 'rx_length' are 0 - this case may be used - // to test if the slave is presentand ready for transfer (by just - // sending the address and checking if it is acknowledged). - } else { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STARTTX); - if (stop) { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_STOP); - } else { - nrf_twi_task_trigger(twi, NRF_TWI_TASK_SUSPEND); - nrf_twi_int_enable(twi, NRF_TWI_INT_SUSPENDED_MASK); - } - twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE; - } - - nrf_twi_int_enable(twi, NRF_TWI_INT_TXDSENT_MASK | - NRF_TWI_INT_RXDREADY_MASK | - NRF_TWI_INT_STOPPED_MASK | - NRF_TWI_INT_ERROR_MASK); -} - -uint32_t i2c_irq_handler_asynch(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); - return (twi_info->events & twi_info->evt_mask); -} - -uint8_t i2c_active(i2c_t *obj) -{ - twi_info_t *twi_info = TWI_INFO(obj); - return twi_info->active; -} - -void i2c_abort_asynch(i2c_t *obj) -{ - i2c_reset(obj); -} -#endif // DEVICE_I2C_ASYNCH - -#endif // DEVICE_I2C diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/irq_handlers_hw.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/irq_handlers_hw.h deleted file mode 100644 index 7eba37ad99..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/irq_handlers_hw.h +++ /dev/null @@ -1,55 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -/** - * @file irq_handlers_hw.h - * @brief Heleper file for wiring irq handlers to theirs vectors. - */ - -#ifndef IRQ_HANDLERS_HW_H__ -#define IRQ_HANDLERS_HW_H__ - - -typedef struct -{ - IRQn_Type IRQn; - uint32_t vector; -} peripheral_handler_desc_t; - -#endif // IRQ_HANDLERS_HW_H__ - diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/nordic_critical.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/nordic_critical.c deleted file mode 100644 index f1937d3787..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/nordic_critical.c +++ /dev/null @@ -1,107 +0,0 @@ -/* - * Copyright (c) 2015-2016, ARM Limited, All Rights Reserved - * SPDX-License-Identifier: Apache-2.0 - * - * Licensed under the Apache License, Version 2.0 (the "License"); you may - * not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#include -#include "app_util_platform.h" - -#if defined(SOFTDEVICE_PRESENT) -static volatile bool state_saved = false; - -static void nordic_nvic_critical_region_enter(void); -static void nordic_nvic_critical_region_exit(void); -#endif - -void hal_critical_section_enter() -{ -#ifdef NRF52 - ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) -#endif - -#if defined(SOFTDEVICE_PRESENT) - /* return value can be safely ignored */ - nordic_nvic_critical_region_enter(); -#else - app_util_disable_irq(); -#endif -} - -void hal_critical_section_exit() -{ -#ifdef NRF52 - ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get()) -#endif - -#if defined(SOFTDEVICE_PRESENT) - /* return value can be safely ignored */ - nordic_nvic_critical_region_exit(); -#else - app_util_enable_irq(); -#endif -} - - -bool hal_in_critical_section(void) -{ - return (state_saved != 0); -} - - -#if defined(SOFTDEVICE_PRESENT) -/**@brief Enters critical region. - * - * @post Application interrupts will be disabled. - * @sa nordic_nvic_critical_region_exit - */ -static inline void nordic_nvic_critical_region_enter(void) -{ - int was_masked = __sd_nvic_irq_disable(); - - if (state_saved == false) { - nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 ); - NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0; -#ifdef NRF52 - nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 ); - NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1; -#endif - } - - state_saved = true; - - if (!was_masked) { - __sd_nvic_irq_enable(); - } -} - -/**@brief Exit critical region. - * - * @pre Application has entered a critical region using ::nordic_nvic_critical_region_enter. - * @post If not in a nested critical region, the application interrupts will restored to the state before ::nordic_nvic_critical_region_enter was called. - */ -static inline void nordic_nvic_critical_region_exit(void) -{ - state_saved = false; - - int was_masked = __sd_nvic_irq_disable(); - NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0]; -#ifdef NRF52 - NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1]; -#endif - if (!was_masked) { - __sd_nvic_irq_enable(); - } -} -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/objects.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/objects.h deleted file mode 100644 index c626bc20bc..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/objects.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#ifndef MBED_OBJECTS_H -#define MBED_OBJECTS_H - -#include "cmsis.h" -#include "PortNames.h" -#include "PeripheralNames.h" -#include "PinNames.h" - -#ifdef __cplusplus -extern "C" { -#endif - -struct serial_s { - uint32_t placeholder; // struct is unused by nRF5x API implementation -}; // but it must be not empty (required by strict compiler - IAR) - -struct spi_s { - uint8_t spi_idx; -}; - -struct port_s { - PortName port; - uint32_t mask; -}; - -struct pwmout_s { - PWMName pwm_name; - PinName pin; - uint8_t pwm_channel; - void * pwm_struct; -}; - -struct i2c_s { - uint8_t twi_idx; -}; - -struct analogin_s { - ADCName adc; - uint8_t adc_pin; -}; - -struct gpio_irq_s { - uint32_t ch; -}; - -struct flash_s { - uint32_t placeholder; -}; - -struct trng_s { - uint32_t placeholder; -}; - -#include "gpio_object.h" - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/reloc_vector_table.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/reloc_vector_table.c deleted file mode 100644 index 8bf23254de..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/reloc_vector_table.c +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2016 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "nrf.h" -#include "cmsis_nvic.h" -#include "stdint.h" -#include "nrf_sdm.h" -#include "section_vars.h" - -#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) - __attribute__ ((section(".bss.noinit"),zero_init)) - uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS]; -#elif defined(__GNUC__) - __attribute__ ((section(".noinit"))) - uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS]; -#elif defined(__ICCARM__) - uint32_t nrf_dispatch_vector[NVIC_NUM_VECTORS] @ ".noinit"; -#endif - - -typedef void (*generic_irq_handler_t)(void); - - -extern uint32_t __Vectors[]; -#define VECTORS_FLASH_START __Vectors - -/** - * @brief Function for relocation of the vector to RAM on nRF5x devices. - * This function is intended to be called during startup. - */ -void nrf_reloc_vector_table(void) -{ - // Copy and switch to dynamic vectors - uint32_t *old_vectors = (uint32_t*)VECTORS_FLASH_START; - uint32_t i; - for (i = 0; i< NVIC_NUM_VECTORS; i++) { - nrf_dispatch_vector[i] = old_vectors[i]; - } - - sd_softdevice_vector_table_base_set((uint32_t) nrf_dispatch_vector); -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/serial_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/serial_api.c deleted file mode 100644 index bd29f4ccbc..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/serial_api.c +++ /dev/null @@ -1,720 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "serial_api.h" - -#if DEVICE_SERIAL - -#include -#include "mbed_assert.h" -#include "mbed_error.h" -#include "nrf_uart.h" -#include "nrf_drv_common.h" -#include "app_util_platform.h" -#include "nrf_gpio.h" -#include "sdk_config.h" - -#define UART_INSTANCE_COUNT 1 -#define UART_INSTANCE NRF_UART0 -#define UART_IRQn UART0_IRQn -#define UART_IRQ_HANDLER UART0_IRQHandler -#define UART_INSTANCE_ID 0 -#define UART_CB uart_cb[UART_INSTANCE_ID] - -#define UART_DEFAULT_BAUDRATE UART_DEFAULT_CONFIG_BAUDRATE -#define UART_DEFAULT_PARITY UART_DEFAULT_CONFIG_PARITY - -// expected the macro from mbed configuration system -#ifndef MBED_CONF_NORDIC_UART_HWFC - #define MBED_CONF_NORDIC_UART_HWFC 1 - #warning None of UART flow control configuration (expected macro MBED_CONF_NORDIC_UART_HWFC). The RTSCTS flow control is used by default . -#endif - -#if MBED_CONF_NORDIC_UART_HWFC == 1 - #define UART_DEFAULT_HWFC UART_DEFAULT_CONFIG_HWFC -#else - #define UART_DEFAULT_HWFC NRF_UART_HWFC_DISABLED -#endif - -#define UART_DEFAULT_CTS CTS_PIN_NUMBER -#define UART_DEFAULT_RTS RTS_PIN_NUMBER - -#ifdef NRF51 - #define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW -#elif defined(NRF52) || defined(NRF52840_XXAA) - #define NRFx_MBED_UART_IRQ_PRIORITY APP_IRQ_PRIORITY_LOWEST -#endif - -// Required by "retarget.cpp". -int stdio_uart_inited = 0; -serial_t stdio_uart; - -typedef struct { - bool initialized; - uint32_t irq_context; - uart_irq_handler irq_handler; - - uint32_t pselrxd; - uint32_t pseltxd; - uint32_t pselcts; - uint32_t pselrts; - nrf_uart_hwfc_t hwfc; - nrf_uart_parity_t parity; - nrf_uart_baudrate_t baudrate; - -#if DEVICE_SERIAL_ASYNCH - bool volatile rx_active; - uint8_t *rx_buffer; - size_t rx_length; - size_t rx_pos; - void (*rx_asynch_handler)(); - uint8_t char_match; - - bool volatile tx_active; - const uint8_t *tx_buffer; - size_t tx_length; - size_t tx_pos; - void (*tx_asynch_handler)(); - - uint32_t events_wanted; - uint32_t events_occured; - - #define UART_IRQ_TX 1 - #define UART_IRQ_RX 2 - uint8_t irq_enabled; -#endif // DEVICE_SERIAL_ASYNCH -} uart_ctlblock_t; - -static uart_ctlblock_t uart_cb[UART_INSTANCE_COUNT]; - -static void internal_set_hwfc(FlowControl type, - PinName rxflow, PinName txflow); - -// Pinmap used for testing only -static const PinMap PinMap_UART_testing[] = { - {p0, 0, 0}, - {p1, 0, 0}, - {p2, 0, 0}, - {p3, 0, 0}, - {p4, 0, 0}, - {p5, 0, 0}, - {p6, 0, 0}, - {p7, 0, 0}, - {p8, 0, 0}, - {p9, 0, 0}, - {p10, 0, 0}, - {p11, 0, 0}, - {p12, 0, 0}, - {p13, 0, 0}, - {p14, 0, 0}, - {p15, 0, 0}, - {p16, 0, 0}, - {p17, 0, 0}, - {p18, 0, 0}, - {p19, 0, 0}, - {p20, 0, 0}, - {p21, 0, 0}, - {p22, 0, 0}, - {p23, 0, 0}, - {p24, 0, 0}, - {p25, 0, 0}, - - {p28, 0, 0}, - {p29, 0, 0}, - {p30, 0, 0}, - - {NC, NC, 0} -}; - -#if DEVICE_SERIAL_ASYNCH -static void end_asynch_rx(void) -{ - // If RX interrupt is activated for synchronous operations, - // don't disable it, just stop handling it here. - if (!(UART_CB.irq_enabled & UART_IRQ_RX)) { - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY); - } - UART_CB.rx_active = false; -} -static void end_asynch_tx(void) -{ - // If TX interrupt is activated for synchronous operations, - // don't disable it, just stop handling it here. - if (!(UART_CB.irq_enabled & UART_IRQ_TX)) { - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY); - } - UART_CB.tx_active = false; -} -#endif // DEVICE_SERIAL_ASYNCH - -void UART_IRQ_HANDLER(void) -{ - if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY) && - nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY)) { - - #if DEVICE_SERIAL_ASYNCH - if (UART_CB.rx_active) { - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY); - - uint8_t rx_data = nrf_uart_rxd_get(UART_INSTANCE); - UART_CB.rx_buffer[UART_CB.rx_pos] = rx_data; - - bool end_rx = false; - // If character matching should be performed, check if the current - // data matches the given one. - if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH && - rx_data == UART_CB.char_match) { - // If it does, report the match and abort further receiving. - UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH; - if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) { - end_rx = true; - } - } - if (++UART_CB.rx_pos >= UART_CB.rx_length) { - UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE; - end_rx = true; - } - if (end_rx) { - end_asynch_rx(); - - if (UART_CB.rx_asynch_handler) { - // Use local variable to make it possible to start a next - // transfer from callback routine. - void (*handler)() = UART_CB.rx_asynch_handler; - UART_CB.rx_asynch_handler = NULL; - handler(); - } - } - } - else - #endif - - if (UART_CB.irq_handler) { - UART_CB.irq_handler(UART_CB.irq_context, RxIrq); - } - } - - if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY) && - nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) { - - #if DEVICE_SERIAL_ASYNCH - if (UART_CB.tx_active) { - if (UART_CB.tx_pos < UART_CB.tx_length) { - // When there is still something to send, clear the TXDRDY event - // and put next byte to transmitter. - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY); - nrf_uart_txd_set(UART_INSTANCE, - UART_CB.tx_buffer[UART_CB.tx_pos]); - UART_CB.tx_pos++; - } - else { - // When the TXDRDY event is set after the last byte to be sent - // has been passed to the transmitter, the job is done and TX - // complete can be indicated. - // Don't clear the TXDRDY event, it needs to remain set for the - // 'serial_writable' function to work properly. - end_asynch_tx(); - - UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE; - if (UART_CB.tx_asynch_handler) { - // Use local variable to make it possible to start a next - // transfer from callback routine. - void (*handler)() = UART_CB.tx_asynch_handler; - UART_CB.tx_asynch_handler = NULL; - handler(); - } - } - } - else - #endif - - if (UART_CB.irq_handler) { - UART_CB.irq_handler(UART_CB.irq_context, TxIrq); - } - } - -#if DEVICE_SERIAL_ASYNCH - if (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_ERROR)) { - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR); - - uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE); - if (UART_CB.rx_asynch_handler) { - UART_CB.events_occured |= SERIAL_EVENT_ERROR; - if (errorsrc & NRF_UART_ERROR_PARITY_MASK) { - UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR; - } - if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) { - UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR; - } - if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) { - UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR; - } - UART_CB.rx_asynch_handler(); - } - } -#endif // DEVICE_SERIAL_ASYNCH -} - -void serial_init(serial_t *obj, PinName tx, PinName rx) { - - NVIC_SetVector(UART0_IRQn, (uint32_t) UART0_IRQHandler); - - - UART_CB.pseltxd = - (tx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)tx; - UART_CB.pselrxd = - (rx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rx; - if (UART_CB.pseltxd != NRF_UART_PSEL_DISCONNECTED) { - nrf_gpio_pin_set(UART_CB.pseltxd); - nrf_gpio_cfg_output(UART_CB.pseltxd); - } - if (UART_CB.pselrxd != NRF_UART_PSEL_DISCONNECTED) { - nrf_gpio_cfg_input(UART_CB.pselrxd, NRF_GPIO_PIN_NOPULL); - } - - if (UART_CB.initialized) { - // For already initialized peripheral it is sufficient to reconfigure - // RX/TX pins only. - - // Ensure that there is no unfinished TX transfer. - while (!serial_writable(obj)) { - } - // UART pins can be configured only when the peripheral is disabled. - nrf_uart_disable(UART_INSTANCE); - nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd); - nrf_uart_enable(UART_INSTANCE); - } - else { - UART_CB.baudrate = UART_DEFAULT_BAUDRATE; - UART_CB.parity = UART_DEFAULT_PARITY; - UART_CB.hwfc = UART_DEFAULT_HWFC; - UART_CB.pselcts = UART_DEFAULT_CTS; - UART_CB.pselrts = UART_DEFAULT_RTS; - - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY); - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX); - - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_TXDRDY); - #if DEVICE_SERIAL_ASYNCH - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR); - #endif - nrf_drv_common_irq_enable(UART_IRQn, NRFx_MBED_UART_IRQ_PRIORITY); - - // TX interrupt needs to be signaled when transmitter buffer is empty, - // so a dummy transmission is needed to get the TXDRDY event initially - // set. - nrf_uart_configure(UART_INSTANCE, - NRF_UART_PARITY_EXCLUDED, NRF_UART_HWFC_DISABLED); - // Use maximum baud rate, so this dummy transmission takes as little - // time as possible. - nrf_uart_baudrate_set(UART_INSTANCE, NRF_UART_BAUDRATE_1000000); - // Perform it with disconnected TX pin, so nothing actually comes out - // of the device. - nrf_uart_txrx_pins_disconnect(UART_INSTANCE); - nrf_uart_hwfc_pins_disconnect(UART_INSTANCE); - nrf_uart_enable(UART_INSTANCE); - nrf_uart_txd_set(UART_INSTANCE, 0); - while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) { - } - nrf_uart_disable(UART_INSTANCE); - - // Now everything is prepared to set the default configuration and - // connect the peripheral to actual pins. - nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd); - nrf_uart_baudrate_set(UART_INSTANCE, UART_CB.baudrate); - nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); - if (UART_CB.hwfc == NRF_UART_HWFC_ENABLED) { - internal_set_hwfc(FlowControlRTSCTS, - (PinName) UART_CB.pselrts, (PinName) UART_CB.pselcts); - } - - nrf_uart_enable(UART_INSTANCE); - - UART_CB.initialized = true; - } - - if (tx == STDIO_UART_TX && rx == STDIO_UART_RX) { - stdio_uart_inited = 1; - memcpy(&stdio_uart, obj, sizeof(serial_t)); - } - else { - stdio_uart_inited = 0; - } -} - -void serial_free(serial_t *obj) -{ - (void)obj; - - if (UART_CB.initialized) { - nrf_uart_disable(UART_INSTANCE); - nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY | - NRF_UART_INT_MASK_TXDRDY | - NRF_UART_INT_MASK_ERROR); - nrf_drv_common_irq_disable(UART_IRQn); - UART_CB.initialized = false; - - // There is only one UART instance, thus at this point the stdio UART - // can no longer be initialized. - stdio_uart_inited = 0; - } -} - -void serial_baud(serial_t *obj, int baudrate) -{ - // nrf_uart_baudrate_set() is not used here (registers are accessed - // directly) to make it possible to set special baud rates like 56000 - // or 31250. - - static uint32_t const acceptedSpeeds[][2] = { - { 1200, UART_BAUDRATE_BAUDRATE_Baud1200 }, - { 2400, UART_BAUDRATE_BAUDRATE_Baud2400 }, - { 4800, UART_BAUDRATE_BAUDRATE_Baud4800 }, - { 9600, UART_BAUDRATE_BAUDRATE_Baud9600 }, - { 14400, UART_BAUDRATE_BAUDRATE_Baud14400 }, - { 19200, UART_BAUDRATE_BAUDRATE_Baud19200 }, - { 28800, UART_BAUDRATE_BAUDRATE_Baud28800 }, - { 31250, (0x00800000UL) /* 31250 baud */ }, - { 38400, UART_BAUDRATE_BAUDRATE_Baud38400 }, - { 56000, (0x00E51000UL) /* 56000 baud */ }, - { 57600, UART_BAUDRATE_BAUDRATE_Baud57600 }, - { 76800, UART_BAUDRATE_BAUDRATE_Baud76800 }, - { 115200, UART_BAUDRATE_BAUDRATE_Baud115200 }, - { 230400, UART_BAUDRATE_BAUDRATE_Baud230400 }, - { 250000, UART_BAUDRATE_BAUDRATE_Baud250000 }, - { 460800, UART_BAUDRATE_BAUDRATE_Baud460800 }, - { 921600, UART_BAUDRATE_BAUDRATE_Baud921600 }, - { 1000000, UART_BAUDRATE_BAUDRATE_Baud1M } - }; - - if (baudrate <= 1200) { - UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1200; - return; - } - - int const item_cnt = sizeof(acceptedSpeeds)/sizeof(acceptedSpeeds[0]); - for (int i = 1; i < item_cnt; i++) { - if ((uint32_t)baudrate < acceptedSpeeds[i][0]) { - UART_INSTANCE->BAUDRATE = acceptedSpeeds[i - 1][1]; - return; - } - } - - UART_INSTANCE->BAUDRATE = UART_BAUDRATE_BAUDRATE_Baud1M; -} - -void serial_format(serial_t *obj, - int data_bits, SerialParity parity, int stop_bits) -{ - (void)obj; - - if (data_bits != 8) { - error("UART supports only 8 data bits.\r\n"); - } - if (stop_bits != 1) { - error("UART supports only 1 stop bits.\r\n"); - } - if (parity == ParityNone) { - UART_CB.parity = NRF_UART_PARITY_EXCLUDED; - } else if (parity == ParityEven) { - UART_CB.parity = NRF_UART_PARITY_INCLUDED; - } else { - error("UART supports only even parity.\r\n"); - } - - // Reconfigure UART peripheral. - nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); -} - -void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) -{ - (void)obj; - UART_CB.irq_handler = handler; - UART_CB.irq_context = id; -} - -void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) -{ - (void)obj; - if (enable) { - switch (irq) { - case RxIrq: - #if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled |= UART_IRQ_RX; - #endif - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY); - break; - - case TxIrq: - #if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled |= UART_IRQ_TX; - #endif - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY); - break; - } - } else { - switch (irq) { - case RxIrq: - #if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled &= ~UART_IRQ_RX; - if (!UART_CB.rx_active) - #endif - { - nrf_uart_int_disable(UART_INSTANCE, - NRF_UART_INT_MASK_RXDRDY); - } - break; - - case TxIrq: - #if DEVICE_SERIAL_ASYNCH - UART_CB.irq_enabled &= ~UART_IRQ_TX; - if (!UART_CB.tx_active) - #endif - { - nrf_uart_int_disable(UART_INSTANCE, - NRF_UART_INT_MASK_TXDRDY); - } - break; - } - } -} - -int serial_getc(serial_t *obj) -{ - while (!serial_readable(obj)) { - } - - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY); - return nrf_uart_rxd_get(UART_INSTANCE); -} - -void serial_putc(serial_t *obj, int c) -{ - while (!serial_writable(obj)) { - } - - nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY); - nrf_uart_txd_set(UART_INSTANCE, (uint8_t)c); -} - -int serial_readable(serial_t *obj) -{ - (void)obj; -#if DEVICE_SERIAL_ASYNCH - if (UART_CB.rx_active) { - return 0; - } -#endif - return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY)); -} - -int serial_writable(serial_t *obj) -{ - (void)obj; -#if DEVICE_SERIAL_ASYNCH - if (UART_CB.tx_active) { - return 0; - } -#endif - return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)); -} - -void serial_break_set(serial_t *obj) -{ - (void)obj; - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_SUSPEND); - nrf_uart_txrx_pins_disconnect(UART_INSTANCE); - nrf_gpio_pin_clear(UART_CB.pseltxd); -} - -void serial_break_clear(serial_t *obj) -{ - (void)obj; - nrf_gpio_pin_set(UART_CB.pseltxd); - nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX); - nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX); -} - - -static void internal_set_hwfc(FlowControl type, - PinName rxflow, PinName txflow) -{ - UART_CB.pselrts = - ((rxflow == NC) || (type == FlowControlCTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rxflow; - UART_CB.pselcts = - ((txflow == NC) || (type == FlowControlRTS)) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)txflow; - - if (UART_CB.pselrts != NRF_UART_PSEL_DISCONNECTED) { - nrf_gpio_pin_set(UART_CB.pselrts); - nrf_gpio_cfg_output(UART_CB.pselrts); - } - if (UART_CB.pselcts != NRF_UART_PSEL_DISCONNECTED) { - nrf_gpio_cfg_input(UART_CB.pselcts, NRF_GPIO_PIN_NOPULL); - } - - UART_CB.hwfc = (nrf_uart_hwfc_t)((type == FlowControlNone)? NRF_UART_HWFC_DISABLED : UART_DEFAULT_CONFIG_HWFC); - - nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc); - nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_CB.pselrts, UART_CB.pselcts); -} - -void serial_set_flow_control(serial_t *obj, FlowControl type, - PinName rxflow, PinName txflow) -{ - (void)obj; - - nrf_uart_disable(UART_INSTANCE); - internal_set_hwfc(type, rxflow, txflow); - nrf_uart_enable(UART_INSTANCE); -} - - -void serial_clear(serial_t *obj) { - (void)obj; -} - -const PinMap *serial_tx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rx_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_cts_pinmap() -{ - return PinMap_UART_testing; -} - -const PinMap *serial_rts_pinmap() -{ - return PinMap_UART_testing; -} - -#if DEVICE_SERIAL_ASYNCH - -int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, - uint8_t tx_width, uint32_t handler, uint32_t event, - DMAUsage hint) -{ - (void)obj; - (void)tx_width; - (void)hint; - if (UART_CB.tx_active || !tx_length) { - return 0; - } - - UART_CB.tx_buffer = tx; - UART_CB.tx_length = tx_length; - UART_CB.tx_pos = 0; - UART_CB.tx_asynch_handler = (void(*)())handler; - UART_CB.events_wanted &= ~SERIAL_EVENT_TX_ALL; - UART_CB.events_wanted |= event; - - UART_CB.tx_active = true; - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY); - - return 0; -} - -void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, - uint8_t rx_width, uint32_t handler, uint32_t event, - uint8_t char_match, DMAUsage hint) -{ - (void)obj; - (void)rx_width; - (void)hint; - if (UART_CB.rx_active || !rx_length) { - return; - } - - UART_CB.rx_buffer = rx; - UART_CB.rx_length = rx_length; - UART_CB.rx_pos = 0; - UART_CB.rx_asynch_handler = (void(*)())handler; - UART_CB.events_wanted &= ~SERIAL_EVENT_RX_ALL; - UART_CB.events_wanted |= event; - UART_CB.char_match = char_match; - - UART_CB.rx_active = true; - nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY); -} - -uint8_t serial_tx_active(serial_t *obj) -{ - (void)obj; - return UART_CB.tx_active; -} - -uint8_t serial_rx_active(serial_t *obj) -{ - (void)obj; - return UART_CB.rx_active; -} - -int serial_irq_handler_asynch(serial_t *obj) -{ - (void)obj; - uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured; - UART_CB.events_occured &= (~events_to_report); - return events_to_report; -} - -void serial_tx_abort_asynch(serial_t *obj) -{ - (void)obj; - end_asynch_tx(); - UART_CB.tx_asynch_handler = NULL; -} - -void serial_rx_abort_asynch(serial_t *obj) -{ - (void)obj; - end_asynch_rx(); - UART_CB.rx_asynch_handler = NULL; -} - -#endif // DEVICE_SERIAL_ASYNCH - -#endif // DEVICE_SERIAL diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/sleep.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/sleep.c deleted file mode 100644 index 97e22c6541..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/sleep.c +++ /dev/null @@ -1,93 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2006-2013 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ -#include "sleep_api.h" -#include "cmsis.h" -#include "mbed_interface.h" -#include "softdevice_handler.h" -#include "nrf_soc.h" -#include "nrf_timer.h" -#include "us_ticker.h" - -// Mask of reserved bits of the register ICSR in the System Control Block peripheral -// In this case, bits which are equal to 0 are the bits reserved in this register -#define SCB_ICSR_RESERVED_BITS_MASK 0x9E43F03F - -#define FPU_EXCEPTION_MASK 0x0000009F - -extern bool us_ticker_initialized; - -void hal_sleep(void) -{ - // ensure debug is disconnected if semihost is enabled.... - - // Trigger an event when an interrupt is pending. This allows to wake up - // the processor from disabled interrupts. - SCB->SCR |= SCB_SCR_SEVONPEND_Msk; - -#if defined(NRF52) || defined(NRF52840_XXAA) - /* Clear exceptions and PendingIRQ from the FPU unit */ - __set_FPSCR(__get_FPSCR() & ~(FPU_EXCEPTION_MASK)); - (void) __get_FPSCR(); - NVIC_ClearPendingIRQ(FPU_IRQn); -#endif - - // If the SoftDevice is enabled, its API must be used to go to sleep. - if (softdevice_handler_is_enabled()) { - sd_power_mode_set(NRF_POWER_MODE_LOWPWR); - sd_app_evt_wait(); - } else { - NRF_POWER->TASKS_LOWPWR = 1; - - // Note: it is not sufficient to just use WFE here, since the internal - // event register may be already set from an event that occurred in the - // past (like an SVC call to the SoftDevice) and in such case WFE will - // just clear the register and continue execution. - // Therefore, the strategy here is to first clear the event register - // by using SEV/WFE pair, and then execute WFE again, unless there is - // a pending interrupt. - - // Set an event and wake up whatsoever, this will clear the event - // register from all previous events set (SVC call included) - __SEV(); - __WFE(); - - // Test if there is an interrupt pending (mask reserved regions) - if (SCB->ICSR & (SCB_ICSR_RESERVED_BITS_MASK)) { - // Ok, there is an interrut pending, no need to go to sleep - return; - } else { - // next event will wakeup the CPU - // If an interrupt occured between the test of SCB->ICSR and this - // instruction, WFE will just not put the CPU to sleep - __WFE(); - } - } -} - -void hal_deepsleep(void) -{ - if (us_ticker_initialized) { - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_STOP); - } - - hal_sleep(); - - if (us_ticker_initialized) { - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_START); - } - - // NRF_POWER->SYSTEMOFF=1; -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/spi_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/spi_api.c deleted file mode 100644 index 1a21a63193..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/spi_api.c +++ /dev/null @@ -1,650 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - - -#include "spi_api.h" - -#if DEVICE_SPI - -#include "cmsis.h" -#include "pinmap.h" -#include "mbed_assert.h" -#include "mbed_error.h" -#include "nrf_drv_spi.h" -#include "nrf_drv_spis.h" -#include "app_util_platform.h" -#include "sdk_config.h" - -#if DEVICE_SPI_ASYNCH - #define SPI_IDX(obj) ((obj)->spi.spi_idx) -#else - #define SPI_IDX(obj) ((obj)->spi_idx) -#endif -#define SPI_INFO(obj) (&m_spi_info[SPI_IDX(obj)]) -#define MASTER_INST(obj) (&m_instances[SPI_IDX(obj)].master) -#define SLAVE_INST(obj) (&m_instances[SPI_IDX(obj)].slave) - -typedef struct { - bool initialized; - bool master; - uint8_t sck_pin; - uint8_t mosi_pin; - uint8_t miso_pin; - uint8_t ss_pin; - uint8_t spi_mode; - nrf_drv_spi_frequency_t frequency; - volatile union { - bool busy; // master - bool readable; // slave - } flag; - volatile uint8_t tx_buf; - volatile uint8_t rx_buf; - -#if DEVICE_SPI_ASYNCH - uint32_t handler; - uint32_t event; -#endif -} spi_info_t; -static spi_info_t m_spi_info[SPI_COUNT]; - -typedef struct { - nrf_drv_spi_t master; - nrf_drv_spis_t slave; -} sdk_driver_instances_t; - -void SPI0_TWI0_IRQHandler(void); -void SPI1_TWI1_IRQHandler(void); -void SPIM2_SPIS2_SPI2_IRQHandler(void); - -// Pinmap used for testing only -static const PinMap PinMap_SPI_testing[] = { - {p0, 0, 0}, - {p1, 0, 0}, - {p2, 0, 0}, - {p3, 0, 0}, - {p4, 0, 0}, - {p5, 0, 0}, - {p6, 0, 0}, - {p7, 0, 0}, - {p8, 0, 0}, - {p9, 0, 0}, - {p10, 0, 0}, - {p11, 0, 0}, - {p12, 0, 0}, - {p13, 0, 0}, - {p14, 0, 0}, - {p15, 0, 0}, - {p16, 0, 0}, - {p17, 0, 0}, - {p18, 0, 0}, - {p19, 0, 0}, - {p20, 0, 0}, - {p21, 0, 0}, - {p22, 0, 0}, - {p23, 0, 0}, - {p24, 0, 0}, - {p25, 0, 0}, - - {p28, 0, 0}, - {p29, 0, 0}, - {p30, 0, 0}, - - {NC, NC, 0} -}; - -static const peripheral_handler_desc_t spi_handler_desc[SPI_COUNT] = { -#if SPI0_ENABLED - { - SPI0_IRQ, - (uint32_t) SPI0_TWI0_IRQHandler - }, -#endif -#if SPI1_ENABLED - { - SPI1_IRQ, - (uint32_t) SPI1_TWI1_IRQHandler - }, -#endif -#if SPI2_ENABLED - { - SPI2_IRQ, - (uint32_t) SPIM2_SPIS2_SPI2_IRQHandler - }, -#endif -}; - - -static sdk_driver_instances_t m_instances[SPI_COUNT] = { -#if SPI0_ENABLED - { - NRF_DRV_SPI_INSTANCE(0), - NRF_DRV_SPIS_INSTANCE(0) - }, -#endif -#if SPI1_ENABLED - { - NRF_DRV_SPI_INSTANCE(1), - NRF_DRV_SPIS_INSTANCE(1) - }, -#endif -#if SPI2_ENABLED - { - NRF_DRV_SPI_INSTANCE(2), - NRF_DRV_SPIS_INSTANCE(2) - }, -#endif -}; - -static void master_event_handler(uint8_t spi_idx, - nrf_drv_spi_evt_t const *p_event) -{ - spi_info_t *p_spi_info = &m_spi_info[spi_idx]; - - if (p_event->type == NRF_DRV_SPI_EVENT_DONE) { - p_spi_info->flag.busy = false; -#if DEVICE_SPI_ASYNCH - if (p_spi_info->handler) { - void (*handler)(void) = (void (*)(void))p_spi_info->handler; - p_spi_info->handler = 0; - handler(); - } -#endif - } -} -#define MASTER_EVENT_HANDLER(idx) \ - static void master_event_handler_##idx(nrf_drv_spi_evt_t const *p_event) { \ - master_event_handler(SPI##idx##_INSTANCE_INDEX, p_event); \ - } -#if SPI0_ENABLED - MASTER_EVENT_HANDLER(0) -#endif -#if SPI1_ENABLED - MASTER_EVENT_HANDLER(1) -#endif -#if SPI2_ENABLED - MASTER_EVENT_HANDLER(2) -#endif - -static nrf_drv_spi_handler_t const m_master_event_handlers[SPI_COUNT] = { -#if SPI0_ENABLED - master_event_handler_0, -#endif -#if SPI1_ENABLED - master_event_handler_1, -#endif -#if SPI2_ENABLED - master_event_handler_2, -#endif -}; - - -static void slave_event_handler(uint8_t spi_idx, - nrf_drv_spis_event_t event) -{ - spi_info_t *p_spi_info = &m_spi_info[spi_idx]; - - if (event.evt_type == NRF_DRV_SPIS_XFER_DONE) { - // Signal that there is some data received that could be read. - p_spi_info->flag.readable = true; - - // And prepare for the next transfer. - // Previous data set in 'spi_slave_write' (if any) has been transmitted, - // now use the default one, until some new is set by 'spi_slave_write'. - p_spi_info->tx_buf = SPIS_DEFAULT_ORC; - nrf_drv_spis_buffers_set(&m_instances[spi_idx].slave, - (uint8_t const *)&p_spi_info->tx_buf, 1, - (uint8_t *)&p_spi_info->rx_buf, 1); - } -} -#define SLAVE_EVENT_HANDLER(idx) \ - static void slave_event_handler_##idx(nrf_drv_spis_event_t event) { \ - slave_event_handler(SPIS##idx##_INSTANCE_INDEX, event); \ - } -#if SPIS0_ENABLED - SLAVE_EVENT_HANDLER(0) -#endif -#if SPIS1_ENABLED - SLAVE_EVENT_HANDLER(1) -#endif -#if SPIS2_ENABLED - SLAVE_EVENT_HANDLER(2) -#endif - -static nrf_drv_spis_event_handler_t const m_slave_event_handlers[SPIS_COUNT] = { -#if SPIS0_ENABLED - slave_event_handler_0, -#endif -#if SPIS1_ENABLED - slave_event_handler_1, -#endif -#if SPIS2_ENABLED - slave_event_handler_2, -#endif -}; - -static void prepare_master_config(nrf_drv_spi_config_t *p_config, - spi_info_t const *p_spi_info) -{ - p_config->sck_pin = p_spi_info->sck_pin; - p_config->mosi_pin = p_spi_info->mosi_pin; - p_config->miso_pin = p_spi_info->miso_pin; - p_config->ss_pin = p_spi_info->ss_pin; - p_config->frequency = p_spi_info->frequency; - p_config->mode = (nrf_drv_spi_mode_t)p_spi_info->spi_mode; - - p_config->irq_priority = SPI_DEFAULT_CONFIG_IRQ_PRIORITY; - p_config->orc = 0xFF; - p_config->bit_order = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST; -} - -static void prepare_slave_config(nrf_drv_spis_config_t *p_config, - spi_info_t const *p_spi_info) -{ - p_config->sck_pin = p_spi_info->sck_pin; - p_config->mosi_pin = p_spi_info->mosi_pin; - p_config->miso_pin = p_spi_info->miso_pin; - p_config->csn_pin = p_spi_info->ss_pin; - p_config->mode = (nrf_drv_spis_mode_t)p_spi_info->spi_mode; - - p_config->irq_priority = SPIS_DEFAULT_CONFIG_IRQ_PRIORITY; - p_config->orc = SPIS_DEFAULT_ORC; - p_config->def = SPIS_DEFAULT_DEF; - p_config->bit_order = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST; - p_config->csn_pullup = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP; - p_config->miso_drive = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE; -} - -void spi_init(spi_t *obj, - PinName mosi, PinName miso, PinName sclk, PinName ssel) -{ - int i; - - // This block is only a workaround that allows to create SPI object several - // times, what would be otherwise impossible in the current implementation - // of mbed driver that does not call spi_free() from SPI destructor. - // Once this mbed's imperfection is corrected, this block should be removed. - for (i = 0; i < SPI_COUNT; ++i) { - spi_info_t *p_spi_info = &m_spi_info[i]; - if (p_spi_info->initialized && - p_spi_info->mosi_pin == (uint8_t)mosi && - p_spi_info->miso_pin == (uint8_t)miso && - p_spi_info->sck_pin == (uint8_t)sclk && - p_spi_info->ss_pin == (uint8_t)ssel) { - // Reuse the already allocated SPI instance (instead of allocating - // a new one), if it appears to be initialized with exactly the same - // pin assignments. - SPI_IDX(obj) = i; - return; - } - } - - for (i = SPI_COUNT - 1; i >= 0; i--) { - spi_info_t *p_spi_info = &m_spi_info[i]; - - if (!p_spi_info->initialized) { - - p_spi_info->sck_pin = (uint8_t)sclk; - p_spi_info->mosi_pin = (mosi != NC) ? - (uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED; - p_spi_info->miso_pin = (miso != NC) ? - (uint8_t)miso : NRF_DRV_SPI_PIN_NOT_USED; - p_spi_info->ss_pin = (ssel != NC) ? - (uint8_t)ssel : NRF_DRV_SPI_PIN_NOT_USED; - p_spi_info->spi_mode = (uint8_t)NRF_DRV_SPI_MODE_0; - p_spi_info->frequency = NRF_DRV_SPI_FREQ_1M; - - // By default each SPI instance is initialized to work as a master. - // Should the slave mode be used, the instance will be reconfigured - // appropriately in 'spi_format'. - nrf_drv_spi_config_t config; - prepare_master_config(&config, p_spi_info); - - nrf_drv_spi_t const *p_spi = &m_instances[i].master; - ret_code_t ret_code = nrf_drv_spi_init(p_spi, - &config, m_master_event_handlers[i]); - if (ret_code == NRF_SUCCESS) { - p_spi_info->initialized = true; - p_spi_info->master = true; - p_spi_info->flag.busy = false; -#if DEVICE_SPI_ASYNCH - p_spi_info->handler = 0; -#endif - SPI_IDX(obj) = i; - NVIC_SetVector(spi_handler_desc[i].IRQn, spi_handler_desc[i].vector); - return; - } - } - } - - // No available peripheral - error("No available SPI peripheral\r\n"); -} - -void spi_free(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - if (p_spi_info->master) { - nrf_drv_spi_uninit(MASTER_INST(obj)); - } - else { - nrf_drv_spis_uninit(SLAVE_INST(obj)); - } - p_spi_info->initialized = false; -} - -int spi_busy(spi_t *obj) -{ - return (int)(SPI_INFO(obj)->flag.busy); -} - -void spi_format(spi_t *obj, int bits, int mode, int slave) -{ - if (bits != 8) { - error("Only 8-bits SPI is supported\r\n"); - } - if (mode > 3) { - error("SPI format error\r\n"); - } - - spi_info_t *p_spi_info = SPI_INFO(obj); - - if (slave) - { - nrf_drv_spis_mode_t spi_modes[4] = { - NRF_DRV_SPIS_MODE_0, - NRF_DRV_SPIS_MODE_1, - NRF_DRV_SPIS_MODE_2, - NRF_DRV_SPIS_MODE_3, - }; - nrf_drv_spis_mode_t new_mode = spi_modes[mode]; - - // If the peripheral is currently working as a master, the SDK driver - // it uses needs to be switched from SPI to SPIS. - if (p_spi_info->master) { - nrf_drv_spi_uninit(MASTER_INST(obj)); - } - // I the SPI mode has to be changed, the SDK's SPIS driver needs to be - // re-initialized (there is no other way to change its configuration). - else if (p_spi_info->spi_mode != (uint8_t)new_mode) { - nrf_drv_spis_uninit(SLAVE_INST(obj)); - } - else { - return; - } - - p_spi_info->spi_mode = (uint8_t)new_mode; - p_spi_info->master = false; - p_spi_info->flag.readable = false; - - // Initialize SDK's SPIS driver with the new configuration. - nrf_drv_spis_config_t config; - prepare_slave_config(&config, p_spi_info); - (void)nrf_drv_spis_init(SLAVE_INST(obj), &config, - m_slave_event_handlers[SPI_IDX(obj)]); - - // Prepare the slave for transfer. - p_spi_info->tx_buf = SPIS_DEFAULT_ORC; - nrf_drv_spis_buffers_set(SLAVE_INST(obj), - (uint8_t const *)&p_spi_info->tx_buf, 1, - (uint8_t *)&p_spi_info->rx_buf, 1); - } - else // master - { - nrf_drv_spi_mode_t spi_modes[4] = { - NRF_DRV_SPI_MODE_0, - NRF_DRV_SPI_MODE_1, - NRF_DRV_SPI_MODE_2, - NRF_DRV_SPI_MODE_3, - }; - nrf_drv_spi_mode_t new_mode = spi_modes[mode]; - - // If the peripheral is currently working as a slave, the SDK driver - // it uses needs to be switched from SPIS to SPI. - if (!p_spi_info->master) { - nrf_drv_spis_uninit(SLAVE_INST(obj)); - } - // I the SPI mode has to be changed, the SDK's SPI driver needs to be - // re-initialized (there is no other way to change its configuration). - else if (p_spi_info->spi_mode != (uint8_t)new_mode) { - nrf_drv_spi_uninit(MASTER_INST(obj)); - } - else { - return; - } - - p_spi_info->spi_mode = (uint8_t)new_mode; - p_spi_info->master = true; - p_spi_info->flag.busy = false; - - // Initialize SDK's SPI driver with the new configuration. - nrf_drv_spi_config_t config; - prepare_master_config(&config, p_spi_info); - (void)nrf_drv_spi_init(MASTER_INST(obj), &config, - m_master_event_handlers[SPI_IDX(obj)]); - } -} - -static nrf_drv_spi_frequency_t freq_translate(int hz) -{ - nrf_drv_spi_frequency_t frequency; - if (hz<250000) { //125Kbps - frequency = NRF_DRV_SPI_FREQ_125K; - } else if (hz<500000) { //250Kbps - frequency = NRF_DRV_SPI_FREQ_250K; - } else if (hz<1000000) { //500Kbps - frequency = NRF_DRV_SPI_FREQ_500K; - } else if (hz<2000000) { //1Mbps - frequency = NRF_DRV_SPI_FREQ_1M; - } else if (hz<4000000) { //2Mbps - frequency = NRF_DRV_SPI_FREQ_2M; - } else if (hz<8000000) { //4Mbps - frequency = NRF_DRV_SPI_FREQ_4M; - } else { //8Mbps - frequency = NRF_DRV_SPI_FREQ_8M; - } - return frequency; -} - -void spi_frequency(spi_t *obj, int hz) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - nrf_drv_spi_frequency_t new_frequency = freq_translate(hz); - - if (p_spi_info->master) - { - if (p_spi_info->frequency != new_frequency) { - p_spi_info->frequency = new_frequency; - - nrf_drv_spi_config_t config; - prepare_master_config(&config, p_spi_info); - - nrf_drv_spi_t const *p_spi = MASTER_INST(obj); - nrf_drv_spi_uninit(p_spi); - (void)nrf_drv_spi_init(p_spi, &config, - m_master_event_handlers[SPI_IDX(obj)]); - } - } - // There is no need to set anything in slaves when it comes to frequency, - // since slaves just synchronize with the clock provided by a master. -} - -int spi_master_write(spi_t *obj, int value) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - -#if DEVICE_SPI_ASYNCH - while (p_spi_info->flag.busy) { - } -#endif - - p_spi_info->tx_buf = value; - p_spi_info->flag.busy = true; - (void)nrf_drv_spi_transfer(MASTER_INST(obj), - (uint8_t const *)&p_spi_info->tx_buf, 1, - (uint8_t *)&p_spi_info->rx_buf, 1); - while (p_spi_info->flag.busy) { - } - - return p_spi_info->rx_buf; -} - -int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, - char *rx_buffer, int rx_length, char write_fill) { - int total = (tx_length > rx_length) ? tx_length : rx_length; - - for (int i = 0; i < total; i++) { - char out = (i < tx_length) ? tx_buffer[i] : write_fill; - char in = spi_master_write(obj, out); - if (i < rx_length) { - rx_buffer[i] = in; - } - } - - return total; -} - -int spi_slave_receive(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(!p_spi_info->master); - return p_spi_info->flag.readable; -; -} - -int spi_slave_read(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(!p_spi_info->master); - while (!p_spi_info->flag.readable) { - } - p_spi_info->flag.readable = false; - return p_spi_info->rx_buf; -} - -void spi_slave_write(spi_t *obj, int value) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(!p_spi_info->master); - - p_spi_info->tx_buf = (uint8_t)value; -} - -const PinMap *spi_master_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_master_cs_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_mosi_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_miso_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_clk_pinmap() -{ - return PinMap_SPI_testing; -} - -const PinMap *spi_slave_cs_pinmap() -{ - return PinMap_SPI_testing; -} - -#if DEVICE_SPI_ASYNCH - -void spi_master_transfer(spi_t *obj, - const void *tx, size_t tx_length, - void *rx, size_t rx_length, uint8_t bit_width, - uint32_t handler, uint32_t event, DMAUsage hint) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(p_spi_info->master); - (void)hint; - (void)bit_width; - - p_spi_info->handler = handler; - p_spi_info->event = event; - - p_spi_info->flag.busy = true; - (void)nrf_drv_spi_transfer(MASTER_INST(obj), - (uint8_t const *)tx, tx_length, - (uint8_t *)rx, rx_length); -} - -uint32_t spi_irq_handler_asynch(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(p_spi_info->master); - return p_spi_info->event & SPI_EVENT_COMPLETE; -} - -uint8_t spi_active(spi_t *obj) -{ - spi_info_t *p_spi_info = SPI_INFO(obj); - MBED_ASSERT(p_spi_info->master); - return p_spi_info->flag.busy; -} - -void spi_abort_asynch(spi_t *obj) -{ - MBED_ASSERT(SPI_INFO(obj)->master); - nrf_drv_spi_abort(MASTER_INST(obj)); -} - -#endif // DEVICE_SPI_ASYNCH - -#endif // DEVICE_SPI diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/trng_api.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/trng_api.c deleted file mode 100644 index f003bc7d88..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/trng_api.c +++ /dev/null @@ -1,181 +0,0 @@ -/* - * Copyright (c) 2017 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#if DEVICE_TRNG && DEVICE_LPTICKER - -#include "hal/trng_api.h" -#include "hal/lp_ticker_api.h" - -#include "nrf_drv_rng.h" - -#define DEFAULT_TIMEOUT_US (1000*1000) - -/* Macro for testing if the SoftDevice is active, regardless of whether the - * application is build with the SoftDevice or not. - */ -#if defined(SOFTDEVICE_PRESENT) -#include "nrf_sdm.h" -static uint8_t wrapper(void) { - uint8_t softdevice_is_enabled; - ret_code_t result = sd_softdevice_is_enabled(&softdevice_is_enabled); - return ((result == NRF_SUCCESS) && (softdevice_is_enabled == 1)); -} -#define NRF_HAL_SD_IS_ENABLED() wrapper() -#else -#define NRF_HAL_SD_IS_ENABLED() 0 -#endif - -/** Initialize the TRNG peripheral - * - * @param obj The TRNG object - */ -void trng_init(trng_t *obj) -{ - (void) obj; - - /* Initialize low power ticker. Used for timeouts. */ - static bool first_init = true; - - if (first_init) { - first_init = false; - } -} - -/** Deinitialize the TRNG peripheral - * - * @param obj The TRNG object - */ -void trng_free(trng_t *obj) -{ - (void) obj; -} - -/** Get random data from TRNG peripheral - * - * @param obj The TRNG object - * @param output The pointer to an output array - * @param length The size of output data, to avoid buffer overwrite - * @param output_length The length of generated data - * @return 0 success, -1 fail - */ -int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length) -{ - (void) obj; - - /* Use SDK RNG driver if SoftDevice is enabled. */ - if (NRF_HAL_SD_IS_ENABLED()) { - - /* Initialize driver once. */ - static bool nordic_driver_init = true; - - if (nordic_driver_init) { - nordic_driver_init = false; - nrf_drv_rng_init(NULL); - } - - /* Query how many bytes are available. */ - uint8_t bytes_available; - nrf_drv_rng_bytes_available(&bytes_available); - - /* If no bytes are cached, block until at least 1 byte is available. */ - if (bytes_available == 0) { - nrf_drv_rng_block_rand(output, 1); - *output_length = 1; - } else { - - /* Get up to the requested number of bytes. */ - if (bytes_available > length) { - bytes_available = length; - } - - ret_code_t result = nrf_drv_rng_rand(output, bytes_available); - - /* Set output length with available bytes. */ - if (result == NRF_SUCCESS) { - *output_length = bytes_available; - } else { - *output_length = 0; - } - } - } else { - - /* Initialize low-level registers once. */ - static bool nordic_register_init = true; - - if (nordic_register_init) { - nordic_register_init = false; - - /* Enable RNG */ - nrf_rng_error_correction_enable(); - nrf_rng_task_trigger(NRF_RNG_TASK_START); - } - - /* Copy out one byte at a time. */ - size_t index = 0; - for ( ; index < length; index++) { - - /* Setup stop watch for timeout. */ - uint32_t start_us = lp_ticker_read(); - uint32_t now_us = start_us; - - /* Block until timeout or random numer is ready. */ - while (((now_us - start_us) < DEFAULT_TIMEOUT_US) && - !nrf_rng_event_get(NRF_RNG_EVENT_VALRDY)) { - now_us = lp_ticker_read(); - } - - /* Abort if timeout was reached. */ - if ((now_us - start_us) >= DEFAULT_TIMEOUT_US) { - break; - } else { - - /* Read random byte and clear event in preparation for the next byte. */ - nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY); - output[index] = nrf_rng_random_value_get(); - } - } - - /* Set output length with available bytes. */ - *output_length = index; - } - - /* Set return value based on how many bytes was read. */ - return (*output_length == 0) ? -1 : 0; -} - -#endif diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.c b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.c deleted file mode 100644 index 7ab6b2f610..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.c +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2013 Nordic Semiconductor ASA - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * - * 1. Redistributions of source code must retain the above copyright notice, this list - * of conditions and the following disclaimer. - * - * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA - * integrated circuit in a product or a software update for such product, must reproduce - * the above copyright notice, this list of conditions and the following disclaimer in - * the documentation and/or other materials provided with the distribution. - * - * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be - * used to endorse or promote products derived from this software without specific prior - * written permission. - * - * 4. This software, with or without modification, must only be used with a - * Nordic Semiconductor ASA integrated circuit. - * - * 5. Any software provided in binary or object form under this license must not be reverse - * engineered, decompiled, modified and/or disassembled. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - */ - -#include "us_ticker.h" - -#include "us_ticker_api.h" -#include "nrf_timer.h" -#include "app_util_platform.h" -#include "nrf_drv_common.h" -#include "mbed_critical.h" - -bool us_ticker_initialized = false; - -/* us ticker is driven by 1MHz clock and counter length is 16 bits. */ -const ticker_info_t* us_ticker_get_info() -{ - static const ticker_info_t info = { - US_TICKER_FREQ, - US_TICKER_COUNTER_BITS - }; - return &info; -} - -void us_ticker_init(void) -{ - if (us_ticker_initialized) { - nrf_timer_event_clear(NRF_TIMER1, NRF_TIMER_EVENT_COMPARE0); - nrf_timer_int_disable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0)); - return; - } - - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_STOP); - - nrf_timer_int_disable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0)); - - /* Configure timer as follows: - * - timer mode, - * - timer width 16 bits for NRF51 and 32 bits for NRF52, - * - timer freq 1 MHz. - */ - nrf_timer_mode_set(NRF_TIMER1, NRF_TIMER_MODE_TIMER); - - nrf_timer_frequency_set(NRF_TIMER1, NRF_TIMER_FREQ_1MHz); - -#ifdef TARGET_NRF52 - nrf_timer_bit_width_set(NRF_TIMER1, NRF_TIMER_BIT_WIDTH_32); -#else - nrf_timer_bit_width_set(NRF_TIMER1, NRF_TIMER_BIT_WIDTH_16); -#endif - - nrf_timer_cc_write(NRF_TIMER1, NRF_TIMER_CC_CHANNEL0, 0); - - nrf_timer_event_clear(NRF_TIMER1, NRF_TIMER_EVENT_COMPARE0); - - NVIC_SetVector(TIMER1_IRQn, (uint32_t)us_ticker_irq_handler); - - nrf_drv_common_irq_enable(TIMER1_IRQn, APP_IRQ_PRIORITY_HIGH); - - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_START); - - /* Bug fix. First value can't be trusted. */ - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_CAPTURE1); - - us_ticker_initialized = true; -} - -uint32_t us_ticker_read() -{ - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_CAPTURE1); - - return nrf_timer_cc_read(NRF_TIMER1, NRF_TIMER_CC_CHANNEL1); -} - -void us_ticker_set_interrupt(timestamp_t timestamp) -{ - core_util_critical_section_enter(); - - const uint32_t counter_mask = ((1ULL << US_TICKER_COUNTER_BITS) - 1); - - nrf_timer_cc_write(NRF_TIMER1, NRF_TIMER_CC_CHANNEL0, timestamp & counter_mask); - - if (!nrf_timer_int_enable_check(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0))) { - nrf_timer_event_clear(NRF_TIMER1, NRF_TIMER_EVENT_COMPARE0); - nrf_timer_int_enable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0)); - } - - core_util_critical_section_exit(); -} - -void us_ticker_fire_interrupt(void) -{ - NVIC_SetPendingIRQ(TIMER1_IRQn); -} - -void us_ticker_disable_interrupt(void) -{ - nrf_timer_int_disable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0)); -} - -void us_ticker_clear_interrupt(void) -{ - nrf_timer_event_clear(NRF_TIMER1, NRF_TIMER_EVENT_COMPARE0); -} - -void us_ticker_free(void) -{ - nrf_timer_task_trigger(NRF_TIMER1, NRF_TIMER_TASK_STOP); - nrf_timer_int_disable(NRF_TIMER1, nrf_timer_compare_int_get(NRF_TIMER_CC_CHANNEL0)); - NVIC_DisableIRQ(TIMER1_IRQn); - us_ticker_initialized = false; -} diff --git a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.h b/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.h deleted file mode 100644 index f9bf80424c..0000000000 --- a/targets/TARGET_NORDIC/TARGET_NRF5x/TARGET_NRF51/us_ticker.h +++ /dev/null @@ -1,26 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2018 ARM Limited - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - -#ifndef US_TICKER_H -#define US_TICKER_H - -/* TIMER0 is reserved for SoftDevice. We will use TIMER1 for us ticker - * which counter size is 16 bits. */ - -#define US_TICKER_COUNTER_BITS 16u -#define US_TICKER_FREQ 1000000 - -#endif // US_TICKER_H diff --git a/targets/TARGET_NORDIC/mbed_rtx.h b/targets/TARGET_NORDIC/mbed_rtx.h index 06a73ad531..4ba2929d99 100644 --- a/targets/TARGET_NORDIC/mbed_rtx.h +++ b/targets/TARGET_NORDIC/mbed_rtx.h @@ -17,21 +17,7 @@ #ifndef MBED_MBED_RTX_H #define MBED_MBED_RTX_H -#if defined(TARGET_MCU_NRF51822) - -#ifndef INITIAL_SP -# if defined(TARGET_MCU_NORDIC_32K) -# define INITIAL_SP (0x20008000UL) -# elif defined(TARGET_MCU_NORDIC_16K) -# define INITIAL_SP (0x20004000UL) -# endif -#endif - -#ifndef OS_SYSTICK -#define OS_SYSTICK 0 -#endif - -#elif defined(TARGET_MCU_NRF52832) +#if defined(TARGET_MCU_NRF52832) #ifndef INITIAL_SP #define INITIAL_SP (0x20010000UL) @@ -43,6 +29,6 @@ #define INITIAL_SP (0x20040000UL) #endif -#endif // defined(TARGET_MCU_NRF51822)... +#endif // defined(TARGET_MCU_NRF52832)... #endif // #ifndef MBED_MBED_RTX_H diff --git a/targets/targets.json b/targets/targets.json index d1db8ed702..2ff7732fd7 100644 --- a/targets/targets.json +++ b/targets/targets.json @@ -5436,423 +5436,6 @@ "5" ] }, - "MCU_NRF51": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0", - "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex", - "macros": [ - "NRF51", - "NRF5x", - "TARGET_NRF51822", - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"" - ], - "MERGE_BOOTLOADER": false, - "extra_labels": [ - "NORDIC", - "MCU_NRF51", - "MCU_NRF51822" - ], - "OUTPUT_EXT": "hex", - "is_disk_virtual": true, - "supported_toolchains": [ - "ARM", - "GCC_ARM" - ], - "public": false, - "MERGE_SOFT_DEVICE": true, - "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [ - { - "boot": "s130_nrf51_1.0.0_bootloader.hex", - "name": "s130_nrf51_1.0.0_softdevice.hex", - "offset": 114688 - }, - { - "boot": "s110_nrf51822_8.0.0_bootloader.hex", - "name": "s110_nrf51822_8.0.0_softdevice.hex", - "offset": 98304 - }, - { - "boot": "s110_nrf51822_7.1.0_bootloader.hex", - "name": "s110_nrf51822_7.1.0_softdevice.hex", - "offset": 90112 - }, - { - "boot": "s110_nrf51822_7.0.0_bootloader.hex", - "name": "s110_nrf51822_7.0.0_softdevice.hex", - "offset": 90112 - }, - { - "boot": "s110_nrf51822_6.0.0_bootloader.hex", - "name": "s110_nrf51822_6.0.0_softdevice.hex", - "offset": 81920 - } - ], - "detect_code": [ - "1070" - ], - "post_binary_hook": { - "function": "MCU_NRF51Code.binary_hook", - "toolchains": [ - "ARM_STD", - "GCC_ARM" - ] - }, - "program_cycle_s": 6, - "device_has": [ - "ANALOGIN", - "I2C", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE", - "USTICKER" - ], - "overrides": { - "tickless-from-us-ticker": true, - "boot-stack-size": "0x400" - } - }, - "MCU_NRF51_16K_BASE": { - "inherits": [ - "MCU_NRF51" - ], - "extra_labels_add": [ - "MCU_NORDIC_16K", - "MCU_NRF51_16K" - ], - "macros_add": [ - "TARGET_MCU_NORDIC_16K", - "TARGET_MCU_NRF51_16K" - ], - "public": false, - "default_lib": "small" - }, - "MCU_NRF51_16K_BOOT_BASE": { - "inherits": [ - "MCU_NRF51_16K_BASE" - ], - "MERGE_BOOTLOADER": true, - "extra_labels_add": [ - "MCU_NRF51_16K_BOOT" - ], - "macros_add": [ - "TARGET_MCU_NRF51_16K_BOOT", - "TARGET_OTA_ENABLED" - ], - "public": false - }, - "MCU_NRF51_16K_OTA_BASE": { - "inherits": [ - "MCU_NRF51_16K_BASE" - ], - "public": false, - "extra_labels_add": [ - "MCU_NRF51_16K_OTA" - ], - "macros_add": [ - "TARGET_MCU_NRF51_16K_OTA", - "TARGET_OTA_ENABLED" - ], - "MERGE_SOFT_DEVICE": false - }, - "MCU_NRF51_16K": { - "inherits": [ - "MCU_NRF51_16K_BASE" - ], - "extra_labels_add": [ - "MCU_NRF51_16K_S130" - ], - "macros_add": [ - "TARGET_MCU_NRF51_16K_S130" - ], - "public": false - }, - "MCU_NRF51_S110": { - "extra_labels_add": [ - "MCU_NRF51_16K_S110" - ], - "macros_add": [ - "TARGET_MCU_NRF51_16K_S110" - ], - "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [ - { - "name": "s110_nrf51822_8.0.0_softdevice.hex", - "boot": "s110_nrf51822_8.0.0_bootloader.hex", - "offset": 98304 - }, - { - "name": "s110_nrf51822_7.1.0_softdevice.hex", - "boot": "s110_nrf51822_7.1.0_bootloader.hex", - "offset": 90112 - } - ], - "public": false - }, - "MCU_NRF51_16K_S110": { - "inherits": [ - "MCU_NRF51_S110", - "MCU_NRF51_16K_BASE" - ], - "public": false - }, - "MCU_NRF51_16K_BOOT": { - "inherits": [ - "MCU_NRF51_16K_BOOT_BASE" - ], - "extra_labels_add": [ - "MCU_NRF51_16K_S130" - ], - "macros_add": [ - "TARGET_MCU_NRF51_16K_S130" - ], - "public": false - }, - "MCU_NRF51_16K_BOOT_S110": { - "inherits": [ - "MCU_NRF51_S110", - "MCU_NRF51_16K_BOOT_BASE" - ], - "public": false - }, - "MCU_NRF51_16K_OTA": { - "inherits": [ - "MCU_NRF51_16K_OTA_BASE" - ], - "extra_labels_add": [ - "MCU_NRF51_16K_S130" - ], - "macros_add": [ - "TARGET_MCU_NRF51_16K_S130" - ], - "public": false - }, - "MCU_NRF51_16K_OTA_S110": { - "inherits": [ - "MCU_NRF51_S110", - "MCU_NRF51_16K_OTA_BASE" - ], - "public": false - }, - "MCU_NRF51_32K": { - "inherits": [ - "MCU_NRF51" - ], - "extra_labels_add": [ - "MCU_NORDIC_32K", - "MCU_NRF51_32K" - ], - "macros_add": [ - "TARGET_MCU_NORDIC_32K", - "TARGET_MCU_NRF51_32K" - ], - "public": false - }, - "MCU_NRF51_32K_BOOT": { - "inherits": [ - "MCU_NRF51_32K" - ], - "MERGE_BOOTLOADER": true, - "extra_labels_add": [ - "MCU_NRF51_32K_BOOT" - ], - "macros_add": [ - "TARGET_MCU_NRF51_32K_BOOT", - "TARGET_OTA_ENABLED" - ], - "public": false - }, - "MCU_NRF51_32K_OTA": { - "inherits": [ - "MCU_NRF51_32K" - ], - "public": false, - "extra_labels_add": [ - "MCU_NRF51_32K_OTA" - ], - "macros_add": [ - "TARGET_MCU_NRF51_32K_OTA", - "TARGET_OTA_ENABLED" - ], - "MERGE_SOFT_DEVICE": false - }, - "NRF51822": { - "inherits": [ - "MCU_NRF51_16K" - ], - "extra_labels_add": [ - "NRF51822", - "NRF51822_MKIT" - ], - "macros_add": [ - "TARGET_NRF51822_MKIT" - ], - "release_versions": [ - "2" - ], - "device_name": "nRF51822_xxAA", - "detect_code": [ - "1070" - ] - }, - "NRF51822_BOOT": { - "inherits": [ - "MCU_NRF51_16K_BOOT" - ], - "extra_labels_add": [ - "NRF51822", - "NRF51822_MKIT" - ], - "macros_add": [ - "TARGET_NRF51822_MKIT" - ] - }, - "NRF51822_OTA": { - "inherits": [ - "MCU_NRF51_16K_OTA" - ], - "extra_labels_add": [ - "NRF51822", - "NRF51822_MKIT" - ], - "macros_add": [ - "TARGET_NRF51822_MKIT" - ], - "detect_code": [ - "1075" - ] - }, - "NRF51_DK_LEGACY": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K" - ], - "extra_labels_add": [ - "NRF51_DK" - ] - }, - "NRF51_DK_BOOT": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K_BOOT" - ], - "extra_labels_add": [ - "NRF51_DK" - ], - "macros_add": [ - "TARGET_NRF51_DK" - ] - }, - "NRF51_DK_OTA": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K_OTA" - ], - "extra_labels_add": [ - "NRF51_DK" - ], - "macros_add": [ - "TARGET_NRF51_DK" - ], - "detect_code": [ - "1105" - ] - }, - "NRF51_MICROBIT": { - "inherits": [ - "MCU_NRF51_16K_S110" - ], - "macros_add": [ - "TARGET_NRF_LFCLK_RC" - ], - "release_versions": [ - "2" - ], - "device_name": "nRF51822_xxAA", - "supported_toolchains": [ - "ARMC5", - "GCC_ARM" - ], - "detect_code": [ - "9900" - ] - }, - "NRF51_MICROBIT_BOOT": { - "inherits": [ - "MCU_NRF51_16K_BOOT_S110" - ], - "extra_labels_add": [ - "NRF51_MICROBIT" - ], - "macros_add": [ - "TARGET_NRF51_MICROBIT", - "TARGET_NRF_LFCLK_RC" - ] - }, - "NRF51_MICROBIT_OTA": { - "inherits": [ - "MCU_NRF51_16K_OTA_S110" - ], - "extra_labels_add": [ - "NRF51_MICROBIT" - ], - "macros_add": [ - "TARGET_NRF51_MICROBIT", - "TARGET_NRF_LFCLK_RC" - ] - }, - "NRF51_MICROBIT_B": { - "inherits": [ - "MCU_NRF51_16K" - ], - "extra_labels_add": [ - "NRF51_MICROBIT" - ], - "macros_add": [ - "TARGET_NRF51_MICROBIT", - "TARGET_NRF_LFCLK_RC" - ], - "release_versions": [ - "2" - ] - }, - "NRF51_MICROBIT_B_BOOT": { - "inherits": [ - "MCU_NRF51_16K_BOOT" - ], - "extra_labels_add": [ - "NRF51_MICROBIT" - ], - "macros_add": [ - "TARGET_NRF51_MICROBIT", - "TARGET_NRF_LFCLK_RC" - ] - }, - "NRF51_MICROBIT_B_OTA": { - "inherits": [ - "MCU_NRF51_16K_OTA" - ], - "extra_labels_add": [ - "NRF51_MICROBIT" - ], - "macros_add": [ - "TARGET_NRF51_MICROBIT", - "TARGET_NRF_LFCLK_RC" - ] - }, "ARM_MPS2_Target": { "inherits": [ "Target" @@ -7023,140 +6606,6 @@ "2042" ] }, - "MCU_NRF51_UNIFIED": { - "inherits": [ - "Target" - ], - "core": "Cortex-M0", - "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex", - "macros": [ - "BOARD_PCA10028", - "NRF51", - "TARGET_NRF51822", - "TARGET_MCU_NRF51822", - "CMSIS_VECTAB_VIRTUAL", - "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", - "NO_SYSTICK", - "MBED_TICKLESS" - ], - "MERGE_BOOTLOADER": false, - "extra_labels": [ - "NORDIC", - "MCU_NRF51", - "MCU_NRF51822_UNIFIED", - "NRF5x", - "NRF51" - ], - "OUTPUT_EXT": "hex", - "is_disk_virtual": true, - "supported_toolchains": [ - "ARM", - "GCC_ARM", - "IAR" - ], - "public": false, - "detect_code": [ - "1070" - ], - "post_binary_hook": { - "function": "MCU_NRF51Code.binary_hook", - "toolchains": [ - "ARM_STD", - "GCC_ARM", - "IAR" - ] - }, - "program_cycle_s": 6, - "config": { - "lf_clock_src": { - "value": "NRF_LF_SRC_XTAL", - "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC" - }, - "uart_hwfc": { - "help": "Value: 1 for enable, 0 for disable", - "value": 1, - "macro_name": "MBED_CONF_NORDIC_UART_HWFC" - } - }, - "device_has": [ - "ANALOGIN", - "I2C", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SLEEP", - "SPI", - "SPISLAVE" - ] - }, - "MCU_NRF51_16K_UNIFIED_S130": { - "inherits": [ - "MCU_NRF51_UNIFIED" - ], - "extra_labels_add": [ - "MCU_NORDIC_16K", - "MCU_NRF51_16K_S130", - "MCU_NRF51_16K" - ], - "macros_add": [ - "TARGET_MCU_NORDIC_16K", - "TARGET_MCU_NRF51_16K_S130", - "TARGET_MCU_NRF51_16K" - ], - "public": false - }, - "MCU_NRF51_32K_UNIFIED": { - "inherits": [ - "MCU_NRF51_UNIFIED" - ], - "extra_labels_add": [ - "MCU_NORDIC_32K", - "MCU_NRF51_32K" - ], - "macros_add": [ - "TARGET_MCU_NORDIC_32K", - "TARGET_MCU_NRF51_32K" - ], - "public": false - }, - "NRF51_DK": { - "supported_form_factors": [ - "ARDUINO" - ], - "inherits": [ - "MCU_NRF51_32K_UNIFIED" - ], - "device_has": [ - "USTICKER", - "LPTICKER", - "ANALOGIN", - "I2C", - "I2C_ASYNCH", - "INTERRUPTIN", - "PORTIN", - "PORTINOUT", - "PORTOUT", - "PWMOUT", - "SERIAL", - "SERIAL_ASYNCH", - "SERIAL_FC", - "SLEEP", - "SPI", - "SPI_ASYNCH", - "SPISLAVE" - ], - "release_versions": [ - "2", - "5" - ], - "device_name": "nRF51822_xxAC", - "detect_code": [ - "1100" - ] - }, "MCU_NRF52832": { "inherits": [ "Target" diff --git a/tools/export/cmake/__init__.py b/tools/export/cmake/__init__.py index 5163c03643..16018a40bb 100644 --- a/tools/export/cmake/__init__.py +++ b/tools/export/cmake/__init__.py @@ -42,7 +42,6 @@ class CMake(Exporter): PREPROCESS_ASM = False POST_BINARY_WHITELIST = set([ - "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch", "PSOC6Code.complete" ]) diff --git a/tools/export/codeblocks/__init__.py b/tools/export/codeblocks/__init__.py index 527994a4f6..fbbdb351d0 100644 --- a/tools/export/codeblocks/__init__.py +++ b/tools/export/codeblocks/__init__.py @@ -126,13 +126,6 @@ class CodeBlocks(GccArm): 'DISCO_F769NI': 'board/stm32f7discovery.cfg', 'DISCO_L475VG_IOT01A': 'board/stm32l4discovery.cfg', 'DISCO_L476VG': 'board/stm32l4discovery.cfg', - 'NRF51822': 'board/nordic_nrf51822_mkit.cfg', - 'NRF51822_BOOT': 'board/nordic_nrf51822_mkit.cfg', - 'NRF51822_OTA': 'board/nordic_nrf51822_mkit.cfg', - 'NRF51_DK_LEGACY': 'board/nordic_nrf51_dk.cfg', - 'NRF51_DK_BOOT': 'board/nordic_nrf51_dk.cfg', - 'NRF51_DK_OTA': 'board/nordic_nrf51_dk.cfg', - 'NRF51_DK': 'board/nordic_nrf51_dk.cfg', 'CY8CKIT_062_WIFI_BT': 'board/cy8ckit_062_ble.cfg' } diff --git a/tools/export/gnuarmeclipse/__init__.py b/tools/export/gnuarmeclipse/__init__.py index 380e43f076..5e65e182c9 100644 --- a/tools/export/gnuarmeclipse/__init__.py +++ b/tools/export/gnuarmeclipse/__init__.py @@ -61,7 +61,6 @@ u = UID() POST_BINARY_WHITELIST = set([ - "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch", "PSOC6Code.complete" ]) diff --git a/tools/export/iar/iar_definitions.json b/tools/export/iar/iar_definitions.json index 8c281ef385..aaad13e8f8 100644 --- a/tools/export/iar/iar_definitions.json +++ b/tools/export/iar/iar_definitions.json @@ -102,12 +102,6 @@ "STM32F072RB": { "OGChipSelectEditMenu": "STM32F072RB\tST STM32F072RB" }, - "nRF51822_xxAA": { - "OGChipSelectEditMenu": "nRF51822-QFAA\tNordicSemi nRF51822-QFAA", - "CExtraOptionsCheck": 1, - "CExtraOptions": "--drv_vector_table_base=0x0", - "CMSISDAPJtagSpeedList": 10 - }, "EFM32GG990F1024": { "OGChipSelectEditMenu": "EFM32GG990F1024\tSiliconLaboratories EFM32GG990F1024" }, diff --git a/tools/export/makefile/__init__.py b/tools/export/makefile/__init__.py index 07cae6c455..bc47a74810 100644 --- a/tools/export/makefile/__init__.py +++ b/tools/export/makefile/__init__.py @@ -61,7 +61,6 @@ class Makefile(Exporter): PREPROCESS_ASM = False POST_BINARY_WHITELIST = set([ - "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch", "PSOC6Code.complete" ]) diff --git a/tools/export/mcuxpresso/__init__.py b/tools/export/mcuxpresso/__init__.py index 278c43da18..47d9dacf9b 100644 --- a/tools/export/mcuxpresso/__init__.py +++ b/tools/export/mcuxpresso/__init__.py @@ -43,7 +43,6 @@ from tools.build_api import prepare_toolchain POST_BINARY_WHITELIST = set([ - "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch" ]) diff --git a/tools/export/nb/__init__.py b/tools/export/nb/__init__.py index 90c6522cfc..f50e363238 100644 --- a/tools/export/nb/__init__.py +++ b/tools/export/nb/__init__.py @@ -15,7 +15,6 @@ from tools.utils import NotSupportedException from tools.build_api import prepare_toolchain POST_BINARY_WHITELIST = set([ - "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch" ]) diff --git a/tools/export/uvision/__init__.py b/tools/export/uvision/__init__.py index 467b70263a..3a28977dfa 100644 --- a/tools/export/uvision/__init__.py +++ b/tools/export/uvision/__init__.py @@ -132,7 +132,6 @@ class Uvision(Exporter): """ POST_BINARY_WHITELIST = set([ - "MCU_NRF51Code.binary_hook", "LPCTargetCode.lpc_patch", "MTSCode.combine_bins_mts_dragonfly", "LPC55S69Code.binary_hook", diff --git a/tools/singletest.py b/tools/singletest.py index dbd7097a7b..714aea531c 100644 --- a/tools/singletest.py +++ b/tools/singletest.py @@ -25,8 +25,7 @@ File format example: test_spec.json: "targets": { "KL46Z": ["ARM", "GCC_ARM"], "LPC1768": ["ARM", "GCC_ARM", "IAR"], - "LPC11U24": ["uARM"], - "NRF51822": ["ARM"] + "LPC11U24": ["uARM"] } } diff --git a/tools/targets/__init__.py b/tools/targets/__init__.py index 72ce4e9b24..086e01faab 100644 --- a/tools/targets/__init__.py +++ b/tools/targets/__init__.py @@ -504,75 +504,6 @@ class MTSCode(object): """A hoof for the MTS Dragonfly""" MTSCode._combine_bins_helper("MTS_DRAGONFLY_F411RE", binf) - -class MCU_NRF51Code(object): - """NRF51 Hooks""" - @staticmethod - def binary_hook(t_self, resources, _, binf): - """Hook that merges the soft device with the bin file""" - # Scan to find the actual paths of soft device - sdf = None - sd_with_offsets = t_self.target.EXPECTED_SOFTDEVICES_WITH_OFFSETS - for softdevice_and_offset_entry in sd_with_offsets: - for hexf in resources.get_file_paths(FileType.HEX): - if hexf.find(softdevice_and_offset_entry['name']) != -1: - t_self.notify.debug("SoftDevice file found %s." - % softdevice_and_offset_entry['name']) - sdf = hexf - - if sdf is not None: - break - if sdf is not None: - break - - if sdf is None: - t_self.notify.debug("Hex file not found. Aborting.") - return - - # Look for bootloader file that matches this soft device or bootloader - # override image - blf = None - if t_self.target.MERGE_BOOTLOADER is True: - for hexf in resources.get_file_paths(FileType.HEX): - if hexf.find(t_self.target.OVERRIDE_BOOTLOADER_FILENAME) != -1: - t_self.notify.debug( - "Bootloader file found %s." - % t_self.target.OVERRIDE_BOOTLOADER_FILENAME - ) - blf = hexf - break - elif hexf.find(softdevice_and_offset_entry['boot']) != -1: - t_self.notify.debug("Bootloader file found %s." - % softdevice_and_offset_entry['boot']) - blf = hexf - break - - # Merge user code with softdevice - from intelhex import IntelHex - binh = IntelHex() - _, ext = os.path.splitext(binf) - if ext == ".hex": - binh.loadhex(binf) - elif ext == ".bin": - binh.loadbin(binf, softdevice_and_offset_entry['offset']) - - if t_self.target.MERGE_SOFT_DEVICE is True: - t_self.notify.debug("Merge SoftDevice file %s" - % softdevice_and_offset_entry['name']) - sdh = IntelHex(sdf) - sdh.start_addr = None - binh.merge(sdh) - - if t_self.target.MERGE_BOOTLOADER is True and blf is not None: - t_self.notify.debug("Merge BootLoader file %s" % blf) - blh = IntelHex(blf) - blh.start_addr = None - binh.merge(blh) - - with open(binf.replace(".bin", ".hex"), "w") as fileout: - binh.write_hex_file(fileout, write_start_addr=False) - - class RTL8195ACode(object): """RTL8195A Hooks""" @staticmethod diff --git a/tools/test/examples/examples.json b/tools/test/examples/examples.json index f62d98db82..8ab2edecc4 100644 --- a/tools/test/examples/examples.json +++ b/tools/test/examples/examples.json @@ -76,7 +76,7 @@ "BLE_Thermometer" ], "features" : [], - "targets" : ["NRF51_DK", "NRF52_DK", "DISCO_L475VG_IOT01A"], + "targets" : ["NRF52_DK", "DISCO_L475VG_IOT01A"], "toolchains" : [], "exporters": [], "compile" : true, diff --git a/tools/tests.py b/tools/tests.py index 03f7a7f1e8..8109f43cdb 100644 --- a/tools/tests.py +++ b/tools/tests.py @@ -416,7 +416,7 @@ TESTS = [ "id": "MBED_4", "description": "Sleep", "source_dir": join(TEST_DIR, "mbed", "sleep"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], - "mcu": ["LPC1768", "LPC11U24", "NRF51822", "LPC11U68"] + "mcu": ["LPC1768", "LPC11U24", "LPC11U68"] }, { "id": "MBED_5", "description": "PWM", @@ -485,11 +485,7 @@ TESTS = [ "source_dir": join(TEST_DIR, "mbed", "rtc"), "dependencies": [MBED_LIBRARIES, TEST_MBED_LIB], "automated": True, - "exclude_mcu": ["NRF51822", "NRF51822_BOOT", "NRF51822_OTA", - "NRF51_DK", "NRF51_DK_BOOT", "NRF51_DK_OTA", - "NRF51_MICROBIT", "NRF51_MICROBIT_B", "NRF51_MICROBIT_BOOT", - "NRF51_MICROBIT_B_BOOT", "NRF51_MICROBIT_B_OTA", "NRF51_MICROBIT_OTA", - "NUCLEO_L011K4", + "exclude_mcu": ["NUCLEO_L011K4", "ARCH_BLE", "ARCH_BLE_BOOT", "ARCH_BLE_OTA", "ARCH_LINK", "ARCH_LINK_BOOT", "ARCH_LINK_OTA", "SEEED_TINY_BLE", "SEEED_TINY_BLE_BOOT", "SEEED_TINY_BLE_OTA",