diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dac.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dac.c
new file mode 100644
index 0000000000..3660d557b9
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dac.c
@@ -0,0 +1,764 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dac.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Digital-to-Analog Converter (DAC) peripheral:
+ * + DAC channels configuration: trigger, output buffer, data format
+ * + DMA management
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### DAC Peripheral features #####
+ ===============================================================================
+ [..] The device integrates two 12-bit Digital Analog Converters that can
+ be used independently or simultaneously (dual mode):
+ (#) DAC1 integrates two DAC channels:
+ (++) DAC1 channel 1 with DAC1_OUT1 as output
+ (++) DAC1 channel 2 with DAC1_OUT2 as output
+ (++) The two channels can be used independently or simultaneously (dual mode)
+
+ (#) DAC2 integrates only one channel DAC2 channel 1 with DAC2_OUT1 as output
+
+ [..] Digital to Analog conversion can be non-triggered using DAC_Trigger_None
+ and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register using
+ DAC_SetChannel1Data()/DAC_SetChannel2Data.
+
+ [..] Digital to Analog conversion can be triggered by:
+ (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
+ The used pin (GPIOx_Pin9) must be configured in input mode.
+
+ (#) Timers TRGO: TIM2, TIM8/TIM3, TIM4, TIM6, TIM7, and TIM15
+ (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
+ The timer TRGO event should be selected using TIM_SelectOutputTrigger()
+ (++) To trigger DAC conversions by TIM3 instead of TIM8 follow
+ this sequence:
+ (+++) Enable SYSCFG APB clock by calling
+ RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+ (+++) Select DAC_Trigger_T3_TRGO when calling DAC_Init()
+ (+++) Remap the DAC trigger from TIM8 to TIM3 by calling
+ SYSCFG_TriggerRemapConfig(SYSCFG_TriggerRemap_DACTIM3, ENABLE)
+ (#) Software using DAC_Trigger_Software
+
+ [..] Each DAC channel integrates an output buffer that can be used to
+ reduce the output impedance, and to drive external loads directly
+ without having to add an external operational amplifier.
+ To enable, the output buffer use
+ DAC_InitStructure.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+
+ [..] Refer to the device datasheet for more details about output impedance
+ value with and without output buffer.
+
+ [..] Both DAC channels can be used to generate:
+ (+) Noise wave using DAC_WaveGeneration_Noise
+ (+) Triangle wave using DAC_WaveGeneration_Triangle
+
+ [..] Wave generation can be disabled using DAC_WaveGeneration_None
+
+ [..] The DAC data format can be:
+ (+) 8-bit right alignment using DAC_Align_8b_R
+ (+) 12-bit left alignment using DAC_Align_12b_L
+ (+) 12-bit right alignment using DAC_Align_12b_R
+
+ [..] The analog output voltage on each DAC channel pin is determined
+ by the following equation:
+ (+) DAC_OUTx = VREF+ * DOR / 4095 with DOR is the Data Output Register.
+ VREF+ is the input voltage reference (refer to the device datasheet)
+ e.g. To set DAC_OUT1 to 0.7V, use DAC_SetChannel1Data(DAC_Align_12b_R, 868);
+ Assuming that VREF+ = 3.3, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
+
+ [..] A DMA1 request can be generated when an external trigger (but not
+ a software trigger) occurs if DMA1 requests are enabled using
+ DAC_DMACmd()
+ DMA1 requests are mapped as following:
+ (+) DAC channel1 is mapped on DMA1 channel3 which must be already
+ configured
+ (+) DAC channel2 is mapped on DMA1 channel4 which must be already
+ configured
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (+) Enable DAC APB1 clock to get write access to DAC registers
+ using RCC_APB1PeriphClockCmd(RCC_APB1Periph_DAC, ENABLE)
+
+ (+) Configure DACx_OUTy (DAC1_OUT1: PA4, DAC1_OUT2: PA5, DAC2_OUT1: PA6)
+ in analog mode.
+
+ (+) Configure the DAC channel using DAC_Init()
+
+ (+) Enable the DAC channel using DAC_Cmd()
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dac.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DAC
+ * @brief DAC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CR register Mask */
+#define CR_CLEAR_MASK ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+ * @{
+ */
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ * @brief DAC channels configuration: trigger, output buffer, data format
+ *
+@verbatim
+ ===============================================================================
+ ##### DAC channels configuration: trigger, output buffer, data format #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DAC peripheral registers to their default reset values.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @retval None
+ */
+void DAC_DeInit(DAC_TypeDef* DACx)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+
+ if (DACx == DAC1)
+ {
+ /* Enable DAC1 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, ENABLE);
+ /* Release DAC1 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC1, DISABLE);
+ }
+ else
+ {
+ /* Enable DAC2 reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, ENABLE);
+ /* Release DAC2 from reset state */
+ RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC2, DISABLE);
+ }
+}
+
+/**
+ * @brief Initializes the DAC peripheral according to the specified
+ * parameters in the DAC_InitStruct.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure that
+ * contains the configuration information for the specified DAC channel.
+ * @retval None
+ */
+void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+ uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+ /* Check the DAC parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+ assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+ assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+ assert_param(IS_DAC_BUFFER_SWITCH_STATE(DAC_InitStruct->DAC_Buffer_Switch));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+ /* Get the DAC CR value */
+ tmpreg1 = DACx->CR;
+ /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+ tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+ /* Configure for the selected DAC channel: buffer output, trigger, wave generation,
+ mask/amplitude for wave generation */
+
+ /* Set TSELx and TENx bits according to DAC_Trigger value */
+ /* Set WAVEx bits according to DAC_WaveGeneration value */
+ /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */
+ /* Set BOFFx OUTENx bit according to DAC_Buffer_Switch value */
+ tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | DAC_InitStruct->DAC_Buffer_Switch);
+
+ /* Calculate CR register value depending on DAC_Channel */
+ tmpreg1 |= tmpreg2 << DAC_Channel;
+ /* Write to DAC CR */
+ DACx->CR = tmpreg1;
+}
+
+/**
+ * @brief Fills each DAC_InitStruct member with its default value.
+ * @param DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+ /* Initialize the DAC_Trigger member */
+ DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+ /* Initialize the DAC_WaveGeneration member */
+ DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+ /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+ DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+ /* Initialize the DAC_Buffer_Switch member */
+ DAC_InitStruct->DAC_Buffer_Switch = DAC_BufferSwitch_Enable;
+}
+
+/**
+ * @brief Enables or disables the specified DAC channel.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: The selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the DAC channel.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note When the DAC channel is enabled the trigger source can no more
+ * be modified.
+ * @retval None
+ */
+void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel */
+ DACx->CR |= (DAC_CR_EN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel */
+ DACx->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel software trigger.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel software trigger.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for the selected DAC channel */
+ DACx->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+ }
+ else
+ {
+ /* Disable software trigger for the selected DAC channel */
+ DACx->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+ }
+}
+
+/**
+ * @brief Enables or disables simultaneously the two DAC channels software
+ * triggers.
+ * @param DACx: where x can be 1 to select the DAC1 peripheral.
+ * @note Dual trigger is not applicable for DAC2 (DAC2 integrates one channel).
+ * @param NewState: new state of the DAC channels software triggers.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable software trigger for both DAC channels */
+ DACx->SWTRIGR |= DUAL_SWTRIG_SET;
+ }
+ else
+ {
+ /* Disable software trigger for both DAC channels */
+ DACx->SWTRIGR &= DUAL_SWTRIG_RESET;
+ }
+}
+
+/**
+ * @brief Enables or disables the selected DAC channel wave generation.
+ * @param DACx: where x can be 1 to select the DAC1 peripheral.
+ * @note Wave generation is not available in DAC2.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_Wave: Specifies the wave type to enable or disable.
+ * This parameter can be one of the following values:
+ * @arg DAC_Wave_Noise: noise wave generation
+ * @arg DAC_Wave_Triangle: triangle wave generation
+ * @param NewState: new state of the selected DAC channel wave generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note
+ * @retval None
+ */
+void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_WAVE(DAC_Wave));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected wave generation for the selected DAC channel */
+ DACx->CR |= DAC_Wave << DAC_Channel;
+ }
+ else
+ {
+ /* Disable the selected wave generation for the selected DAC channel */
+ DACx->CR &= ~(DAC_Wave << DAC_Channel);
+ }
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel1.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Align: Specifies the data alignment for DAC channel1.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data: Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DACx;
+ tmp += DHR12R1_OFFSET + DAC_Align;
+
+ /* Set the DAC channel1 selected data holding register */
+ *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for DAC channel2.
+ * @param DACx: where x can be 1 to select the DAC peripheral.
+ * @note This function is available only for DAC1.
+ * @param DAC_Align: Specifies the data alignment for DAC channel2.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data : Data to be loaded in the selected data holding register.
+ * @retval None
+ */
+void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data));
+
+ tmp = (uint32_t)DACx;
+ tmp += DHR12R2_OFFSET + DAC_Align;
+
+ /* Set the DAC channel2 selected data holding register */
+ *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+ * @brief Set the specified data holding register value for dual channel DAC.
+ * @param DACx: where x can be 1 to select the DAC peripheral.
+ * @note This function isn't applicable for DAC2.
+ * @param DAC_Align: Specifies the data alignment for dual channel DAC.
+ * This parameter can be one of the following values:
+ * @arg DAC_Align_8b_R: 8bit right data alignment selected
+ * @arg DAC_Align_12b_L: 12bit left data alignment selected
+ * @arg DAC_Align_12b_R: 12bit right data alignment selected
+ * @param Data2: Data for DAC Channel2 to be loaded in the selected data
+ * holding register.
+ * @param Data1: Data for DAC Channel1 to be loaded in the selected data
+ * holding register.
+ * @note In dual mode, a unique register access is required to write in both
+ * DAC channels at the same time.
+ * @retval None
+ */
+void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+ uint32_t data = 0, tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_LIST1_PERIPH(DACx));
+ assert_param(IS_DAC_ALIGN(DAC_Align));
+ assert_param(IS_DAC_DATA(Data1));
+ assert_param(IS_DAC_DATA(Data2));
+
+ /* Calculate and set dual DAC data holding register value */
+ if (DAC_Align == DAC_Align_8b_R)
+ {
+ data = ((uint32_t)Data2 << 8) | Data1;
+ }
+ else
+ {
+ data = ((uint32_t)Data2 << 16) | Data1;
+ }
+
+ tmp = (uint32_t)DACx;
+ tmp += DHR12RD_OFFSET + DAC_Align;
+
+ /* Set the dual DAC selected data holding register */
+ *(__IO uint32_t *)tmp = data;
+}
+
+/**
+ * @brief Returns the last data output value of the selected DAC channel.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @retval The selected DAC channel data output value.
+ */
+uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+
+ tmp = (uint32_t) DACx;
+ tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+
+ /* Returns the DAC channel data output register value */
+ return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group2 DMA management functions
+ * @brief DMA management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified DAC channel DMA request.
+ * When enabled DMA1 is generated when an external trigger (EXTI Line9,
+ * TIM2, TIM4, TIM6, TIM7 or TIM9 but not a software trigger) occurs
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param NewState: new state of the selected DAC channel DMA request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note The DAC channel1 (channel2) is mapped on DMA1 channel3 (channel4) which
+ * must be already configured.
+ * @retval None
+ */
+void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC channel DMA request */
+ DACx->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC channel DMA request */
+ DACx->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified DAC interrupts.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt sources to be enabled or disabled.
+ * This parameter can be:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @note The DMA underrun occurs when a second external trigger arrives before
+ * the acknowledgement for the first external trigger is received (first request).
+ * @param NewState: new state of the specified DAC interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DAC interrupts */
+ DACx->CR |= (DAC_IT << DAC_Channel);
+ }
+ else
+ {
+ /* Disable the selected DAC interrupts */
+ DACx->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+ }
+}
+
+/**
+ * @brief Checks whether the specified DAC flag is set or not.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: thee selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to check.
+ * This parameter can be:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @note The DMA underrun occurs when a second external trigger arrives before
+ * the acknowledgement for the first external trigger is received (first request).
+ * @retval The new state of DAC_FLAG (SET or RESET).
+ */
+FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Check the status of the specified DAC flag */
+ if ((DACx->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+ {
+ /* DAC_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_FLAG is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channel's pending flags.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_FLAG: specifies the flag to clear.
+ * This parameter can be:
+ * @arg DAC_FLAG_DMAUDR: DMA underrun flag
+ * @retval None
+ */
+void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+ /* Clear the selected DAC flags */
+ DACx->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+ * @brief Checks whether the specified DAC interrupt has occurred or not.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt source to check.
+ * This parameter can be:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @note The DMA underrun occurs when a second external trigger arrives before
+ * the acknowledgement for the first external trigger is received (first request).
+ * @retval The new state of DAC_IT (SET or RESET).
+ */
+ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Get the DAC_IT enable bit status */
+ enablestatus = (DACx->CR & (DAC_IT << DAC_Channel)) ;
+
+ /* Check the status of the specified DAC interrupt */
+ if (((DACx->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+ {
+ /* DAC_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DAC_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DAC_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DAC channel's interrupt pending bits.
+ * @param DACx: where x can be 1 or 2 to select the DAC peripheral.
+ * @param DAC_Channel: the selected DAC channel.
+ * This parameter can be one of the following values:
+ * @arg DAC_Channel_1: DAC Channel1 selected
+ * @arg DAC_Channel_2: DAC Channel2 selected
+ * @param DAC_IT: specifies the DAC interrupt pending bit to clear.
+ * This parameter can be the following values:
+ * @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+ * @retval None
+ */
+void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DAC_ALL_PERIPH(DACx));
+ assert_param(IS_DAC_CHANNEL(DAC_Channel));
+ assert_param(IS_DAC_IT(DAC_IT));
+
+ /* Clear the selected DAC interrupt pending bits */
+ DACx->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dac.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dac.h
new file mode 100644
index 0000000000..bcb29c63a0
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dac.h
@@ -0,0 +1,332 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dac.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the DAC firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DAC_H
+#define __STM32F30x_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DAC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+#define DAC_CR_DMAUDRIE ((uint32_t)0x00002000) /*!< DAC channel DMA underrun interrupt enable */
+
+/**
+ * @brief DAC Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t DAC_Trigger; /*!< Specifies the external trigger for the selected DAC channel.
+ This parameter can be a value of @ref DAC_trigger_selection */
+
+ uint32_t DAC_WaveGeneration; /*!< Specifies whether DAC channel noise waves or triangle waves
+ are generated, or whether no wave is generated.
+ This parameter can be a value of @ref DAC_wave_generation */
+
+ uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+ the maximum amplitude triangle generation for the DAC channel.
+ This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+ uint32_t DAC_Buffer_Switch; /*!< Specifies whether the DAC channel output buffer is enabled or disabled or
+ the DAC channel output switch is enabled or disabled.
+ This parameter can be a value of @ref DAC_buffer_switch */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+ * @{
+ */
+
+#define IS_DAC_ALL_PERIPH(PERIPH) (((PERIPH) == DAC1) || \
+ ((PERIPH) == DAC2))
+
+#define IS_DAC_LIST1_PERIPH(PERIPH) (((PERIPH) == DAC1))
+
+/** @defgroup DAC_trigger_selection
+ * @{
+ */
+
+#define DAC_Trigger_None ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register
+ has been loaded, and not by external trigger */
+#define DAC_Trigger_T6_TRGO ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T3_TRGO ((uint32_t)0x0000000C) /*!< TIM3 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T8_TRGO ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_T7_TRGO ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T15_TRGO ((uint32_t)0x0000001C) /*!< TIM15 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_HRTIM1_DACTRG1 ((uint32_t)0x0000001C) /*!< HRTIM1 DACTRG1 selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_T2_TRGO ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_T4_TRGO ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_HRTIM1_DACTRG2 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG2 selected as external conversion trigger for DAC1 channel1/2 */
+#define DAC_Trigger_HRTIM1_DACTRG3 ((uint32_t)0x0000002C) /*!< HRTIM1 DACTRG3 selected as external conversion trigger for DAC2 channel1 */
+#define DAC_Trigger_Ext_IT9 ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC1/2 channel1/2 */
+#define DAC_Trigger_Software ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC1/2 channel1/2 */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+ ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T3_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T15_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG1)|| \
+ ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+ ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG2)|| \
+ ((TRIGGER) == DAC_Trigger_HRTIM1_DACTRG3)|| \
+ ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+ ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_WaveGeneration_None ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle ((uint32_t)0x00000080)
+
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+ ((WAVE) == DAC_WaveGeneration_Noise) || \
+ ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+ * @{
+ */
+
+#define DAC_LFSRUnmask_Bit0 ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0 ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0 ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0 ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0 ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0 ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0 ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0 ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0 ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0 ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0 ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0 ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1 ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3 ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7 ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15 ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31 ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63 ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127 ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255 ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511 ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023 ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047 ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095 ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+ ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+ ((VALUE) == DAC_TriangleAmplitude_1) || \
+ ((VALUE) == DAC_TriangleAmplitude_3) || \
+ ((VALUE) == DAC_TriangleAmplitude_7) || \
+ ((VALUE) == DAC_TriangleAmplitude_15) || \
+ ((VALUE) == DAC_TriangleAmplitude_31) || \
+ ((VALUE) == DAC_TriangleAmplitude_63) || \
+ ((VALUE) == DAC_TriangleAmplitude_127) || \
+ ((VALUE) == DAC_TriangleAmplitude_255) || \
+ ((VALUE) == DAC_TriangleAmplitude_511) || \
+ ((VALUE) == DAC_TriangleAmplitude_1023) || \
+ ((VALUE) == DAC_TriangleAmplitude_2047) || \
+ ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_buffer_switch
+ * @{
+ */
+
+#define DAC_BufferSwitch_Disable ((uint32_t)0x00000000)
+#define DAC_BufferSwitch_Enable ((uint32_t)0x00000002)
+
+#define IS_DAC_BUFFER_SWITCH_STATE(STATE) (((STATE) == DAC_BufferSwitch_Enable) || \
+ ((STATE) == DAC_BufferSwitch_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_Channel_selection
+ * @{
+ */
+#define DAC_Channel_1 ((uint32_t)0x00000000)
+#define DAC_Channel_2 ((uint32_t)0x00000010)
+
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+ ((CHANNEL) == DAC_Channel_2))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data_alignement
+ * @{
+ */
+
+#define DAC_Align_12b_R ((uint32_t)0x00000000)
+#define DAC_Align_12b_L ((uint32_t)0x00000004)
+#define DAC_Align_8b_R ((uint32_t)0x00000008)
+
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+ ((ALIGN) == DAC_Align_12b_L) || \
+ ((ALIGN) == DAC_Align_8b_R))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_wave_generation
+ * @{
+ */
+
+#define DAC_Wave_Noise ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle ((uint32_t)0x00000080)
+
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+ ((WAVE) == DAC_Wave_Triangle))
+/**
+ * @}
+ */
+
+/** @defgroup DAC_data
+ * @{
+ */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0)
+/**
+ * @}
+ */
+
+/** @defgroup DAC_interrupts_definition
+ * @{
+ */
+#define DAC_IT_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR))
+
+/**
+ * @}
+ */
+
+/** @defgroup DAC_flags_definition
+ * @{
+ */
+
+#define DAC_FLAG_DMAUDR ((uint32_t)0x00002000)
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Function used to set the DAC configuration to the default reset state *****/
+void DAC_DeInit(DAC_TypeDef* DACx);
+
+/* DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(DAC_TypeDef* DACx, FunctionalState NewState);
+void DAC_WaveGenerationCmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(DAC_TypeDef* DACx, uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(DAC_TypeDef* DACx, uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(DAC_TypeDef* DACx, uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(DAC_TypeDef* DACx, uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_DAC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dbgmcu.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dbgmcu.c
new file mode 100644
index 0000000000..a460bc9ef8
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dbgmcu.c
@@ -0,0 +1,223 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dbgmcu.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Debug MCU (DBGMCU) peripheral:
+ * + Device and Revision ID management
+ * + Peripherals Configuration
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dbgmcu.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DBGMCU
+ * @brief DBGMCU driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions
+ * @{
+ */
+
+/** @defgroup DBGMCU_Group1 Device and Revision ID management functions
+ * @brief Device and Revision ID management functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Device and Revision ID management functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns the device revision identifier.
+ * @param None
+ * @retval Device revision identifier
+ */
+uint32_t DBGMCU_GetREVID(void)
+{
+ return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+ * @brief Returns the device identifier.
+ * @param None
+ * @retval Device identifier
+ */
+uint32_t DBGMCU_GetDEVID(void)
+{
+ return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DBGMCU_Group2 Peripherals Configuration functions
+ * @brief Peripherals Configuration
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripherals Configuration functions #####
+ ==============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures low power mode behavior when the MCU is in Debug mode.
+ * @param DBGMCU_Periph: specifies the low power mode.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode.
+ * @arg DBGMCU_STOP: Keep debugger connection during STOP mode.
+ * @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode.
+ * @param NewState: new state of the specified low power mode in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ DBGMCU->CR |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->CR &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
+ * @param DBGMCU_Periph: specifies the APB1 peripheral.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted.
+ * @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter are stopped when
+ * Core is halted.
+ * @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted.
+ * @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted.
+ * @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when
+ * Core is halted.
+ * @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when
+ * Core is halted.
+ * @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted.
+ * @param NewState: new state of the specified APB1 peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->APB1FZ |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @brief Configures APB2 peripheral behavior when the MCU is in Debug mode.
+ * @param DBGMCU_Periph: specifies the APB2 peripheral.
+ * This parameter can be any combination of the following values:
+ * @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM15_STOP: TIM15 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM16_STOP: TIM16 counter stopped when Core is halted.
+ * @arg DBGMCU_TIM17_STOP: TIM17 counter stopped when Core is halted.
+ * @param NewState: new state of the specified APB2 peripheral in Debug mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ DBGMCU->APB2FZ |= DBGMCU_Periph;
+ }
+ else
+ {
+ DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dbgmcu.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dbgmcu.h
new file mode 100644
index 0000000000..79008087d9
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dbgmcu.h
@@ -0,0 +1,118 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dbgmcu.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the DBGMCU firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DBGMCU_H
+#define __STM32F30x_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DBGMCU
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+ * @{
+ */
+#define DBGMCU_SLEEP ((uint32_t)0x00000001)
+#define DBGMCU_STOP ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP ((uint32_t)0x00000004)
+#define DBGMCU_TIM6_STOP ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP ((uint32_t)0x00000020)
+#define DBGMCU_RTC_STOP ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
+#define DBGMCU_CAN1_STOP ((uint32_t)0x02000000)
+
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE3C8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP ((uint32_t)0x00000001)
+#define DBGMCU_TIM8_STOP ((uint32_t)0x00000002)
+#define DBGMCU_TIM15_STOP ((uint32_t)0x00000004)
+#define DBGMCU_TIM16_STOP ((uint32_t)0x00000008)
+#define DBGMCU_TIM17_STOP ((uint32_t)0x00000010)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFE0) == 0x00) && ((PERIPH) != 0x00))
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/* Device and Revision ID management functions ********************************/
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+
+/* Peripherals Configuration functions ****************************************/
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_DBGMCU_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dma.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dma.c
new file mode 100644
index 0000000000..3bfe0524f7
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dma.c
@@ -0,0 +1,876 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dma.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Direct Memory Access controller (DMA):
+ * + Initialization and Configuration
+ * + Data Counter
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable The DMA controller clock using
+ RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE) function for DMA1 or
+ using RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA2, ENABLE) function for DMA2.
+ (#) Enable and configure the peripheral to be connected to the DMA channel
+ (except for internal SRAM / FLASH memories: no initialization is necessary).
+ (#) For a given Channel, program the Source and Destination addresses,
+ the transfer Direction, the Buffer Size, the Peripheral and Memory
+ Incrementation mode and Data Size, the Circular or Normal mode,
+ the channel transfer Priority and the Memory-to-Memory transfer
+ mode (if needed) using the DMA_Init() function.
+ (#) Enable the NVIC and the corresponding interrupt(s) using the function
+ DMA_ITConfig() if you need to use DMA interrupts.
+ (#) Enable the DMA channel using the DMA_Cmd() function.
+ (#) Activate the needed channel Request using PPP_DMACmd() function for
+ any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
+ The function allowing this operation is provided in each PPP peripheral
+ driver (ie. SPI_DMACmd for SPI peripheral).
+ (#) Optionally, you can configure the number of data to be transferred
+ when the channel is disabled (ie. after each Transfer Complete event
+ or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+ And you can get the number of remaining data to be transferred using
+ the function DMA_GetCurrDataCounter() at run time (when the DMA channel is
+ enabled and running).
+ (#) To control DMA events you can use one of the following two methods:
+ (##) Check on DMA channel flags using the function DMA_GetFlagStatus().
+ (##) Use DMA interrupts through the function DMA_ITConfig() at initialization
+ phase and DMA_GetITStatus() function into interrupt routines in
+ communication phase.
+ After checking on a flag you should clear it using DMA_ClearFlag()
+ function. And after checking on an interrupt event you should
+ clear it using DMA_ClearITPendingBit() function.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_dma.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup DMA
+ * @brief DMA driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define CCR_CLEAR_MASK ((uint32_t)0xFFFF800F) /* DMA Channel config registers Masks */
+#define FLAG_Mask ((uint32_t)0x10000000) /* DMA2 FLAG mask */
+
+
+/* DMA1 Channelx interrupt pending bit masks */
+#define DMA1_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA1_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA1_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA1_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA1_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+#define DMA1_CHANNEL6_IT_MASK ((uint32_t)(DMA_ISR_GIF6 | DMA_ISR_TCIF6 | DMA_ISR_HTIF6 | DMA_ISR_TEIF6))
+#define DMA1_CHANNEL7_IT_MASK ((uint32_t)(DMA_ISR_GIF7 | DMA_ISR_TCIF7 | DMA_ISR_HTIF7 | DMA_ISR_TEIF7))
+
+/* DMA2 Channelx interrupt pending bit masks */
+#define DMA2_CHANNEL1_IT_MASK ((uint32_t)(DMA_ISR_GIF1 | DMA_ISR_TCIF1 | DMA_ISR_HTIF1 | DMA_ISR_TEIF1))
+#define DMA2_CHANNEL2_IT_MASK ((uint32_t)(DMA_ISR_GIF2 | DMA_ISR_TCIF2 | DMA_ISR_HTIF2 | DMA_ISR_TEIF2))
+#define DMA2_CHANNEL3_IT_MASK ((uint32_t)(DMA_ISR_GIF3 | DMA_ISR_TCIF3 | DMA_ISR_HTIF3 | DMA_ISR_TEIF3))
+#define DMA2_CHANNEL4_IT_MASK ((uint32_t)(DMA_ISR_GIF4 | DMA_ISR_TCIF4 | DMA_ISR_HTIF4 | DMA_ISR_TEIF4))
+#define DMA2_CHANNEL5_IT_MASK ((uint32_t)(DMA_ISR_GIF5 | DMA_ISR_TCIF5 | DMA_ISR_HTIF5 | DMA_ISR_TEIF5))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DMA_Private_Functions
+ * @{
+ */
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+ [..] This subsection provides functions allowing to initialize the DMA channel
+ source and destination addresses, incrementation and data sizes, transfer
+ direction, buffer size, circular/normal mode selection, memory-to-memory
+ mode selection and channel priority value.
+ [..] The DMA_Init() function follows the DMA configuration procedures as described
+ in reference manual (RM00316).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the DMAy Channelx registers to their default reset
+ * values.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval None
+ */
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+
+ /* Reset DMAy Channelx control register */
+ DMAy_Channelx->CCR = 0;
+
+ /* Reset DMAy Channelx remaining bytes register */
+ DMAy_Channelx->CNDTR = 0;
+
+ /* Reset DMAy Channelx peripheral address register */
+ DMAy_Channelx->CPAR = 0;
+
+ /* Reset DMAy Channelx memory address register */
+ DMAy_Channelx->CMAR = 0;
+
+ if (DMAy_Channelx == DMA1_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel1 */
+ DMA1->IFCR |= DMA1_CHANNEL1_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel2 */
+ DMA1->IFCR |= DMA1_CHANNEL2_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel3 */
+ DMA1->IFCR |= DMA1_CHANNEL3_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel4 */
+ DMA1->IFCR |= DMA1_CHANNEL4_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel5 */
+ DMA1->IFCR |= DMA1_CHANNEL5_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel6)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel6 */
+ DMA1->IFCR |= DMA1_CHANNEL6_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA1_Channel7)
+ {
+ /* Reset interrupt pending bits for DMA1 Channel7 */
+ DMA1->IFCR |= DMA1_CHANNEL7_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel1)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel1 */
+ DMA2->IFCR |= DMA2_CHANNEL1_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel2)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel2 */
+ DMA2->IFCR |= DMA2_CHANNEL2_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel3)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel3 */
+ DMA2->IFCR |= DMA2_CHANNEL3_IT_MASK;
+ }
+ else if (DMAy_Channelx == DMA2_Channel4)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel4 */
+ DMA2->IFCR |= DMA2_CHANNEL4_IT_MASK;
+ }
+ else
+ {
+ if (DMAy_Channelx == DMA2_Channel5)
+ {
+ /* Reset interrupt pending bits for DMA2 Channel5 */
+ DMA2->IFCR |= DMA2_CHANNEL5_IT_MASK;
+ }
+ }
+}
+
+/**
+ * @brief Initializes the DMAy Channelx according to the specified parameters
+ * in the DMA_InitStruct.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+ * the configuration information for the specified DMA Channel.
+ * @retval None
+ */
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_DIR(DMA_InitStruct->DMA_DIR));
+ assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+ assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+ assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+ assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+ assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+ assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+ assert_param(IS_DMA_M2M_STATE(DMA_InitStruct->DMA_M2M));
+
+/*--------------------------- DMAy Channelx CCR Configuration ----------------*/
+ /* Get the DMAy_Channelx CCR value */
+ tmpreg = DMAy_Channelx->CCR;
+
+ /* Clear MEM2MEM, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+ tmpreg &= CCR_CLEAR_MASK;
+
+ /* Configure DMAy Channelx: data transfer, data size, priority level and mode */
+ /* Set DIR bit according to DMA_DIR value */
+ /* Set CIRC bit according to DMA_Mode value */
+ /* Set PINC bit according to DMA_PeripheralInc value */
+ /* Set MINC bit according to DMA_MemoryInc value */
+ /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+ /* Set MSIZE bits according to DMA_MemoryDataSize value */
+ /* Set PL bits according to DMA_Priority value */
+ /* Set the MEM2MEM bit according to DMA_M2M value */
+ tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
+ DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+ DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+ DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
+
+ /* Write to DMAy Channelx CCR */
+ DMAy_Channelx->CCR = tmpreg;
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DMA_InitStruct->DMA_BufferSize;
+
+/*--------------------------- DMAy Channelx CPAR Configuration ---------------*/
+ /* Write to DMAy Channelx CPAR */
+ DMAy_Channelx->CPAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+/*--------------------------- DMAy Channelx CMAR Configuration ---------------*/
+ /* Write to DMAy Channelx CMAR */
+ DMAy_Channelx->CMAR = DMA_InitStruct->DMA_MemoryBaseAddr;
+}
+
+/**
+ * @brief Fills each DMA_InitStruct member with its default value.
+ * @param DMA_InitStruct: pointer to a DMA_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+/*-------------- Reset DMA init structure parameters values ------------------*/
+ /* Initialize the DMA_PeripheralBaseAddr member */
+ DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+ /* Initialize the DMA_MemoryBaseAddr member */
+ DMA_InitStruct->DMA_MemoryBaseAddr = 0;
+ /* Initialize the DMA_DIR member */
+ DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
+ /* Initialize the DMA_BufferSize member */
+ DMA_InitStruct->DMA_BufferSize = 0;
+ /* Initialize the DMA_PeripheralInc member */
+ DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+ /* Initialize the DMA_MemoryInc member */
+ DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+ /* Initialize the DMA_PeripheralDataSize member */
+ DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+ /* Initialize the DMA_MemoryDataSize member */
+ DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+ /* Initialize the DMA_Mode member */
+ DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+ /* Initialize the DMA_Priority member */
+ DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+ /* Initialize the DMA_M2M member */
+ DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
+}
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param NewState: new state of the DMAy Channelx.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMAy Channelx */
+ DMAy_Channelx->CCR |= DMA_CCR_EN;
+ }
+ else
+ {
+ /* Disable the selected DMAy Channelx */
+ DMAy_Channelx->CCR &= (uint16_t)(~DMA_CCR_EN);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ * @brief Data Counter functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data Counter functions #####
+ ===============================================================================
+ [..] This subsection provides function allowing to configure and read the buffer
+ size (number of data to be transferred).The DMA data counter can be written
+ only when the DMA channel is disabled (ie. after transfer complete event).
+ [..] The following function can be used to write the Channel data counter value:
+ (+) void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber).
+ [..]
+ (@) It is advised to use this function rather than DMA_Init() in situations
+ where only the Data buffer needs to be reloaded.
+ [..] The DMA data counter can be read to indicate the number of remaining transfers
+ for the relative DMA channel. This counter is decremented at the end of each
+ data transfer and when the transfer is complete:
+ (+) If Normal mode is selected: the counter is set to 0.
+ (+) If Circular mode is selected: the counter is reloaded with the initial
+ value(configured before enabling the DMA channel).
+ [..] The following function can be used to read the Channel data counter value:
+ (+) uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the number of data units in the current DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DataNumber: The number of data units in the current DMAy Channelx
+ * transfer.
+ * @note This function can only be used when the DMAy_Channelx is disabled.
+ * @retval None.
+ */
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+
+/*--------------------------- DMAy Channelx CNDTR Configuration --------------*/
+ /* Write to DMAy Channelx CNDTR */
+ DMAy_Channelx->CNDTR = DataNumber;
+}
+
+/**
+ * @brief Returns the number of remaining data units in the current
+ * DMAy Channelx transfer.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @retval The number of remaining data units in the current DMAy Channelx
+ * transfer.
+ */
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ /* Return the number of remaining data units for DMAy Channelx */
+ return ((uint16_t)(DMAy_Channelx->CNDTR));
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_Group3 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This subsection provides functions allowing to configure the DMA Interrupt
+ sources and check or clear the flags or pending bits status.
+ The user should identify which mode will be used in his application to manage
+ the DMA controller events: Polling mode or Interrupt mode.
+
+ *** Polling Mode ***
+ ====================
+ [..] Each DMA channel can be managed through 4 event Flags (y : DMA Controller
+ number, x : DMA channel number):
+ (#) DMAy_FLAG_TCx : to indicate that a Transfer Complete event occurred.
+ (#) DMAy_FLAG_HTx : to indicate that a Half-Transfer Complete event occurred.
+ (#) DMAy_FLAG_TEx : to indicate that a Transfer Error occurred.
+ (#) DMAy_FLAG_GLx : to indicate that at least one of the events described
+ above occurred.
+ [..]
+ (@) Clearing DMAy_FLAG_GLx results in clearing all other pending flags of the
+ same channel (DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+ [..] In this Mode it is advised to use the following functions:
+ (+) FlagStatus DMA_GetFlagStatus(uint32_t DMA_FLAG);
+ (+) void DMA_ClearFlag(uint32_t DMA_FLAG);
+
+ *** Interrupt Mode ***
+ ======================
+ [..] Each DMA channel can be managed through 4 Interrupts:
+ (+) Interrupt Source
+ (##) DMA_IT_TC: specifies the interrupt source for the Transfer Complete
+ event.
+ (##) DMA_IT_HT: specifies the interrupt source for the Half-transfer Complete
+ event.
+ (##) DMA_IT_TE: specifies the interrupt source for the transfer errors event.
+ (##) DMA_IT_GL: to indicate that at least one of the interrupts described
+ above occurred.
+ -@@- Clearing DMA_IT_GL interrupt results in clearing all other interrupts of
+ the same channel (DMA_IT_TCx, DMA_IT_HT and DMA_IT_TE).
+ [..] In this Mode it is advised to use the following functions:
+ (+) void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+ (+) ITStatus DMA_GetITStatus(uint32_t DMA_IT);
+ (+) void DMA_ClearITPendingBit(uint32_t DMA_IT);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified DMAy Channelx interrupts.
+ * @param DMAy_Channelx: where y can be 1 or 2 to select the DMA and
+ * x can be 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
+ * @param DMA_IT: specifies the DMA interrupts sources to be enabled
+ * or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg DMA_IT_TC: Transfer complete interrupt mask
+ * @arg DMA_IT_HT: Half transfer interrupt mask
+ * @arg DMA_IT_TE: Transfer error interrupt mask
+ * @param NewState: new state of the specified DMA interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_ALL_PERIPH(DMAy_Channelx));
+ assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected DMA interrupts */
+ DMAy_Channelx->CCR |= DMA_IT;
+ }
+ else
+ {
+ /* Disable the selected DMA interrupts */
+ DMAy_Channelx->CCR &= ~DMA_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx flag is set or not.
+ * @param DMAy_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ *
+ * @note
+ * The Global flag (DMAy_FLAG_GLx) is set whenever any of the other flags
+ * relative to the same channel is set (Transfer Complete, Half-transfer
+ * Complete or Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx or
+ * DMAy_FLAG_TEx).
+ *
+ * @retval The new state of DMAy_FLAG (SET or RESET).
+ */
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_FLAG(DMAy_FLAG));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR ;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR ;
+ }
+
+ /* Check the status of the specified DMAy flag */
+ if ((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
+ {
+ /* DMAy_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_FLAG is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the DMAy_FLAG status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's pending flags.
+ * @param DMAy_FLAG: specifies the flag to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_FLAG_GL1: DMA1 Channel1 global flag.
+ * @arg DMA1_FLAG_TC1: DMA1 Channel1 transfer complete flag.
+ * @arg DMA1_FLAG_HT1: DMA1 Channel1 half transfer flag.
+ * @arg DMA1_FLAG_TE1: DMA1 Channel1 transfer error flag.
+ * @arg DMA1_FLAG_GL2: DMA1 Channel2 global flag.
+ * @arg DMA1_FLAG_TC2: DMA1 Channel2 transfer complete flag.
+ * @arg DMA1_FLAG_HT2: DMA1 Channel2 half transfer flag.
+ * @arg DMA1_FLAG_TE2: DMA1 Channel2 transfer error flag.
+ * @arg DMA1_FLAG_GL3: DMA1 Channel3 global flag.
+ * @arg DMA1_FLAG_TC3: DMA1 Channel3 transfer complete flag.
+ * @arg DMA1_FLAG_HT3: DMA1 Channel3 half transfer flag.
+ * @arg DMA1_FLAG_TE3: DMA1 Channel3 transfer error flag.
+ * @arg DMA1_FLAG_GL4: DMA1 Channel4 global flag.
+ * @arg DMA1_FLAG_TC4: DMA1 Channel4 transfer complete flag.
+ * @arg DMA1_FLAG_HT4: DMA1 Channel4 half transfer flag.
+ * @arg DMA1_FLAG_TE4: DMA1 Channel4 transfer error flag.
+ * @arg DMA1_FLAG_GL5: DMA1 Channel5 global flag.
+ * @arg DMA1_FLAG_TC5: DMA1 Channel5 transfer complete flag.
+ * @arg DMA1_FLAG_HT5: DMA1 Channel5 half transfer flag.
+ * @arg DMA1_FLAG_TE5: DMA1 Channel5 transfer error flag.
+ * @arg DMA1_FLAG_GL6: DMA1 Channel6 global flag.
+ * @arg DMA1_FLAG_TC6: DMA1 Channel6 transfer complete flag.
+ * @arg DMA1_FLAG_HT6: DMA1 Channel6 half transfer flag.
+ * @arg DMA1_FLAG_TE6: DMA1 Channel6 transfer error flag.
+ * @arg DMA1_FLAG_GL7: DMA1 Channel7 global flag.
+ * @arg DMA1_FLAG_TC7: DMA1 Channel7 transfer complete flag.
+ * @arg DMA1_FLAG_HT7: DMA1 Channel7 half transfer flag.
+ * @arg DMA1_FLAG_TE7: DMA1 Channel7 transfer error flag.
+ * @arg DMA2_FLAG_GL1: DMA2 Channel1 global flag.
+ * @arg DMA2_FLAG_TC1: DMA2 Channel1 transfer complete flag.
+ * @arg DMA2_FLAG_HT1: DMA2 Channel1 half transfer flag.
+ * @arg DMA2_FLAG_TE1: DMA2 Channel1 transfer error flag.
+ * @arg DMA2_FLAG_GL2: DMA2 Channel2 global flag.
+ * @arg DMA2_FLAG_TC2: DMA2 Channel2 transfer complete flag.
+ * @arg DMA2_FLAG_HT2: DMA2 Channel2 half transfer flag.
+ * @arg DMA2_FLAG_TE2: DMA2 Channel2 transfer error flag.
+ * @arg DMA2_FLAG_GL3: DMA2 Channel3 global flag.
+ * @arg DMA2_FLAG_TC3: DMA2 Channel3 transfer complete flag.
+ * @arg DMA2_FLAG_HT3: DMA2 Channel3 half transfer flag.
+ * @arg DMA2_FLAG_TE3: DMA2 Channel3 transfer error flag.
+ * @arg DMA2_FLAG_GL4: DMA2 Channel4 global flag.
+ * @arg DMA2_FLAG_TC4: DMA2 Channel4 transfer complete flag.
+ * @arg DMA2_FLAG_HT4: DMA2 Channel4 half transfer flag.
+ * @arg DMA2_FLAG_TE4: DMA2 Channel4 transfer error flag.
+ * @arg DMA2_FLAG_GL5: DMA2 Channel5 global flag.
+ * @arg DMA2_FLAG_TC5: DMA2 Channel5 transfer complete flag.
+ * @arg DMA2_FLAG_HT5: DMA2 Channel5 half transfer flag.
+ * @arg DMA2_FLAG_TE5: DMA2 Channel5 transfer error flag.
+ *
+ * @note
+ * Clearing the Global flag (DMAy_FLAG_GLx) results in clearing all other flags
+ * relative to the same channel (Transfer Complete, Half-transfer Complete and
+ * Transfer Error flags: DMAy_FLAG_TCx, DMAy_FLAG_HTx and DMAy_FLAG_TEx).
+ *
+ * @retval None
+ */
+void DMA_ClearFlag(uint32_t DMAy_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_FLAG(DMAy_FLAG));
+
+/* Calculate the used DMAy */
+ if ((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy flags */
+ DMA2->IFCR = DMAy_FLAG;
+ }
+ else
+ {
+ /* Clear the selected DMAy flags */
+ DMA1->IFCR = DMAy_FLAG;
+ }
+}
+
+/**
+ * @brief Checks whether the specified DMAy Channelx interrupt has occurred or not.
+ * @param DMAy_IT: specifies the DMAy interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ *
+ * @note
+ * The Global interrupt (DMAy_FLAG_GLx) is set whenever any of the other
+ * interrupts relative to the same channel is set (Transfer Complete,
+ * Half-transfer Complete or Transfer Error interrupts: DMAy_IT_TCx,
+ * DMAy_IT_HTx or DMAy_IT_TEx).
+ *
+ * @retval The new state of DMAy_IT (SET or RESET).
+ */
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_DMA_GET_IT(DMAy_IT));
+
+ /* Calculate the used DMA */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Get DMA2 ISR register value */
+ tmpreg = DMA2->ISR;
+ }
+ else
+ {
+ /* Get DMA1 ISR register value */
+ tmpreg = DMA1->ISR;
+ }
+
+ /* Check the status of the specified DMAy interrupt */
+ if ((tmpreg & DMAy_IT) != (uint32_t)RESET)
+ {
+ /* DMAy_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* DMAy_IT is reset */
+ bitstatus = RESET;
+ }
+ /* Return the DMAy_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the DMAy Channelx's interrupt pending bits.
+ * @param DMAy_IT: specifies the DMAy interrupt pending bit to clear.
+ * This parameter can be any combination (for the same DMA) of the following values:
+ * @arg DMA1_IT_GL1: DMA1 Channel1 global interrupt.
+ * @arg DMA1_IT_TC1: DMA1 Channel1 transfer complete interrupt.
+ * @arg DMA1_IT_HT1: DMA1 Channel1 half transfer interrupt.
+ * @arg DMA1_IT_TE1: DMA1 Channel1 transfer error interrupt.
+ * @arg DMA1_IT_GL2: DMA1 Channel2 global interrupt.
+ * @arg DMA1_IT_TC2: DMA1 Channel2 transfer complete interrupt.
+ * @arg DMA1_IT_HT2: DMA1 Channel2 half transfer interrupt.
+ * @arg DMA1_IT_TE2: DMA1 Channel2 transfer error interrupt.
+ * @arg DMA1_IT_GL3: DMA1 Channel3 global interrupt.
+ * @arg DMA1_IT_TC3: DMA1 Channel3 transfer complete interrupt.
+ * @arg DMA1_IT_HT3: DMA1 Channel3 half transfer interrupt.
+ * @arg DMA1_IT_TE3: DMA1 Channel3 transfer error interrupt.
+ * @arg DMA1_IT_GL4: DMA1 Channel4 global interrupt.
+ * @arg DMA1_IT_TC4: DMA1 Channel4 transfer complete interrupt.
+ * @arg DMA1_IT_HT4: DMA1 Channel4 half transfer interrupt.
+ * @arg DMA1_IT_TE4: DMA1 Channel4 transfer error interrupt.
+ * @arg DMA1_IT_GL5: DMA1 Channel5 global interrupt.
+ * @arg DMA1_IT_TC5: DMA1 Channel5 transfer complete interrupt.
+ * @arg DMA1_IT_HT5: DMA1 Channel5 half transfer interrupt.
+ * @arg DMA1_IT_TE5: DMA1 Channel5 transfer error interrupt.
+ * @arg DMA1_IT_GL6: DMA1 Channel6 global interrupt.
+ * @arg DMA1_IT_TC6: DMA1 Channel6 transfer complete interrupt.
+ * @arg DMA1_IT_HT6: DMA1 Channel6 half transfer interrupt.
+ * @arg DMA1_IT_TE6: DMA1 Channel6 transfer error interrupt.
+ * @arg DMA1_IT_GL7: DMA1 Channel7 global interrupt.
+ * @arg DMA1_IT_TC7: DMA1 Channel7 transfer complete interrupt.
+ * @arg DMA1_IT_HT7: DMA1 Channel7 half transfer interrupt.
+ * @arg DMA1_IT_TE7: DMA1 Channel7 transfer error interrupt.
+ * @arg DMA2_IT_GL1: DMA2 Channel1 global interrupt.
+ * @arg DMA2_IT_TC1: DMA2 Channel1 transfer complete interrupt.
+ * @arg DMA2_IT_HT1: DMA2 Channel1 half transfer interrupt.
+ * @arg DMA2_IT_TE1: DMA2 Channel1 transfer error interrupt.
+ * @arg DMA2_IT_GL2: DMA2 Channel2 global interrupt.
+ * @arg DMA2_IT_TC2: DMA2 Channel2 transfer complete interrupt.
+ * @arg DMA2_IT_HT2: DMA2 Channel2 half transfer interrupt.
+ * @arg DMA2_IT_TE2: DMA2 Channel2 transfer error interrupt.
+ * @arg DMA2_IT_GL3: DMA2 Channel3 global interrupt.
+ * @arg DMA2_IT_TC3: DMA2 Channel3 transfer complete interrupt.
+ * @arg DMA2_IT_HT3: DMA2 Channel3 half transfer interrupt.
+ * @arg DMA2_IT_TE3: DMA2 Channel3 transfer error interrupt.
+ * @arg DMA2_IT_GL4: DMA2 Channel4 global interrupt.
+ * @arg DMA2_IT_TC4: DMA2 Channel4 transfer complete interrupt.
+ * @arg DMA2_IT_HT4: DMA2 Channel4 half transfer interrupt.
+ * @arg DMA2_IT_TE4: DMA2 Channel4 transfer error interrupt.
+ * @arg DMA2_IT_GL5: DMA2 Channel5 global interrupt.
+ * @arg DMA2_IT_TC5: DMA2 Channel5 transfer complete interrupt.
+ * @arg DMA2_IT_HT5: DMA2 Channel5 half transfer interrupt.
+ * @arg DMA2_IT_TE5: DMA2 Channel5 transfer error interrupt.
+ *
+ * @note
+ * Clearing the Global interrupt (DMAy_IT_GLx) results in clearing all other
+ * interrupts relative to the same channel (Transfer Complete, Half-transfer
+ * Complete and Transfer Error interrupts: DMAy_IT_TCx, DMAy_IT_HTx and
+ * DMAy_IT_TEx).
+ *
+ * @retval None
+ */
+void DMA_ClearITPendingBit(uint32_t DMAy_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_DMA_CLEAR_IT(DMAy_IT));
+
+ /* Calculate the used DMAy */
+ if ((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA2->IFCR = DMAy_IT;
+ }
+ else
+ {
+ /* Clear the selected DMAy interrupt pending bits */
+ DMA1->IFCR = DMAy_IT;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dma.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dma.h
new file mode 100644
index 0000000000..1f9b79cf54
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_dma.h
@@ -0,0 +1,446 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_dma.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the DMA firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_DMA_H
+#define __STM32F30x_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup DMA
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief DMA Init structures definition
+ */
+typedef struct
+{
+ uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Channelx. */
+
+ uint32_t DMA_MemoryBaseAddr; /*!< Specifies the memory base address for DMAy Channelx. */
+
+ uint32_t DMA_DIR; /*!< Specifies if the peripheral is the source or destination.
+ This parameter can be a value of @ref DMA_data_transfer_direction */
+
+ uint16_t DMA_BufferSize; /*!< Specifies the buffer size, in data unit, of the specified Channel.
+ The data unit is equal to the configuration set in DMA_PeripheralDataSize
+ or DMA_MemoryDataSize members depending in the transfer direction. */
+
+ uint32_t DMA_PeripheralInc; /*!< Specifies whether the Peripheral address register is incremented or not.
+ This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+ uint32_t DMA_MemoryInc; /*!< Specifies whether the memory address register is incremented or not.
+ This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+ uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+ This parameter can be a value of @ref DMA_peripheral_data_size */
+
+ uint32_t DMA_MemoryDataSize; /*!< Specifies the Memory data width.
+ This parameter can be a value of @ref DMA_memory_data_size */
+
+ uint32_t DMA_Mode; /*!< Specifies the operation mode of the DMAy Channelx.
+ This parameter can be a value of @ref DMA_circular_normal_mode
+ @note: The circular buffer mode cannot be used if the memory-to-memory
+ data transfer is configured on the selected Channel */
+
+ uint32_t DMA_Priority; /*!< Specifies the software priority for the DMAy Channelx.
+ This parameter can be a value of @ref DMA_priority_level */
+
+ uint32_t DMA_M2M; /*!< Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
+ This parameter can be a value of @ref DMA_memory_to_memory */
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+ * @{
+ */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
+ ((PERIPH) == DMA1_Channel2) || \
+ ((PERIPH) == DMA1_Channel3) || \
+ ((PERIPH) == DMA1_Channel4) || \
+ ((PERIPH) == DMA1_Channel5) || \
+ ((PERIPH) == DMA1_Channel6) || \
+ ((PERIPH) == DMA1_Channel7) || \
+ ((PERIPH) == DMA2_Channel1) || \
+ ((PERIPH) == DMA2_Channel2) || \
+ ((PERIPH) == DMA2_Channel3) || \
+ ((PERIPH) == DMA2_Channel4) || \
+ ((PERIPH) == DMA2_Channel5))
+
+/** @defgroup DMA_data_transfer_direction
+ * @{
+ */
+
+#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
+#define DMA_DIR_PeripheralDST DMA_CCR_DIR
+
+#define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
+ ((DIR) == DMA_DIR_PeripheralDST))
+/**
+ * @}
+ */
+
+
+/** @defgroup DMA_peripheral_incremented_mode
+ * @{
+ */
+
+#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
+#define DMA_PeripheralInc_Enable DMA_CCR_PINC
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
+ ((STATE) == DMA_PeripheralInc_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_incremented_mode
+ * @{
+ */
+
+#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
+#define DMA_MemoryInc_Enable DMA_CCR_MINC
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
+ ((STATE) == DMA_MemoryInc_Enable))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_peripheral_data_size
+ * @{
+ */
+
+#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
+#define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
+ ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+ ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_data_size
+ * @{
+ */
+
+#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
+#define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
+#define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
+ ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+ ((SIZE) == DMA_MemoryDataSize_Word))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_circular_normal_mode
+ * @{
+ */
+
+#define DMA_Mode_Normal ((uint32_t)0x00000000)
+#define DMA_Mode_Circular DMA_CCR_CIRC
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_priority_level
+ * @{
+ */
+
+#define DMA_Priority_VeryHigh DMA_CCR_PL
+#define DMA_Priority_High DMA_CCR_PL_1
+#define DMA_Priority_Medium DMA_CCR_PL_0
+#define DMA_Priority_Low ((uint32_t)0x00000000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
+ ((PRIORITY) == DMA_Priority_High) || \
+ ((PRIORITY) == DMA_Priority_Medium) || \
+ ((PRIORITY) == DMA_Priority_Low))
+/**
+ * @}
+ */
+
+/** @defgroup DMA_memory_to_memory
+ * @{
+ */
+
+#define DMA_M2M_Disable ((uint32_t)0x00000000)
+#define DMA_M2M_Enable DMA_CCR_MEM2MEM
+
+#define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_interrupts_definition
+ * @{
+ */
+
+#define DMA_IT_TC ((uint32_t)0x00000002)
+#define DMA_IT_HT ((uint32_t)0x00000004)
+#define DMA_IT_TE ((uint32_t)0x00000008)
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
+
+#define DMA1_IT_GL1 ((uint32_t)0x00000001)
+#define DMA1_IT_TC1 ((uint32_t)0x00000002)
+#define DMA1_IT_HT1 ((uint32_t)0x00000004)
+#define DMA1_IT_TE1 ((uint32_t)0x00000008)
+#define DMA1_IT_GL2 ((uint32_t)0x00000010)
+#define DMA1_IT_TC2 ((uint32_t)0x00000020)
+#define DMA1_IT_HT2 ((uint32_t)0x00000040)
+#define DMA1_IT_TE2 ((uint32_t)0x00000080)
+#define DMA1_IT_GL3 ((uint32_t)0x00000100)
+#define DMA1_IT_TC3 ((uint32_t)0x00000200)
+#define DMA1_IT_HT3 ((uint32_t)0x00000400)
+#define DMA1_IT_TE3 ((uint32_t)0x00000800)
+#define DMA1_IT_GL4 ((uint32_t)0x00001000)
+#define DMA1_IT_TC4 ((uint32_t)0x00002000)
+#define DMA1_IT_HT4 ((uint32_t)0x00004000)
+#define DMA1_IT_TE4 ((uint32_t)0x00008000)
+#define DMA1_IT_GL5 ((uint32_t)0x00010000)
+#define DMA1_IT_TC5 ((uint32_t)0x00020000)
+#define DMA1_IT_HT5 ((uint32_t)0x00040000)
+#define DMA1_IT_TE5 ((uint32_t)0x00080000)
+#define DMA1_IT_GL6 ((uint32_t)0x00100000)
+#define DMA1_IT_TC6 ((uint32_t)0x00200000)
+#define DMA1_IT_HT6 ((uint32_t)0x00400000)
+#define DMA1_IT_TE6 ((uint32_t)0x00800000)
+#define DMA1_IT_GL7 ((uint32_t)0x01000000)
+#define DMA1_IT_TC7 ((uint32_t)0x02000000)
+#define DMA1_IT_HT7 ((uint32_t)0x04000000)
+#define DMA1_IT_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_IT_GL1 ((uint32_t)0x10000001)
+#define DMA2_IT_TC1 ((uint32_t)0x10000002)
+#define DMA2_IT_HT1 ((uint32_t)0x10000004)
+#define DMA2_IT_TE1 ((uint32_t)0x10000008)
+#define DMA2_IT_GL2 ((uint32_t)0x10000010)
+#define DMA2_IT_TC2 ((uint32_t)0x10000020)
+#define DMA2_IT_HT2 ((uint32_t)0x10000040)
+#define DMA2_IT_TE2 ((uint32_t)0x10000080)
+#define DMA2_IT_GL3 ((uint32_t)0x10000100)
+#define DMA2_IT_TC3 ((uint32_t)0x10000200)
+#define DMA2_IT_HT3 ((uint32_t)0x10000400)
+#define DMA2_IT_TE3 ((uint32_t)0x10000800)
+#define DMA2_IT_GL4 ((uint32_t)0x10001000)
+#define DMA2_IT_TC4 ((uint32_t)0x10002000)
+#define DMA2_IT_HT4 ((uint32_t)0x10004000)
+#define DMA2_IT_TE4 ((uint32_t)0x10008000)
+#define DMA2_IT_GL5 ((uint32_t)0x10010000)
+#define DMA2_IT_TC5 ((uint32_t)0x10020000)
+#define DMA2_IT_HT5 ((uint32_t)0x10040000)
+#define DMA2_IT_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_IT(IT) (((((IT) & 0xF0000000) == 0x00) || (((IT) & 0xEFF00000) == 0x00)) && ((IT) != 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
+ ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
+ ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
+ ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
+ ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
+ ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
+ ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
+ ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
+ ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
+ ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5) || \
+ ((IT) == DMA1_IT_GL6) || ((IT) == DMA1_IT_TC6) || \
+ ((IT) == DMA1_IT_HT6) || ((IT) == DMA1_IT_TE6) || \
+ ((IT) == DMA1_IT_GL7) || ((IT) == DMA1_IT_TC7) || \
+ ((IT) == DMA1_IT_HT7) || ((IT) == DMA1_IT_TE7) || \
+ ((IT) == DMA2_IT_GL1) || ((IT) == DMA2_IT_TC1) || \
+ ((IT) == DMA2_IT_HT1) || ((IT) == DMA2_IT_TE1) || \
+ ((IT) == DMA2_IT_GL2) || ((IT) == DMA2_IT_TC2) || \
+ ((IT) == DMA2_IT_HT2) || ((IT) == DMA2_IT_TE2) || \
+ ((IT) == DMA2_IT_GL3) || ((IT) == DMA2_IT_TC3) || \
+ ((IT) == DMA2_IT_HT3) || ((IT) == DMA2_IT_TE3) || \
+ ((IT) == DMA2_IT_GL4) || ((IT) == DMA2_IT_TC4) || \
+ ((IT) == DMA2_IT_HT4) || ((IT) == DMA2_IT_TE4) || \
+ ((IT) == DMA2_IT_GL5) || ((IT) == DMA2_IT_TC5) || \
+ ((IT) == DMA2_IT_HT5) || ((IT) == DMA2_IT_TE5))
+
+/**
+ * @}
+ */
+
+/** @defgroup DMA_flags_definition
+ * @{
+ */
+
+#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
+#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
+#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
+#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
+#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
+#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
+#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
+#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
+#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
+#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
+#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
+#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
+#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
+#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
+#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
+#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
+#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
+#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
+#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
+#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
+#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
+#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
+#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
+#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
+#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
+#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
+#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
+#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
+
+#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
+#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
+#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
+#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
+#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
+#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
+#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
+#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
+#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
+#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
+#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
+#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
+#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
+#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
+#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
+#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
+#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
+#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
+#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
+#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) (((((FLAG) & 0xF0000000) == 0x00) || (((FLAG) & 0xEFF00000) == 0x00)) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
+ ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
+ ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
+ ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
+ ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
+ ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
+ ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
+ ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
+ ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
+ ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5) || \
+ ((FLAG) == DMA1_FLAG_GL6) || ((FLAG) == DMA1_FLAG_TC6) || \
+ ((FLAG) == DMA1_FLAG_HT6) || ((FLAG) == DMA1_FLAG_TE6) || \
+ ((FLAG) == DMA1_FLAG_GL7) || ((FLAG) == DMA1_FLAG_TC7) || \
+ ((FLAG) == DMA1_FLAG_HT7) || ((FLAG) == DMA1_FLAG_TE7) || \
+ ((FLAG) == DMA2_FLAG_GL1) || ((FLAG) == DMA2_FLAG_TC1) || \
+ ((FLAG) == DMA2_FLAG_HT1) || ((FLAG) == DMA2_FLAG_TE1) || \
+ ((FLAG) == DMA2_FLAG_GL2) || ((FLAG) == DMA2_FLAG_TC2) || \
+ ((FLAG) == DMA2_FLAG_HT2) || ((FLAG) == DMA2_FLAG_TE2) || \
+ ((FLAG) == DMA2_FLAG_GL3) || ((FLAG) == DMA2_FLAG_TC3) || \
+ ((FLAG) == DMA2_FLAG_HT3) || ((FLAG) == DMA2_FLAG_TE3) || \
+ ((FLAG) == DMA2_FLAG_GL4) || ((FLAG) == DMA2_FLAG_TC4) || \
+ ((FLAG) == DMA2_FLAG_HT4) || ((FLAG) == DMA2_FLAG_TE4) || \
+ ((FLAG) == DMA2_FLAG_GL5) || ((FLAG) == DMA2_FLAG_TC5) || \
+ ((FLAG) == DMA2_FLAG_HT5) || ((FLAG) == DMA2_FLAG_TE5))
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the DMA configuration to the default reset state ******/
+void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Channel_TypeDef* DMAy_Channelx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
+
+/* Data Counter functions******************************************************/
+void DMA_SetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx, uint16_t DataNumber);
+uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef* DMAy_Channelx);
+
+/* Interrupts and flags management functions **********************************/
+void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
+FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
+void DMA_ClearFlag(uint32_t DMAy_FLAG);
+ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
+void DMA_ClearITPendingBit(uint32_t DMAy_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_DMA_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_exti.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_exti.c
new file mode 100644
index 0000000000..4361afc971
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_exti.c
@@ -0,0 +1,359 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_exti.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the EXTI peripheral:
+ * + Initialization and Configuration
+ * + Interrupts and flags management
+ *
+ @verbatim
+ ===============================================================================
+ ##### EXTI features #####
+ ===============================================================================
+ [..] External interrupt/event lines are mapped as following:
+ (#) All available GPIO pins are connected to the 16 external
+ interrupt/event lines from EXTI0 to EXTI15.
+ (#) EXTI line 16 is connected to the PVD output
+ (#) EXTI line 17 is connected to the RTC Alarm event
+ (#) EXTI line 18 is connected to USB Device wakeup event
+ (#) EXTI line 19 is connected to the RTC Tamper and TimeStamp events
+ (#) EXTI line 20 is connected to the RTC wakeup event
+ (#) EXTI line 21 is connected to the Comparator 1 wakeup event
+ (#) EXTI line 22 is connected to the Comparator 2 wakeup event
+ (#) EXTI line 23 is connected to the I2C1 wakeup event
+ (#) EXTI line 24 is connected to the I2C2 wakeup event
+ (#) EXTI line 25 is connected to the USART1 wakeup event
+ (#) EXTI line 26 is connected to the USART2 wakeup event
+ (#) EXTI line 27 is reserved
+ (#) EXTI line 28 is connected to the USART3 wakeup event
+ (#) EXTI line 29 is connected to the Comparator 3 event
+ (#) EXTI line 30 is connected to the Comparator 4 event
+ (#) EXTI line 31 is connected to the Comparator 5 event
+ (#) EXTI line 32 is connected to the Comparator 6 event
+ (#) EXTI line 33 is connected to the Comparator 7 event
+ (#) EXTI line 34 is connected for thr UART4 wakeup event
+ (#) EXTI line 35 is connected for the UART5 wakeup event
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] In order to use an I/O pin as an external interrupt source,
+ follow steps below:
+ (#) Configure the I/O in input mode using GPIO_Init().
+ (#) Select the input source pin for the EXTI line using
+ SYSCFG_EXTILineConfig().
+ (#) Select the mode(interrupt, event) and configure the trigger
+ selection (Rising, falling or both) using EXTI_Init(). For the
+ internal interrupt, the trigger selection is not needed
+ (the active edge is always the rising one).
+ (#) Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init().
+ (#) Optionally, you can generate a software interrupt using the function
+ EXTI_GenerateSWInterrupt().
+ [..]
+ (@) SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+ registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_exti.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup EXTI
+ * @brief EXTI driver modules
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define EXTI_LINENONE ((uint32_t)0x00000) /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+ * @{
+ */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the EXTI peripheral registers to their default reset
+ * values.
+ * @param None
+ * @retval None
+ */
+void EXTI_DeInit(void)
+{
+ EXTI->IMR = 0x1F800000;
+ EXTI->EMR = 0x00000000;
+ EXTI->RTSR = 0x00000000;
+ EXTI->FTSR = 0x00000000;
+ EXTI->SWIER = 0x00000000;
+ EXTI->PR = 0xE07FFFFF;
+ EXTI->IMR2 = 0x0000000C;
+ EXTI->EMR2 = 0x00000000;
+ EXTI->RTSR2 = 0x00000000;
+ EXTI->FTSR2 = 0x00000000;
+ EXTI->SWIER2 = 0x00000000;
+ EXTI->PR2 = 0x00000003;
+}
+
+/**
+ * @brief Initializes the EXTI peripheral according to the specified
+ * parameters in the EXTI_InitStruct.
+ * EXTI_Line specifies the EXTI line (EXTI0....EXTI35).
+ * EXTI_Mode specifies which EXTI line is used as interrupt or an event.
+ * EXTI_Trigger selects the trigger. When the trigger occurs, interrupt
+ * pending bit will be set.
+ * EXTI_LineCmd controls (Enable/Disable) the EXTI line.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure that
+ * contains the configuration information for the EXTI peripheral.
+ * @retval None
+ */
+
+
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+ assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+ assert_param(IS_EXTI_LINE_ALL(EXTI_InitStruct->EXTI_Line));
+ assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+ {
+ /* Clear EXTI line configuration */
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->IMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->EMR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+
+ tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+ *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+
+ tmp = (uint32_t)EXTI_BASE;
+
+ /* Clear Rising Falling edge configuration */
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+
+ /* Select the trigger for the selected interrupts */
+ if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+ {
+ /* Rising Falling edge */
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->RTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->FTSR)) + ((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ }
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Trigger + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+ *(__IO uint32_t *) tmp |= (uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ }
+ }
+
+ else
+ {
+ tmp += EXTI_InitStruct->EXTI_Mode + (((EXTI_InitStruct->EXTI_Line) >> 5 ) * 0x20);
+
+ /* Disable the selected external lines */
+ *(__IO uint32_t *) tmp &= ~(uint32_t)(1 << (EXTI_InitStruct->EXTI_Line & 0x1F));
+ }
+
+}
+
+/**
+ * @brief Fills each EXTI_InitStruct member with its reset value.
+ * @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+ EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+ EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+ EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Rising_Falling;
+ EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+ * @brief Generates a Software interrupt on selected EXTI line.
+ * @param EXTI_Line: specifies the EXTI line on which the software interrupt
+ * will be generated.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval None
+ */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->SWIER)) + ((EXTI_Line) >> 5 ) * 0x20) |= (uint32_t)(1 << (EXTI_Line & 0x1F));
+
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ * @brief EXTI Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..]
+ This section provides functions allowing to configure the EXTI Interrupts
+ sources and check or clear the flags or pending bits status.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified EXTI line flag is set or not.
+ * @param EXTI_Line: specifies the EXTI line flag to check.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the EXTI's line pending flags.
+ * @param EXTI_Line: specifies the EXTI lines flags to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval None
+ */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
+}
+
+/**
+ * @brief Checks whether the specified EXTI line is asserted or not.
+ * @param EXTI_Line: specifies the EXTI line to check.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval The new state of EXTI_Line (SET or RESET).
+ */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+ ITStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+
+ if ((*(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20)& (uint32_t)(1 << (EXTI_Line & 0x1F))) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+
+}
+
+/**
+ * @brief Clears the EXTI's line pending bits.
+ * @param EXTI_Line: specifies the EXTI lines to clear.
+ * This parameter can be any combination of EXTI_Linex where x can be (0..20).
+ * @retval None
+ */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+ /* Check the parameters */
+ assert_param(IS_EXTI_LINE_EXT(EXTI_Line));
+
+ *(__IO uint32_t *) (((uint32_t) &(EXTI->PR)) + ((EXTI_Line) >> 5 ) * 0x20) = (1 << (EXTI_Line & 0x1F));
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_exti.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_exti.h
new file mode 100644
index 0000000000..66994fe359
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_exti.h
@@ -0,0 +1,244 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_exti.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the EXTI
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_EXTI_H
+#define __STM32F30x_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup EXTI
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief EXTI mode enumeration
+ */
+
+typedef enum
+{
+ EXTI_Mode_Interrupt = 0x00,
+ EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/**
+ * @brief EXTI Trigger enumeration
+ */
+
+typedef enum
+{
+ EXTI_Trigger_Rising = 0x08,
+ EXTI_Trigger_Falling = 0x0C,
+ EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+ ((TRIGGER) == EXTI_Trigger_Falling) || \
+ ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/**
+ * @brief EXTI Init Structure definition
+ */
+
+typedef struct
+{
+ uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
+ This parameter can be any combination of @ref EXTI_Lines */
+
+ EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.
+ This parameter can be a value of @ref EXTIMode_TypeDef */
+
+ EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+ This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+ FunctionalState EXTI_LineCmd; /*!< Specifies the new state of the selected EXTI lines.
+ This parameter can be set either to ENABLE or DISABLE */
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+ * @{
+ */
+/** @defgroup EXTI_Lines
+ * @{
+ */
+
+#define EXTI_Line0 ((uint32_t)0x00) /*!< External interrupt line 0 */
+#define EXTI_Line1 ((uint32_t)0x01) /*!< External interrupt line 1 */
+#define EXTI_Line2 ((uint32_t)0x02) /*!< External interrupt line 2 */
+#define EXTI_Line3 ((uint32_t)0x03) /*!< External interrupt line 3 */
+#define EXTI_Line4 ((uint32_t)0x04) /*!< External interrupt line 4 */
+#define EXTI_Line5 ((uint32_t)0x05) /*!< External interrupt line 5 */
+#define EXTI_Line6 ((uint32_t)0x06) /*!< External interrupt line 6 */
+#define EXTI_Line7 ((uint32_t)0x07) /*!< External interrupt line 7 */
+#define EXTI_Line8 ((uint32_t)0x08) /*!< External interrupt line 8 */
+#define EXTI_Line9 ((uint32_t)0x09) /*!< External interrupt line 9 */
+#define EXTI_Line10 ((uint32_t)0x0A) /*!< External interrupt line 10 */
+#define EXTI_Line11 ((uint32_t)0x0B) /*!< External interrupt line 11 */
+#define EXTI_Line12 ((uint32_t)0x0C) /*!< External interrupt line 12 */
+#define EXTI_Line13 ((uint32_t)0x0D) /*!< External interrupt line 13 */
+#define EXTI_Line14 ((uint32_t)0x0E) /*!< External interrupt line 14 */
+#define EXTI_Line15 ((uint32_t)0x0F) /*!< External interrupt line 15 */
+#define EXTI_Line16 ((uint32_t)0x10) /*!< External interrupt line 16
+ Connected to the PVD Output */
+#define EXTI_Line17 ((uint32_t)0x11) /*!< Internal interrupt line 17
+ Connected to the RTC Alarm
+ event */
+#define EXTI_Line18 ((uint32_t)0x12) /*!< Internal interrupt line 18
+ Connected to the USB Device
+ Wakeup from suspend event */
+#define EXTI_Line19 ((uint32_t)0x13) /*!< Internal interrupt line 19
+ Connected to the RTC Tamper
+ and Time Stamp events */
+#define EXTI_Line20 ((uint32_t)0x14) /*!< Internal interrupt line 20
+ Connected to the RTC wakeup
+ event */
+#define EXTI_Line21 ((uint32_t)0x15) /*!< Internal interrupt line 21
+ Connected to the Comparator 1
+ event */
+#define EXTI_Line22 ((uint32_t)0x16) /*!< Internal interrupt line 22
+ Connected to the Comparator 2
+ event */
+#define EXTI_Line23 ((uint32_t)0x17) /*!< Internal interrupt line 23
+ Connected to the I2C1 wakeup
+ event */
+#define EXTI_Line24 ((uint32_t)0x18) /*!< Internal interrupt line 24
+ Connected to the I2C2 wakeup
+ event */
+#define EXTI_Line25 ((uint32_t)0x19) /*!< Internal interrupt line 25
+ Connected to the USART1 wakeup
+ event */
+#define EXTI_Line26 ((uint32_t)0x1A) /*!< Internal interrupt line 26
+ Connected to the USART2 wakeup
+ event */
+#define EXTI_Line27 ((uint32_t)0x1B) /*!< Internal interrupt line 27
+ reserved */
+#define EXTI_Line28 ((uint32_t)0x1C) /*!< Internal interrupt line 28
+ Connected to the USART3 wakeup
+ event */
+#define EXTI_Line29 ((uint32_t)0x1D) /*!< Internal interrupt line 29
+ Connected to the Comparator 3
+ event */
+#define EXTI_Line30 ((uint32_t)0x1E) /*!< Internal interrupt line 30
+ Connected to the Comparator 4
+ event */
+#define EXTI_Line31 ((uint32_t)0x1F) /*!< Internal interrupt line 31
+ Connected to the Comparator 5
+ event */
+#define EXTI_Line32 ((uint32_t)0x20) /*!< Internal interrupt line 32
+ Connected to the Comparator 6
+ event */
+#define EXTI_Line33 ((uint32_t)0x21) /*!< Internal interrupt line 33
+ Connected to the Comparator 7
+ event */
+#define EXTI_Line34 ((uint32_t)0x22) /*!< Internal interrupt line 34
+ Connected to the USART4 wakeup
+ event */
+#define EXTI_Line35 ((uint32_t)0x23) /*!< Internal interrupt line 35
+ Connected to the USART5 wakeup
+ event */
+
+#define IS_EXTI_LINE_ALL(LINE) ((LINE) <= 0x23)
+#define IS_EXTI_LINE_EXT(LINE) (((LINE) <= 0x16) || (((LINE) == EXTI_Line29) || ((LINE) == EXTI_Line30) || \
+ ((LINE) == EXTI_Line31) || ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33)))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+ ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+ ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+ ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+ ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+ ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+ ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+ ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+ ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+ ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+ ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) || \
+ ((LINE) == EXTI_Line22) || ((LINE) == EXTI_Line29) || \
+ ((LINE) == EXTI_Line30) || ((LINE) == EXTI_Line31) || \
+ ((LINE) == EXTI_Line32) || ((LINE) == EXTI_Line33))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_EXTI_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_flash.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_flash.c
new file mode 100644
index 0000000000..4058b9f2c5
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_flash.c
@@ -0,0 +1,1180 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_flash.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the FLASH peripheral:
+ * + FLASH Interface configuration
+ * + FLASH Memory Programming
+ * + Option Bytes Programming
+ * + Interrupts and flags management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] This driver provides functions to configure and program the FLASH
+ memory of all STM32F30x devices. These functions are split in 4 groups:
+ (#) FLASH Interface configuration functions: this group includes the
+ management of following features:
+ (++) Set the latency.
+ (++) Enable/Disable the Half Cycle Access.
+ (++) Enable/Disable the prefetch buffer.
+ (#) FLASH Memory Programming functions: this group includes all needed
+ functions to erase and program the main memory:
+ (++) Lock and Unlock the FLASH interface.
+ (++) Erase function: Erase page, erase all pages.
+ (++) Program functions: Half Word and Word write.
+ (#) FLASH Option Bytes Programming functions: this group includes all
+ needed functions to manage the Option Bytes:
+ (++) Lock and Unlock the Flash Option bytes.
+ (++) Launch the Option Bytes loader
+ (++) Erase the Option Bytes
+ (++) Set/Reset the write protection
+ (++) Set the Read protection Level
+ (++) Program the user option Bytes
+ (++) Set/Reset the BOOT1 bit
+ (++) Enable/Disable the VDDA Analog Monitoring
+ (++) Enable/Disable the SRAM parity
+ (++) Get the user option bytes
+ (++) Get the Write protection
+ (++) Get the read protection status
+ (#) FLASH Interrupts and flags management functions: this group includes
+ all needed functions to:
+ (++) Enable/Disable the FLASH interrupt sources.
+ (++) Get flags status.
+ (++) Clear flags.
+ (++) Get FLASH operation status.
+ (++) Wait for last FLASH operation.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_flash.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup FLASH
+ * @brief FLASH driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* FLASH Mask */
+#define RDPRT_MASK ((uint32_t)0x00000002)
+#define WRP01_MASK ((uint32_t)0x0000FFFF)
+#define WRP23_MASK ((uint32_t)0xFFFF0000)
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Private_Functions
+ * @{
+ */
+
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
+ * @brief FLASH Interface configuration functions
+ *
+
+@verbatim
+ ===============================================================================
+ ##### FLASH Interface configuration functions #####
+ ===============================================================================
+ [..] This group includes the following functions:
+ (+) void FLASH_SetLatency(uint32_t FLASH_Latency);
+ (+) void FLASH_HalfCycleAccessCmd(uint32_t FLASH_HalfCycleAccess);
+ (+) void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+ [..] The unlock sequence is not needed for these functions.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sets the code latency value.
+ * @param FLASH_Latency: specifies the FLASH Latency value.
+ * This parameter can be one of the following values:
+ * @arg FLASH_Latency_0: FLASH Zero Latency cycle
+ * @arg FLASH_Latency_1: FLASH One Latency cycle
+ * @arg FLASH_Latency_2: FLASH Two Latency cycles
+ * @retval None
+ */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+
+ /* Read the ACR register */
+ tmpreg = FLASH->ACR;
+
+ /* Sets the Latency value */
+ tmpreg &= (uint32_t) (~((uint32_t)FLASH_ACR_LATENCY));
+ tmpreg |= FLASH_Latency;
+
+ /* Write the ACR register */
+ FLASH->ACR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the Half cycle flash access.
+ * @param FLASH_HalfCycleAccess: specifies the FLASH Half cycle Access mode.
+ * This parameter can be one of the following values:
+ * @arg FLASH_HalfCycleAccess_Enable: FLASH Half Cycle Enable
+ * @arg FLASH_HalfCycleAccess_Disable: FLASH Half Cycle Disable
+ * @retval None
+ */
+void FLASH_HalfCycleAccessCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ FLASH->ACR |= FLASH_ACR_HLFCYA;
+ }
+ else
+ {
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_HLFCYA));
+ }
+}
+
+/**
+ * @brief Enables or disables the Prefetch Buffer.
+ * @param NewState: new state of the Prefetch Buffer.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ FLASH->ACR |= FLASH_ACR_PRFTBE;
+ }
+ else
+ {
+ FLASH->ACR &= (uint32_t)(~((uint32_t)FLASH_ACR_PRFTBE));
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ * @brief FLASH Memory Programming functions
+ *
+@verbatim
+ ===============================================================================
+ ##### FLASH Memory Programming functions #####
+ ===============================================================================
+ [..] This group includes the following functions:
+ (+) void FLASH_Unlock(void);
+ (+) void FLASH_Lock(void);
+ (+) FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+ (+) FLASH_Status FLASH_EraseAllPages(void);
+ (+) FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+ (+) FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the FLASH_Unlock() function to enable the FLASH control register
+ program memory access.
+ (#) Call the desired function to erase page or program data.
+ (#) Call the FLASH_Lock() function to disable the FLASH control register
+ access (recommended to protect the FLASH memory against possible
+ unwanted operation).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlocks the FLASH control register access
+ * @param None
+ * @retval None
+ */
+void FLASH_Unlock(void)
+{
+ if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+ {
+ /* Authorize the FLASH Registers access */
+ FLASH->KEYR = FLASH_KEY1;
+ FLASH->KEYR = FLASH_KEY2;
+ }
+}
+
+/**
+ * @brief Locks the FLASH control register access
+ * @param None
+ * @retval None
+ */
+void FLASH_Lock(void)
+{
+ /* Set the LOCK Bit to lock the FLASH Registers access */
+ FLASH->CR |= FLASH_CR_LOCK;
+}
+
+/**
+ * @brief Erases a specified page in program memory.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Page_Address: The page address in program memory to be erased.
+ * @note A Page is erased in the Program memory only if the address to load
+ * is the start address of a page (multiple of 1024 bytes).
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Page_Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to erase the page */
+ FLASH->CR |= FLASH_CR_PER;
+ FLASH->AR = Page_Address;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the PER Bit */
+ FLASH->CR &= ~FLASH_CR_PER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Erases all FLASH pages.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * all the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_EraseAllPages(void)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* if the previous operation is completed, proceed to erase all pages */
+ FLASH->CR |= FLASH_CR_MER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the MER Bit */
+ FLASH->CR &= ~FLASH_CR_MER;
+ }
+
+ /* Return the Erase Status */
+ return status;
+}
+
+/**
+ * @brief Programs a word at a specified address.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * Call the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to program the new first
+ half word */
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint16_t*)Address = (uint16_t)Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to program the new second
+ half word */
+ tmp = Address + 2;
+
+ *(__IO uint16_t*) tmp = Data >> 16;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+ else
+ {
+ /* Disable the PG Bit */
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @brief Programs a half word at a specified address.
+ * @note To correctly run this function, the FLASH_Unlock() function
+ * must be called before.
+ * Call the FLASH_Lock() to disable the flash memory access
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Address: specifies the address to be programmed.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to program the new data */
+ FLASH->CR |= FLASH_CR_PG;
+
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ /* Disable the PG Bit */
+ FLASH->CR &= ~FLASH_CR_PG;
+ }
+
+ /* Return the Program Status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
+ * @brief Option Bytes Programming functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Option Bytes Programming functions #####
+ ===============================================================================
+ [..] This group includes the following functions:
+ (+) void FLASH_OB_Unlock(void);
+ (+) void FLASH_OB_Lock(void);
+ (+) void FLASH_OB_Erase(void);
+ (+) FLASH_Status FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+ (+) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+ (+) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+ (+) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+ (+) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+ (+) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
+ (+) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+ (+) FLASH_Status FLASH_OB_Launch(void);
+ (+) uint32_t FLASH_OB_GetUser(void);
+ (+) uint8_t FLASH_OB_GetWRP(void);
+ (+) uint8_t FLASH_OB_GetRDP(void);
+ [..] Any operation of erase or program should follow these steps:
+ (#) Call the FLASH_OB_Unlock() function to enable the FLASH option control
+ register access.
+ (#) Call one or several functions to program the desired Option Bytes:
+ (++) void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+ => to Enable/Disable the desired sector write protection.
+ (++) FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the
+ desired read Protection Level.
+ (++) FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+ => to configure the user Option Bytes.
+ (++) FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+ => to set the boot1 mode
+ (++) FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+ => to Enable/Disable the VDDA monotoring.
+ (++) FLASH_Status FLASH_OB_SRMParityConfig(uint8_t OB_SRAM_Parity);
+ => to Enable/Disable the SRAM Parity check.
+ (++) FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+ => to write all user option bytes: OB_IWDG, OB_STOP, OB_STDBY,
+ OB_BOOT1, OB_VDDA_ANALOG and OB_VDD_SD12.
+ (#) Once all needed Option Bytes to be programmed are correctly written,
+ call the FLASH_OB_Launch() function to launch the Option Bytes
+ programming process.
+ (#@) When changing the IWDG mode from HW to SW or from SW to HW, a system
+ reset is needed to make the change effective.
+ (#) Call the FLASH_OB_Lock() function to disable the FLASH option control
+ register access (recommended to protect the Option Bytes against
+ possible unwanted operations).
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Unlocks the option bytes block access.
+ * @param None
+ * @retval None
+ */
+void FLASH_OB_Unlock(void)
+{
+ if((FLASH->CR & FLASH_CR_OPTWRE) == RESET)
+ {
+ /* Unlocking the option bytes block access */
+ FLASH->OPTKEYR = FLASH_OPTKEY1;
+ FLASH->OPTKEYR = FLASH_OPTKEY2;
+ }
+}
+
+/**
+ * @brief Locks the option bytes block access.
+ * @param None
+ * @retval None
+ */
+void FLASH_OB_Lock(void)
+{
+ /* Set the OPTWREN Bit to lock the option bytes block access */
+ FLASH->CR &= ~FLASH_CR_OPTWRE;
+}
+
+/**
+ * @brief Launch the option byte loading.
+ * @param None
+ * @retval None
+ */
+void FLASH_OB_Launch(void)
+{
+ /* Set the OBL_Launch bit to launch the option byte loading */
+ FLASH->CR |= FLASH_CR_OBL_LAUNCH;
+}
+
+/**
+ * @brief Erases the FLASH option bytes.
+ * @note This functions erases all option bytes except the Read protection (RDP).
+ * @param None
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_Erase(void)
+{
+ uint16_t rdptmp = OB_RDP_Level_0;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Get the actual read protection Option Byte value */
+ if(FLASH_OB_GetRDP() != RESET)
+ {
+ rdptmp = 0x00;
+ }
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the previous operation is completed, proceed to erase the option bytes */
+ FLASH->CR |= FLASH_CR_OPTER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= ~FLASH_CR_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ /* Restore the last read protection Option Byte value */
+ OB->RDP = (uint16_t)rdptmp;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ else
+ {
+ if (status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ }
+ /* Return the erase status */
+ return status;
+}
+
+/**
+ * @brief Write protects the desired pages
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param OB_WRP: specifies the address of the pages to be write protected.
+ * This parameter can be:
+ * @arg value between OB_WRP_Pages0to35 and OB_WRP_Pages60to63
+ * @arg OB_WRP_AllPages
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP)
+{
+ uint16_t WRP0_Data = 0xFFFF, WRP1_Data = 0xFFFF;
+
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_WRP(OB_WRP));
+
+ OB_WRP = (uint32_t)(~OB_WRP);
+ WRP0_Data = (uint16_t)(OB_WRP & OB_WRP0_WRP0);
+ WRP1_Data = (uint16_t)((OB_WRP & OB_WRP0_nWRP0) >> 8);
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ if(WRP0_Data != 0xFF)
+ {
+ OB->WRP0 = WRP0_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ }
+ if((status == FLASH_COMPLETE) && (WRP1_Data != 0xFF))
+ {
+ OB->WRP1 = WRP1_Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+ }
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the write protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Enables or disables the read out protection.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param FLASH_ReadProtection_Level: specifies the read protection level.
+ * This parameter can be:
+ * @arg OB_RDP_Level_0: No protection
+ * @arg OB_RDP_Level_1: Read protection of the memory
+ * @arg OB_RDP_Level_2: Chip protection
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_RDP(OB_RDP));
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ FLASH->CR |= FLASH_CR_OPTER;
+ FLASH->CR |= FLASH_CR_STRT;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* If the erase operation is completed, disable the OPTER Bit */
+ FLASH->CR &= ~FLASH_CR_OPTER;
+
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->RDP = OB_RDP;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ else
+ {
+ if(status != FLASH_TIMEOUT)
+ {
+ /* Disable the OPTER Bit */
+ FLASH->CR &= ~FLASH_CR_OPTER;
+ }
+ }
+ }
+ /* Return the protection operation Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
+ * @param OB_IWDG: Selects the IWDG mode
+ * This parameter can be one of the following values:
+ * @arg OB_IWDG_SW: Software IWDG selected
+ * @arg OB_IWDG_HW: Hardware IWDG selected
+ * @param OB_STOP: Reset event when entering STOP mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STOP_NoRST: No reset generated when entering in STOP
+ * @arg OB_STOP_RST: Reset generated when entering in STOP
+ * @param OB_STDBY: Reset event when entering Standby mode.
+ * This parameter can be one of the following values:
+ * @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+ * @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+ assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+ assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = (uint8_t)((uint8_t)(OB_IWDG | OB_STOP) | (uint8_t)(OB_STDBY |0xF8));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the BOOT1.
+ * @param OB_BOOT1: Set or Reset the BOOT1.
+ * This parameter can be one of the following values:
+ * @arg OB_BOOT1_RESET: BOOT1 Reset
+ * @arg OB_BOOT1_SET: BOOT1 Set
+ * @retval None
+ */
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_BOOT1(OB_BOOT1));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_BOOT1|0xEF;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the analogue monitoring on VDDA Power source.
+ * @param OB_VDDA_ANALOG: Selects the analog monitoring on VDDA Power source.
+ * This parameter can be one of the following values:
+ * @arg OB_VDDA_ANALOG_ON: Analog monitoring on VDDA Power source ON
+ * @arg OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source OFF
+ * @retval None
+ */
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_VDDA_ANALOG(OB_VDDA_ANALOG));
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_VDDA_ANALOG |0xDF;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Sets or resets the SRAM partiy.
+ * @param OB_SRAM_Parity: Set or Reset the SRAM partiy enable bit.
+ * This parameter can be one of the following values:
+ * @arg OB_SRAM_PARITY_SET: Set SRAM partiy.
+ * @arg OB_SRAM_PARITY_RESET: Reset SRAM partiy.
+ * @retval None
+ */
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check the parameters */
+ assert_param(IS_OB_SRAM_PARITY(OB_SRAM_Parity));
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_SRAM_Parity | 0xBF;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+}
+
+/**
+ * @brief Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY/ BOOT1 and OB_VDDA_ANALOG.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * @note Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param OB_USER: Selects all user option bytes
+ * This parameter is a combination of the following values:
+ * @arg OB_IWDG_SW / OB_IWDG_HW: Software / Hardware WDG selected
+ * @arg OB_STOP_NoRST / OB_STOP_RST: No reset / Reset generated when entering in STOP
+ * @arg OB_STDBY_NoRST / OB_STDBY_RST: No reset / Reset generated when entering in STANDBY
+ * @arg OB_BOOT1_RESET / OB_BOOT1_SET: BOOT1 Reset / Set
+ * @arg OB_VDDA_ANALOG_ON / OB_VDDA_ANALOG_OFF: Analog monitoring on VDDA Power source ON / OFF
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Authorize the small information block programming */
+ FLASH->OPTKEYR = FLASH_KEY1;
+ FLASH->OPTKEYR = FLASH_KEY2;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enable the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+
+ OB->USER = OB_USER | 0x88;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* if the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte program Status */
+ return status;
+
+}
+
+/**
+ * @brief Programs a half word at a specified Option Byte Data address.
+ * @note To correctly run this function, the FLASH_OB_Unlock() function
+ * must be called before.
+ * Call the FLASH_OB_Lock() to disable the flash control register access and the option bytes
+ * (recommended to protect the FLASH memory against possible unwanted operation)
+ * @param Address: specifies the address to be programmed.
+ * This parameter can be 0x1FFFF804 or 0x1FFFF806.
+ * @param Data: specifies the data to be programmed.
+ * @retval FLASH Status: The returned value can be: FLASH_ERROR_PG,
+ * FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+ /* Check the parameters */
+ assert_param(IS_OB_DATA_ADDRESS(Address));
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status == FLASH_COMPLETE)
+ {
+ /* Enables the Option Bytes Programming operation */
+ FLASH->CR |= FLASH_CR_OPTPG;
+ *(__IO uint16_t*)Address = Data;
+
+ /* Wait for last operation to be completed */
+ status = FLASH_WaitForLastOperation(FLASH_ER_PRG_TIMEOUT);
+
+ if(status != FLASH_TIMEOUT)
+ {
+ /* If the program operation is completed, disable the OPTPG Bit */
+ FLASH->CR &= ~FLASH_CR_OPTPG;
+ }
+ }
+ /* Return the Option Byte Data Program Status */
+ return status;
+}
+
+/**
+ * @brief Returns the FLASH User Option Bytes values.
+ * @param None
+ * @retval The FLASH User Option Bytes .
+ */
+uint8_t FLASH_OB_GetUser(void)
+{
+ /* Return the User Option Byte */
+ return (uint8_t)(FLASH->OBR >> 8);
+}
+
+/**
+ * @brief Returns the FLASH Write Protection Option Bytes value.
+ * @param None
+ * @retval The FLASH Write Protection Option Bytes value
+ */
+uint32_t FLASH_OB_GetWRP(void)
+{
+ /* Return the FLASH write protection Register value */
+ return (uint32_t)(FLASH->WRPR);
+}
+
+/**
+ * @brief Checks whether the FLASH Read out Protection Status is set or not.
+ * @param None
+ * @retval FLASH ReadOut Protection Status(SET or RESET)
+ */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+ FlagStatus readstatus = RESET;
+
+ if ((uint8_t)(FLASH->OBR & (FLASH_OBR_RDPRT1 | FLASH_OBR_RDPRT2)) != RESET)
+ {
+ readstatus = SET;
+ }
+ else
+ {
+ readstatus = RESET;
+ }
+ return readstatus;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the specified FLASH interrupts.
+ * @param FLASH_IT: specifies the FLASH interrupt sources to be enabled or
+ * disabled.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_IT_EOP: FLASH end of programming Interrupt
+ * @arg FLASH_IT_ERR: FLASH Error Interrupt
+ * @retval None
+ */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_IT(FLASH_IT));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if(NewState != DISABLE)
+ {
+ /* Enable the interrupt sources */
+ FLASH->CR |= FLASH_IT;
+ }
+ else
+ {
+ /* Disable the interrupt sources */
+ FLASH->CR &= ~(uint32_t)FLASH_IT;
+ }
+}
+
+/**
+ * @brief Checks whether the specified FLASH flag is set or not.
+ * @param FLASH_FLAG: specifies the FLASH flag to check.
+ * This parameter can be one of the following values:
+ * @arg FLASH_FLAG_BSY: FLASH write/erase operations in progress flag
+ * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+ * @retval The new state of FLASH_FLAG (SET or RESET).
+ */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+ if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the new state of FLASH_FLAG (SET or RESET) */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the FLASH's pending flags.
+ * @param FLASH_FLAG: specifies the FLASH flags to clear.
+ * This parameter can be any combination of the following values:
+ * @arg FLASH_FLAG_PGERR: FLASH Programming error flag flag
+ * @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag
+ * @arg FLASH_FLAG_EOP: FLASH End of Programming flag
+ * @retval None
+ */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+
+ /* Clear the flags */
+ FLASH->SR = FLASH_FLAG;
+}
+
+/**
+ * @brief Returns the FLASH Status.
+ * @param None
+ * @retval FLASH Status: The returned value can be:
+ * FLASH_BUSY, FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP or FLASH_COMPLETE.
+ */
+FLASH_Status FLASH_GetStatus(void)
+{
+ FLASH_Status FLASHstatus = FLASH_COMPLETE;
+
+ if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY)
+ {
+ FLASHstatus = FLASH_BUSY;
+ }
+ else
+ {
+ if((FLASH->SR & (uint32_t)FLASH_FLAG_WRPERR)!= (uint32_t)0x00)
+ {
+ FLASHstatus = FLASH_ERROR_WRP;
+ }
+ else
+ {
+ if((FLASH->SR & (uint32_t)(FLASH_SR_PGERR)) != (uint32_t)0x00)
+ {
+ FLASHstatus = FLASH_ERROR_PROGRAM;
+ }
+ else
+ {
+ FLASHstatus = FLASH_COMPLETE;
+ }
+ }
+ }
+ /* Return the FLASH Status */
+ return FLASHstatus;
+}
+
+/**
+ * @brief Waits for a FLASH operation to complete or a TIMEOUT to occur.
+ * @param Timeout: FLASH programming Timeout
+ * @retval FLASH Status: The returned value can be: FLASH_BUSY,
+ * FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
+ */
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout)
+{
+ FLASH_Status status = FLASH_COMPLETE;
+
+ /* Check for the FLASH Status */
+ status = FLASH_GetStatus();
+
+ /* Wait for a FLASH operation to complete or a TIMEOUT to occur */
+ while((status == FLASH_BUSY) && (Timeout != 0x00))
+ {
+ status = FLASH_GetStatus();
+ Timeout--;
+ }
+
+ if(Timeout == 0x00 )
+ {
+ status = FLASH_TIMEOUT;
+ }
+ /* Return the operation status */
+ return status;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_flash.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_flash.h
new file mode 100644
index 0000000000..e2728a677c
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_flash.h
@@ -0,0 +1,339 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_flash.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the FLASH
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_FLASH_H
+#define __STM32F30x_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup FLASH
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/**
+ * @brief FLASH Status
+ */
+typedef enum
+{
+ FLASH_BUSY = 1,
+ FLASH_ERROR_WRP,
+ FLASH_ERROR_PROGRAM,
+ FLASH_COMPLETE,
+ FLASH_TIMEOUT
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+ * @{
+ */
+
+/** @defgroup Flash_Latency
+ * @{
+ */
+#define FLASH_Latency_0 ((uint8_t)0x0000) /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1 FLASH_ACR_LATENCY_0 /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2 FLASH_ACR_LATENCY_1 /*!< FLASH Two Latency cycles */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+ ((LATENCY) == FLASH_Latency_1) || \
+ ((LATENCY) == FLASH_Latency_2))
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Interrupts
+ * @{
+ */
+
+#define FLASH_IT_EOP FLASH_CR_EOPIE /*!< End of programming interrupt source */
+#define FLASH_IT_ERR FLASH_CR_ERRIE /*!< Error interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFFFFEBFF) == 0x00000000) && (((IT) != 0x00000000)))
+/**
+ * @}
+ */
+/** @defgroup FLASH_Address
+ * @{
+ */
+
+#define IS_FLASH_PROGRAM_ADDRESS(ADDRESS) (((ADDRESS) >= 0x08000000) && ((ADDRESS) <= 0x0803FFFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_OB_DATA_ADDRESS
+ * @{
+ */
+#define IS_OB_DATA_ADDRESS(ADDRESS) (((ADDRESS) == 0x1FFFF804) || ((ADDRESS) == 0x1FFFF806))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Write_Protection
+ * @{
+ */
+
+#define OB_WRP_Pages0to1 ((uint32_t)0x00000001) /* Write protection of page 0 to 1 */
+#define OB_WRP_Pages2to3 ((uint32_t)0x00000002) /* Write protection of page 2 to 3 */
+#define OB_WRP_Pages4to5 ((uint32_t)0x00000004) /* Write protection of page 4 to 5 */
+#define OB_WRP_Pages6to7 ((uint32_t)0x00000008) /* Write protection of page 6 to 7 */
+#define OB_WRP_Pages8to9 ((uint32_t)0x00000010) /* Write protection of page 8 to 9 */
+#define OB_WRP_Pages10to11 ((uint32_t)0x00000020) /* Write protection of page 10 to 11 */
+#define OB_WRP_Pages12to13 ((uint32_t)0x00000040) /* Write protection of page 12 to 13 */
+#define OB_WRP_Pages14to15 ((uint32_t)0x00000080) /* Write protection of page 14 to 15 */
+#define OB_WRP_Pages16to17 ((uint32_t)0x00000100) /* Write protection of page 16 to 17 */
+#define OB_WRP_Pages18to19 ((uint32_t)0x00000200) /* Write protection of page 18 to 19 */
+#define OB_WRP_Pages20to21 ((uint32_t)0x00000400) /* Write protection of page 20 to 21 */
+#define OB_WRP_Pages22to23 ((uint32_t)0x00000800) /* Write protection of page 22 to 23 */
+#define OB_WRP_Pages24to25 ((uint32_t)0x00001000) /* Write protection of page 24 to 25 */
+#define OB_WRP_Pages26to27 ((uint32_t)0x00002000) /* Write protection of page 26 to 27 */
+#define OB_WRP_Pages28to29 ((uint32_t)0x00004000) /* Write protection of page 28 to 29 */
+#define OB_WRP_Pages30to31 ((uint32_t)0x00008000) /* Write protection of page 30 to 31 */
+#define OB_WRP_Pages32to33 ((uint32_t)0x00010000) /* Write protection of page 32 to 33 */
+#define OB_WRP_Pages34to35 ((uint32_t)0x00020000) /* Write protection of page 34 to 35 */
+#define OB_WRP_Pages36to37 ((uint32_t)0x00040000) /* Write protection of page 36 to 37 */
+#define OB_WRP_Pages38to39 ((uint32_t)0x00080000) /* Write protection of page 38 to 39 */
+#define OB_WRP_Pages40to41 ((uint32_t)0x00100000) /* Write protection of page 40 to 41 */
+#define OB_WRP_Pages42to43 ((uint32_t)0x00200000) /* Write protection of page 42 to 43 */
+#define OB_WRP_Pages44to45 ((uint32_t)0x00400000) /* Write protection of page 44 to 45 */
+#define OB_WRP_Pages46to47 ((uint32_t)0x00800000) /* Write protection of page 46 to 47 */
+#define OB_WRP_Pages48to49 ((uint32_t)0x01000000) /* Write protection of page 48 to 49 */
+#define OB_WRP_Pages50to51 ((uint32_t)0x02000000) /* Write protection of page 50 to 51 */
+#define OB_WRP_Pages52to53 ((uint32_t)0x04000000) /* Write protection of page 52 to 53 */
+#define OB_WRP_Pages54to55 ((uint32_t)0x08000000) /* Write protection of page 54 to 55 */
+#define OB_WRP_Pages56to57 ((uint32_t)0x10000000) /* Write protection of page 56 to 57 */
+#define OB_WRP_Pages58to59 ((uint32_t)0x20000000) /* Write protection of page 58 to 59 */
+#define OB_WRP_Pages60to61 ((uint32_t)0x40000000) /* Write protection of page 60 to 61 */
+#define OB_WRP_Pages62to127 ((uint32_t)0x80000000) /* Write protection of page 62 to 127 */
+
+#define OB_WRP_AllPages ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(PAGE) (((PAGE) != 0x0000000))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_Read_Protection
+ * @{
+ */
+
+/**
+ * @brief Read Protection Level
+ */
+#define OB_RDP_Level_0 ((uint8_t)0xAA)
+#define OB_RDP_Level_1 ((uint8_t)0xBB)
+/*#define OB_RDP_Level_2 ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2
+ it's no more possible to go back to level 1 or 0 */
+
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+ ((LEVEL) == OB_RDP_Level_1))/*||\
+ ((LEVEL) == OB_RDP_Level_2))*/
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_IWatchdog
+ * @{
+ */
+
+#define OB_IWDG_SW ((uint8_t)0x01) /*!< Software IWDG selected */
+#define OB_IWDG_HW ((uint8_t)0x00) /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STOP
+ * @{
+ */
+
+#define OB_STOP_NoRST ((uint8_t)0x02) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+
+/**
+ * @}
+ */
+
+/** @defgroup Option_Bytes_nRST_STDBY
+ * @{
+ */
+
+#define OB_STDBY_NoRST ((uint8_t)0x04) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_BOOT1
+ * @{
+ */
+
+#define OB_BOOT1_RESET ((uint8_t)0x00) /*!< BOOT1 Reset */
+#define OB_BOOT1_SET ((uint8_t)0x10) /*!< BOOT1 Set */
+#define IS_OB_BOOT1(BOOT1) (((BOOT1) == OB_BOOT1_RESET) || ((BOOT1) == OB_BOOT1_SET))
+
+/**
+ * @}
+ */
+/** @defgroup Option_Bytes_VDDA_Analog_Monitoring
+ * @{
+ */
+
+#define OB_VDDA_ANALOG_ON ((uint8_t)0x20) /*!< Analog monitoring on VDDA Power source ON */
+#define OB_VDDA_ANALOG_OFF ((uint8_t)0x00) /*!< Analog monitoring on VDDA Power source OFF */
+
+#define IS_OB_VDDA_ANALOG(ANALOG) (((ANALOG) == OB_VDDA_ANALOG_ON) || ((ANALOG) == OB_VDDA_ANALOG_OFF))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Option_Bytes_SRAM_Parity_Enable
+ * @{
+ */
+
+#define OB_SRAM_PARITY_SET ((uint8_t)0x00) /*!< SRAM parity enable Set */
+#define OB_SRAM_PARITY_RESET ((uint8_t)0x40) /*!< SRAM parity enable reset */
+
+#define IS_OB_SRAM_PARITY(PARITY) (((PARITY) == OB_SRAM_PARITY_SET) || ((PARITY) == OB_SRAM_PARITY_RESET))
+
+/**
+ * @}
+ */
+
+/** @defgroup FLASH_Flags
+ * @{
+ */
+
+#define FLASH_FLAG_BSY FLASH_SR_BSY /*!< FLASH Busy flag */
+#define FLASH_FLAG_PGERR FLASH_SR_PGERR /*!< FLASH Programming error flag */
+#define FLASH_FLAG_WRPERR FLASH_SR_WRPERR /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_EOP FLASH_SR_EOP /*!< FLASH End of Programming flag */
+
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFCB) == 0x00000000) && ((FLAG) != 0x00000000))
+
+#define IS_FLASH_GET_FLAG(FLAG) (((FLAG) == FLASH_FLAG_BSY) || ((FLAG) == FLASH_FLAG_PGERR) || \
+ ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_EOP))
+/**
+ * @}
+ */
+/** @defgroup Timeout_definition
+ * @{
+ */
+#define FLASH_ER_PRG_TIMEOUT ((uint32_t)0x000B0000)
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_HalfCycleAccessCmd(FunctionalState NewState);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+
+/* FLASH Memory Programming functions *****************************************/
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
+FLASH_Status FLASH_EraseAllPages(void);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+
+/* Option Bytes Programming functions *****************************************/
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_Launch(void);
+FLASH_Status FLASH_OB_Erase(void);
+FLASH_Status FLASH_OB_EnableWRP(uint32_t OB_WRP);
+FLASH_Status FLASH_OB_RDPConfig(uint8_t OB_RDP);
+FLASH_Status FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+FLASH_Status FLASH_OB_BOOTConfig(uint8_t OB_BOOT1);
+FLASH_Status FLASH_OB_VDDAConfig(uint8_t OB_VDDA_ANALOG);
+FLASH_Status FLASH_OB_SRAMParityConfig(uint8_t OB_SRAM_Parity);
+FLASH_Status FLASH_OB_WriteUser(uint8_t OB_USER);
+FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
+uint8_t FLASH_OB_GetUser(void);
+uint32_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+
+/* Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_FLASH_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_gpio.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_gpio.c
new file mode 100644
index 0000000000..484d17215a
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_gpio.c
@@ -0,0 +1,545 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_gpio.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the GPIO peripheral:
+ * + Initialization and Configuration functions
+ * + GPIO Read and Write functions
+ * + GPIO Alternate functions configuration functions
+ *
+ * @verbatim
+
+
+ ===============================================================================
+ ##### How to use this driver #####
+ ===============================================================================
+ [..]
+ (#) Enable the GPIO AHB clock using RCC_AHBPeriphClockCmd()
+ (#) Configure the GPIO pin(s) using GPIO_Init()
+ Four possible configuration are available for each pin:
+ (++) Input: Floating, Pull-up, Pull-down.
+ (++) Output: Push-Pull (Pull-up, Pull-down or no Pull),
+ Open Drain (Pull-up, Pull-down or no Pull).
+ In output mode, the speed is configurable: Low, Medium, Fast or High.
+ (++) Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull),
+ Open Drain (Pull-up, Pull-down or no Pull).
+ (++) Analog: required mode when a pin is to be used as ADC channel,
+ DAC output or comparator input.
+ (#) Peripherals alternate function:
+ (++) For ADC, DAC and comparators, configure the desired pin in
+ analog mode using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN
+ (++) For other peripherals (TIM, USART...):
+ (+++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (+++) Configure the desired pin in alternate function mode using
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ (+++) Select the type, pull-up/pull-down and output speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members.
+ (+++) Call GPIO_Init() function.
+ (#) To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+ (#) To set/reset the level of a pin configured in output mode use
+ GPIO_SetBits()/GPIO_ResetBits()
+ (#) During and just after reset, the alternate functions are not active
+ and the GPIO pins are configured in input floating mode (except JTAG pins).
+ (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as
+ general-purpose (PC14 and PC15, respectively) when the LSE
+ oscillator is off. The LSE has priority over the GPIO function.
+ (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose
+ (PF0 and PF1 respectively) when the HSE oscillator is off. The HSE has
+ the priority over the GPIO function.
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_gpio.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup GPIO
+ * @brief GPIO driver modules
+ * @{
+ */
+
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+ * @{
+ */
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ * @brief Initialization and Configuration
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes the GPIOx peripheral registers to their default reset
+ * values.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval None
+ */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ if(GPIOx == GPIOA)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOA, DISABLE);
+ }
+ else if(GPIOx == GPIOB)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOB, DISABLE);
+ }
+ else if(GPIOx == GPIOC)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOC, DISABLE);
+ }
+ else if(GPIOx == GPIOD)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOD, DISABLE);
+ }
+ else if(GPIOx == GPIOE)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOE, DISABLE);
+ }
+ else
+ {
+ if(GPIOx == GPIOF)
+ {
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, ENABLE);
+ RCC_AHBPeriphResetCmd(RCC_AHBPeriph_GPIOF, DISABLE);
+ }
+ }
+}
+
+/**
+ * @brief Initializes the GPIOx peripheral according to the specified
+ * parameters in the GPIO_InitStruct.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that
+ * contains the configuration information for the specified GPIO
+ * peripheral.
+ * @note GPIO_Pin: selects the pin to be configured:
+ * GPIO_Pin_0->GPIO_Pin_15 for GPIOA, GPIOB, GPIOC, GPIOD and GPIOE;
+ * GPIO_Pin_0->GPIO_Pin_2, GPIO_Pin_4, GPIO_Pin_6, GPIO_Pin_9
+ * and GPIO_Pin_10 for GPIOF.
+ * @retval None
+ */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+ uint32_t tmpreg = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+ assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+ assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+ /*-------------------------- Configure the port pins -----------------------*/
+ /*-- GPIO Mode Configuration --*/
+ for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+ {
+ pos = ((uint32_t)0x01) << pinpos;
+
+ /* Get the port pins position */
+ currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+ if (currentpin == pos)
+ {
+ if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+ {
+ /* Check Speed mode parameters */
+ assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+ /* Speed mode configuration */
+ GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+ GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+ /* Check Output mode parameters */
+ assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+ /* Output mode configuration */
+ GPIOx->OTYPER &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos));
+ GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+ }
+
+ GPIOx->MODER &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+
+ GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+ /* Use temporary variable to update PUPDR register configuration, to avoid
+ unexpected transition in the GPIO pin configuration. */
+ tmpreg = GPIOx->PUPDR;
+ tmpreg &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+ tmpreg |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+ GPIOx->PUPDR = tmpreg;
+ }
+ }
+}
+
+/**
+ * @brief Fills each GPIO_InitStruct member with its default value.
+ * @param GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+ /* Reset GPIO init structure parameters values */
+ GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+ GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+ GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+ GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+ * @brief Locks GPIO Pins configuration registers.
+ * The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+ * @note The configuration of the locked GPIO pins can no longer be modified
+ * until the next reset.
+ * @param GPIOx: where x can be (A or B or D) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+ * @retval None
+ */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint32_t tmp = 0x00010000;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_LIST_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ tmp |= GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Reset LCKK bit */
+ GPIOx->LCKR = GPIO_Pin;
+ /* Set LCKK bit */
+ GPIOx->LCKR = tmp;
+ /* Read LCKK bit */
+ tmp = GPIOx->LCKR;
+ /* Read LCKK bit */
+ tmp = GPIOx->LCKR;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ * @brief GPIO Read and Write
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Read and Write #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to read.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval The input port pin value.
+ */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified input port pin.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval The input port pin value.
+ */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+ * @brief Reads the specified output data port bit.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: Specifies the port bit to read.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval The output port pin value.
+ */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ uint8_t bitstatus = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+ if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+ {
+ bitstatus = (uint8_t)Bit_SET;
+ }
+ else
+ {
+ bitstatus = (uint8_t)Bit_RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Reads the specified GPIO output data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @retval GPIO output data port value.
+ */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+ * @brief Sets the selected data port bits.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval None
+ */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BSRR = GPIO_Pin;
+}
+
+/**
+ * @brief Clears the selected data port bits.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bits to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @retval None
+ */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+ GPIOx->BRR = GPIO_Pin;
+}
+
+/**
+ * @brief Sets or clears the selected data port bit.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_Pin: specifies the port bit to be written.
+ * @note This parameter can be GPIO_Pin_x where x can be :
+ * (0..15) for GPIOA, GPIOB, GPIOC, GPIOD or GPIOE;
+ * (0..2, 4, 6, 9..10) for GPIOF.
+ * @param BitVal: specifies the value to be written to the selected bit.
+ * This parameter can be one of the BitAction enumeration values:
+ * @arg Bit_RESET: to clear the port pin
+ * @arg Bit_SET: to set the port pin
+ * @retval None
+ */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+ assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+ if (BitVal != Bit_RESET)
+ {
+ GPIOx->BSRR = GPIO_Pin;
+ }
+ else
+ {
+ GPIOx->BRR = GPIO_Pin ;
+ }
+}
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param PortVal: specifies the value to be written to the port output data
+ * register.
+ * @retval None
+ */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+ GPIOx->ODR = PortVal;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration functions
+ * @brief GPIO Alternate functions configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### GPIO Alternate functions configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Writes data to the specified GPIO data port.
+ * @param GPIOx: where x can be (A, B, C, D, E or F) to select the GPIO peripheral.
+ * @param GPIO_PinSource: specifies the pin for the Alternate function.
+ * This parameter can be GPIO_PinSourcex where x can be (0..15).
+ * @param GPIO_AF: selects the pin to be used as Alternate function.
+ * This parameter can be one of the following value:
+ * @arg GPIO_AF_0: JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT, MCO, NJTRST,
+ * TRACED, TRACECK.
+ * @arg GPIO_AF_1: OUT, TIM2, TIM15, TIM16, TIM17.
+ * @arg GPIO_AF_2: COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16.
+ * @arg GPIO_AF_3: COMP7_OUT, TIM8, TIM15, Touch, HRTIM.
+ * @arg GPIO_AF_4: I2C1, I2C2, TIM1, TIM8, TIM16, TIM17.
+ * @arg GPIO_AF_5: IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5
+ * @arg GPIO_AF_6: IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8
+ * @arg GPIO_AF_7: AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT, USART1,
+ * USART2, USART3.
+ * @arg GPIO_AF_8: COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT, COMP5_OUT,
+ * COMP6_OUT.
+ * @arg GPIO_AF_9: AOP4_OUT, CAN, TIM1, TIM8, TIM15.
+ * @arg GPIO_AF_10: AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17.
+ * @arg GPIO_AF_11: TIM1, TIM8.
+ * @arg GPIO_AF_12: TIM1, HRTIM.
+ * @arg GPIO_AF_13: HRTIM, AOP2_OUT.
+ * @arg GPIO_AF_14: USBDM, USBDP.
+ * @arg GPIO_AF_15: OUT.
+ * @note The pin should already been configured in Alternate Function mode(AF)
+ * using GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ * @note Refer to the Alternate function mapping table in the device datasheet
+ * for the detailed mapping of the system and peripherals alternate
+ * function I/O pins.
+ * @retval None
+ */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+ uint32_t temp = 0x00;
+ uint32_t temp_2 = 0x00;
+
+ /* Check the parameters */
+ assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+ assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+ assert_param(IS_GPIO_AF(GPIO_AF));
+
+ temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+ GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4));
+ temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+ GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_gpio.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_gpio.h
new file mode 100644
index 0000000000..09539a8805
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_gpio.h
@@ -0,0 +1,410 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_gpio.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the GPIO
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_GPIO_H
+#define __STM32F30x_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup GPIO
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOC) || \
+ ((PERIPH) == GPIOD) || \
+ ((PERIPH) == GPIOE) || \
+ ((PERIPH) == GPIOF))
+
+#define IS_GPIO_LIST_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+ ((PERIPH) == GPIOB) || \
+ ((PERIPH) == GPIOD))
+/** @defgroup Configuration_Mode_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
+ GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
+ GPIO_Mode_AF = 0x02, /*!< GPIO Alternate function Mode */
+ GPIO_Mode_AN = 0x03 /*!< GPIO Analog In/Out Mode */
+}GPIOMode_TypeDef;
+
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)|| ((MODE) == GPIO_Mode_OUT) || \
+ ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+/**
+ * @}
+ */
+
+/** @defgroup Output_type_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_OType_PP = 0x00,
+ GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+/**
+ * @}
+ */
+
+/** @defgroup Output_Maximum_frequency_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_Speed_Level_1 = 0x01, /*!< Fast Speed */
+ GPIO_Speed_Level_2 = 0x02, /*!< Meduim Speed */
+ GPIO_Speed_Level_3 = 0x03 /*!< High Speed */
+}GPIOSpeed_TypeDef;
+
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_Level_1) || ((SPEED) == GPIO_Speed_Level_2) || \
+ ((SPEED) == GPIO_Speed_Level_3))
+/**
+ * @}
+ */
+
+/** @defgroup Configuration_Pull-Up_Pull-Down_enumeration
+ * @{
+ */
+typedef enum
+{
+ GPIO_PuPd_NOPULL = 0x00,
+ GPIO_PuPd_UP = 0x01,
+ GPIO_PuPd_DOWN = 0x02
+}GPIOPuPd_TypeDef;
+
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+ ((PUPD) == GPIO_PuPd_DOWN))
+/**
+ * @}
+ */
+
+/** @defgroup Bit_SET_and_Bit_RESET_enumeration
+ * @{
+ */
+typedef enum
+{
+ Bit_RESET = 0,
+ Bit_SET
+}BitAction;
+
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+/**
+ * @}
+ */
+
+/**
+ * @brief GPIO Init structure definition
+ */
+typedef struct
+{
+ uint32_t GPIO_Pin; /*!< Specifies the GPIO pins to be configured.
+ This parameter can be any value of @ref GPIO_pins_define */
+
+ GPIOMode_TypeDef GPIO_Mode; /*!< Specifies the operating mode for the selected pins.
+ This parameter can be a value of @ref GPIOMode_TypeDef */
+
+ GPIOSpeed_TypeDef GPIO_Speed; /*!< Specifies the speed for the selected pins.
+ This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+ GPIOOType_TypeDef GPIO_OType; /*!< Specifies the operating output type for the selected pins.
+ This parameter can be a value of @ref GPIOOType_TypeDef */
+
+ GPIOPuPd_TypeDef GPIO_PuPd; /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+ This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+ * @{
+ */
+
+/** @defgroup GPIO_pins_define
+ * @{
+ */
+#define GPIO_Pin_0 ((uint16_t)0x0001) /*!< Pin 0 selected */
+#define GPIO_Pin_1 ((uint16_t)0x0002) /*!< Pin 1 selected */
+#define GPIO_Pin_2 ((uint16_t)0x0004) /*!< Pin 2 selected */
+#define GPIO_Pin_3 ((uint16_t)0x0008) /*!< Pin 3 selected */
+#define GPIO_Pin_4 ((uint16_t)0x0010) /*!< Pin 4 selected */
+#define GPIO_Pin_5 ((uint16_t)0x0020) /*!< Pin 5 selected */
+#define GPIO_Pin_6 ((uint16_t)0x0040) /*!< Pin 6 selected */
+#define GPIO_Pin_7 ((uint16_t)0x0080) /*!< Pin 7 selected */
+#define GPIO_Pin_8 ((uint16_t)0x0100) /*!< Pin 8 selected */
+#define GPIO_Pin_9 ((uint16_t)0x0200) /*!< Pin 9 selected */
+#define GPIO_Pin_10 ((uint16_t)0x0400) /*!< Pin 10 selected */
+#define GPIO_Pin_11 ((uint16_t)0x0800) /*!< Pin 11 selected */
+#define GPIO_Pin_12 ((uint16_t)0x1000) /*!< Pin 12 selected */
+#define GPIO_Pin_13 ((uint16_t)0x2000) /*!< Pin 13 selected */
+#define GPIO_Pin_14 ((uint16_t)0x4000) /*!< Pin 14 selected */
+#define GPIO_Pin_15 ((uint16_t)0x8000) /*!< Pin 15 selected */
+#define GPIO_Pin_All ((uint16_t)0xFFFF) /*!< All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
+
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+ ((PIN) == GPIO_Pin_1) || \
+ ((PIN) == GPIO_Pin_2) || \
+ ((PIN) == GPIO_Pin_3) || \
+ ((PIN) == GPIO_Pin_4) || \
+ ((PIN) == GPIO_Pin_5) || \
+ ((PIN) == GPIO_Pin_6) || \
+ ((PIN) == GPIO_Pin_7) || \
+ ((PIN) == GPIO_Pin_8) || \
+ ((PIN) == GPIO_Pin_9) || \
+ ((PIN) == GPIO_Pin_10) || \
+ ((PIN) == GPIO_Pin_11) || \
+ ((PIN) == GPIO_Pin_12) || \
+ ((PIN) == GPIO_Pin_13) || \
+ ((PIN) == GPIO_Pin_14) || \
+ ((PIN) == GPIO_Pin_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Pin_sources
+ * @{
+ */
+#define GPIO_PinSource0 ((uint8_t)0x00)
+#define GPIO_PinSource1 ((uint8_t)0x01)
+#define GPIO_PinSource2 ((uint8_t)0x02)
+#define GPIO_PinSource3 ((uint8_t)0x03)
+#define GPIO_PinSource4 ((uint8_t)0x04)
+#define GPIO_PinSource5 ((uint8_t)0x05)
+#define GPIO_PinSource6 ((uint8_t)0x06)
+#define GPIO_PinSource7 ((uint8_t)0x07)
+#define GPIO_PinSource8 ((uint8_t)0x08)
+#define GPIO_PinSource9 ((uint8_t)0x09)
+#define GPIO_PinSource10 ((uint8_t)0x0A)
+#define GPIO_PinSource11 ((uint8_t)0x0B)
+#define GPIO_PinSource12 ((uint8_t)0x0C)
+#define GPIO_PinSource13 ((uint8_t)0x0D)
+#define GPIO_PinSource14 ((uint8_t)0x0E)
+#define GPIO_PinSource15 ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+ ((PINSOURCE) == GPIO_PinSource1) || \
+ ((PINSOURCE) == GPIO_PinSource2) || \
+ ((PINSOURCE) == GPIO_PinSource3) || \
+ ((PINSOURCE) == GPIO_PinSource4) || \
+ ((PINSOURCE) == GPIO_PinSource5) || \
+ ((PINSOURCE) == GPIO_PinSource6) || \
+ ((PINSOURCE) == GPIO_PinSource7) || \
+ ((PINSOURCE) == GPIO_PinSource8) || \
+ ((PINSOURCE) == GPIO_PinSource9) || \
+ ((PINSOURCE) == GPIO_PinSource10) || \
+ ((PINSOURCE) == GPIO_PinSource11) || \
+ ((PINSOURCE) == GPIO_PinSource12) || \
+ ((PINSOURCE) == GPIO_PinSource13) || \
+ ((PINSOURCE) == GPIO_PinSource14) || \
+ ((PINSOURCE) == GPIO_PinSource15))
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Alternate_function_selection_define
+ * @{
+ */
+
+/**
+ * @brief AF 0 selection
+ */
+#define GPIO_AF_0 ((uint8_t)0x00) /* JTCK-SWCLK, JTDI, JTDO/TRACESW0, JTMS-SWDAT,
+ MCO, NJTRST, TRACED, TRACECK */
+/**
+ * @brief AF 1 selection
+ */
+#define GPIO_AF_1 ((uint8_t)0x01) /* OUT, TIM2, TIM15, TIM16, TIM17 */
+
+/**
+ * @brief AF 2 selection
+ */
+#define GPIO_AF_2 ((uint8_t)0x02) /* COMP1_OUT, TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 */
+
+/**
+ * @brief AF 3 selection
+ */
+#define GPIO_AF_3 ((uint8_t)0x03) /* COMP7_OUT, TIM8, TIM15, Touch, HRTIM1 */
+
+/**
+ * @brief AF 4 selection
+ */
+#define GPIO_AF_4 ((uint8_t)0x04) /* I2C1, I2C2, TIM1, TIM8, TIM16, TIM17 */
+
+/**
+ * @brief AF 5 selection
+ */
+#define GPIO_AF_5 ((uint8_t)0x05) /* IR_OUT, I2S2, I2S3, SPI1, SPI2, TIM8, USART4, USART5 */
+
+/**
+ * @brief AF 6 selection
+ */
+#define GPIO_AF_6 ((uint8_t)0x06) /* IR_OUT, I2S2, I2S3, SPI2, SPI3, TIM1, TIM8 */
+
+/**
+ * @brief AF 7 selection
+ */
+#define GPIO_AF_7 ((uint8_t)0x07) /* AOP2_OUT, CAN, COMP3_OUT, COMP5_OUT, COMP6_OUT,
+ USART1, USART2, USART3 */
+
+/**
+ * @brief AF 8 selection
+ */
+#define GPIO_AF_8 ((uint8_t)0x08) /* COMP1_OUT, COMP2_OUT, COMP3_OUT, COMP4_OUT,
+ COMP5_OUT, COMP6_OUT */
+
+/**
+ * @brief AF 9 selection
+ */
+#define GPIO_AF_9 ((uint8_t)0x09) /* AOP4_OUT, CAN, TIM1, TIM8, TIM15 */
+
+/**
+ * @brief AF 10 selection
+ */
+#define GPIO_AF_10 ((uint8_t)0x0A) /* AOP1_OUT, AOP3_OUT, TIM2, TIM3, TIM4, TIM8, TIM17 */
+
+/**
+ * @brief AF 11 selection
+ */
+#define GPIO_AF_11 ((uint8_t)0x0B) /* TIM1, TIM8 */
+
+/**
+ * @brief AF 12 selection
+ */
+#define GPIO_AF_12 ((uint8_t)0x0C) /* TIM1, HRTIM1 */
+
+/**
+ * @brief AF 13 selection
+ */
+#define GPIO_AF_13 ((uint8_t)0x0D) /* HRTIM1, AOP2_OUT */
+
+/**
+ * @brief AF 14 selection
+ */
+#define GPIO_AF_14 ((uint8_t)0x0E) /* USBDM, USBDP */
+
+/**
+ * @brief AF 15 selection
+ */
+#define GPIO_AF_15 ((uint8_t)0x0F) /* OUT */
+
+#define IS_GPIO_AF(AF) (((AF) == GPIO_AF_0)||((AF) == GPIO_AF_1)||\
+ ((AF) == GPIO_AF_2)||((AF) == GPIO_AF_3)||\
+ ((AF) == GPIO_AF_4)||((AF) == GPIO_AF_5)||\
+ ((AF) == GPIO_AF_6)||((AF) == GPIO_AF_7)||\
+ ((AF) == GPIO_AF_8)||((AF) == GPIO_AF_9)||\
+ ((AF) == GPIO_AF_10)||((AF) == GPIO_AF_11)||\
+ ((AF) == GPIO_AF_12)||((AF) == GPIO_AF_13)||\
+ ((AF) == GPIO_AF_14)||((AF) == GPIO_AF_15))
+
+/**
+ * @}
+ */
+
+/** @defgroup GPIO_Speed_Legacy
+ * @{
+ */
+
+#define GPIO_Speed_10MHz GPIO_Speed_Level_1 /*!< Fast Speed:10MHz */
+#define GPIO_Speed_2MHz GPIO_Speed_Level_2 /*!< Medium Speed:2MHz */
+#define GPIO_Speed_50MHz GPIO_Speed_Level_3 /*!< High Speed:50MHz */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+/* Function used to set the GPIO configuration to the default reset state *****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+
+/* GPIO Alternate functions configuration functions ***************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_GPIO_H */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_hrtim.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_hrtim.c
new file mode 100644
index 0000000000..84c09d565f
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_hrtim.c
@@ -0,0 +1,3968 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_hrtim.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief HRTIMx module driver.
+ *
+ * This file provides firmware functions to manage the following
+ * functionalities of the HRTIMx peripheral:
+ * + Initialization/de-initialization methods
+ * + I/O operation methods
+ * + Peripheral Control methods
+ *
+ @verbatim
+================================================================================
+ ##### #####
+================================================================================
+
+ [..] < HRTIM introduction:
+ (#) The high-resolution timer can generate up to 10 digital signals with
+ highly accurate timings.
+ It is primarily intended to drive power conversion systems such as
+ switch mode power supplies or lighting systems,
+ but can be of general purpose usage, whenever a very fine timing
+ resolution is expected.
+
+ (#) Its modular architecture allows to generate either independent or
+ coupled waveforms.
+ The wave-shape is defined by self-contained timings
+ (using counters and compare units) and a broad range of external events,
+ such as analog or digital feedbacks and synchronisation signals.
+ This allows to produce a large variety of control signal (PWM, phase-shifted,
+ constant Ton,...) and address most of conversion topologies.
+
+ (#) For control and monitoring purposes, the timer has also timing measure
+ capabilities and links to built-in ADC and DAC converters.
+ Last, it features light-load management mode and is able to handle
+ various fault schemes for safe shut-down purposes.
+
+
+ ##### How to use this driver #####
+================================================================================
+ [..] This driver provides functions to configure and program the HRTIM
+ of all stm32f33x devices.
+ These functions are split in 9 groups:
+
+ (#) HRTIM Simple TimeBase management: this group includes all needed functions
+ to configure the HRTIM Timebase unit:
+ (++) Initializes the HRTIMx timer in simple time base mode
+ (++) Start/Stop the time base generation
+ (++) Deinitialize the HRTIM peripheral
+
+
+ (#) HRTIM simple Output Compare management: this group includes all needed
+ functions to configure the Compare unit used in Output compare mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit in in simple Output Compare mode
+ (++) Start/Stop the Output compare generation
+
+ (#) HRTIM simple PWM management: this group includes all needed
+ functions to configure the Compare unit used in PWM mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit in in simple PWM mode
+ (++) Start/Stop the PWM generation
+
+ (#) HRTIM simple Capture management: this group includes all needed
+ functions to configure the Capture unit used in Capture mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit in in simple Capture mode
+ (++) Start/Stop the Capture mode
+
+ (#) HRTIM simple One Pulse management: this group includes all needed
+ functions to configure the Capture unit and Compare unit used in One Pulse mode:
+ (++) Initializes the HRTIMx timer time base unit
+ (++) Configure the compare unit and the capture unit in in simple One Pulse mode
+ (++) Start/Stop the One Pulse mode generation
+
+ (#) HRTIM Waveform management: this group includes all needed
+ functions to configure the HRTIM possible waveform mode:
+ (++) Initializes the HRTIMx timer Master time base unit
+ (++) Initializes the HRTIMx timer Slaves time base unit
+ (++) Configures the HRTIMx timer Compare unit
+ (++) Configures the HRTIMx Slave timer Capture unit
+ (++) Configures the HRTIMx timer Output unit
+ (++) Configures the HRTIMx timer DeadTime / Chopper / Burst features
+ (++) Configures the HRTIMx timer Fault / External event features
+ (++) Configures the HRTIMx timer Synchronization features: Internal/External connection, DACs,...
+ (++) Configures the HRTIMx timer Synchronization features: ADCs Triggers
+ (++) HRTIMx timer Outputs Start/Stop
+ (++) Start/Stop the HRTIMx Timer counters
+
+ (#) HRTIM interrupts, DMA and flags management
+ (++) Enable/Disable interrupt sources
+ (++) Get flags status
+ (++) Clear flags/ Pending bits
+ (++) Enable/Disable DMA requests
+ (++) Configure DMA burst mode
+
+ (#) TIM specific interface management, this group includes all
+ needed functions to use the specific TIM interface:
+ (++) HRTIMx timer DLL calibration
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_hrtim.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup HRTIM
+ * @brief HRTIM driver module
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define HRTIM_FLTR_FLTxEN (HRTIM_FLTR_FLT1EN |\
+ HRTIM_FLTR_FLT2EN |\
+ HRTIM_FLTR_FLT3EN |\
+ HRTIM_FLTR_FLT4EN | \
+ HRTIM_FLTR_FLT5EN)
+
+#define HRTIM_TIMCR_TIMUPDATETRIGGER (HRTIM_TIMUPDATETRIGGER_MASTER |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_A |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_B |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_C |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_D |\
+ HRTIM_TIMUPDATETRIGGER_TIMER_E)
+
+#define HRTIM_TIM_OFFSET (uint32_t)0x00000080
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static uint32_t TimerIdxToTimerId[] =
+{
+ HRTIM_TIMERID_TIMER_A,
+ HRTIM_TIMERID_TIMER_B,
+ HRTIM_TIMERID_TIMER_C,
+ HRTIM_TIMERID_TIMER_D,
+ HRTIM_TIMERID_TIMER_E,
+ HRTIM_TIMERID_MASTER,
+};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static void HRTIM_MasterBase_Config(HRTIM_TypeDef* HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruc);
+static void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+static void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx, HRTIM_TimerInitTypeDef * TimerInit);
+static void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_TimerInitTypeDef * TimerInit);
+static void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * CompareCfg);
+static void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event);
+static void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * OutputCfg);
+static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef * EventCfg);
+static void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Event);
+ /** @defgroup HRTIM_Private_Functions
+ * @{
+ */
+
+/** @defgroup HRTIM_Group1 Initialization/de-initialization methods
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization/de-initialization methods #####
+ ===============================================================================
+ [..] This section provides functions allowing to:
+ (+)Initializes timer in basic time base mode
+ (+)Initializes timer in basic OC mode
+ (+)Initializes timer in basic PWM mode
+ (+)Initializes timer in basic Capture mode
+ (+)Initializes timer in One Pulse mode
+ (+)Initializes a timer operating in waveform mode
+ (+)De-initializes the HRTIMx timer
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the HRTIMx timer in basic time base mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 for master timer
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note The time-base unit initialization parameters specify:
+ * The timer counter operating mode (continuous, one shot)
+ * The timer clock prescaler
+ * The timer period
+ * The timer repetition counter.
+ * @retval None
+ */
+void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure master timer */
+ HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
+ }
+ else
+ {
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+ }
+}
+
+/**
+ * @brief De-initializes a timer operating in all mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @retval None
+ */
+void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx)
+{
+ /* Check the parameters */
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, ENABLE);
+ RCC_APB2PeriphResetCmd(RCC_APB2Periph_HRTIM1, DISABLE);
+ }
+
+/**
+ * @brief Initializes the HRTIMx timer in basic output compare mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note Initializes the time-base unit of the timer and prepare it to
+ * operate in output compare mode
+ * @retval None
+ */
+void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes the HRTIMx timer in basic PWM mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note Initializes the time-base unit of the timer and prepare it to
+ * operate in capture mode
+ * @retval None
+ */
+void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes a timer operating in basic capture mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @retval None
+ */
+void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes the HRTIMx timer in basic one pulse mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x1 to 0x5 for timers A to E
+ * @note Initializes the time-base unit of the timer and prepare it to
+ * operate in one pulse mode. In this mode the counter operates
+ * in single shot mode (retriggerable or not)
+ * @retval None
+ */
+void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+ assert_param(IS_HRTIM_MODE(HRTIM_BaseInitStruct->Mode));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+}
+
+/**
+ * @brief Initializes a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 for master timer
+ * @arg 0x1 to 0x5 for timers A to E
+ * @param pTimerInit: pointer to the timer initialization data structure
+ * @retval None
+ */
+void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
+ HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_HALFMODE(HRTIM_TimerInitStruct->HalfModeEnable));
+ assert_param(IS_HRTIM_SYNCSTART(HRTIM_TimerInitStruct->StartOnSync));
+ assert_param(IS_HRTIM_SYNCRESET(HRTIM_TimerInitStruct->ResetOnSync));
+ assert_param(IS_HRTIM_DACSYNC(HRTIM_TimerInitStruct->DACSynchro));
+ assert_param(IS_HRTIM_PRELOAD(HRTIM_TimerInitStruct->PreloadEnable));
+ assert_param(IS_HRTIM_TIMERBURSTMODE(HRTIM_TimerInitStruct->BurstMode));
+ assert_param(IS_HRTIM_UPDATEONREPETITION(HRTIM_TimerInitStruct->RepetitionUpdate));
+
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_MASTER(HRTIM_TimerInitStruct->UpdateGating));
+
+ /* Configure master timer */
+ HRTIM_MasterBase_Config(HRTIMx, HRTIM_BaseInitStruct);
+ HRTIM_MasterWaveform_Config(HRTIMx, HRTIM_TimerInitStruct);
+ }
+ else
+ {
+ /* Check parameters */
+ assert_param(IS_HRTIM_UPDATEGATING_TIM(HRTIM_TimerInitStruct->UpdateGating));
+
+ /* Configure timing unit */
+ HRTIM_TimingUnitBase_Config(HRTIMx, TimerIdx, HRTIM_BaseInitStruct);
+ HRTIM_TimingUnitWaveform_Config(HRTIMx, TimerIdx, HRTIM_TimerInitStruct);
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Group2 I/O operation methods
+ * @brief Data transfers functions
+ *
+@verbatim
+ ===============================================================================
+ ##### IO operation methods #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to manage the HRTIMx data
+ transfers.
+ (+) Starts the DLL calibration.
+ (+) Starts / stops the counter of a timer operating in basic time base mode
+ (+) Starts / stops the output compare signal generation on the designed timer output
+ (+) Starts / stops the PWM output signal generation on the designed timer output
+ (+) Enables / disables a basic capture on the designed capture unit
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Starts the DLL calibration
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param CalibrationRate: DLL calibration period
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CALIBRATIONRATE_7300: 7.3 ms
+ * @arg HRTIM_CALIBRATIONRATE_910: 910 us
+ * @arg HRTIM_CALIBRATIONRATE_114: 114 us
+ * @arg HRTIM_CALIBRATIONRATE_14: 14 us
+ * @retval None
+ */
+void HRTIM_DLLCalibrationStart(HRTIM_TypeDef * HRTIMx, uint32_t CalibrationRate)
+{
+ uint32_t HRTIM_dllcr;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_CALIBRATIONRATE(CalibrationRate));
+
+ /* Configure DLL Calibration */
+ HRTIM_dllcr = (HRTIMx->HRTIM_COMMON).DLLCR;
+
+ /* Set the Calibration rate */
+ HRTIM_dllcr &= ~(HRTIM_DLLCR_CALRTE);
+ HRTIM_dllcr |= CalibrationRate;
+
+ /* Start DLL calibration */
+ HRTIM_dllcr |= HRTIM_DLLCR_CAL;
+
+ /* Update HRTIMx register */
+ (HRTIMx->HRTIM_COMMON).DLLCR = HRTIM_dllcr;
+
+}
+/**
+ * @brief Starts the counter of a timer operating in basic time base mode
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval None
+ */
+void HRTIM_SimpleBaseStart(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Stops the counter of a timer operating in basic time base mode
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval None
+ */
+void HRTIM_SimpleBaseStop(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMERINDEX(TimerIdx));
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Starts the output compare signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOCStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Enable the timer output */
+ (HRTIMx->HRTIM_COMMON).OENR |= OCChannel;
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+
+}
+
+/**
+ * @brief Stops the output compare signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OCChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+
+ /* Disable the timer output */
+ HRTIMx->HRTIM_COMMON.DISR |= OCChannel;
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Starts the PWM output signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Enable the timer output */
+ HRTIMx->HRTIM_COMMON.OENR |= PWMChannel;
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Stops the PWM output signal generation on the designed timer output
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+
+ /* Disable the timer output */
+ HRTIMx->HRTIM_COMMON.DISR |= PWMChannel;
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Enables a basic capture on the designed capture unit
+ * @param HRTIMx: pointer to HRTIM peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval None
+ * @note The external event triggering the capture is available for all timing
+ * units. It can be used directly and is active as soon as the timing
+ * unit counter is enabled.
+ */
+void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+
+}
+
+/**
+ * @brief Disables a basic capture on the designed capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval None
+ */
+void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+
+ /* Set the capture unit trigger */
+ switch (CaptureChannel)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = HRTIM_CAPTURETRIGGER_NONE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Disable the timer counter */
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR == HRTIM_CAPTURETRIGGER_NONE) &&
+ (HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR == HRTIM_CAPTURETRIGGER_NONE))
+ {
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+ }
+
+}
+
+/**
+ * @brief Enables the basic one pulse signal generation on the designed output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Enable the timer output */
+ HRTIMx->HRTIM_COMMON.OENR |= OnePulseChannel;
+
+ /* Enable the timer counter */
+ __HRTIM_ENABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Disables the basic one pulse signal generation on the designed output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel)
+{
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+
+ /* Disable the timer output */
+ HRTIMx->HRTIM_COMMON.DISR |= OnePulseChannel;
+
+ /* Disable the timer counter */
+ __HRTIM_DISABLE(HRTIMx, TimerIdxToTimerId[TimerIdx]);
+}
+
+/**
+ * @brief Starts the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter start
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToStart: Timer counter(s) to start
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERID_MASTER
+ * @arg HRTIM_TIMERID_TIMER_A
+ * @arg HRTIM_TIMERID_TIMER_B
+ * @arg HRTIM_TIMERID_TIMER_C
+ * @arg HRTIM_TIMERID_TIMER_D
+ * @arg HRTIM_TIMERID_TIMER_E
+ * @retval None
+ */
+void HRTIM_WaveformCounterStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToStart)
+{
+ /* Enable timer(s) counter */
+ HRTIMx->HRTIM_MASTER.MCR |= TimersToStart;
+}
+
+/**
+ * @brief Stops the counter of the designated timer(s) operating in waveform mode
+ * Timers can be combined (ORed) to allow for simultaneous counter stop
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToStop: Timer counter(s) to stop
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval None
+ */
+void HRTIM_WaveformCounterStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToStop)
+{
+ /* Disable timer(s) counter */
+ HRTIMx->HRTIM_MASTER.MCR &= ~TimersToStop;
+}
+
+/**
+ * @brief Enables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output enabling
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param OutputsToStart: Timer output(s) to enable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_WaveformOutputStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t OutputsToStart)
+{
+ /* Enable the HRTIM outputs */
+ HRTIMx->HRTIM_COMMON.OENR = OutputsToStart;
+}
+
+/**
+ * @brief Disables the generation of the waveform signal on the designated output(s)
+ * Outputs can be combined (ORed) to allow for simultaneous output disabling
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param OutputsToStop: Timer output(s) to disable
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval None
+ */
+void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t OutputsToStop)
+{
+ /* Disable the HRTIM outputs */
+ HRTIMx->HRTIM_COMMON.DISR = OutputsToStop;
+}
+
+/**
+ * @brief Enables or disables the Master and slaves interrupt request
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
+ * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
+ * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
+ * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
+ * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
+ * @arg HRTIM_TIM_IT_DLYPRT1: Timer delay protection Interrupt source
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT, FunctionalState NewState)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_IT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_IT;
+ }
+ }
+ else
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_IT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_IT;
+ }
+ }
+}
+
+/**
+ * @brief Enables or disables the common interrupt request
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
+ * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
+ * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
+ * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
+ * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
+ * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
+ * @param NewState: new state of the TIM interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState)
+{
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_COMMON.IER |= HRTIM_CommonIT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_COMMON.IER &= ~HRTIM_CommonIT;
+ }
+}
+
+/**
+ * @brief Clears the Master and slaves interrupt flags
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_FLAG: specifies the HRTIM flags sources to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
+ * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_DLYPRT1: Timer delay protection Interrupt flag
+ * @retval None
+ */
+void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ HRTIMx->HRTIM_MASTER.MICR |= HRTIM_FLAG;
+ }
+ else
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_FLAG;
+ }
+}
+
+/**
+ * @brief Clears the common interrupt flags
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_FLAG: specifies the HRTIM flags to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
+ * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
+ * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
+ * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
+ * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
+ * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
+ * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
+ * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
+ * @retval None
+ */
+void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
+{
+ HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonFLAG;
+}
+
+/**
+ * @brief Clears the Master and slaves interrupt request pending bits
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt source
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt source
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt source
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt source
+ * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt source
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt source
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt source
+ * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt source
+ * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt source
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt source
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt source
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt source
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt source
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt source
+ * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt source
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt source
+ * @retval None
+ */
+void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxICR |= HRTIM_IT;
+ }
+ else
+ {
+ HRTIMx->HRTIM_MASTER.MICR |= HRTIM_IT;
+ }
+}
+
+/**
+ * @brief Clears the common interrupt pending bits
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_IT: specifies the HRTIM interrupts sources to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt source
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt source
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt source
+ * @arg HRTIM_IT_FLT4: Fault 4 Interrupt source
+ * @arg HRTIM_IT_FLT5: Fault 5 Interrupt source
+ * @arg HRTIM_IT_SYSFLT: System Fault Interrupt source
+ * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt source
+ * @arg HRTIM_IT_BMPER: Burst mode period Interrupt source
+ * @retval None
+ */
+void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
+{
+ HRTIMx->HRTIM_COMMON.ICR |= HRTIM_CommonIT;
+}
+
+
+/**
+ * @brief Checks whether the specified HRTIM flag is set or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_FLAG: specifies the HRTIM flags to check.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_FLAG_MCMP1: Master compare 1 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP2: Master compare 2 interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP3: Master compare 3 interrupt Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MCMP4: Master compare 4 Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MREP: Master Repetition Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_SYNC: Synchronization input Interrupt flag
+ * @arg HRTIM_MASTER_FLAG_MUPD: Master update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP1: Timer compare 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP2: Timer compare 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP3: Timer compare 3 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CMP4: Timer compare 4 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_REP: Timer repetition Interrupt flag
+ * @arg HRTIM_TIM_FLAG_UPD: Timer update Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT1: Timer capture 1 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_CPT2: Timer capture 2 Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET1: Timer output 1 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST1: Timer output 1 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_SET2: Timer output 2 set Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST2: Timer output 2 reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_RST: Timer reset Interrupt flag
+ * @arg HRTIM_TIM_FLAG_DLYPRT: Timer delay protection Interrupt flag
+ * @retval The new state of HRTIM_FLAG (SET or RESET).
+ */
+FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_FLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ if ((HRTIMx->HRTIM_MASTER.MISR & HRTIM_FLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified HRTIM common flag is set or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_FLAG: specifies the HRTIM flags to check.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_FLAG_FLT1: Fault 1 interrupt flag
+ * @arg HRTIM_FLAG_FLT2: Fault 2 interrupt flag
+ * @arg HRTIM_FLAG_FLT3: Fault 3 interrupt Interrupt flag
+ * @arg HRTIM_FLAG_FLT4: Fault 4 Interrupt flag
+ * @arg HRTIM_FLAG_FLT5: Fault 5 Interrupt flag
+ * @arg HRTIM_FLAG_SYSFLT: System Fault Interrupt flag
+ * @arg HRTIM_FLAG_DLLRDY: DLL ready Interrupt flag
+ * @arg HRTIM_FLAG_BMPER: Burst mode period Interrupt flag
+ * @retval The new state of HRTIM_FLAG (SET or RESET).
+ */
+FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG)
+{
+ FlagStatus bitstatus = RESET;
+
+ if((HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonFLAG) != RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified HRTIM interrupt has occurred or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_IT: specifies the HRTIM flags sources to be cleared.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt
+ * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt
+ * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt Interrupt
+ * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 Interrupt
+ * @arg HRTIM_MASTER_IT_MREP: Master Repetition Interrupt
+ * @arg HRTIM_MASTER_IT_SYNC: Synchronization input Interrupt
+ * @arg HRTIM_MASTER_IT_MUPD: Master update Interrupt
+ * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 Interrupt
+ * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 Interrupt
+ * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 Interrupt
+ * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 Interrupt
+ * @arg HRTIM_TIM_IT_REP: Timer repetition Interrupt
+ * @arg HRTIM_TIM_IT_UPD: Timer update Interrupt
+ * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 Interrupt
+ * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 Interrupt
+ * @arg HRTIM_TIM_IT_SET1: Timer output 1 set Interrupt
+ * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset Interrupt
+ * @arg HRTIM_TIM_IT_SET2: Timer output 2 set Interrupt
+ * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset Interrupt
+ * @arg HRTIM_TIM_IT_RST: Timer reset Interrupt
+ * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection Interrupt
+ * @retval The new state of the HRTIM_IT(SET or RESET).
+ */
+ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ itstatus = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_IT;
+
+ itenable = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER & HRTIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ else
+ {
+ itstatus = HRTIMx->HRTIM_MASTER.MISR & HRTIM_IT;
+
+ itenable = HRTIMx->HRTIM_MASTER.MDIER & HRTIM_IT;
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Checks whether the specified HRTIM common interrupt has occurred or not.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param HRTIM_IT: specifies the HRTIM interrupt source to check.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_IT_FLT1: Fault 1 interrupt
+ * @arg HRTIM_IT_FLT2: Fault 2 interrupt
+ * @arg HRTIM_IT_FLT3: Fault 3 interrupt Interrupt
+ * @arg HRTIM_IT_FLT4: Fault 4 Interrupt
+ * @arg HRTIM_IT_FLT5: Fault 5 Interrupt
+ * @arg HRTIM_IT_SYSFLT: System Fault Interrupt
+ * @arg HRTIM_IT_DLLRDY: DLL ready Interrupt flag
+ * @arg HRTIM_IT_BMPER: Burst mode period Interrupt
+ * @retval The new state of HRTIM_FLAG (SET or RESET).
+ */
+ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT)
+{
+ ITStatus bitstatus = RESET;
+ uint16_t itstatus = 0x0, itenable = 0x0;
+
+ itstatus = HRTIMx->HRTIM_COMMON.ISR & HRTIM_CommonIT;
+ itenable = HRTIMx->HRTIM_COMMON.IER & HRTIM_CommonIT;
+
+ if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+
+ return bitstatus;
+}
+
+/**
+ * @brief Enables or disables the HRTIMx's DMA Requests.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param HRTIM_DMA: specifies the DMA Request sources.
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA request source
+ * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA request source
+ * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA request source
+ * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA request source
+ * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA request source
+ * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA request source
+ * @arg HRTIM_MASTER_DMA_MUPD:Master update DMA request source
+ * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA request source
+ * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA request source
+ * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA request source
+ * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA request source
+ * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA request source
+ * @arg HRTIM_TIM_DMA_UPD: Timer update DMA request source
+ * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA request source
+ * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA request source
+ * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA request source
+ * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA request source
+ * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA request source
+ * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA request source
+ * @arg HRTIM_TIM_DMA_RST: Timer reset DMA request source
+ * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA request source
+ * @param NewState: new state of the DMA Request sources.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState)
+{
+ if(TimerIdx != HRTIM_TIMERINDEX_MASTER)
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER |= HRTIM_DMA;
+ }
+ else
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxDIER &= ~HRTIM_DMA;
+ }
+ }
+ else
+ {
+ if(NewState != DISABLE)
+ {
+ HRTIMx->HRTIM_MASTER.MDIER |= HRTIM_DMA;
+ }
+ else
+ {
+ HRTIMx->HRTIM_MASTER.MDIER &= ~HRTIM_DMA;
+ }
+ }
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Group3 Peripheral Control methods
+ * @brief management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral Control methods #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the HRTIMx data
+ transfers.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures an output in basic output compare mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OCChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pBasicOCChannelCfg: pointer to the basic output compare output configuration structure
+ * @note When the timer operates in basic output compare mode:
+ * Output 1 is implicitely controled by the compare unit 1
+ * Output 2 is implicitely controled by the compare unit 2
+ * Output Set/Reset crossbar is set according to the selected output compare mode:
+ * Toggle: SETxyR = RSTxyR = CMPy
+ * Active: SETxyR = CMPy, RSTxyR = 0
+ * Inactive: SETxy =0, RSTxy = CMPy
+ * @retval None
+ */
+void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg)
+{
+ uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OCChannel));
+ assert_param(IS_HRTIM_BASICOCMODE(pBasicOCChannelCfg->Mode));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOCChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOCChannelCfg->IdleState));
+
+ /* Configure timer compare unit */
+ switch (OCChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pBasicOCChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(HRTIM_,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pBasicOCChannelCfg->Polarity;
+ OutputCfg.IdleState = pBasicOCChannelCfg->IdleState;
+ OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ switch (pBasicOCChannelCfg->Mode)
+ {
+ case HRTIM_BASICOCMODE_TOGGLE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = OutputCfg.SetSource;
+ }
+ break;
+ case HRTIM_BASICOCMODE_ACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_NONE;
+ }
+ break;
+ case HRTIM_BASICOCMODE_INACTIVE:
+ {
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.ResetSource = HRTIM_OUTPUTRESET_TIMCMP2;
+ }
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_NONE;
+ }
+ break;
+ default:
+ break;
+ }
+
+ HRTIM_OutputConfig(HRTIM_, TimerIdx, OCChannel, &OutputCfg);
+}
+
+/**
+ * @brief Configures an output in basic PWM mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param PWMChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pBasicPWMChannelCfg: pointer to the basic PWM output configuration structure
+ * @note When the timer operates in basic PWM output mode:
+ * Output 1 is implicitly controled by the compare unit 1
+ * Output 2 is implicitly controled by the compare unit 2
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * @retval None
+ */
+void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg)
+{
+ uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, PWMChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicPWMChannelCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicPWMChannelCfg->IdleState));
+
+ /* Configure timer compare unit */
+ switch (PWMChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pBasicPWMChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(HRTIM_,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pBasicPWMChannelCfg->Polarity;
+ OutputCfg.IdleState = pBasicPWMChannelCfg->IdleState;
+ OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(HRTIM_, TimerIdx, PWMChannel, &OutputCfg);
+}
+
+/**
+ * @brief Configures a basic capture
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Capture unit
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pBasicCaptureChannelCfg: pointer to the basic capture configuration structure
+ * @note When the timer operates in basic capture mode the capture is triggered
+ * by the designated external event and GPIO input is implicitly used as event source.
+ * The cature can be triggered by a rising edge, a falling edge or both
+ * edges on event channel.
+ * @retval None
+ */
+void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg)
+{
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureChannel));
+ assert_param(IS_HRTIM_EVENT(pBasicCaptureChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pBasicCaptureChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicCaptureChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pBasicCaptureChannelCfg->EventFilter));
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pBasicCaptureChannelCfg->EventFilter;
+ EventCfg.Polarity = pBasicCaptureChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pBasicCaptureChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_ExternalEventConfig(HRTIMx,
+ pBasicCaptureChannelCfg->Event,
+ &EventCfg);
+
+ /* Memorize capture trigger (will be configured when the capture is started */
+ HRTIM_CaptureUnitConfig(HRTIMx,
+ TimerIdx,
+ CaptureChannel,
+ pBasicCaptureChannelCfg->Event);
+}
+
+/**
+ * @brief Configures an output basic one pulse mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param OnePulseChannel: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pBasicOnePulseChannelCfg: pointer to the basic one pulse output configuration structure
+ * @note When the timer operates in basic one pulse mode:
+ * the timer counter is implicitly started by the reset event,
+ * the reset of the timer counter is triggered by the designated external event
+ * GPIO input is implicitly used as event source,
+ * Output 1 is implicitly controled by the compare unit 1,
+ * Output 2 is implicitly controled by the compare unit 2.
+ * Output Set/Reset crossbar is set as follows:
+ * Output 1: SETx1R = CMP1, RSTx1R = PER
+ * Output 2: SETx2R = CMP2, RST2R = PER
+ * The counter mode should be HRTIM_MODE_SINGLESHOT_RETRIGGERABLE
+ * @retval None
+ */
+void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg)
+{
+ uint32_t CompareUnit = HRTIM_COMPAREUNIT_1;
+ HRTIM_CompareCfgTypeDef CompareCfg;
+ HRTIM_OutputCfgTypeDef OutputCfg;
+ HRTIM_EventCfgTypeDef EventCfg;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, OnePulseChannel));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pBasicOnePulseChannelCfg->OutputPolarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pBasicOnePulseChannelCfg->OutputIdleState));
+ assert_param(IS_HRTIM_EVENT(pBasicOnePulseChannelCfg->Event));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pBasicOnePulseChannelCfg->EventPolarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pBasicOnePulseChannelCfg->EventSensitivity));
+ assert_param(IS_HRTIM_EVENTFILTER(pBasicOnePulseChannelCfg->EventFilter));
+
+ /* Configure timer compare unit */
+ switch (OnePulseChannel)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_1;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ CompareUnit = HRTIM_COMPAREUNIT_2;
+ }
+ break;
+ default:
+ break;
+ }
+
+ CompareCfg.CompareValue = pBasicOnePulseChannelCfg->Pulse;
+ CompareCfg.AutoDelayedMode = HRTIM_AUTODELAYEDMODE_REGULAR;
+ CompareCfg.AutoDelayedTimeout = 0;
+
+ HRTIM_CompareUnitConfig(HRTIM_,
+ TimerIdx,
+ CompareUnit,
+ &CompareCfg);
+
+ /* Configure timer output */
+ OutputCfg.Polarity = pBasicOnePulseChannelCfg->OutputPolarity;
+ OutputCfg.IdleState = pBasicOnePulseChannelCfg->OutputIdleState;
+ OutputCfg.FaultState = HRTIM_OUTPUTFAULTSTATE_NONE;
+ OutputCfg.IdleMode = HRTIM_OUTPUTIDLEMODE_NONE;
+ OutputCfg.ChopperModeEnable = HRTIM_OUTPUTCHOPPERMODE_DISABLED;
+ OutputCfg.BurstModeEntryDelayed = HRTIM_OUTPUTBURSTMODEENTRY_REGULAR;
+
+ if (CompareUnit == HRTIM_COMPAREUNIT_1)
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP1;
+ }
+ else
+ {
+ OutputCfg.SetSource = HRTIM_OUTPUTSET_TIMCMP2;
+ }
+ OutputCfg.ResetSource = HRTIM_OUTPUTSET_TIMPER;
+
+ HRTIM_OutputConfig(HRTIM_,
+ TimerIdx,
+ OnePulseChannel,
+ &OutputCfg);
+
+ /* Configure external event channel */
+ EventCfg.FastMode = HRTIM_EVENTFASTMODE_DISABLE;
+ EventCfg.Filter = pBasicOnePulseChannelCfg->EventFilter;
+ EventCfg.Polarity = pBasicOnePulseChannelCfg->EventPolarity;
+ EventCfg.Sensitivity = pBasicOnePulseChannelCfg->EventSensitivity;
+ EventCfg.Source = HRTIM_EVENTSRC_1;
+
+ HRTIM_ExternalEventConfig(HRTIM_,
+ pBasicOnePulseChannelCfg->Event,
+ &EventCfg);
+
+ /* Configure the timer reset register */
+ HRTIM_TIM_ResetConfig(HRTIM_,
+ TimerIdx,
+ pBasicOnePulseChannelCfg->Event);
+}
+
+/**
+ * @brief Configures the general behavior of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param pTimerCfg: pointer to the timer configuration structure
+ * @note When the timer operates in waveform mode, all the features supported by
+ * the HRTIMx are available without any limitation.
+ * @retval None
+ */
+void HRTIM_WaveformTimerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * pTimerCfg)
+{
+ uint32_t HRTIM_timcr;
+ uint32_t HRTIM_timfltr;
+ uint32_t HRTIM_timoutr;
+ uint32_t HRTIM_timrstr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_TIMPUSHPULLMODE(pTimerCfg->PushPull));
+ assert_param(IS_HRTIM_TIMFAULTENABLE(pTimerCfg->FaultEnable));
+ assert_param(IS_HRTIM_TIMFAULTLOCK(pTimerCfg->FaultLock));
+ assert_param(IS_HRTIM_TIMDEADTIMEINSERTION(pTimerCfg->DeadTimeInsertion));
+ assert_param(IS_HRTIM_TIMDELAYEDPROTECTION(pTimerCfg->DelayedProtectionMode));
+ assert_param(IS_HRTIM_TIMUPDATETRIGGER(pTimerCfg->UpdateTrigger));
+ assert_param(IS_HRTIM_TIMRESETTRIGGER(pTimerCfg->ResetTrigger));
+ assert_param(IS_HRTIM_TIMUPDATEONRESET(pTimerCfg->ResetUpdate));
+
+ /* Configure timing unit (Timer A to Timer E) */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_timfltr = HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR;
+ HRTIM_timoutr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
+ HRTIM_timrstr = HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR;
+
+ /* Set the push-pull mode */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_PSHPLL);
+ HRTIM_timcr |= pTimerCfg->PushPull;
+
+ /* Enable/Disable registers update on timer counter reset */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_TRSTU);
+ HRTIM_timcr |= pTimerCfg->ResetUpdate;
+
+ /* Set the timer update trigger */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_TIMUPDATETRIGGER);
+ HRTIM_timcr |= pTimerCfg->UpdateTrigger;
+
+ /* Enable/Disable the fault channel at timer level */
+ HRTIM_timfltr &= ~(HRTIM_FLTR_FLTxEN);
+ HRTIM_timfltr |= (pTimerCfg->FaultEnable & HRTIM_FLTR_FLTxEN);
+
+ /* Lock/Unlock fault sources at timer level */
+ HRTIM_timfltr &= ~(HRTIM_FLTR_FLTCLK);
+ HRTIM_timfltr |= pTimerCfg->FaultLock;
+
+ /* Enable/Disable dead time insertion at timer level */
+ HRTIM_timoutr &= ~(HRTIM_OUTR_DTEN);
+ HRTIM_timoutr |= pTimerCfg->DeadTimeInsertion;
+
+ /* Enable/Disable delayed protection at timer level */
+ HRTIM_timoutr &= ~(HRTIM_OUTR_DLYPRT| HRTIM_OUTR_DLYPRTEN);
+ HRTIM_timoutr |= pTimerCfg->DelayedProtectionMode;
+
+ /* Set the timer counter reset trigger */
+ HRTIM_timrstr = pTimerCfg->ResetTrigger;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].FLTxR = HRTIM_timfltr;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_timoutr;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_timrstr;
+ }
+
+/**
+ * @brief Configures the compare unit of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * 0xFF for master timer
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CompareUnit: Compare unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param pCompareCfg: pointer to the compare unit configuration structure
+ * @note When auto delayed mode is required for compare unit 2 or compare unit 4,
+ * application has to configure separately the capture unit. Capture unit
+ * to configure in that case depends on the compare unit auto delayed mode
+ * is applied to (see below):
+ * Auto delayed on output compare 2: capture unit 1 must be configured
+ * Auto delayed on output compare 4: capture unit 2 must be configured
+ * @retval None
+ */
+ void HRTIM_WaveformCompareConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg)
+{
+ uint32_t HRTIM_timcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(CompareUnit, pCompareCfg->AutoDelayedMode));
+
+ /* Configure the compare unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP2;
+ HRTIM_timcr |= pCompareCfg->AutoDelayedMode;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+
+ if (pCompareCfg->AutoDelayedMode != HRTIM_AUTODELAYEDMODE_REGULAR)
+ {
+ /* Configure auto-delayed mode */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_timcr &= ~HRTIM_TIMCR_DELCMP4;
+ HRTIM_timcr |= (pCompareCfg->AutoDelayedMode << 2);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+
+ /* Set the compare value for timeout compare unit (if any) */
+ if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ else if (pCompareCfg->AutoDelayedMode == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3)
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->AutoDelayedTimeout;
+ }
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Sets the HRTIMx Master Comparex Register value
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param CompareUnit: Compare unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
+ * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
+ * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
+ * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
+ * @param Compare: specifies the Comparex register new value
+ * @retval None
+ */
+void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
+ uint32_t CompareUnit,
+ uint32_t Compare)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_COMPAREUNIT(CompareUnit));
+
+ /* Configure the compare unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP1R = Compare;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP2R = Compare;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP3R = Compare;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ /* Set the compare value */
+ HRTIMx->HRTIM_MASTER.MCMP4R = Compare;
+ }
+ break;
+ default:
+ break;
+ }
+}
+/**
+ * @brief Configures the capture unit of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureChannel: Capture unit to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @param pCaptureCfg: pointer to the compare unit configuration structure
+ * @retval None
+ */
+void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg)
+{
+ /* Configure the capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = pCaptureCfg->Trigger;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the output of a timer operating in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param pOutputCfg: pointer to the timer output configuration structure
+ * @retval None
+ */
+void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTPOLARITY(pOutputCfg->Polarity));
+ assert_param(IS_HRTIM_OUTPUTIDLESTATE(pOutputCfg->IdleState));
+ assert_param(IS_HRTIM_OUTPUTIDLEMODE(pOutputCfg->IdleMode));
+ assert_param(IS_HRTIM_OUTPUTFAULTSTATE(pOutputCfg->FaultState));
+ assert_param(IS_HRTIM_OUTPUTCHOPPERMODE(pOutputCfg->ChopperModeEnable));
+ assert_param(IS_HRTIM_OUTPUTBURSTMODEENTRY(pOutputCfg->BurstModeEntryDelayed));
+
+ /* Configure the timer output */
+ HRTIM_OutputConfig(HRTIM_, TimerIdx, Output, pOutputCfg);
+}
+
+/**
+ * @brief Configures the event filtering capabilities of a timer (blanking, windowing)
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Event: external event for which timer event filtering must be configured
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pTimerEventFilteringCfg: pointer to the timer event filtering configuration structure
+ * @retval None
+ */
+void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef* pTimerEventFilteringCfg)
+{
+ uint32_t HRTIM_eefr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_EVENT(Event));
+ assert_param(IS_HRTIM_TIMEVENTFILTER(pTimerEventFilteringCfg->Filter));
+ assert_param(IS_HRTIM_TIMEVENTLATCH(pTimerEventFilteringCfg->Latch));
+
+ /* Configure timer event filtering capabilities */
+ switch (Event)
+ {
+ case HRTIM_TIMEVENTFILTER_NONE:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = 0;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = 0;
+ }
+ break;
+ case HRTIM_EVENT_1:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE1FLTR | HRTIM_EEFR1_EE1LTCH);
+ HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE2FLTR | HRTIM_EEFR1_EE2LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE3FLTR | HRTIM_EEFR1_EE3LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE4FLTR | HRTIM_EEFR1_EE4LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1;
+ HRTIM_eefr &= ~(HRTIM_EEFR1_EE5FLTR | HRTIM_EEFR1_EE5LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR1 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE6FLTR | HRTIM_EEFR2_EE6LTCH);
+ HRTIM_eefr |= (pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE7FLTR | HRTIM_EEFR2_EE7LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 6);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE8FLTR | HRTIM_EEFR2_EE8LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 12);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE9FLTR | HRTIM_EEFR2_EE9LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 18);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ HRTIM_eefr = HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2;
+ HRTIM_eefr &= ~(HRTIM_EEFR2_EE10FLTR | HRTIM_EEFR2_EE10LTCH);
+ HRTIM_eefr |= ((pTimerEventFilteringCfg->Filter | pTimerEventFilteringCfg->Latch) << 24);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].EEFxR2 = HRTIM_eefr;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the dead time insertion feature for a timer
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param pDeadTimeCfg: pointer to the dead time insertion configuration structure
+ * @retval None
+ */
+void HRTIM_DeadTimeConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg)
+{
+ uint32_t HRTIM_dtr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGN(pDeadTimeCfg->RisingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGLOCK(pDeadTimeCfg->RisingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(pDeadTimeCfg->RisingSignLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGN(pDeadTimeCfg->FallingSign));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGLOCK(pDeadTimeCfg->FallingLock));
+ assert_param(IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(pDeadTimeCfg->FallingSignLock));
+
+ HRTIM_dtr = HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR;
+
+ /* Clear timer dead times configuration */
+ HRTIM_dtr &= ~(HRTIM_DTR_DTR | HRTIM_DTR_SDTR | HRTIM_DTR_DTPRSC |
+ HRTIM_DTR_DTRSLK | HRTIM_DTR_DTRLK | HRTIM_DTR_SDTF |
+ HRTIM_DTR_SDTR | HRTIM_DTR_DTFSLK | HRTIM_DTR_DTFLK);
+
+ /* Set timer dead times configuration */
+ HRTIM_dtr |= (pDeadTimeCfg->Prescaler << 10);
+ HRTIM_dtr |= pDeadTimeCfg->RisingValue;
+ HRTIM_dtr |= pDeadTimeCfg->RisingSign;
+ HRTIM_dtr |= pDeadTimeCfg->RisingSignLock;
+ HRTIM_dtr |= pDeadTimeCfg->RisingLock;
+ HRTIM_dtr |= (pDeadTimeCfg->FallingValue << 16);
+ HRTIM_dtr |= pDeadTimeCfg->FallingSign;
+ HRTIM_dtr |= pDeadTimeCfg->FallingSignLock;
+ HRTIM_dtr |= pDeadTimeCfg->FallingLock;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].DTxR = HRTIM_dtr;
+}
+
+/**
+ * @brief Configures the chopper mode feature for a timer
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param pChopperModeCfg: pointer to the chopper mode configuration structure
+ * @retval None
+ */
+void HRTIM_ChopperModeConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg)
+{
+ uint32_t HRTIM_chpr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ HRTIM_chpr = HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR;
+
+ /* Clear timer chopper mode configuration */
+ HRTIM_chpr &= ~(HRTIM_CHPR_CARFRQ | HRTIM_CHPR_CARDTY | HRTIM_CHPR_STRPW);
+
+ /* Set timer chopper mode configuration */
+ HRTIM_chpr |= pChopperModeCfg->CarrierFreq;
+ HRTIM_chpr |= (pChopperModeCfg->DutyCycle << 4);
+ HRTIM_chpr |= (pChopperModeCfg->StartPulse << 7);
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CHPxR = HRTIM_chpr;
+}
+
+/**
+ * @brief Configures the burst DMA controller for a timer
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x5 for master timer
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param RegistersToUpdate: registers to be written by DMA
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_BURSTDMA_CR: HRTIM_MCR or HRTIM_TIMxCR
+ * @arg HRTIM_BURSTDMA_ICR: HRTIM_MICR or HRTIM_TIMxICR
+ * @arg HRTIM_BURSTDMA_DIER: HRTIM_MDIER or HRTIM_TIMxDIER
+ * @arg HRTIM_BURSTDMA_CNT: HRTIM_MCNT or HRTIM_TIMxCNT
+ * @arg HRTIM_BURSTDMA_PER: HRTIM_MPER or HRTIM_TIMxPER
+ * @arg HRTIM_BURSTDMA_REP: HRTIM_MREP or HRTIM_TIMxREP
+ * @arg HRTIM_BURSTDMA_CMP1: HRTIM_MCMP1 or HRTIM_TIMxCMP1
+ * @arg HRTIM_BURSTDMA_CMP2: HRTIM_MCMP2 or HRTIM_TIMxCMP2
+ * @arg HRTIM_BURSTDMA_CMP3: HRTIM_MCMP3 or HRTIM_TIMxCMP3
+ * @arg HRTIM_BURSTDMA_CMP4: HRTIM_MCMP4 or HRTIM_TIMxCMP4
+ * @arg HRTIM_BURSTDMA_DTR: HRTIM_TIMxDTR
+ * @arg HRTIM_BURSTDMA_SET1R: HRTIM_TIMxSET1R
+ * @arg HRTIM_BURSTDMA_RST1R: HRTIM_TIMxRST1R
+ * @arg HRTIM_BURSTDMA_SET2R: HRTIM_TIMxSET2R
+ * @arg HRTIM_BURSTDMA_RST2R: HRTIM_TIMxRST2R
+ * @arg HRTIM_BURSTDMA_EEFR1: HRTIM_TIMxEEFR1
+ * @arg HRTIM_BURSTDMA_EEFR2: HRTIM_TIMxEEFR2
+ * @arg HRTIM_BURSTDMA_RSTR: HRTIM_TIMxRSTR
+ * @arg HRTIM_BURSTDMA_CHPR: HRTIM_TIMxCHPR
+ * @arg HRTIM_BURSTDMA_OUTR: HRTIM_TIMxOUTR
+ * @arg HRTIM_BURSTDMA_FLTR: HRTIM_TIMxFLTR
+ * @retval None
+ */
+void HRTIM_BurstDMAConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_BURSTDMA(TimerIdx, RegistersToUpdate));
+
+ /* Set the burst DMA timer update register */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ HRTIMx->HRTIM_COMMON.BDTAUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ HRTIMx->HRTIM_COMMON.BDTBUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ HRTIMx->HRTIM_COMMON.BDTCUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ HRTIMx->HRTIM_COMMON.BDTDUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ HRTIMx->HRTIM_COMMON.BDTEUPR = RegistersToUpdate;
+ }
+ break;
+ case HRTIM_TIMERINDEX_MASTER:
+ {
+ HRTIMx->HRTIM_COMMON.BDMUPDR = RegistersToUpdate;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the external input/output synchronization of the HRTIMx
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param pSynchroCfg: pointer to the input/output synchronization configuration structure
+ * @retval None
+ */
+void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx, HRTIM_SynchroCfgTypeDef * pSynchroCfg)
+{
+ uint32_t HRTIM_mcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_SYNCINPUTSOURCE(pSynchroCfg->SyncInputSource));
+ assert_param(IS_HRTIM_SYNCOUTPUTSOURCE(pSynchroCfg->SyncOutputSource));
+ assert_param(IS_HRTIM_SYNCOUTPUTPOLARITY(pSynchroCfg->SyncOutputPolarity));
+
+ HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
+
+ /* Set the synchronization input source */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNC_IN);
+ HRTIM_mcr |= pSynchroCfg->SyncInputSource;
+
+ /* Set the event to be sent on the synchronization output */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNC_SRC);
+ HRTIM_mcr |= pSynchroCfg->SyncOutputSource;
+
+ /* Set the polarity of the synchronization output */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNC_OUT);
+ HRTIM_mcr |= pSynchroCfg->SyncOutputPolarity;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
+}
+
+/**
+ * @brief Configures the burst mode feature of the HRTIMx
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param pBurstModeCfg: pointer to the burst mode configuration structure
+ * @retval None
+ */
+void HRTIM_BurstModeConfig(HRTIM_TypeDef * HRTIMx,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg)
+{
+ uint32_t HRTIM_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODE(pBurstModeCfg->Mode));
+ assert_param(IS_HRTIM_BURSTMODECLOCKSOURCE(pBurstModeCfg->ClockSource));
+ assert_param(IS_HRTIM_HRTIM_BURSTMODEPRESCALER(pBurstModeCfg->Prescaler));
+ assert_param(IS_HRTIM_BURSTMODEPRELOAD(pBurstModeCfg->PreloadEnable));
+
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+
+ /* Set the burst mode operating mode */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMOM);
+ HRTIM_bmcr |= pBurstModeCfg->Mode;
+
+ /* Set the burst mode clock source */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMCLK);
+ HRTIM_bmcr |= pBurstModeCfg->ClockSource;
+
+ /* Set the burst mode prescaler */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMPSC);
+ HRTIM_bmcr |= pBurstModeCfg->Prescaler;
+
+ /* Enable/disable burst mode registers preload */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BMPREN);
+ HRTIM_bmcr |= pBurstModeCfg->PreloadEnable;
+
+ /* Set the burst mode trigger */
+ HRTIMx->HRTIM_COMMON.BMTRGR = pBurstModeCfg->Trigger;
+
+ /* Set the burst mode compare value */
+ HRTIMx->HRTIM_COMMON.BMCMPR = pBurstModeCfg->IdleDuration;
+
+ /* Set the burst mode period */
+ HRTIMx->HRTIM_COMMON.BMPER = pBurstModeCfg->Period;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+}
+
+/**
+ * @brief Configures the conditioning of an external event
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Event: external event to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENT_1: External event 1
+ * @arg HRTIM_EVENT_2: External event 2
+ * @arg HRTIM_EVENT_3: External event 3
+ * @arg HRTIM_EVENT_4: External event 4
+ * @arg HRTIM_EVENT_5: External event 5
+ * @arg HRTIM_EVENT_6: External event 6
+ * @arg HRTIM_EVENT_7: External event 7
+ * @arg HRTIM_EVENT_8: External event 8
+ * @arg HRTIM_EVENT_9: External event 9
+ * @arg HRTIM_EVENT_10: External event 10
+ * @param pEventCfg: pointer to the event conditioning configuration structure
+ * @retval None
+ */
+void HRTIM_EventConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTSRC(pEventCfg->Source));
+ assert_param(IS_HRTIM_EVENTPOLARITY(pEventCfg->Polarity));
+ assert_param(IS_HRTIM_EVENTSENSITIVITY(pEventCfg->Sensitivity));
+ assert_param(IS_HRTIM_EVENTFASTMODE(pEventCfg->FastMode));
+ assert_param(IS_HRTIM_EVENTFILTER(pEventCfg->Filter));
+
+ /* Configure the event channel */
+ HRTIM_ExternalEventConfig(HRTIMx, Event, pEventCfg);
+
+}
+
+/**
+ * @brief Configures the external event conditioning block prescaler
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Prescaler: Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_EVENTPRESCALER_DIV1: fEEVS=fHRTIMx
+ * @arg HRTIM_EVENTPRESCALER_DIV2: fEEVS=fHRTIMx / 2
+ * @arg HRTIM_EVENTPRESCALER_DIV4: fEEVS=fHRTIMx / 4
+ * @arg HRTIM_EVENTPRESCALER_DIV8: fEEVS=fHRTIMx / 8
+ * @retval None
+ */
+void HRTIM_EventPrescalerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Prescaler)
+{
+ uint32_t HRTIM_eecr3;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_EVENTPRESCALER(Prescaler));
+
+ /* Set the external event prescaler */
+ HRTIM_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
+ HRTIM_eecr3 &= ~(HRTIM_EECR3_EEVSD);
+ HRTIM_eecr3 |= Prescaler;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.EECR3 = HRTIM_eecr3;
+}
+
+/**
+ * @brief Configures the conditioning of fault input
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Fault: fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param pFaultCfg: pointer to the fault conditioning configuration structure
+ * @retval None
+ */
+void HRTIM_FaultConfig(HRTIM_TypeDef * HRTIMx,
+ HRTIM_FaultCfgTypeDef* pFaultCfg,
+ uint32_t Fault)
+{
+ uint32_t HRTIM_fltinr1;
+ uint32_t HRTIM_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Fault));
+ assert_param(IS_HRTIM_FAULTSOURCE(pFaultCfg->Source));
+ assert_param(IS_HRTIM_FAULTPOLARITY(pFaultCfg->Polarity));
+ assert_param(IS_HRTIM_FAULTFILTER(pFaultCfg->Filter));
+ assert_param(IS_HRTIM_FAULTLOCK(pFaultCfg->Lock));
+
+ /* Configure fault channel */
+ HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
+ HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
+
+ switch (Fault)
+ {
+ case HRTIM_FAULT_1:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT1P | HRTIM_FLTINR1_FLT1SRC | HRTIM_FLTINR1_FLT1F | HRTIM_FLTINR1_FLT1LCK);
+ HRTIM_fltinr1 |= pFaultCfg->Polarity;
+ HRTIM_fltinr1 |= pFaultCfg->Source;
+ HRTIM_fltinr1 |= pFaultCfg->Filter;
+ HRTIM_fltinr1 |= pFaultCfg->Lock;
+ }
+ break;
+ case HRTIM_FAULT_2:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT2P | HRTIM_FLTINR1_FLT2SRC | HRTIM_FLTINR1_FLT2F | HRTIM_FLTINR1_FLT2LCK);
+ HRTIM_fltinr1 |= (pFaultCfg->Polarity << 8);
+ HRTIM_fltinr1 |= (pFaultCfg->Source << 8);
+ HRTIM_fltinr1 |= (pFaultCfg->Filter << 8);
+ HRTIM_fltinr1 |= (pFaultCfg->Lock << 8);
+ }
+ break;
+ case HRTIM_FAULT_3:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT3P | HRTIM_FLTINR1_FLT3SRC | HRTIM_FLTINR1_FLT3F | HRTIM_FLTINR1_FLT3LCK);
+ HRTIM_fltinr1 |= (pFaultCfg->Polarity << 16);
+ HRTIM_fltinr1 |= (pFaultCfg->Source << 16);
+ HRTIM_fltinr1 |= (pFaultCfg->Filter << 16);
+ HRTIM_fltinr1 |= (pFaultCfg->Lock << 16);
+ }
+ break;
+ case HRTIM_FAULT_4:
+ {
+ HRTIM_fltinr1 &= ~(HRTIM_FLTINR1_FLT4P | HRTIM_FLTINR1_FLT4SRC | HRTIM_FLTINR1_FLT4F | HRTIM_FLTINR1_FLT4LCK);
+ HRTIM_fltinr1 |= (pFaultCfg->Polarity << 24);
+ HRTIM_fltinr1 |= (pFaultCfg->Source << 24);
+ HRTIM_fltinr1 |= (pFaultCfg->Filter << 24);
+ HRTIM_fltinr1 |= (pFaultCfg->Lock << 24);
+ }
+ break;
+ case HRTIM_FAULT_5:
+ {
+ HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLT5P | HRTIM_FLTINR2_FLT5SRC | HRTIM_FLTINR2_FLT5F | HRTIM_FLTINR2_FLT5LCK);
+ HRTIM_fltinr2 |= pFaultCfg->Polarity;
+ HRTIM_fltinr2 |= pFaultCfg->Source;
+ HRTIM_fltinr2 |= pFaultCfg->Filter;
+ HRTIM_fltinr2 |= pFaultCfg->Lock;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
+ HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
+}
+
+/**
+ * @brief Configures the fault conditioning block prescaler
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Prescaler: Prescaler value
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULTPRESCALER_DIV1: fFLTS=fHRTIMx
+ * @arg HRTIM_FAULTPRESCALER_DIV2: fFLTS=fHRTIMx / 2
+ * @arg HRTIM_FAULTPRESCALER_DIV4: fFLTS=fHRTIMx / 4
+ * @arg HRTIM_FAULTPRESCALER_DIV8: fFLTS=fHRTIMx / 8
+ * @retval None
+ */
+void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Prescaler)
+{
+ uint32_t HRTIM_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULTPRESCALER(Prescaler));
+
+ /* Set the external event prescaler */
+ HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
+ HRTIM_fltinr2 &= ~(HRTIM_FLTINR2_FLTSD);
+ HRTIM_fltinr2 |= Prescaler;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
+}
+
+/**
+ * @brief Enables or disables the HRTIMx Fault mode.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Fault: fault input to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_1: Fault input 1
+ * @arg HRTIM_FAULT_2: Fault input 2
+ * @arg HRTIM_FAULT_3: Fault input 3
+ * @arg HRTIM_FAULT_4: Fault input 4
+ * @arg HRTIM_FAULT_5: Fault input 5
+ * @param Enable: Fault mode controller enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_FAULT_ENABLED: Fault mode enabled
+ * @arg HRTIM_FAULT_DISABLED: Fault mode disabled
+ * @retval None
+ */
+void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable)
+{
+ uint32_t HRTIM_fltinr1;
+ uint32_t HRTIM_fltinr2;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_FAULT(Fault));
+ assert_param(IS_HRTIM_FAULTCTL(Enable));
+
+ /* Configure fault channel */
+ HRTIM_fltinr1 = HRTIMx->HRTIM_COMMON.FLTINxR1;
+ HRTIM_fltinr2 = HRTIMx->HRTIM_COMMON.FLTINxR2;
+
+ switch (Fault)
+ {
+ case HRTIM_FAULT_1:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT1E;
+ HRTIM_fltinr1 |= Enable;
+ }
+ break;
+ case HRTIM_FAULT_2:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT2E;
+ HRTIM_fltinr1 |= (Enable<< 8);
+ }
+ break;
+ case HRTIM_FAULT_3:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT3E;
+ HRTIM_fltinr1 |= (Enable << 16);
+ }
+ break;
+ case HRTIM_FAULT_4:
+ {
+ HRTIM_fltinr1 &= ~HRTIM_FLTINR1_FLT4E;
+ HRTIM_fltinr1 |= (Enable << 24);
+ }
+ break;
+ case HRTIM_FAULT_5:
+ {
+ HRTIM_fltinr2 &= ~HRTIM_FLTINR2_FLT5E;
+ HRTIM_fltinr2 |= Enable;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.FLTINxR1 = HRTIM_fltinr1;
+ HRTIMx->HRTIM_COMMON.FLTINxR2 = HRTIM_fltinr2;
+}
+
+/**
+ * @brief Configures both the ADC trigger register update source and the ADC
+ * trigger source.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param ADC trigger: ADC trigger to configure
+ * This parameter can be one of the following values:
+ * @arg HRTIM_ADCTRIGGER_1: ADC trigger 1
+ * @arg HRTIM_ADCTRIGGER_2: ADC trigger 2
+ * @arg HRTIM_ADCTRIGGER_3: ADC trigger 3
+ * @arg HRTIM_ADCTRIGGER_4: ADC trigger 4
+ * @param pADCTriggerCfg: pointer to the ADC trigger configuration structure
+ * @retval None
+ */
+void HRTIM_ADCTriggerConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg)
+{
+ uint32_t HRTIM_cr1;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_ADCTRIGGER(ADCTrigger));
+ assert_param(IS_HRTIM_ADCTRIGGERUPDATE(pADCTriggerCfg->UpdateSource));
+
+ /* Set the ADC trigger update source */
+ HRTIM_cr1 = HRTIMx->HRTIM_COMMON.CR1;
+
+ switch (ADCTrigger)
+ {
+ case HRTIM_ADCTRIGGER_1:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC1USRC);
+ HRTIM_cr1 |= pADCTriggerCfg->UpdateSource;
+
+ /* Set the ADC trigger 1 source */
+ HRTIMx->HRTIM_COMMON.ADC1R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_2:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC2USRC);
+ HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 3);
+
+ /* Set the ADC trigger 2 source */
+ HRTIMx->HRTIM_COMMON.ADC2R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ case HRTIM_ADCTRIGGER_3:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC3USRC);
+ HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 6);
+
+ /* Set the ADC trigger 3 source */
+ HRTIMx->HRTIM_COMMON.ADC3R = pADCTriggerCfg->Trigger;
+ }
+ case HRTIM_ADCTRIGGER_4:
+ {
+ HRTIM_cr1 &= ~(HRTIM_CR1_ADC4USRC);
+ HRTIM_cr1 |= (pADCTriggerCfg->UpdateSource << 9);
+
+ /* Set the ADC trigger 4 source */
+ HRTIMx->HRTIM_COMMON.ADC4R = pADCTriggerCfg->Trigger;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.CR1 = HRTIM_cr1;
+}
+
+
+/**
+ * @brief Enables or disables the HRTIMx burst mode controller.
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Enable: Burst mode controller enabling
+ * This parameter can be one of the following values:
+ * @arg HRTIM_BURSTMODECTL_ENABLED: Burst mode enabled
+ * @arg HRTIM_BURSTMODECTL_DISABLED: Burst mode disabled
+ * @retval None
+ */
+void HRTIM_BurstModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Enable)
+{
+ uint32_t HRTIM_bmcr;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_BURSTMODECTL(Enable));
+
+ /* Enable/Disable the burst mode controller */
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+ HRTIM_bmcr &= ~(HRTIM_BMCR_BME);
+ HRTIM_bmcr |= Enable;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+}
+
+/**
+ * @brief Triggers a software capture on the designed capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureUnit: Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval None
+ * @note The 'software capture' bit in the capure configuration register is
+ * automatically reset by hardware
+ */
+void HRTIM_SoftwareCapture(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ /* Force a software capture on concerned capture unit */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR |= HRTIM_CPT1CR_SWCPT;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR |= HRTIM_CPT2CR_SWCPT;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Triggers the update of the registers of one or several timers
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToUpdate: timers concerned with the software register update
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMERUPDATE_MASTER
+ * @arg HRTIM_TIMERUPDATE_A
+ * @arg HRTIM_TIMERUPDATE_B
+ * @arg HRTIM_TIMERUPDATE_C
+ * @arg HRTIM_TIMERUPDATE_D
+ * @arg HRTIM_TIMERUPDATE_E
+ * @retval None
+ * @note The 'software update' bits in the HRTIMx control register 2 register are
+ * automatically reset by hardware
+ */
+void HRTIM_SoftwareUpdate(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToUpdate)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERUPDATE(TimersToUpdate));
+
+ /* Force timer(s) registers update */
+ HRTIMx->HRTIM_COMMON.CR2 |= TimersToUpdate;
+
+}
+
+/**
+ * @brief Triggers the reset of one or several timers
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimersToUpdate: timers concerned with the software counter reset
+ * This parameter can be any combination of the following values:
+ * @arg HRTIM_TIMER_MASTER
+ * @arg HRTIM_TIMER_A
+ * @arg HRTIM_TIMER_B
+ * @arg HRTIM_TIMER_C
+ * @arg HRTIM_TIMER_D
+ * @arg HRTIM_TIMER_E
+ * @retval None
+ * @note The 'software reset' bits in the HRTIMx control register 2 are
+ * automatically reset by hardware
+ */
+void HRTIM_SoftwareReset(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimersToReset)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMERRESET(TimersToReset));
+
+ /* Force timer(s) registers update */
+ HRTIMx->HRTIM_COMMON.CR2 |= TimersToReset;
+
+}
+
+/**
+ * @brief Forces the timer output to its active or inactive state
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @param OutputLevel: indicates whether the output is forced to its active or inactive state
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUTLEVEL_ACTIVE: output is forced to its active state
+ * @arg HRTIM_OUTPUTLEVEL_INACTIVE: output is forced to its inactive state
+ * @retval None
+ * @note The 'software set/reset trigger' bit in the output set/reset registers
+ * is automatically reset by hardware
+ */
+void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel)
+{
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+ assert_param(IS_HRTIM_OUTPUTLEVEL(OutputLevel));
+
+ /* Force timer output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R |= HRTIM_SET1R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R |= HRTIM_RST1R_SRT;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if (OutputLevel == HRTIM_OUTPUTLEVEL_ACTIVE)
+ {
+ /* Force output to its active state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R |= HRTIM_SET2R_SST;
+ }
+ else
+ {
+ /* Force output to its inactive state */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R |= HRTIM_RST2R_SRT;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup HRTIM_Group4 Peripheral State methods
+ * @brief Peripheral State functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Peripheral State methods #####
+ ===============================================================================
+ [..]
+ This subsection permit to get in run-time the status of the peripheral
+ and the data flow.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Returns actual value of the capture register of the designated capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param CaptureUnit: Capture unit to trig
+ * This parameter can be one of the following values:
+ * @arg HRTIM_CAPTUREUNIT_1: Capture unit 1
+ * @arg HRTIM_CAPTUREUNIT_2: Capture unit 2
+ * @retval Captured value
+ */
+uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit)
+{
+ uint32_t captured_value = 0;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+ assert_param(IS_HRTIM_CAPTUREUNIT(CaptureUnit));
+
+ /* Read captured value */
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xR;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ captured_value = HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xR;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return captured_value;
+}
+
+/**
+ * @brief Returns actual level (active or inactive) of the designated output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output level
+ * @note Returned output level is taken before the output stage (chopper,
+ * polarity).
+ */
+uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the output level */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2CPY) != RESET)
+ {
+ output_level = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ output_level = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return output_level;
+}
+
+/**
+ * @brief Returns actual state (RUN, IDLE, FAULT) of the designated output
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TE1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TE2: Timer E - Output 2
+ * @retval Output state
+ */
+uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t output_bit = 0;
+ uint32_t output_state = HRTIM_OUTPUTSTATE_IDLE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Set output state according to output control status and output disable status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ {
+ output_bit = HRTIM_OENR_TA1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ {
+ output_bit = HRTIM_OENR_TA2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB1:
+ {
+ output_bit = HRTIM_OENR_TB1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TB2:
+ {
+ output_bit = HRTIM_OENR_TB2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC1:
+ {
+ output_bit = HRTIM_OENR_TC1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TC2:
+ {
+ output_bit = HRTIM_OENR_TC2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD1:
+ {
+ output_bit = HRTIM_OENR_TD1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TD2:
+ {
+ output_bit = HRTIM_OENR_TD2OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE1:
+ {
+ output_bit = HRTIM_OENR_TE1OEN;
+ }
+ break;
+ case HRTIM_OUTPUT_TE2:
+ {
+ output_bit = HRTIM_OENR_TE2OEN;
+ }
+ break;
+ default:
+ break;
+ }
+
+ if ((HRTIMx->HRTIM_COMMON.OENR & output_bit) != RESET)
+ {
+ /* Output is enabled: output in RUN state (whatever ouput disable status is)*/
+ output_state = HRTIM_OUTPUTSTATE_RUN;
+ }
+ else
+ {
+ if ((HRTIMx->HRTIM_COMMON.ODSR & output_bit) != RESET)
+ {
+ /* Output is disabled: output in FAULT state */
+ output_state = HRTIM_OUTPUTSTATE_FAULT;
+ }
+ else
+ {
+ /* Output is disabled: output in IDLE state */
+ output_state = HRTIM_OUTPUTSTATE_IDLE;
+ }
+ }
+
+ return(output_state);
+}
+
+/**
+ * @brief Returns the level (active or inactive) of the designated output
+ * when the delayed protection was triggered
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @param Output: Timer output
+ * This parameter can be one of the following values:
+ * @arg HRTIM_OUTPUT_TA1: Timer A - Output 1
+ * @arg HRTIM_OUTPUT_TA2: Timer A - Output 2
+ * @arg HRTIM_OUTPUT_TB1: Timer B - Output 1
+ * @arg HRTIM_OUTPUT_TB2: Timer B - Output 2
+ * @arg HRTIM_OUTPUT_TC1: Timer C - Output 1
+ * @arg HRTIM_OUTPUT_TC2: Timer C - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer D - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer D - Output 2
+ * @arg HRTIM_OUTPUT_TD1: Timer E - Output 1
+ * @arg HRTIM_OUTPUT_TD2: Timer E - Output 2
+ * @retval Delayed protection status
+ */
+uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output)
+{
+ uint32_t delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+
+ /* Check parameters */
+ assert_param(IS_HRTIM_TIMER_OUTPUT(TimerIdx, Output));
+
+ /* Read the delayed protection status */
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O1STAT) != RESET)
+ {
+ /* Output 1 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 1 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ if ((HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_O2STAT) != RESET)
+ {
+ /* Output 2 was active when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_ACTIVE;
+ }
+ else
+ {
+ /* Output 2 was inactive when the delayed idle protection was triggered */
+ delayed_protection_status = HRTIM_OUTPUTLEVEL_INACTIVE;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return delayed_protection_status;
+}
+
+/**
+ * @brief Returns the actual status (active or inactive) of the burst mode controller
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @retval Burst mode controller status
+ */
+uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef * HRTIMx)
+{
+ uint32_t burst_mode_status;
+
+ /* Read burst mode status */
+ burst_mode_status = (HRTIMx->HRTIM_COMMON.BMCR & HRTIM_BMCR_BMSTAT);
+
+ return burst_mode_status;
+}
+
+/**
+ * @brief Indicates on which output the signal is currently active (when the
+ * push pull mode is enabled)
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval Burst mode controller status
+ */
+uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx)
+{
+ uint32_t current_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ current_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_CPPSTAT);
+
+ return current_pushpull_status;
+}
+
+
+/**
+ * @brief Indicates on which output the signal was applied, in push-pull mode
+ balanced fault mode or delayed idle mode, when the protection was triggered
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * This parameter can be one of the following values:
+ * @arg 0x0 to 0x4 for timers A to E
+ * @retval Idle Push Pull Status
+ */
+uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx)
+{
+ uint32_t idle_pushpull_status;
+
+ /* Check the parameters */
+ assert_param(IS_HRTIM_TIMING_UNIT(TimerIdx));
+
+ /* Read current push pull status */
+ idle_pushpull_status = (HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxISR & HRTIM_TIMISR_IPPSTAT);
+
+ return idle_pushpull_status;
+}
+
+/**
+ * @brief Configures the master timer time base
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @retval None
+ */
+void HRTIM_MasterBase_Config(HRTIM_TypeDef * HRTIMx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Set the prescaler ratio */
+ HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CK_PSC);
+ HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
+
+ /* Set the operating mode */
+ HRTIMx->HRTIM_MASTER.MCR &= (uint32_t) ~(HRTIM_MCR_CONT | HRTIM_MCR_RETRIG);
+ HRTIMx->HRTIM_MASTER.MCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_MASTER.MPER = HRTIM_BaseInitStruct->Period;
+ HRTIMx->HRTIM_MASTER.MREP = HRTIM_BaseInitStruct->RepetitionCounter;
+}
+
+/**
+ * @brief Configures timing unit (timer A to timer E) time base
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @retval None
+ */
+void HRTIM_TimingUnitBase_Config(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct)
+{
+ /* Set the prescaler ratio */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CK_PSC);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->PrescalerRatio;
+
+ /* Set the operating mode */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR &= (uint32_t) ~(HRTIM_TIMCR_CONT | HRTIM_TIMCR_RETRIG);
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR |= (uint32_t)HRTIM_BaseInitStruct->Mode;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].PERxR = HRTIM_BaseInitStruct->Period;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].REPxR = HRTIM_BaseInitStruct->RepetitionCounter;
+}
+
+/**
+ * @brief Configures the master timer in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param pTimerInit: pointer to the timer initialization data structure
+ * @retval None
+ */
+void HRTIM_MasterWaveform_Config(HRTIM_TypeDef * HRTIMx,
+ HRTIM_TimerInitTypeDef * pTimerInit)
+{
+ uint32_t HRTIM_mcr;
+ uint32_t HRTIM_bmcr;
+
+ /* Configure master timer */
+ HRTIM_mcr = HRTIMx->HRTIM_MASTER.MCR;
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+
+ /* Enable/Disable the half mode */
+ HRTIM_mcr &= ~(HRTIM_MCR_HALF);
+ HRTIM_mcr |= pTimerInit->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNCSTRTM);
+ HRTIM_mcr |= pTimerInit->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ HRTIM_mcr &= ~(HRTIM_MCR_SYNCRSTM);
+ HRTIM_mcr |= pTimerInit->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ HRTIM_mcr &= ~(HRTIM_MCR_DACSYNC);
+ HRTIM_mcr |= pTimerInit->DACSynchro;
+
+ /* Enable/Disable preload mechanism for timer registers */
+ HRTIM_mcr &= ~(HRTIM_MCR_PREEN);
+ HRTIM_mcr |= pTimerInit->PreloadEnable;
+
+ /* Master timer registers update handling */
+ HRTIM_mcr &= ~(HRTIM_MCR_BRSTDMA);
+ HRTIM_mcr |= (pTimerInit->UpdateGating << 2);
+
+ /* Enable/Disable registers update on repetition */
+ HRTIM_mcr &= ~(HRTIM_MCR_MREPU);
+ HRTIM_mcr |= pTimerInit->RepetitionUpdate;
+
+ /* Set the timer burst mode */
+ HRTIM_bmcr &= ~(HRTIM_BMCR_MTBM);
+ HRTIM_bmcr |= pTimerInit->BurstMode;
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_MASTER.MCR = HRTIM_mcr;
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+
+}
+
+/**
+ * @brief Configures timing unit (timer A to timer E) in waveform mode
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param pTimerInit: pointer to the timer initialization data structure
+ * @retval None
+ */
+void HRTIM_TimingUnitWaveform_Config(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_TimerInitTypeDef * pTimerInit)
+{
+ uint32_t HRTIM_timcr;
+ uint32_t HRTIM_bmcr;
+
+ /* Configure timing unit */
+ HRTIM_timcr = HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR;
+ HRTIM_bmcr = HRTIMx->HRTIM_COMMON.BMCR;
+
+ /* Enable/Disable the half mode */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_HALF);
+ HRTIM_timcr |= pTimerInit->HalfModeEnable;
+
+ /* Enable/Disable the timer start upon synchronization event reception */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCSTRT);
+ HRTIM_timcr |= pTimerInit->StartOnSync;
+
+ /* Enable/Disable the timer reset upon synchronization event reception */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_SYNCRST);
+ HRTIM_timcr |= pTimerInit->ResetOnSync;
+
+ /* Enable/Disable the DAC synchronization event generation */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_DACSYNC);
+ HRTIM_timcr |= pTimerInit->DACSynchro;
+
+ /* Enable/Disable preload mechanism for timer registers */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_PREEN);
+ HRTIM_timcr |= pTimerInit->PreloadEnable;
+
+ /* Timing unit registers update handling */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_UPDGAT);
+ HRTIM_timcr |= pTimerInit->UpdateGating;
+
+ /* Enable/Disable registers update on repetition */
+ HRTIM_timcr &= ~(HRTIM_TIMCR_TREPU);
+ if (pTimerInit->RepetitionUpdate == HRTIM_UPDATEONREPETITION_ENABLED)
+ {
+ HRTIM_timcr |= HRTIM_TIMCR_TREPU;
+ }
+
+ /* Set the timer burst mode */
+ switch (TimerIdx)
+ {
+ case HRTIM_TIMERINDEX_TIMER_A:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TABM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 1);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_B:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TBBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 2);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_C:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TCBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 3);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_D:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TDBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 4);
+ }
+ break;
+ case HRTIM_TIMERINDEX_TIMER_E:
+ {
+ HRTIM_bmcr &= ~(HRTIM_BMCR_TEBM);
+ HRTIM_bmcr |= ( pTimerInit->BurstMode << 5);
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Update the HRTIMx registers */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].TIMxCR = HRTIM_timcr;
+ HRTIMx->HRTIM_COMMON.BMCR = HRTIM_bmcr;
+}
+
+/**
+ * @brief Configures a compare unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param CompareUnit: Compare unit identifier
+ * @param pCompareCfg: pointer to the compare unit configuration data structure
+ * @retval None
+ */
+void HRTIM_CompareUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef * pCompareCfg)
+{
+ if (TimerIdx == HRTIM_TIMERINDEX_MASTER)
+ {
+ /* Configure the compare unit of the master timer */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP1R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP2R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP3R = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ HRTIMx->HRTIM_MASTER.MCMP4R = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+ else
+ {
+ /* Configure the compare unit of the timing unit */
+ switch (CompareUnit)
+ {
+ case HRTIM_COMPAREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP1xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP2xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_3:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP3xR = pCompareCfg->CompareValue;
+ }
+ break;
+ case HRTIM_COMPAREUNIT_4:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CMP4xR = pCompareCfg->CompareValue;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+/**
+ * @brief Configures a capture unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param CaptureUnit: Capture unit identifier
+ * @param pCaptureCfg: pointer to the compare unit configuration data structure
+ * @retval None
+ */
+void HRTIM_CaptureUnitConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ uint32_t Event)
+{
+ uint32_t CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ CaptureTrigger = HRTIM_CAPTURETRIGGER_EEV_10;
+ }
+ break;
+ default:
+ break;
+
+ }
+ switch (CaptureUnit)
+ {
+ case HRTIM_CAPTUREUNIT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT1xCR = CaptureTrigger;
+ }
+ break;
+ case HRTIM_CAPTUREUNIT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].CPT2xCR = CaptureTrigger;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the output of a timing unit
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param Output: timing unit output identifier
+ * @param pOutputCfg: pointer to the output configuration data structure
+ * @retval None
+ */
+void HRTIM_OutputConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg)
+{
+ uint32_t HRTIM_outr;
+ uint32_t shift = 0;
+
+ HRTIM_outr = HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR;
+
+ switch (Output)
+ {
+ case HRTIM_OUTPUT_TA1:
+ case HRTIM_OUTPUT_TB1:
+ case HRTIM_OUTPUT_TC1:
+ case HRTIM_OUTPUT_TD1:
+ case HRTIM_OUTPUT_TE1:
+ {
+ /* Set the output set/reset crossbar */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx1R = pOutputCfg->SetSource;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx1R = pOutputCfg->ResetSource;
+
+ shift = 0;
+ }
+ break;
+ case HRTIM_OUTPUT_TA2:
+ case HRTIM_OUTPUT_TB2:
+ case HRTIM_OUTPUT_TC2:
+ case HRTIM_OUTPUT_TD2:
+ case HRTIM_OUTPUT_TE2:
+ {
+ /* Set the output set/reset crossbar */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].SETx2R = pOutputCfg->SetSource;
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTx2R = pOutputCfg->ResetSource;
+
+ shift = 16;
+ }
+ break;
+ default:
+ break;
+ }
+
+ /* Clear output config */
+ HRTIM_outr &= ~((HRTIM_OUTR_POL1 |
+ HRTIM_OUTR_IDLM1 |
+ HRTIM_OUTR_IDLES1|
+ HRTIM_OUTR_FAULT1|
+ HRTIM_OUTR_CHP1 |
+ HRTIM_OUTR_DIDL1) << shift);
+
+ /* Set the polarity */
+ HRTIM_outr |= (pOutputCfg->Polarity << shift);
+
+ /* Set the IDLE mode */
+ HRTIM_outr |= (pOutputCfg->IdleMode << shift);
+
+ /* Set the IDLE state */
+ HRTIM_outr |= (pOutputCfg->IdleState << shift);
+
+ /* Set the FAULT state */
+ HRTIM_outr |= (pOutputCfg->FaultState << shift);
+
+ /* Set the chopper mode */
+ HRTIM_outr |= (pOutputCfg->ChopperModeEnable << shift);
+
+ /* Set the burst mode entry mode */
+ HRTIM_outr |= (pOutputCfg->BurstModeEntryDelayed << shift);
+
+ /* Update HRTIMx register */
+ HRTIMx->HRTIM_TIMERx[TimerIdx].OUTxR = HRTIM_outr;
+}
+
+/**
+ * @brief Configures an external event channel
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param Event: Event channel identifier
+ * @param pEventCfg: pointer to the event channel configuration data structure
+ * @retval None
+ */
+static void HRTIM_ExternalEventConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef *pEventCfg)
+{
+ uint32_t hrtim_eecr1;
+ uint32_t hrtim_eecr2;
+ uint32_t hrtim_eecr3;
+
+ /* Configure external event channel */
+ hrtim_eecr1 = HRTIMx->HRTIM_COMMON.EECR1;
+ hrtim_eecr2 = HRTIMx->HRTIM_COMMON.EECR2;
+ hrtim_eecr3 = HRTIMx->HRTIM_COMMON.EECR3;
+
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE1SRC | HRTIM_EECR1_EE1POL | HRTIM_EECR1_EE1SNS | HRTIM_EECR1_EE1FAST);
+ hrtim_eecr1 |= pEventCfg->Source;
+ hrtim_eecr1 |= pEventCfg->Polarity;
+ hrtim_eecr1 |= pEventCfg->Sensitivity;
+ /* Update the HRTIM registers (all bit fields but EE1FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE1FAST bit) */
+ hrtim_eecr1 |= pEventCfg->FastMode;
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE2SRC | HRTIM_EECR1_EE2POL | HRTIM_EECR1_EE2SNS | HRTIM_EECR1_EE2FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 6);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 6);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 6);
+ /* Update the HRTIM registers (all bit fields but EE2FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE2FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 6);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE3SRC | HRTIM_EECR1_EE3POL | HRTIM_EECR1_EE3SNS | HRTIM_EECR1_EE3FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 12);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 12);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 12);
+ /* Update the HRTIM registers (all bit fields but EE3FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE3FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 12);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE4SRC | HRTIM_EECR1_EE4POL | HRTIM_EECR1_EE4SNS | HRTIM_EECR1_EE4FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 18);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 18);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 18);
+ /* Update the HRTIM registers (all bit fields but EE4FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE4FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 18);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ hrtim_eecr1 &= ~(HRTIM_EECR1_EE5SRC | HRTIM_EECR1_EE5POL | HRTIM_EECR1_EE5SNS | HRTIM_EECR1_EE5FAST);
+ hrtim_eecr1 |= (pEventCfg->Source << 24);
+ hrtim_eecr1 |= (pEventCfg->Polarity << 24);
+ hrtim_eecr1 |= (pEventCfg->Sensitivity << 24);
+ /* Update the HRTIM registers (all bit fields but EE5FAST bit) */
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ /* Update the HRTIM registers (EE5FAST bit) */
+ hrtim_eecr1 |= (pEventCfg->FastMode << 24);
+ HRTIMx->HRTIM_COMMON.EECR1 = hrtim_eecr1;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE6SRC | HRTIM_EECR2_EE6POL | HRTIM_EECR2_EE6SNS);
+ hrtim_eecr2 |= pEventCfg->Source;
+ hrtim_eecr2 |= pEventCfg->Polarity;
+ hrtim_eecr2 |= pEventCfg->Sensitivity;
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE6F);
+ hrtim_eecr3 |= pEventCfg->Filter;
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE7SRC | HRTIM_EECR2_EE7POL | HRTIM_EECR2_EE7SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 6);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 6);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 6);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE7F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 6);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE8SRC | HRTIM_EECR2_EE8POL | HRTIM_EECR2_EE8SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 12);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 12);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 12);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE8F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 12);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE9SRC | HRTIM_EECR2_EE9POL | HRTIM_EECR2_EE9SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 18);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 18);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 18);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE9F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 18);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ hrtim_eecr2 &= ~(HRTIM_EECR2_EE10SRC | HRTIM_EECR2_EE10POL | HRTIM_EECR2_EE10SNS);
+ hrtim_eecr2 |= (pEventCfg->Source << 24);
+ hrtim_eecr2 |= (pEventCfg->Polarity << 24);
+ hrtim_eecr2 |= (pEventCfg->Sensitivity << 24);
+ hrtim_eecr3 &= ~(HRTIM_EECR3_EE10F);
+ hrtim_eecr3 |= (pEventCfg->Filter << 24);
+ /* Update the HRTIM registers */
+ HRTIMx->HRTIM_COMMON.EECR2 = hrtim_eecr2;
+ HRTIMx->HRTIM_COMMON.EECR3 = hrtim_eecr3;
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/**
+ * @brief Configures the timer counter reset
+ * @param HRTIMx: pointer to HRTIMx peripheral
+ * @param TimerIdx: Timer index
+ * @param Event: Event channel identifier
+ * @retval None
+ */
+void HRTIM_TIM_ResetConfig(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t Event)
+{
+ switch (Event)
+ {
+ case HRTIM_EVENT_1:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_1;
+ }
+ break;
+ case HRTIM_EVENT_2:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_2;
+ }
+ break;
+ case HRTIM_EVENT_3:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_3;
+ }
+ break;
+ case HRTIM_EVENT_4:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_4;
+ }
+ break;
+ case HRTIM_EVENT_5:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_5;
+ }
+ break;
+ case HRTIM_EVENT_6:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_6;
+ }
+ break;
+ case HRTIM_EVENT_7:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_7;
+ }
+ break;
+ case HRTIM_EVENT_8:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_8;
+ }
+ break;
+ case HRTIM_EVENT_9:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_9;
+ }
+ break;
+ case HRTIM_EVENT_10:
+ {
+ HRTIMx->HRTIM_TIMERx[TimerIdx].RSTxR = HRTIM_TIMRESETTRIGGER_EEV_10;
+ }
+ break;
+ default:
+ break;
+ }
+}
+/**
+ * @}
+ */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
+
+
+
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_hrtim.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_hrtim.h
new file mode 100644
index 0000000000..87a57b5faf
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_hrtim.h
@@ -0,0 +1,2723 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_hrtim.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the HRTIM firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_HRTIM_H
+#define __STM32F30x_HRTIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup ADC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief HRTIM Configuration Structure definition - Time base related parameters
+ */
+typedef struct
+{
+ uint32_t Period; /*!< Specifies the timer period
+ The period value must be above 3 periods of the fHRTIM clock.
+ Maximum value is = 0xFFDF */
+ uint32_t RepetitionCounter; /*!< Specifies the timer repetition period
+ This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
+ uint32_t PrescalerRatio; /*!< Specifies the timer clock prescaler ratio.
+ This parameter can be any value of @ref HRTIM_PrescalerRatio */
+ uint32_t Mode; /*!< Specifies the counter operating mode
+ This parameter can be any value of @ref HRTIM_Mode */
+} HRTIM_BaseInitTypeDef;
+/**
+ * @brief Waveform mode initialization parameters definition
+ */
+typedef struct {
+ uint32_t HalfModeEnable; /*!< Specifies whether or not half mode is enabled
+ This parameter can be a combination of @ref HRTIM_HalfModeEnable */
+ uint32_t StartOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
+ This parameter can be a combination of @ref HRTIM_StartOnSyncInputEvent */
+ uint32_t ResetOnSync; /*!< Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled)
+ This parameter can be a combination of @ref HRTIM_ResetOnSyncInputEvent */
+ uint32_t DACSynchro; /*!< Indicates whether or not the a DAC synchronization event is generated
+ This parameter can be any value of @ref HRTIM_DACSynchronization */
+ uint32_t PreloadEnable; /*!< Specifies whether or not register preload is enabled
+ This parameter can be a combination of @ref HRTIM_RegisterPreloadEnable */
+ uint32_t UpdateGating; /*!< Specifies how the update occurs with respect to a burst DMA transaction or
+ update enable inputs (Slave timers only)
+ This parameter can be any value of @ref HRTIM_UpdateGating */
+ uint32_t BurstMode; /*!< Specifies how the timer behaves during a burst mode operation
+ This parameter can be a combination of @ref HRTIM_TimerBurstMode */
+ uint32_t RepetitionUpdate; /*!< Specifies whether or not registers update is triggered by the repetition event
+ This parameter can be a combination of @ref HRTIM_TimerRepetitionUpdate */
+} HRTIM_TimerInitTypeDef;
+
+/**
+ * @brief Basic output compare mode configuration definition
+ */
+typedef struct {
+ uint32_t Mode; /*!< Specifies the output compare mode (toggle, active, inactive)
+ This parameter can be a combination of @ref HRTIM_BasicOCMode */
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_OutputIDLEState */
+} HRTIM_BasicOCChannelCfgTypeDef;
+
+/**
+ * @brief Basic PWM output mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t Polarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_OutputPolarity */
+ uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_OutputIDLEState */
+} HRTIM_BasicPWMChannelCfgTypeDef;
+
+/**
+ * @brief Basic capture mode configuration definition
+ */
+typedef struct {
+ uint32_t CaptureUnit; /*!< Specifies the external event Channel
+ This parameter can be any 'EEVx' value of @ref HRTIM_CaptureUnit */
+ uint32_t Event; /*!< Specifies the external event triggering the capture
+ This parameter can be any 'EEVx' value of @ref HRTIM_ExternalEventChannels */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
+ This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
+ This parameter can be a value of @ref HRTIM_ExternalEventFilter */
+} HRTIM_BasicCaptureChannelCfgTypeDef;
+
+/**
+ * @brief Basic One Pulse mode configuration definition
+ */
+typedef struct {
+ uint32_t Pulse; /*!< Specifies the compare value to be loaded into the Compare Register.
+ The compare value must be above or equal to 3 periods of the fHRTIM clock */
+ uint32_t OutputPolarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t OutputIdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_Output_IDLE_State */
+ uint32_t Event; /*!< Specifies the external event triggering the pulse generation
+ This parameter can be any 'EEVx' value of @ref HRTIM_Capture_Unit_Trigger */
+ uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity)
+ This parameter can be a value of @ref HRTIM_ExternalEventPolarity */
+ uint32_t EventSensitivity; /*!< Specifies the sensitivity of the external event
+ This parameter can be a value of @ref HRTIM_ExternalEventSensitivity */
+ uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter
+ This parameter can be a value of @ref HRTIM_ExternalEventFilter */
+} HRTIM_BasicOnePulseChannelCfgTypeDef;
+
+/**
+ * @brief Timer configuration definition
+ */
+typedef struct {
+ uint32_t PushPull; /*!< Specifies whether or not the push-pull mode is enabled
+ This parameter can be a value of @ref HRTIM_TimerPushPullMode */
+ uint32_t FaultEnable; /*!< Specifies which fault channels are enabled for the timer
+ This parameter can be a combination of @ref HRTIM_TimerFaultEnabling */
+ uint32_t FaultLock; /*!< Specifies whether or not fault enabling status is write protected
+ This parameter can be a value of @ref HRTIM_TimerFaultLock */
+ uint32_t DeadTimeInsertion; /*!< Specifies whether or not dead time insertion is enabled for the timer
+ This parameter can be a value of @ref HRTIM_TimerDeadtimeInsertion */
+ uint32_t DelayedProtectionMode; /*!< Specifies the delayed protection mode
+ This parameter can be a value of @ref HRTIM_TimerDelayedProtectionMode */
+ uint32_t UpdateTrigger; /*!< Specifies source(s) triggering the timer registers update
+ This parameter can be a combination of @ref HRTIM_TimerUpdateTrigger */
+ uint32_t ResetTrigger; /*!< Specifies source(s) triggering the timer counter reset
+ This parameter can be a combination of @ref HRTIM_TimerResetTrigger */
+ uint32_t ResetUpdate; /*!< Specifies whether or not registers update is triggered when the timer counter is reset
+ This parameter can be a combination of @ref HRTIM_TimerResetUpdate */
+} HRTIM_TimerCfgTypeDef;
+
+/**
+ * @brief Compare unit configuration definition
+ */
+typedef struct {
+ uint32_t CompareValue; /*!< Specifies the compare value of the timer compare unit
+ the minimum value must be greater than or equal to 3 periods of the fHRTIM clock
+ the maximum value must be less than or equal to 0xFFFF - 1 periods of the fHRTIM clock */
+ uint32_t AutoDelayedMode; /*!< Specifies the auto delayed mode for compare unit 2 or 4
+ This parameter can be a value of @ref HRTIM_CompareUnitAutoDelayedMode */
+ uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected
+ CompareValue + AutoDelayedTimeout must be less than 0xFFFF */
+} HRTIM_CompareCfgTypeDef;
+
+/**
+ * @brief Capture unit configuration definition
+ */
+typedef struct {
+ uint32_t Trigger; /*!< Specifies source(s) triggering the capture
+ This parameter can be a combination of @ref HRTIM_CaptureUnitTrigger */
+} HRTIM_CaptureCfgTypeDef;
+
+/**
+ * @brief Output configuration definition
+ */
+typedef struct {
+ uint32_t Polarity; /*!< Specifies the output polarity
+ This parameter can be any value of @ref HRTIM_Output_Polarity */
+ uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level
+ This parameter can be any value of @ref HRTIM_OutputSetSource */
+ uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level
+ This parameter can be any value of @ref HRTIM_OutputResetSource */
+ uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation
+ This parameter can be any value of @ref HRTIM_OutputIdleMode */
+ uint32_t IdleState; /*!< Specifies whether the output level is active or inactive when in IDLE state
+ This parameter can be any value of @ref HRTIM_OutputIDLEState */
+ uint32_t FaultState; /*!< Specifies whether the output level is active or inactive when in FAULT state
+ This parameter can be any value of @ref HRTIM_OutputFAULTState */
+ uint32_t ChopperModeEnable; /*!< Indicates whether or not the chopper mode is enabled
+ This parameter can be any value of @ref HRTIM_OutputChopperModeEnable */
+ uint32_t BurstModeEntryDelayed; /* !HRTIM_MASTER.MCR |= (__TIMERS__))
+
+/* The counter of a timing unit is disabled only if all the timer outputs */
+/* are disabled and no capture is configured */
+#define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
+#define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
+#define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
+#define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
+#define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
+#define __HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
+ do {\
+ if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_MASTER);\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TAOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_A);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TBOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_B);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TCOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_C);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TDOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_D);\
+ }\
+ }\
+ if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
+ {\
+ if (((__HANDLE__)->HRTIM_COMMON.OENR & HRTIM_TEOEN_MASK) == RESET)\
+ {\
+ ((__HANDLE__)->HRTIM_MASTER.MCR &= ~HRTIM_TIMERID_TIMER_E);\
+ }\
+ }\
+ } while(0)
+
+/* Exported functions --------------------------------------------------------*/
+
+/* Simple time base related functions *****************************************/
+void HRTIM_SimpleBase_Init(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_DeInit(HRTIM_TypeDef* HRTIMx);
+
+void HRTIM_SimpleBaseStart(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
+void HRTIM_SimpleBaseStop(HRTIM_TypeDef *hrtim, uint32_t TimerIdx);
+
+/* Simple output compare related functions ************************************/
+void HRTIM_SimpleOC_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimpleOCChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel,
+ HRTIM_BasicOCChannelCfgTypeDef* pBasicOCChannelCfg);
+
+void HRTIM_SimpleOCStart(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+void HRTIM_SimpleOCStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OCChannel);
+/* Simple PWM output related functions ****************************************/
+void HRTIM_SimplePWM_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimplePWMChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel,
+ HRTIM_BasicPWMChannelCfgTypeDef* pBasicPWMChannelCfg);
+
+void HRTIM_SimplePWMStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+void HRTIM_SimplePWMStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t PWMChannel);
+/* Simple capture related functions *******************************************/
+void HRTIM_SimpleCapture_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimpleCaptureChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel,
+ HRTIM_BasicCaptureChannelCfgTypeDef* pBasicCaptureChannelCfg);
+
+void HRTIM_SimpleCaptureStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+void HRTIM_SimpleCaptureStop(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t CaptureChannel);
+/* SImple one pulse related functions *****************************************/
+void HRTIM_SimpleOnePulse_Init(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct);
+
+void HRTIM_SimpleOnePulseChannelConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel,
+ HRTIM_BasicOnePulseChannelCfgTypeDef* pBasicOnePulseChannelCfg);
+
+void HRTIM_SimpleOnePulseStart(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+void HRTIM_SimpleOnePulseStop(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t OnePulseChannel);
+/* Waveform related functions *************************************************/
+void HRTIM_Waveform_Init(HRTIM_TypeDef * HRTIMx,
+ uint32_t TimerIdx,
+ HRTIM_BaseInitTypeDef* HRTIM_BaseInitStruct,
+ HRTIM_TimerInitTypeDef* HRTIM_TimerInitStruct);
+
+void HRTIM_WaveformTimerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ HRTIM_TimerCfgTypeDef * HRTIM_TimerCfgStruct);
+
+void HRTIM_WaveformCompareConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CompareUnit,
+ HRTIM_CompareCfgTypeDef* pCompareCfg);
+
+void HRTIM_MasterSetCompare(HRTIM_TypeDef * HRTIMx,
+ uint32_t CompareUnit,
+ uint32_t Compare);
+void HRTIM_WaveformCaptureConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit,
+ HRTIM_CaptureCfgTypeDef* pCaptureCfg);
+
+void HRTIM_WaveformOuputConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+void HRTIM_TimerEventFilteringConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Event,
+ HRTIM_TimerEventFilteringCfgTypeDef * pTimerEventFilteringCfg);
+
+void HRTIM_DeadTimeConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ HRTIM_DeadTimeCfgTypeDef* pDeadTimeCfg);
+
+void HRTIM_ChopperModeConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ HRTIM_ChopperModeCfgTypeDef* pChopperModeCfg);
+
+void HRTIM_BurstDMAConfig(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t RegistersToUpdate);
+
+void HRTIM_SynchronizationConfig(HRTIM_TypeDef *HRTIMx,
+ HRTIM_SynchroCfgTypeDef * pSynchroCfg);
+
+void HRTIM_BurstModeConfig(HRTIM_TypeDef *hrtim,
+ HRTIM_BurstModeCfgTypeDef* pBurstModeCfg);
+
+void HRTIM_EventConfig(HRTIM_TypeDef *hrtim,
+ uint32_t Event,
+ HRTIM_EventCfgTypeDef* pEventCfg);
+
+void HRTIM_EventPrescalerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t Prescaler);
+
+void HRTIM_FaultConfig(HRTIM_TypeDef *hrtim,
+ HRTIM_FaultCfgTypeDef* pFaultCfg,
+ uint32_t Fault);
+
+void HRTIM_FaultPrescalerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t Prescaler);
+void HRTIM_FaultModeCtl(HRTIM_TypeDef * HRTIMx, uint32_t Fault, uint32_t Enable);
+
+void HRTIM_ADCTriggerConfig(HRTIM_TypeDef *hrtim,
+ uint32_t ADCTrigger,
+ HRTIM_ADCTriggerCfgTypeDef* pADCTriggerCfg);
+
+void HRTIM_WaveformCounterStart(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToStart);
+
+void HRTIM_WaveformCounterStop(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToStop);
+
+void HRTIM_WaveformOutputStart(HRTIM_TypeDef *hrtim,
+ uint32_t OuputsToStart);
+void HRTIM_WaveformOutputStop(HRTIM_TypeDef * HRTIM_,
+ uint32_t OuputsToStop);
+
+void HRTIM_DLLCalibrationStart(HRTIM_TypeDef *hrtim,
+ uint32_t CalibrationRate);
+
+/* Interrupt/flags and DMA management */
+void HRTIM_ITConfig(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_TIM_IT, FunctionalState NewState);
+void HRTIM_ITCommonConfig(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT, FunctionalState NewState);
+
+void HRTIM_ClearFlag(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
+void HRTIM_ClearCommonFlag(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
+
+void HRTIM_ClearITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
+void HRTIM_ClearCommonITPendingBit(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
+
+FlagStatus HRTIM_GetFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_FLAG);
+FlagStatus HRTIM_GetCommonFlagStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonFLAG);
+
+ITStatus HRTIM_GetITStatus(HRTIM_TypeDef * HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_IT);
+ITStatus HRTIM_GetCommonITStatus(HRTIM_TypeDef * HRTIMx, uint32_t HRTIM_CommonIT);
+
+
+void HRTIM_DMACmd(HRTIM_TypeDef* HRTIMx, uint32_t TimerIdx, uint32_t HRTIM_DMA, FunctionalState NewState);
+
+void HRTIM_BurstModeCtl(HRTIM_TypeDef *hrtim,
+ uint32_t Enable);
+
+void HRTIM_SoftwareCapture(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+void HRTIM_SoftwareUpdate(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToUpdate);
+
+void HRTIM_SoftwareReset(HRTIM_TypeDef *hrtim,
+ uint32_t TimersToReset);
+
+
+uint32_t HRTIM_GetCapturedValue(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t CaptureUnit);
+
+void HRTIM_WaveformOutputConfig(HRTIM_TypeDef * HRTIM_,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ HRTIM_OutputCfgTypeDef * pOutputCfg);
+
+void HRTIM_WaveformSetOutputLevel(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output,
+ uint32_t OutputLevel);
+
+uint32_t HRTIM_WaveformGetOutputLevel(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HRTIM_WaveformGetOutputState(HRTIM_TypeDef * hhrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HRTIM_GetDelayedProtectionStatus(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx,
+ uint32_t Output);
+
+uint32_t HRTIM_GetBurstStatus(HRTIM_TypeDef *hrtim);
+
+uint32_t HRTIM_GetCurrentPushPullStatus(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx);
+
+uint32_t HRTIM_GetIdlePushPullStatus(HRTIM_TypeDef *hrtim,
+ uint32_t TimerIdx);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_HRTIM_H */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_i2c.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_i2c.c
new file mode 100644
index 0000000000..a518889880
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_i2c.c
@@ -0,0 +1,1595 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_i2c.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Inter-Integrated circuit (I2C):
+ * + Initialization and Configuration
+ * + Communications handling
+ * + SMBUS management
+ * + I2C registers management
+ * + Data transfers management
+ * + DMA transfers management
+ * + Interrupts and flags management
+ *
+ * @verbatim
+ ============================================================================
+ ##### How to use this driver #####
+ ============================================================================
+ [..]
+ (#) Enable peripheral clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_I2Cx, ENABLE)
+ function for I2C1 or I2C2.
+ (#) Enable SDA, SCL and SMBA (when used) GPIO clocks using
+ RCC_AHBPeriphClockCmd() function.
+ (#) Peripherals alternate function:
+ (++) Connect the pin to the desired peripherals' Alternate
+ Function (AF) using GPIO_PinAFConfig() function.
+ (++) Configure the desired pin in alternate function by:
+ GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+ (++) Select the type, OpenDrain and speed via
+ GPIO_PuPd, GPIO_OType and GPIO_Speed members
+ (++) Call GPIO_Init() function.
+ (#) Program the Mode, Timing , Own address, Ack and Acknowledged Address
+ using the I2C_Init() function.
+ (#) Optionally you can enable/configure the following parameters without
+ re-initialization (i.e there is no need to call again I2C_Init() function):
+ (++) Enable the acknowledge feature using I2C_AcknowledgeConfig() function.
+ (++) Enable the dual addressing mode using I2C_DualAddressCmd() function.
+ (++) Enable the general call using the I2C_GeneralCallCmd() function.
+ (++) Enable the clock stretching using I2C_StretchClockCmd() function.
+ (++) Enable the PEC Calculation using I2C_CalculatePEC() function.
+ (++) For SMBus Mode:
+ (+++) Enable the SMBusAlert pin using I2C_SMBusAlertCmd() function.
+ (#) Enable the NVIC and the corresponding interrupt using the function
+ I2C_ITConfig() if you need to use interrupt mode.
+ (#) When using the DMA mode
+ (++) Configure the DMA using DMA_Init() function.
+ (++) Active the needed channel Request using I2C_DMACmd() function.
+ (#) Enable the I2C using the I2C_Cmd() function.
+ (#) Enable the DMA using the DMA_Cmd() function when using DMA mode in the
+ transfers.
+ [..]
+ (@) When using I2C in Fast Mode Plus, SCL and SDA pin 20mA current drive capability
+ must be enabled by setting the driving capability control bit in SYSCFG.
+
+ @endverbatim
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_i2c.h"
+#include "stm32f30x_rcc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup I2C
+ * @brief I2C driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK ((uint32_t)0x00CFE0FF) /*I2C_AnalogFilter));
+ assert_param(IS_I2C_DIGITAL_FILTER(I2C_InitStruct->I2C_DigitalFilter));
+ assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+ assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+ assert_param(IS_I2C_ACK(I2C_InitStruct->I2C_Ack));
+ assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+ /* Disable I2Cx Peripheral */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+ /*---------------------------- I2Cx FILTERS Configuration ------------------*/
+ /* Get the I2Cx CR1 value */
+ tmpreg = I2Cx->CR1;
+ /* Clear I2Cx CR1 register */
+ tmpreg &= CR1_CLEAR_MASK;
+ /* Configure I2Cx: analog and digital filter */
+ /* Set ANFOFF bit according to I2C_AnalogFilter value */
+ /* Set DFN bits according to I2C_DigitalFilter value */
+ tmpreg |= (uint32_t)I2C_InitStruct->I2C_AnalogFilter |(I2C_InitStruct->I2C_DigitalFilter << 8);
+
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 = tmpreg;
+
+ /*---------------------------- I2Cx TIMING Configuration -------------------*/
+ /* Configure I2Cx: Timing */
+ /* Set TIMINGR bits according to I2C_Timing */
+ /* Write to I2Cx TIMING */
+ I2Cx->TIMINGR = I2C_InitStruct->I2C_Timing & TIMING_CLEAR_MASK;
+
+ /* Enable I2Cx Peripheral */
+ I2Cx->CR1 |= I2C_CR1_PE;
+
+ /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
+ /* Clear tmpreg local variable */
+ tmpreg = 0;
+ /* Clear OAR1 register */
+ I2Cx->OAR1 = (uint32_t)tmpreg;
+ /* Clear OAR2 register */
+ I2Cx->OAR2 = (uint32_t)tmpreg;
+ /* Configure I2Cx: Own Address1 and acknowledged address */
+ /* Set OA1MODE bit according to I2C_AcknowledgedAddress value */
+ /* Set OA1 bits according to I2C_OwnAddress1 value */
+ tmpreg = (uint32_t)((uint32_t)I2C_InitStruct->I2C_AcknowledgedAddress | \
+ (uint32_t)I2C_InitStruct->I2C_OwnAddress1);
+ /* Write to I2Cx OAR1 */
+ I2Cx->OAR1 = tmpreg;
+ /* Enable Own Address1 acknowledgement */
+ I2Cx->OAR1 |= I2C_OAR1_OA1EN;
+
+ /*---------------------------- I2Cx MODE Configuration ---------------------*/
+ /* Configure I2Cx: mode */
+ /* Set SMBDEN and SMBHEN bits according to I2C_Mode value */
+ tmpreg = I2C_InitStruct->I2C_Mode;
+ /* Write to I2Cx CR1 */
+ I2Cx->CR1 |= tmpreg;
+
+ /*---------------------------- I2Cx ACK Configuration ----------------------*/
+ /* Get the I2Cx CR2 value */
+ tmpreg = I2Cx->CR2;
+ /* Clear I2Cx CR2 register */
+ tmpreg &= CR2_CLEAR_MASK;
+ /* Configure I2Cx: acknowledgement */
+ /* Set NACK bit according to I2C_Ack value */
+ tmpreg |= I2C_InitStruct->I2C_Ack;
+ /* Write to I2Cx CR2 */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Fills each I2C_InitStruct member with its default value.
+ * @param I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+ * @retval None
+ */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+ /*---------------- Reset I2C init structure parameters values --------------*/
+ /* Initialize the I2C_Timing member */
+ I2C_InitStruct->I2C_Timing = 0;
+ /* Initialize the I2C_AnalogFilter member */
+ I2C_InitStruct->I2C_AnalogFilter = I2C_AnalogFilter_Enable;
+ /* Initialize the I2C_DigitalFilter member */
+ I2C_InitStruct->I2C_DigitalFilter = 0;
+ /* Initialize the I2C_Mode member */
+ I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+ /* Initialize the I2C_OwnAddress1 member */
+ I2C_InitStruct->I2C_OwnAddress1 = 0;
+ /* Initialize the I2C_Ack member */
+ I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+ /* Initialize the I2C_AcknowledgedAddress member */
+ I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+ * @brief Enables or disables the specified I2C peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C peripheral */
+ I2Cx->CR1 |= I2C_CR1_PE;
+ }
+ else
+ {
+ /* Disable the selected I2C peripheral */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+ }
+}
+
+
+/**
+ * @brief Enables or disables the specified I2C software reset.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval None
+ */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Disable peripheral */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PE);
+
+ /* Perform a dummy read to delay the disable of peripheral for minimum
+ 3 APB clock cycles to perform the software reset functionality */
+ *(__IO uint32_t *)(uint32_t)I2Cx;
+
+ /* Enable peripheral */
+ I2Cx->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief Enables or disables the specified I2C interrupts.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the I2C interrupts sources to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_ERRI: Error interrupt mask
+ * @arg I2C_IT_TCI: Transfer Complete interrupt mask
+ * @arg I2C_IT_STOPI: Stop Detection interrupt mask
+ * @arg I2C_IT_NACKI: Not Acknowledge received interrupt mask
+ * @arg I2C_IT_ADDRI: Address Match interrupt mask
+ * @arg I2C_IT_RXI: RX interrupt mask
+ * @arg I2C_IT_TXI: TX interrupt mask
+ * @param NewState: new state of the specified I2C interrupts.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C interrupts */
+ I2Cx->CR1 |= I2C_IT;
+ }
+ else
+ {
+ /* Disable the selected I2C interrupts */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_IT);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C Clock stretching.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Clock stretching.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable clock stretching */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_NOSTRETCH);
+ }
+ else
+ {
+ /* Disable clock stretching */
+ I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+ }
+}
+
+/**
+ * @brief Enables or disables I2C wakeup from stop mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx stop mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable wakeup from stop mode */
+ I2Cx->CR1 |= I2C_CR1_WUPEN;
+ }
+ else
+ {
+ /* Disable wakeup from stop mode */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_WUPEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C own address 2.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C own address 2.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable own address 2 */
+ I2Cx->OAR2 |= I2C_OAR2_OA2EN;
+ }
+ else
+ {
+ /* Disable own address 2 */
+ I2Cx->OAR2 &= (uint32_t)~((uint32_t)I2C_OAR2_OA2EN);
+ }
+}
+
+/**
+ * @brief Configures the I2C slave own address 2 and mask.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address to be programmed.
+ * @param Mask: specifies own address 2 mask to be programmed.
+ * This parameter can be one of the following values:
+ * @arg I2C_OA2_NoMask: no mask.
+ * @arg I2C_OA2_Mask01: OA2[1] is masked and don't care.
+ * @arg I2C_OA2_Mask02: OA2[2:1] are masked and don't care.
+ * @arg I2C_OA2_Mask03: OA2[3:1] are masked and don't care.
+ * @arg I2C_OA2_Mask04: OA2[4:1] are masked and don't care.
+ * @arg I2C_OA2_Mask05: OA2[5:1] are masked and don't care.
+ * @arg I2C_OA2_Mask06: OA2[6:1] are masked and don't care.
+ * @arg I2C_OA2_Mask07: OA2[7:1] are masked and don't care.
+ * @retval None
+ */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_OWN_ADDRESS2(Address));
+ assert_param(IS_I2C_OWN_ADDRESS2_MASK(Mask));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->OAR2;
+
+ /* Reset I2Cx OA2 bit [7:1] and OA2MSK bit [1:0] */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_OAR2_OA2 | I2C_OAR2_OA2MSK));
+
+ /* Set I2Cx SADD */
+ tmpreg |= (uint32_t)(((uint32_t)Address & I2C_OAR2_OA2) | \
+ (((uint32_t)Mask << 8) & I2C_OAR2_OA2MSK)) ;
+
+ /* Store the new register value */
+ I2Cx->OAR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the I2C general call mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C general call mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable general call mode */
+ I2Cx->CR1 |= I2C_CR1_GCEN;
+ }
+ else
+ {
+ /* Disable general call mode */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_GCEN);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C slave byte control.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C slave byte control.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable slave byte control */
+ I2Cx->CR1 |= I2C_CR1_SBC;
+ }
+ else
+ {
+ /* Disable slave byte control */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_SBC);
+ }
+}
+
+/**
+ * @brief Configures the slave address to be transmitted after start generation.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address to be programmed.
+ * @note This function should be called before generating start condition.
+ * @retval None
+ */
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->CR2;
+
+ /* Reset I2Cx SADD bit [9:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_SADD);
+
+ /* Set I2Cx SADD */
+ tmpreg |= (uint32_t)((uint32_t)Address & I2C_CR2_SADD);
+
+ /* Store the new register value */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Enables or disables the I2C 10-bit addressing mode for the master.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C 10-bit addressing mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note This function should be called before generating start condition.
+ * @retval None
+ */
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable 10-bit addressing mode */
+ I2Cx->CR2 |= I2C_CR2_ADD10;
+ }
+ else
+ {
+ /* Disable 10-bit addressing mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_ADD10);
+ }
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group2 Communications handling functions
+ * @brief Communications handling functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Communications handling functions #####
+ ===============================================================================
+ [..] This section provides a set of functions that handles I2C communication.
+
+ [..] Automatic End mode is enabled using I2C_AutoEndCmd() function. When Reload
+ mode is enabled via I2C_ReloadCmd() AutoEnd bit has no effect.
+
+ [..] I2C_NumberOfBytesConfig() function set the number of bytes to be transferred,
+ this configuration should be done before generating start condition in master
+ mode.
+
+ [..] When switching from master write operation to read operation in 10Bit addressing
+ mode, master can only sends the 1st 7 bits of the 10 bit address, followed by
+ Read direction by enabling HEADR bit using I2C_10BitAddressHeader() function.
+
+ [..] In master mode, when transferring more than 255 bytes Reload mode should be used
+ to handle communication. In the first phase of transfer, Nbytes should be set to
+ 255. After transferring these bytes TCR flag is set and I2C_TransferHandling()
+ function should be called to handle remaining communication.
+
+ [..] In master mode, when software end mode is selected when all data is transferred
+ TC flag is set I2C_TransferHandling() function should be called to generate STOP
+ or generate ReStart.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the I2C automatic end mode (stop condition is
+ * automatically sent when nbytes data are transferred).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C automatic end mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note This function has effect if Reload mode is disabled.
+ * @retval None
+ */
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Auto end mode */
+ I2Cx->CR2 |= I2C_CR2_AUTOEND;
+ }
+ else
+ {
+ /* Disable Auto end mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_AUTOEND);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C nbytes reload mode.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the nbytes reload mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Auto Reload mode */
+ I2Cx->CR2 |= I2C_CR2_RELOAD;
+ }
+ else
+ {
+ /* Disable Auto Reload mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RELOAD);
+ }
+}
+
+/**
+ * @brief Configures the number of bytes to be transmitted/received.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Number_Bytes: specifies the number of bytes to be programmed.
+ * @retval None
+ */
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->CR2;
+
+ /* Reset I2Cx Nbytes bit [7:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_CR2_NBYTES);
+
+ /* Set I2Cx Nbytes */
+ tmpreg |= (uint32_t)(((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES);
+
+ /* Store the new register value */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @brief Configures the type of transfer request for the master.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Direction: specifies the transfer request direction to be programmed.
+ * This parameter can be one of the following values:
+ * @arg I2C_Direction_Transmitter: Master request a write transfer
+ * @arg I2C_Direction_Receiver: Master request a read transfer
+ * @retval None
+ */
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction)
+{
+/* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_DIRECTION(I2C_Direction));
+
+ /* Test on the direction to set/reset the read/write bit */
+ if (I2C_Direction == I2C_Direction_Transmitter)
+ {
+ /* Request a write Transfer */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_RD_WRN);
+ }
+ else
+ {
+ /* Request a read Transfer */
+ I2Cx->CR2 |= I2C_CR2_RD_WRN;
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication START condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C START condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Generate a START condition */
+ I2Cx->CR2 |= I2C_CR2_START;
+ }
+ else
+ {
+ /* Disable the START condition generation */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_START);
+ }
+}
+
+/**
+ * @brief Generates I2Cx communication STOP condition.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C STOP condition generation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Generate a STOP condition */
+ I2Cx->CR2 |= I2C_CR2_STOP;
+ }
+ else
+ {
+ /* Disable the STOP condition generation */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_STOP);
+ }
+}
+
+/**
+ * @brief Enables or disables the I2C 10-bit header only mode with read direction.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2C 10-bit header only mode.
+ * This parameter can be: ENABLE or DISABLE.
+ * @note This mode can be used only when switching from master transmitter mode
+ * to master receiver mode.
+ * @retval None
+ */
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable 10-bit header only mode */
+ I2Cx->CR2 |= I2C_CR2_HEAD10R;
+ }
+ else
+ {
+ /* Disable 10-bit header only mode */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_HEAD10R);
+ }
+}
+
+/**
+ * @brief Generates I2C communication Acknowledge.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the Acknowledge.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable ACK generation */
+ I2Cx->CR2 &= (uint32_t)~((uint32_t)I2C_CR2_NACK);
+ }
+ else
+ {
+ /* Enable NACK generation */
+ I2Cx->CR2 |= I2C_CR2_NACK;
+ }
+}
+
+/**
+ * @brief Returns the I2C slave matched address .
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the slave matched address .
+ */
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the slave matched address in the SR1 register */
+ return (uint8_t)(((uint32_t)I2Cx->ISR & I2C_ISR_ADDCODE) >> 16) ;
+}
+
+/**
+ * @brief Returns the I2C slave received request.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received request.
+ */
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx)
+{
+ uint32_t tmpreg = 0;
+ uint16_t direction = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the slave matched address in the SR1 register */
+ tmpreg = (uint32_t)(I2Cx->ISR & I2C_ISR_DIR);
+
+ /* If write transfer is requested */
+ if (tmpreg == 0)
+ {
+ /* write transfer is requested */
+ direction = I2C_Direction_Transmitter;
+ }
+ else
+ {
+ /* Read transfer is requested */
+ direction = I2C_Direction_Receiver;
+ }
+ return direction;
+}
+
+/**
+ * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Address: specifies the slave address to be programmed.
+ * @param Number_Bytes: specifies the number of bytes to be programmed.
+ * This parameter must be a value between 0 and 255.
+ * @param ReloadEndMode: new state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg I2C_Reload_Mode: Enable Reload mode .
+ * @arg I2C_AutoEnd_Mode: Enable Automatic end mode.
+ * @arg I2C_SoftEnd_Mode: Enable Software end mode.
+ * @param StartStopMode: new state of the I2C START condition generation.
+ * This parameter can be one of the following values:
+ * @arg I2C_No_StartStop: Don't Generate stop and start condition.
+ * @arg I2C_Generate_Stop: Generate stop condition (Number_Bytes should be set to 0).
+ * @arg I2C_Generate_Start_Read: Generate Restart for read request.
+ * @arg I2C_Generate_Start_Write: Generate Restart for write request.
+ * @retval None
+ */
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_SLAVE_ADDRESS(Address));
+ assert_param(IS_RELOAD_END_MODE(ReloadEndMode));
+ assert_param(IS_START_STOP_MODE(StartStopMode));
+
+ /* Get the CR2 register value */
+ tmpreg = I2Cx->CR2;
+
+ /* clear tmpreg specific bits */
+ tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
+
+ /* update tmpreg */
+ tmpreg |= (uint32_t)(((uint32_t)Address & I2C_CR2_SADD) | (((uint32_t)Number_Bytes << 16 ) & I2C_CR2_NBYTES) | \
+ (uint32_t)ReloadEndMode | (uint32_t)StartStopMode);
+
+ /* update CR2 register */
+ I2Cx->CR2 = tmpreg;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group3 SMBUS management functions
+ * @brief SMBUS management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### SMBUS management functions #####
+ ===============================================================================
+ [..] This section provides a set of functions that handles SMBus communication
+ and timeouts detection.
+
+ [..] The SMBus Device default address (0b1100 001) is enabled by calling I2C_Init()
+ function and setting I2C_Mode member of I2C_InitTypeDef() structure to
+ I2C_Mode_SMBusDevice.
+
+ [..] The SMBus Host address (0b0001 000) is enabled by calling I2C_Init()
+ function and setting I2C_Mode member of I2C_InitTypeDef() structure to
+ I2C_Mode_SMBusHost.
+
+ [..] The Alert Response Address (0b0001 100) is enabled using I2C_SMBusAlertCmd()
+ function.
+
+ [..] To detect cumulative SCL stretch in master and slave mode, TIMEOUTB should be
+ configured (in accordance to SMBus specification) using I2C_TimeoutBConfig()
+ function then I2C_ExtendedClockTimeoutCmd() function should be called to enable
+ the detection.
+
+ [..] SCL low timeout is detected by configuring TIMEOUTB using I2C_TimeoutBConfig()
+ function followed by the call of I2C_ClockTimeoutCmd(). When adding to this
+ procedure the call of I2C_IdleClockTimeoutCmd() function, Bus Idle condition
+ (both SCL and SDA high) is detected also.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables I2C SMBus alert.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx SMBus alert.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable SMBus alert */
+ I2Cx->CR1 |= I2C_CR1_ALERTEN;
+ }
+ else
+ {
+ /* Disable SMBus alert */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_ALERTEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C Clock Timeout (SCL Timeout detection).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx clock Timeout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Clock Timeout */
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIMOUTEN;
+ }
+ else
+ {
+ /* Disable Clock Timeout */
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMOUTEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C Extended Clock Timeout (SCL cumulative Timeout detection).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Extended clock Timeout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Clock Timeout */
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TEXTEN;
+ }
+ else
+ {
+ /* Disable Clock Timeout */
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TEXTEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C Idle Clock Timeout (Bus idle SCL and SDA
+ * high detection).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx Idle clock Timeout.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable Clock Timeout */
+ I2Cx->TIMEOUTR |= I2C_TIMEOUTR_TIDLE;
+ }
+ else
+ {
+ /* Disable Clock Timeout */
+ I2Cx->TIMEOUTR &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIDLE);
+ }
+}
+
+/**
+ * @brief Configures the I2C Bus Timeout A (SCL Timeout when TIDLE = 0 or Bus
+ * idle SCL and SDA high when TIDLE = 1).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Timeout: specifies the TimeoutA to be programmed.
+ * @retval None
+ */
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_TIMEOUT(Timeout));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->TIMEOUTR;
+
+ /* Reset I2Cx TIMEOUTA bit [11:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTA);
+
+ /* Set I2Cx TIMEOUTA */
+ tmpreg |= (uint32_t)((uint32_t)Timeout & I2C_TIMEOUTR_TIMEOUTA) ;
+
+ /* Store the new register value */
+ I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+ * @brief Configures the I2C Bus Timeout B (SCL cumulative Timeout).
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Timeout: specifies the TimeoutB to be programmed.
+ * @retval None
+ */
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_TIMEOUT(Timeout));
+
+ /* Get the old register value */
+ tmpreg = I2Cx->TIMEOUTR;
+
+ /* Reset I2Cx TIMEOUTB bit [11:0] */
+ tmpreg &= (uint32_t)~((uint32_t)I2C_TIMEOUTR_TIMEOUTB);
+
+ /* Set I2Cx TIMEOUTB */
+ tmpreg |= (uint32_t)(((uint32_t)Timeout << 16) & I2C_TIMEOUTR_TIMEOUTB) ;
+
+ /* Store the new register value */
+ I2Cx->TIMEOUTR = tmpreg;
+}
+
+/**
+ * @brief Enables or disables I2C PEC calculation.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC calculation.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable PEC calculation */
+ I2Cx->CR1 |= I2C_CR1_PECEN;
+ }
+ else
+ {
+ /* Disable PEC calculation */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR1_PECEN);
+ }
+}
+
+/**
+ * @brief Enables or disables I2C PEC transmission/reception request.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param NewState: new state of the I2Cx PEC request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable PEC transmission/reception request */
+ I2Cx->CR1 |= I2C_CR2_PECBYTE;
+ }
+ else
+ {
+ /* Disable PEC transmission/reception request */
+ I2Cx->CR1 &= (uint32_t)~((uint32_t)I2C_CR2_PECBYTE);
+ }
+}
+
+/**
+ * @brief Returns the I2C PEC.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the PEC .
+ */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the slave matched address in the SR1 register */
+ return (uint8_t)((uint32_t)I2Cx->PECR & I2C_PECR_PEC);
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group4 I2C registers management functions
+ * @brief I2C registers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### I2C registers management functions #####
+ ===============================================================================
+ [..] This section provides a functions that allow user the management of
+ I2C registers.
+
+@endverbatim
+ * @{
+ */
+
+ /**
+ * @brief Reads the specified I2C register and returns its value.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_Register: specifies the register to read.
+ * This parameter can be one of the following values:
+ * @arg I2C_Register_CR1: CR1 register.
+ * @arg I2C_Register_CR2: CR2 register.
+ * @arg I2C_Register_OAR1: OAR1 register.
+ * @arg I2C_Register_OAR2: OAR2 register.
+ * @arg I2C_Register_TIMINGR: TIMING register.
+ * @arg I2C_Register_TIMEOUTR: TIMEOUTR register.
+ * @arg I2C_Register_ISR: ISR register.
+ * @arg I2C_Register_ICR: ICR register.
+ * @arg I2C_Register_PECR: PECR register.
+ * @arg I2C_Register_RXDR: RXDR register.
+ * @arg I2C_Register_TXDR: TXDR register.
+ * @retval The value of the read register.
+ */
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+ __IO uint32_t tmp = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_REGISTER(I2C_Register));
+
+ tmp = (uint32_t)I2Cx;
+ tmp += I2C_Register;
+
+ /* Return the selected register value */
+ return (*(__IO uint32_t *) tmp);
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Group5 Data transfers management functions
+ * @brief Data transfers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Data transfers management functions #####
+ ===============================================================================
+ [..] This subsection provides a set of functions allowing to manage
+ the I2C data transfers.
+
+ [..] The read access of the I2C_RXDR register can be done using
+ the I2C_ReceiveData() function and returns the received value.
+ Whereas a write access to the I2C_TXDR can be done using I2C_SendData()
+ function and stores the written data into TXDR.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Sends a data byte through the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param Data: Byte to be transmitted..
+ * @retval None
+ */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Write in the DR register the data to be sent */
+ I2Cx->TXDR = (uint8_t)Data;
+}
+
+/**
+ * @brief Returns the most recent received data by the I2Cx peripheral.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @retval The value of the received data.
+ */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+ /* Return the data in the DR register */
+ return (uint8_t)I2Cx->RXDR;
+}
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group6 DMA transfers management functions
+ * @brief DMA transfers management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### DMA transfers management functions #####
+ ===============================================================================
+ [..] This section provides two functions that can be used only in DMA mode.
+ [..] In DMA Mode, the I2C communication can be managed by 2 DMA Channel
+ requests:
+ (#) I2C_DMAReq_Tx: specifies the Tx buffer DMA transfer request.
+ (#) I2C_DMAReq_Rx: specifies the Rx buffer DMA transfer request.
+ [..] In this Mode it is advised to use the following function:
+ (+) I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables the I2C DMA interface.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_DMAReq: specifies the I2C DMA transfer request to be enabled or disabled.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_DMAReq_Tx: Tx DMA transfer request
+ * @arg I2C_DMAReq_Rx: Rx DMA transfer request
+ * @param NewState: new state of the selected I2C DMA transfer request.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+ assert_param(IS_I2C_DMA_REQ(I2C_DMAReq));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected I2C DMA requests */
+ I2Cx->CR1 |= I2C_DMAReq;
+ }
+ else
+ {
+ /* Disable the selected I2C DMA requests */
+ I2Cx->CR1 &= (uint32_t)~I2C_DMAReq;
+ }
+}
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_Group7 Interrupts and flags management functions
+ * @brief Interrupts and flags management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Interrupts and flags management functions #####
+ ===============================================================================
+ [..] This section provides functions allowing to configure the I2C Interrupts
+ sources and check or clear the flags or pending bits status.
+ The user should identify which mode will be used in his application to manage
+ the communication: Polling mode, Interrupt mode or DMA mode(refer I2C_Group6) .
+
+ *** Polling Mode ***
+ ====================
+ [..] In Polling Mode, the I2C communication can be managed by 15 flags:
+ (#) I2C_FLAG_TXE: to indicate the status of Transmit data register empty flag.
+ (#) I2C_FLAG_TXIS: to indicate the status of Transmit interrupt status flag .
+ (#) I2C_FLAG_RXNE: to indicate the status of Receive data register not empty flag.
+ (#) I2C_FLAG_ADDR: to indicate the status of Address matched flag (slave mode).
+ (#) I2C_FLAG_NACKF: to indicate the status of NACK received flag.
+ (#) I2C_FLAG_STOPF: to indicate the status of STOP detection flag.
+ (#) I2C_FLAG_TC: to indicate the status of Transfer complete flag(master mode).
+ (#) I2C_FLAG_TCR: to indicate the status of Transfer complete reload flag.
+ (#) I2C_FLAG_BERR: to indicate the status of Bus error flag.
+ (#) I2C_FLAG_ARLO: to indicate the status of Arbitration lost flag.
+ (#) I2C_FLAG_OVR: to indicate the status of Overrun/Underrun flag.
+ (#) I2C_FLAG_PECERR: to indicate the status of PEC error in reception flag.
+ (#) I2C_FLAG_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+ (#) I2C_FLAG_ALERT: to indicate the status of SMBus Alert flag.
+ (#) I2C_FLAG_BUSY: to indicate the status of Bus busy flag.
+
+ [..] In this Mode it is advised to use the following functions:
+ (+) FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ (+) void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+ [..]
+ (@)Do not use the BUSY flag to handle each data transmission or reception.It is
+ better to use the TXIS and RXNE flags instead.
+
+ *** Interrupt Mode ***
+ ======================
+ [..] In Interrupt Mode, the I2C communication can be managed by 7 interrupt sources
+ and 15 pending bits:
+ [..] Interrupt Source:
+ (#) I2C_IT_ERRI: specifies the interrupt source for the Error interrupt.
+ (#) I2C_IT_TCI: specifies the interrupt source for the Transfer Complete interrupt.
+ (#) I2C_IT_STOPI: specifies the interrupt source for the Stop Detection interrupt.
+ (#) I2C_IT_NACKI: specifies the interrupt source for the Not Acknowledge received interrupt.
+ (#) I2C_IT_ADDRI: specifies the interrupt source for the Address Match interrupt.
+ (#) I2C_IT_RXI: specifies the interrupt source for the RX interrupt.
+ (#) I2C_IT_TXI: specifies the interrupt source for the TX interrupt.
+
+ [..] Pending Bits:
+ (#) I2C_IT_TXIS: to indicate the status of Transmit interrupt status flag.
+ (#) I2C_IT_RXNE: to indicate the status of Receive data register not empty flag.
+ (#) I2C_IT_ADDR: to indicate the status of Address matched flag (slave mode).
+ (#) I2C_IT_NACKF: to indicate the status of NACK received flag.
+ (#) I2C_IT_STOPF: to indicate the status of STOP detection flag.
+ (#) I2C_IT_TC: to indicate the status of Transfer complete flag (master mode).
+ (#) I2C_IT_TCR: to indicate the status of Transfer complete reload flag.
+ (#) I2C_IT_BERR: to indicate the status of Bus error flag.
+ (#) I2C_IT_ARLO: to indicate the status of Arbitration lost flag.
+ (#) I2C_IT_OVR: to indicate the status of Overrun/Underrun flag.
+ (#) I2C_IT_PECERR: to indicate the status of PEC error in reception flag.
+ (#) I2C_IT_TIMEOUT: to indicate the status of Timeout or Tlow detection flag.
+ (#) I2C_IT_ALERT: to indicate the status of SMBus Alert flag.
+
+ [..] In this Mode it is advised to use the following functions:
+ (+) void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+ (+) ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified I2C flag is set or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_FLAG_TXE: Transmit data register empty
+ * @arg I2C_FLAG_TXIS: Transmit interrupt status
+ * @arg I2C_FLAG_RXNE: Receive data register not empty
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_NACKF: NACK received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_TC: Transfer complete (master mode)
+ * @arg I2C_FLAG_TCR: Transfer complete reload
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus Alert
+ * @arg I2C_FLAG_BUSY: Bus busy
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ uint32_t tmpreg = 0;
+ FlagStatus bitstatus = RESET;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+ /* Get the ISR register value */
+ tmpreg = I2Cx->ISR;
+
+ /* Get flag status */
+ tmpreg &= I2C_FLAG;
+
+ if(tmpreg != 0)
+ {
+ /* I2C_FLAG is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_FLAG is reset */
+ bitstatus = RESET;
+ }
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's pending flags.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_FLAG: specifies the flag to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_FLAG_ADDR: Address matched (slave mode)
+ * @arg I2C_FLAG_NACKF: NACK received flag
+ * @arg I2C_FLAG_STOPF: STOP detection flag
+ * @arg I2C_FLAG_BERR: Bus error
+ * @arg I2C_FLAG_ARLO: Arbitration lost
+ * @arg I2C_FLAG_OVR: Overrun/Underrun
+ * @arg I2C_FLAG_PECERR: PEC error in reception
+ * @arg I2C_FLAG_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_FLAG_ALERT: SMBus Alert
+ * @retval The new state of I2C_FLAG (SET or RESET).
+ */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+
+ /* Clear the selected flag */
+ I2Cx->ICR = I2C_FLAG;
+ }
+
+/**
+ * @brief Checks whether the specified I2C interrupt has occurred or not.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg I2C_IT_TXIS: Transmit interrupt status
+ * @arg I2C_IT_RXNE: Receive data register not empty
+ * @arg I2C_IT_ADDR: Address matched (slave mode)
+ * @arg I2C_IT_NACKF: NACK received flag
+ * @arg I2C_IT_STOPF: STOP detection flag
+ * @arg I2C_IT_TC: Transfer complete (master mode)
+ * @arg I2C_IT_TCR: Transfer complete reload
+ * @arg I2C_IT_BERR: Bus error
+ * @arg I2C_IT_ARLO: Arbitration lost
+ * @arg I2C_IT_OVR: Overrun/Underrun
+ * @arg I2C_IT_PECERR: PEC error in reception
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_IT_ALERT: SMBus Alert
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ uint32_t tmpreg = 0;
+ ITStatus bitstatus = RESET;
+ uint32_t enablestatus = 0;
+
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_GET_IT(I2C_IT));
+
+ /* Check if the interrupt source is enabled or not */
+ /* If Error interrupt */
+ if((uint32_t)(I2C_IT & ERROR_IT_MASK))
+ {
+ enablestatus = (uint32_t)((I2C_CR1_ERRIE) & (I2Cx->CR1));
+ }
+ /* If TC interrupt */
+ else if((uint32_t)(I2C_IT & TC_IT_MASK))
+ {
+ enablestatus = (uint32_t)((I2C_CR1_TCIE) & (I2Cx->CR1));
+ }
+ else
+ {
+ enablestatus = (uint32_t)((I2C_IT) & (I2Cx->CR1));
+ }
+
+ /* Get the ISR register value */
+ tmpreg = I2Cx->ISR;
+
+ /* Get flag status */
+ tmpreg &= I2C_IT;
+
+ /* Check the status of the specified I2C flag */
+ if((tmpreg != RESET) && enablestatus)
+ {
+ /* I2C_IT is set */
+ bitstatus = SET;
+ }
+ else
+ {
+ /* I2C_IT is reset */
+ bitstatus = RESET;
+ }
+
+ /* Return the I2C_IT status */
+ return bitstatus;
+}
+
+/**
+ * @brief Clears the I2Cx's interrupt pending bits.
+ * @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
+ * @param I2C_IT: specifies the interrupt pending bit to clear.
+ * This parameter can be any combination of the following values:
+ * @arg I2C_IT_ADDR: Address matched (slave mode)
+ * @arg I2C_IT_NACKF: NACK received flag
+ * @arg I2C_IT_STOPF: STOP detection flag
+ * @arg I2C_IT_BERR: Bus error
+ * @arg I2C_IT_ARLO: Arbitration lost
+ * @arg I2C_IT_OVR: Overrun/Underrun
+ * @arg I2C_IT_PECERR: PEC error in reception
+ * @arg I2C_IT_TIMEOUT: Timeout or Tlow detection flag
+ * @arg I2C_IT_ALERT: SMBus Alert
+ * @retval The new state of I2C_IT (SET or RESET).
+ */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+ /* Check the parameters */
+ assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+ assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+ /* Clear the selected flag */
+ I2Cx->ICR = I2C_IT;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_i2c.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_i2c.h
new file mode 100644
index 0000000000..02e2ea2836
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_i2c.h
@@ -0,0 +1,487 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_i2c.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the I2C firmware
+ * library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_I2C_H
+#define __STM32F30x_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup I2C
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief I2C Init structure definition
+ */
+
+typedef struct
+{
+ uint32_t I2C_Timing; /*!< Specifies the I2C_TIMINGR_register value.
+ This parameter calculated by referring to I2C initialization
+ section in Reference manual*/
+
+ uint32_t I2C_AnalogFilter; /*!< Enables or disables analog noise filter.
+ This parameter can be a value of @ref I2C_Analog_Filter */
+
+ uint32_t I2C_DigitalFilter; /*!< Configures the digital noise filter.
+ This parameter can be a number between 0x00 and 0x0F */
+
+ uint32_t I2C_Mode; /*!< Specifies the I2C mode.
+ This parameter can be a value of @ref I2C_mode */
+
+ uint32_t I2C_OwnAddress1; /*!< Specifies the device own address 1.
+ This parameter can be a 7-bit or 10-bit address */
+
+ uint32_t I2C_Ack; /*!< Enables or disables the acknowledgement.
+ This parameter can be a value of @ref I2C_acknowledgement */
+
+ uint32_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+ This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+ * @{
+ */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+ ((PERIPH) == I2C2))
+
+/** @defgroup I2C_Analog_Filter
+ * @{
+ */
+
+#define I2C_AnalogFilter_Enable ((uint32_t)0x00000000)
+#define I2C_AnalogFilter_Disable I2C_CR1_ANFOFF
+
+#define IS_I2C_ANALOG_FILTER(FILTER) (((FILTER) == I2C_AnalogFilter_Enable) || \
+ ((FILTER) == I2C_AnalogFilter_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_Digital_Filter
+ * @{
+ */
+
+#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000F)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_mode
+ * @{
+ */
+
+#define I2C_Mode_I2C ((uint32_t)0x00000000)
+#define I2C_Mode_SMBusDevice I2C_CR1_SMBDEN
+#define I2C_Mode_SMBusHost I2C_CR1_SMBHEN
+
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+ ((MODE) == I2C_Mode_SMBusDevice) || \
+ ((MODE) == I2C_Mode_SMBusHost))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledgement
+ * @{
+ */
+
+#define I2C_Ack_Enable ((uint32_t)0x00000000)
+#define I2C_Ack_Disable I2C_CR2_NACK
+
+#define IS_I2C_ACK(ACK) (((ACK) == I2C_Ack_Enable) || \
+ ((ACK) == I2C_Ack_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_acknowledged_address
+ * @{
+ */
+
+#define I2C_AcknowledgedAddress_7bit ((uint32_t)0x00000000)
+#define I2C_AcknowledgedAddress_10bit I2C_OAR1_OA1MODE
+
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+ ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address1
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= (uint32_t)0x000003FF)
+/**
+ * @}
+ */
+
+/** @defgroup I2C_transfer_direction
+ * @{
+ */
+
+#define I2C_Direction_Transmitter ((uint16_t)0x0000)
+#define I2C_Direction_Receiver ((uint16_t)0x0400)
+
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+ ((DIRECTION) == I2C_Direction_Receiver))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_DMA_transfer_requests
+ * @{
+ */
+
+#define I2C_DMAReq_Tx I2C_CR1_TXDMAEN
+#define I2C_DMAReq_Rx I2C_CR1_RXDMAEN
+
+#define IS_I2C_DMA_REQ(REQ) ((((REQ) & (uint32_t)0xFFFF3FFF) == 0x00) && ((REQ) != 0x00))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_slave_address
+ * @{
+ */
+
+#define IS_I2C_SLAVE_ADDRESS(ADDRESS) ((ADDRESS) <= (uint16_t)0x03FF)
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_own_address2
+ * @{
+ */
+
+#define IS_I2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_own_address2_mask
+ * @{
+ */
+
+#define I2C_OA2_NoMask ((uint8_t)0x00)
+#define I2C_OA2_Mask01 ((uint8_t)0x01)
+#define I2C_OA2_Mask02 ((uint8_t)0x02)
+#define I2C_OA2_Mask03 ((uint8_t)0x03)
+#define I2C_OA2_Mask04 ((uint8_t)0x04)
+#define I2C_OA2_Mask05 ((uint8_t)0x05)
+#define I2C_OA2_Mask06 ((uint8_t)0x06)
+#define I2C_OA2_Mask07 ((uint8_t)0x07)
+
+#define IS_I2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == I2C_OA2_NoMask) || \
+ ((MASK) == I2C_OA2_Mask01) || \
+ ((MASK) == I2C_OA2_Mask02) || \
+ ((MASK) == I2C_OA2_Mask03) || \
+ ((MASK) == I2C_OA2_Mask04) || \
+ ((MASK) == I2C_OA2_Mask05) || \
+ ((MASK) == I2C_OA2_Mask06) || \
+ ((MASK) == I2C_OA2_Mask07))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_timeout
+ * @{
+ */
+
+#define IS_I2C_TIMEOUT(TIMEOUT) ((TIMEOUT) <= (uint16_t)0x0FFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_registers
+ * @{
+ */
+
+#define I2C_Register_CR1 ((uint8_t)0x00)
+#define I2C_Register_CR2 ((uint8_t)0x04)
+#define I2C_Register_OAR1 ((uint8_t)0x08)
+#define I2C_Register_OAR2 ((uint8_t)0x0C)
+#define I2C_Register_TIMINGR ((uint8_t)0x10)
+#define I2C_Register_TIMEOUTR ((uint8_t)0x14)
+#define I2C_Register_ISR ((uint8_t)0x18)
+#define I2C_Register_ICR ((uint8_t)0x1C)
+#define I2C_Register_PECR ((uint8_t)0x20)
+#define I2C_Register_RXDR ((uint8_t)0x24)
+#define I2C_Register_TXDR ((uint8_t)0x28)
+
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+ ((REGISTER) == I2C_Register_CR2) || \
+ ((REGISTER) == I2C_Register_OAR1) || \
+ ((REGISTER) == I2C_Register_OAR2) || \
+ ((REGISTER) == I2C_Register_TIMINGR) || \
+ ((REGISTER) == I2C_Register_TIMEOUTR) || \
+ ((REGISTER) == I2C_Register_ISR) || \
+ ((REGISTER) == I2C_Register_ICR) || \
+ ((REGISTER) == I2C_Register_PECR) || \
+ ((REGISTER) == I2C_Register_RXDR) || \
+ ((REGISTER) == I2C_Register_TXDR))
+/**
+ * @}
+ */
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_ERRI I2C_CR1_ERRIE
+#define I2C_IT_TCI I2C_CR1_TCIE
+#define I2C_IT_STOPI I2C_CR1_STOPIE
+#define I2C_IT_NACKI I2C_CR1_NACKIE
+#define I2C_IT_ADDRI I2C_CR1_ADDRIE
+#define I2C_IT_RXI I2C_CR1_RXIE
+#define I2C_IT_TXI I2C_CR1_TXIE
+
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint32_t)0xFFFFFF01) == 0x00) && ((IT) != 0x00))
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_flags_definition
+ * @{
+ */
+
+#define I2C_FLAG_TXE I2C_ISR_TXE
+#define I2C_FLAG_TXIS I2C_ISR_TXIS
+#define I2C_FLAG_RXNE I2C_ISR_RXNE
+#define I2C_FLAG_ADDR I2C_ISR_ADDR
+#define I2C_FLAG_NACKF I2C_ISR_NACKF
+#define I2C_FLAG_STOPF I2C_ISR_STOPF
+#define I2C_FLAG_TC I2C_ISR_TC
+#define I2C_FLAG_TCR I2C_ISR_TCR
+#define I2C_FLAG_BERR I2C_ISR_BERR
+#define I2C_FLAG_ARLO I2C_ISR_ARLO
+#define I2C_FLAG_OVR I2C_ISR_OVR
+#define I2C_FLAG_PECERR I2C_ISR_PECERR
+#define I2C_FLAG_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_FLAG_ALERT I2C_ISR_ALERT
+#define I2C_FLAG_BUSY I2C_ISR_BUSY
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFF4000) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_TXIS) || \
+ ((FLAG) == I2C_FLAG_RXNE) || ((FLAG) == I2C_FLAG_ADDR) || \
+ ((FLAG) == I2C_FLAG_NACKF) || ((FLAG) == I2C_FLAG_STOPF) || \
+ ((FLAG) == I2C_FLAG_TC) || ((FLAG) == I2C_FLAG_TCR) || \
+ ((FLAG) == I2C_FLAG_BERR) || ((FLAG) == I2C_FLAG_ARLO) || \
+ ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_PECERR) || \
+ ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_ALERT) || \
+ ((FLAG) == I2C_FLAG_BUSY))
+
+/**
+ * @}
+ */
+
+
+/** @defgroup I2C_interrupts_definition
+ * @{
+ */
+
+#define I2C_IT_TXIS I2C_ISR_TXIS
+#define I2C_IT_RXNE I2C_ISR_RXNE
+#define I2C_IT_ADDR I2C_ISR_ADDR
+#define I2C_IT_NACKF I2C_ISR_NACKF
+#define I2C_IT_STOPF I2C_ISR_STOPF
+#define I2C_IT_TC I2C_ISR_TC
+#define I2C_IT_TCR I2C_ISR_TCR
+#define I2C_IT_BERR I2C_ISR_BERR
+#define I2C_IT_ARLO I2C_ISR_ARLO
+#define I2C_IT_OVR I2C_ISR_OVR
+#define I2C_IT_PECERR I2C_ISR_PECERR
+#define I2C_IT_TIMEOUT I2C_ISR_TIMEOUT
+#define I2C_IT_ALERT I2C_ISR_ALERT
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFFFFC001) == 0x00) && ((IT) != 0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_TXIS) || ((IT) == I2C_IT_RXNE) || \
+ ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_NACKF) || \
+ ((IT) == I2C_IT_STOPF) || ((IT) == I2C_IT_TC) || \
+ ((IT) == I2C_IT_TCR) || ((IT) == I2C_IT_BERR) || \
+ ((IT) == I2C_IT_ARLO) || ((IT) == I2C_IT_OVR) || \
+ ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_TIMEOUT) || \
+ ((IT) == I2C_IT_ALERT))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_ReloadEndMode_definition
+ * @{
+ */
+
+#define I2C_Reload_Mode I2C_CR2_RELOAD
+#define I2C_AutoEnd_Mode I2C_CR2_AUTOEND
+#define I2C_SoftEnd_Mode ((uint32_t)0x00000000)
+
+
+#define IS_RELOAD_END_MODE(MODE) (((MODE) == I2C_Reload_Mode) || \
+ ((MODE) == I2C_AutoEnd_Mode) || \
+ ((MODE) == I2C_SoftEnd_Mode))
+
+
+/**
+ * @}
+ */
+
+/** @defgroup I2C_StartStopMode_definition
+ * @{
+ */
+
+#define I2C_No_StartStop ((uint32_t)0x00000000)
+#define I2C_Generate_Stop I2C_CR2_STOP
+#define I2C_Generate_Start_Read (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_Generate_Start_Write I2C_CR2_START
+
+
+#define IS_START_STOP_MODE(MODE) (((MODE) == I2C_Generate_Stop) || \
+ ((MODE) == I2C_Generate_Start_Read) || \
+ ((MODE) == I2C_Generate_Start_Write) || \
+ ((MODE) == I2C_No_StartStop))
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+
+/* Initialization and Configuration functions *********************************/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint32_t I2C_IT, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StopModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Mask);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveByteControlCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SlaveAddressConfig(I2C_TypeDef* I2Cx, uint16_t Address);
+void I2C_10BitAddressingModeCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Communications handling functions ******************************************/
+void I2C_AutoEndCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ReloadCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_NumberOfBytesConfig(I2C_TypeDef* I2Cx, uint8_t Number_Bytes);
+void I2C_MasterRequestConfig(I2C_TypeDef* I2Cx, uint16_t I2C_Direction);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_10BitAddressHeaderCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetAddressMatched(I2C_TypeDef* I2Cx);
+uint16_t I2C_GetTransferDirection(I2C_TypeDef* I2Cx);
+void I2C_TransferHandling(I2C_TypeDef* I2Cx, uint16_t Address, uint8_t Number_Bytes, uint32_t ReloadEndMode, uint32_t StartStopMode);
+
+/* SMBUS management functions ************************************************/
+void I2C_SMBusAlertCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_ExtendedClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_IdleClockTimeoutCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_TimeoutAConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_TimeoutBConfig(I2C_TypeDef* I2Cx, uint16_t Timeout);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECRequestCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* I2C registers management functions *****************************************/
+uint32_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+
+/* Data transfers management functions ****************************************/
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, uint32_t I2C_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_I2C_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_iwdg.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_iwdg.c
new file mode 100644
index 0000000000..665a36ab3b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_iwdg.c
@@ -0,0 +1,298 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_iwdg.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Independent watchdog (IWDG) peripheral:
+ * + Prescaler and Counter configuration
+ * + IWDG activation
+ * + Flag management
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### IWDG features #####
+ ===============================================================================
+ [..] The IWDG can be started by either software or hardware (configurable
+ through option byte).
+ [..] The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+ thus stays active even if the main clock fails.
+ Once the IWDG is started, the LSI is forced ON and cannot be disabled
+ (LSI cannot be disabled too), and the counter starts counting down from
+ the reset value of 0xFFF. When it reaches the end of count value (0x000)
+ a system reset is generated.
+ The IWDG counter should be reloaded at regular intervals to prevent
+ an MCU reset.
+ [..] The IWDG is implemented in the VDD voltage domain that is still functional
+ in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
+ [..] IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+ reset occurs.
+ [..] Min-max timeout value @41KHz (LSI): ~0.1ms / ~25.5s
+ The IWDG timeout may vary due to LSI frequency dispersion. STM32F30x
+ devices provide the capability to measure the LSI frequency (LSI clock
+ connected internally to TIM16 CH1 input capture). The measured value
+ can be used to have an IWDG timeout with an acceptable accuracy.
+ For more information, please refer to the STM32F30x Reference manual.
+
+ ##### How to use this driver #####
+ ===============================================================================
+ [..] This driver allows to use IWDG peripheral with either window option enabled
+ or disabled. To do so follow one of the two procedures below.
+ (#) Window option is enabled:
+ (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+ in software mode (no need to enable the LSI, it will be enabled
+ by hardware).
+ (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+ (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+ (++) Configure the IWDG counter value using IWDG_SetReload() function.
+ This value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+ (++) Configure the IWDG refresh window using IWDG_SetWindowValue() function.
+
+ (#) Window option is disabled:
+ (++) Enable write access to IWDG_PR and IWDG_RLR registers using
+ IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function.
+ (++) Configure the IWDG prescaler using IWDG_SetPrescaler() function.
+ (++) Configure the IWDG counter value using IWDG_SetReload() function.
+ This value will be loaded in the IWDG counter each time the counter
+ is reloaded, then the IWDG will start counting down from this value.
+ (++) Wait for the IWDG registers to be updated using IWDG_GetFlagStatus() function.
+ (++) reload the IWDG counter at regular intervals during normal operation
+ to prevent an MCU reset, using IWDG_ReloadCounter() function.
+ (++) Start the IWDG using IWDG_Enable() function, when the IWDG is used
+ in software mode (no need to enable the LSI, it will be enabled
+ by hardware).
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_iwdg.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup IWDG
+ * @brief IWDG driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ---------------------- IWDG registers bit mask ----------------------------*/
+/* KR register bit mask */
+#define KR_KEY_RELOAD ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+ * @{
+ */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ * @brief Prescaler and Counter configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Prescaler and Counter configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+ * @param IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+ * This parameter can be one of the following values:
+ * @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+ * @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+ * @retval None
+ */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+ IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+ * @brief Sets IWDG Prescaler value.
+ * @param IWDG_Prescaler: specifies the IWDG Prescaler value.
+ * This parameter can be one of the following values:
+ * @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+ * @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+ * @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+ * @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+ * @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+ * @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+ * @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+ * @retval None
+ */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+ IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+ * @brief Sets IWDG Reload value.
+ * @param Reload: specifies the IWDG Reload value.
+ * This parameter must be a number between 0 and 0x0FFF.
+ * @retval None
+ */
+void IWDG_SetReload(uint16_t Reload)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_RELOAD(Reload));
+ IWDG->RLR = Reload;
+}
+
+/**
+ * @brief Reloads IWDG counter with value defined in the reload register
+ * (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_ReloadCounter(void)
+{
+ IWDG->KR = KR_KEY_RELOAD;
+}
+
+
+/**
+ * @brief Sets the IWDG window value.
+ * @param WindowValue: specifies the window value to be compared to the downcounter.
+ * @retval None
+ */
+void IWDG_SetWindowValue(uint16_t WindowValue)
+{
+ /* Check the parameters */
+ assert_param(IS_IWDG_WINDOW_VALUE(WindowValue));
+ IWDG->WINR = WindowValue;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ * @brief IWDG activation function
+ *
+@verbatim
+ ===============================================================================
+ ##### IWDG activation function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+ * @param None
+ * @retval None
+ */
+void IWDG_Enable(void)
+{
+ IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Group3 Flag management function
+ * @brief Flag management function
+ *
+@verbatim
+ ===============================================================================
+ ##### Flag management function #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Checks whether the specified IWDG flag is set or not.
+ * @param IWDG_FLAG: specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+ * @arg IWDG_FLAG_RVU: Reload Value Update on going
+ * @arg IWDG_FLAG_WVU: Counter Window Value Update on going
+ * @retval The new state of IWDG_FLAG (SET or RESET).
+ */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+ FlagStatus bitstatus = RESET;
+ /* Check the parameters */
+ assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+ if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+ {
+ bitstatus = SET;
+ }
+ else
+ {
+ bitstatus = RESET;
+ }
+ /* Return the flag status */
+ return bitstatus;
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_iwdg.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_iwdg.h
new file mode 100644
index 0000000000..d122746fcb
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_iwdg.h
@@ -0,0 +1,163 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_iwdg.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the IWDG
+ * firmware library.
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_IWDG_H
+#define __STM32F30x_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup IWDG
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+ * @{
+ */
+
+/** @defgroup IWDG_WriteAccess
+ * @{
+ */
+
+#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+ ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_prescaler
+ * @{
+ */
+
+#define IWDG_Prescaler_4 ((uint8_t)0x00)
+#define IWDG_Prescaler_8 ((uint8_t)0x01)
+#define IWDG_Prescaler_16 ((uint8_t)0x02)
+#define IWDG_Prescaler_32 ((uint8_t)0x03)
+#define IWDG_Prescaler_64 ((uint8_t)0x04)
+#define IWDG_Prescaler_128 ((uint8_t)0x05)
+#define IWDG_Prescaler_256 ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4) || \
+ ((PRESCALER) == IWDG_Prescaler_8) || \
+ ((PRESCALER) == IWDG_Prescaler_16) || \
+ ((PRESCALER) == IWDG_Prescaler_32) || \
+ ((PRESCALER) == IWDG_Prescaler_64) || \
+ ((PRESCALER) == IWDG_Prescaler_128)|| \
+ ((PRESCALER) == IWDG_Prescaler_256))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Flag
+ * @{
+ */
+
+#define IWDG_FLAG_PVU ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU ((uint16_t)0x0002)
+#define IWDG_FLAG_WVU ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU) || \
+ ((FLAG) == IWDG_FLAG_WVU))
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_Reload_Value
+ * @{
+ */
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup IWDG_CounterWindow_Value
+ * @{
+ */
+#define IS_IWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0xFFF)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+void IWDG_SetWindowValue(uint16_t WindowValue);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_IWDG_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_misc.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_misc.c
new file mode 100644
index 0000000000..89b7abf6e7
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_misc.c
@@ -0,0 +1,240 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_misc.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides all the miscellaneous firmware functions (add-on
+ * to CMSIS functions).
+ *
+ @verbatim
+
+ ===============================================================================
+ ##### How to configure Interrupts using driver #####
+ ===============================================================================
+ [..] This section provide functions allowing to configure the NVIC interrupts
+ (IRQ). The Cortex-M4 exceptions are managed by CMSIS functions.
+ (#) Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+ function according to the following table.
+ The table below gives the allowed values of the pre-emption priority
+ and subpriority according to the Priority Grouping configuration
+ performed by NVIC_PriorityGroupConfig function.
+
+ (#) Enable and Configure the priority of the selected IRQ Channels.
+ [..]
+ (@) When the NVIC_PriorityGroup_0 is selected, it will no any nested interrupt,
+ the IRQ priority will be managed only by subpriority.
+ The sub-priority is only used to sort pending exception priorities,
+ and does not affect active exceptions.
+ (@) Lower priority values gives higher priority.
+ (@) Priority Order:
+ (#@) Lowest Preemption priority.
+ (#@) Lowest Subpriority.
+ (#@) Lowest hardware priority (IRQn position).
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_misc.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup MISC
+ * @brief MISC driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+ * @{
+ */
+
+/**
+ * @brief Configures the priority grouping: pre-emption priority and subpriority.
+ * @param NVIC_PriorityGroup: specifies the priority grouping bits length.
+ * This parameter can be one of the following values:
+ * @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority.
+ * 4 bits for subpriority.
+ * @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority.
+ * 3 bits for subpriority.
+ * @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority.
+ * 2 bits for subpriority.
+ * @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority.
+ * 1 bits for subpriority.
+ * @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority.
+ * 0 bits for subpriority.
+ * @note When NVIC_PriorityGroup_0 is selected, it will no be any nested
+ * interrupt. This interrupts priority is managed only with subpriority.
+ * @retval None
+ */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+
+ /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+ SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+ * @brief Initializes the NVIC peripheral according to the specified
+ * parameters in the NVIC_InitStruct.
+ * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+ * function should be called before.
+ * @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+ * the configuration information for the specified NVIC peripheral.
+ * @retval None
+ */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+ uint32_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+
+ /* Check the parameters */
+ assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+ assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));
+ assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+
+ if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+ {
+ /* Compute the Corresponding IRQ Priority --------------------------------*/
+ tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+ tmppre = (0x4 - tmppriority);
+ tmpsub = tmpsub >> tmppriority;
+
+ tmppriority = (uint32_t)NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+ tmppriority |= NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub;
+ tmppriority = tmppriority << 0x04;
+
+ NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+
+ /* Enable the Selected IRQ Channels --------------------------------------*/
+ NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+ else
+ {
+ /* Disable the Selected IRQ Channels -------------------------------------*/
+ NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+ (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+ }
+}
+
+/**
+ * @brief Sets the vector table location and Offset.
+ * @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+ * This parameter can be one of the following values:
+ * @arg NVIC_VectTab_RAM
+ * @arg NVIC_VectTab_FLASH
+ * @param Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+ * @retval None
+ */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+ assert_param(IS_NVIC_OFFSET(Offset));
+
+ SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+ * @brief Selects the condition for the system to enter low power mode.
+ * @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
+ * This parameter can be one of the following values:
+ * @arg NVIC_LP_SEVONPEND
+ * @arg NVIC_LP_SLEEPDEEP
+ * @arg NVIC_LP_SLEEPONEXIT
+ * @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_NVIC_LP(LowPowerMode));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ SCB->SCR |= LowPowerMode;
+ }
+ else
+ {
+ SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+ }
+}
+
+/**
+ * @brief Configures the SysTick clock source.
+ * @param SysTick_CLKSource: specifies the SysTick clock source.
+ * This parameter can be one of the following values:
+ * @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+ * @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+ * @retval None
+ */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+ /* Check the parameters */
+ assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+ if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+ {
+ SysTick->CTRL |= SysTick_CLKSource_HCLK;
+ }
+ else
+ {
+ SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+ }
+}
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_misc.h b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_misc.h
new file mode 100644
index 0000000000..35aefc642d
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_misc.h
@@ -0,0 +1,214 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_misc.h
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file contains all the functions prototypes for the miscellaneous
+ * firmware library functions (add-on to CMSIS functions).
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_MISC_H
+#define __STM32F30x_MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup MISC
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief NVIC Init Structure definition
+ */
+
+typedef struct
+{
+ uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
+ This parameter can be a value of @ref IRQn_Type (For
+ the complete STM32 Devices IRQ Channels list, please
+ refer to stm32f30x.h file) */
+
+ uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
+ specified in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15.
+ A lower priority value indicates a higher priority */
+
+
+ uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
+ in NVIC_IRQChannel. This parameter can be a value
+ between 0 and 15.
+ A lower priority value indicates a higher priority */
+
+ FunctionalState NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+ will be enabled or disabled.
+ This parameter can be set either to ENABLE or DISABLE */
+} NVIC_InitTypeDef;
+
+/**
+ *
+@verbatim
+ The table below gives the allowed values of the pre-emption priority and subpriority according
+ to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+ ============================================================================================================================
+ NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
+ ============================================================================================================================
+ NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
+ | | | 4 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
+ | | | 3 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
+ | | | 2 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
+ | | | 1 bits for subpriority
+ ----------------------------------------------------------------------------------------------------------------------------
+ NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
+ | | | 0 bits for subpriority
+ ============================================================================================================================
+@endverbatim
+*/
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+ * @{
+ */
+
+/** @defgroup MISC_Vector_Table_Base
+ * @{
+ */
+
+#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+ ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_System_Low_Power
+ * @{
+ */
+
+#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+ ((LP) == NVIC_LP_SLEEPDEEP) || \
+ ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+ * @}
+ */
+
+/** @defgroup MISC_Preemption_Priority_Group
+ * @{
+ */
+
+#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+ 4 bits for subpriority */
+#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+ 3 bits for subpriority */
+#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+ 2 bits for subpriority */
+#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+ 1 bits for subpriority */
+#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+ 0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+ ((GROUP) == NVIC_PriorityGroup_1) || \
+ ((GROUP) == NVIC_PriorityGroup_2) || \
+ ((GROUP) == NVIC_PriorityGroup_3) || \
+ ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
+
+/**
+ * @}
+ */
+
+/** @defgroup MISC_SysTick_clock_source
+ */
+
+#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+ ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F30x_MISC_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_opamp.c b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_opamp.c
new file mode 100644
index 0000000000..a8e467f47b
--- /dev/null
+++ b/libraries/mbed/targets/cmsis/TARGET_STM/TARGET_NUCLEO_F302R8/stm32f30x_opamp.c
@@ -0,0 +1,585 @@
+/**
+ ******************************************************************************
+ * @file stm32f30x_opamp.c
+ * @author MCD Application Team
+ * @version V1.1.0
+ * @date 27-February-2014
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the operational amplifiers (OPAMP1,...OPAMP4) peripheral:
+ * + OPAMP Configuration
+ * + OPAMP calibration
+ *
+ @verbatim
+
+ ==============================================================================
+ ##### OPAMP Peripheral Features #####
+ ==============================================================================
+
+ [..]
+ The device integrates 4 operational amplifiers OPAMP1, OPAMP2, OPAMP3 and OPAMP4:
+
+ (+) The OPAMPs non inverting input can be selected among the list shown by
+ table below.
+
+ (+) The OPAMPs inverting input can be selected among the list shown by
+ table below.
+
+ (+) The OPAMPs outputs can be internally connected to the inverting input
+ (follower mode)
+ (+) The OPAMPs outputs can be internally connected to resistor feedback
+ output (Programmable Gain Amplifier mode)
+
+ (+) The OPAMPs outputs can be internally connected to ADC
+
+ (+) The OPAMPs can be calibrated to compensate the offset compensation
+
+ (+) Timer-controlled Mux for automatic switch of inverting and
+ non-inverting input
+
+ OPAMPs inverting/non-inverting inputs:
+ +--------------------------------------------------------------+
+ | | | OPAMP1 | OPAMP2 | OPAMP3 | OPAMP4 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | PGA | OK | OK | OK | OK |
+ | Inverting Input | Vout | OK | OK | OK | OK |
+ | | IO1 | PC5 | PC5 | PB10 | PB10 |
+ | | IO2 | PA3 | PA5 | PB2 | PD8 |
+ |-----------------|--------|--------|--------|--------|--------|
+ | | IO1 | PA7 | PD14 | PB13 | PD11 |
+ | Non Inverting | IO2 | PA5 | PB14 | PA5 | PB11 |
+ | Input | IO3 | PA3 | PB0 | PA1 | PA4 |
+ | | IO4 | PA1 | PA7 | PB0 | PB13 |
+ +--------------------------------------------------------------+
+
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ This driver provides functions to configure and program the OPAMP
+ of all STM32F30x devices.
+
+ To use the OPAMP, perform the following steps:
+
+ (#) Enable the SYSCFG APB clock to get write access to OPAMP
+ register using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+
+ (#) Configure the OPAMP input in analog mode using GPIO_Init()
+
+ (#) Configure the OPAMP using OPAMP_Init() function:
+ (++) Select the inverting input
+ (++) Select the non-inverting inverting input
+
+ (#) Enable the OPAMP using OPAMP_Cmd() function
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * © COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x_opamp.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @defgroup OPAMP
+ * @brief OPAMP driver modules
+ * @{
+ */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define OPAMP_CSR_DEFAULT_MASK ((uint32_t)0xFFFFFF93)
+#define OPAMP_CSR_TIMERMUX_MASK ((uint32_t)0xFFFFF8FF)
+#define OPAMP_CSR_TRIMMING_MASK ((uint32_t)0x0000001F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup OPAMP_Private_Functions
+ * @{
+ */
+
+/** @defgroup OPAMP_Group1 Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Initialization and Configuration functions #####
+ ===============================================================================
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Deinitializes OPAMP peripheral registers to their default reset values.
+ * @note Deinitialization can't be performed if the OPAMP configuration is locked.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param None
+ * @retval None
+ */
+void OPAMP_DeInit(uint32_t OPAMP_Selection)
+{
+ /*!< Set OPAMP_CSR register to reset value */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = ((uint32_t)0x00000000);
+}
+
+/**
+ * @brief Initializes the OPAMP peripheral according to the specified parameters
+ * in OPAMP_InitStruct
+ * @note If the selected OPAMP is locked, initialization can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
+ * the configuration information for the specified OPAMP peripheral.
+ * - OPAMP_InvertingInput specifies the inverting input of OPAMP
+ * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
+ * @retval None
+ */
+void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_INVERTING_INPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the inverting and non inverting bits selection bits */
+ tmpreg &= (uint32_t) (OPAMP_CSR_DEFAULT_MASK);
+
+ /*!< Configure OPAMP: inverting and non inverting inputs */
+ tmpreg |= (uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput | OPAMP_InitStruct->OPAMP_NonInvertingInput);
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Fills each OPAMP_InitStruct member with its default value.
+ * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure which will
+ * be initialized.
+ * @retval None
+ */
+void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+ OPAMP_InitStruct->OPAMP_NonInvertingInput = OPAMP_NonInvertingInput_IO1;
+ OPAMP_InitStruct->OPAMP_InvertingInput = OPAMP_InvertingInput_IO1;
+}
+
+/**
+ * @brief Configure the feedback resistor gain.
+ * @note If the selected OPAMP is locked, gain configuration can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_PGAGAIN(OPAMP_PGAGain));
+ assert_param(IS_OPAMP_PGACONNECT(OPAMP_PGAConnect));
+
+ /* Reset the configuration bits */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_PGGAIN);
+
+ /* Set the new configuration */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_PGAGain | OPAMP_PGAConnect);
+}
+
+/**
+ * @brief Configure the OPAMP's internal reference.
+ * @note This feature is used when calibration enabled or OPAMP's reference
+ * connected to the non inverting input.
+ * @note If the selected OPAMP is locked, Vref configuration can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_Vref: This parameter can be:
+ * OPAMP_Vref_3VDDA: OPMAP Vref = 3.3% VDDA
+ * OPAMP_Vref_10VDDA: OPMAP Vref = 10% VDDA
+ * OPAMP_Vref_50VDDA: OPMAP Vref = 50% VDDA
+ * OPAMP_Vref_90VDDA: OPMAP Vref = 90% VDDA
+ * @retval None
+ */
+void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_VREF(OPAMP_Vref));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the CALSEL bits */
+ tmpreg &= (uint32_t) (~OPAMP_CSR_CALSEL);
+
+ /*!< Configure OPAMP reference */
+ tmpreg |= (uint32_t)(OPAMP_Vref);
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Connnect the internal reference to the OPAMP's non inverting input.
+ * @note If the selected OPAMP is locked, Vref configuration can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Connnect the internal reference to the OPAMP's non inverting input */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_FORCEVP);
+ }
+ else
+ {
+ /* Disconnnect the internal reference to the OPAMP's non inverting input */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_FORCEVP);
+ }
+}
+
+/**
+ * @brief Enables or disables connecting the OPAMP's internal reference to ADC.
+ * @note If the selected OPAMP is locked, Vref connection can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param NewState: new state of the Vrefint output.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable output internal reference */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TSTREF);
+ }
+ else
+ {
+ /* Disable output internal reference */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TSTREF);
+ }
+}
+
+/**
+ * @brief Configure the OPAMP peripheral (secondary inputs) for timer-controlled
+ * mux mode according to the specified parameters in OPAMP_InitStruct.
+ * @note If the selected OPAMP is locked, timer-controlled mux configuration
+ * can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_InitStruct: pointer to an OPAMP_InitTypeDef structure that contains
+ * the configuration information for the specified OPAMP peripheral.
+ * - OPAMP_InvertingInput specifies the inverting input of OPAMP
+ * - OPAMP_NonInvertingInput specifies the non inverting input of OPAMP
+ * @note PGA and Vout can't be selected as seconadry inverting input.
+ * @retval None
+ */
+void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_SECONDARY_INVINPUT(OPAMP_InitStruct->OPAMP_InvertingInput));
+ assert_param(IS_OPAMP_NONINVERTING_INPUT(OPAMP_InitStruct->OPAMP_NonInvertingInput));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the secondary inverting bit, secondary non inverting bit and TCMEN bits */
+ tmpreg &= (uint32_t) (OPAMP_CSR_TIMERMUX_MASK);
+
+ /*!< Configure OPAMP: secondary inverting and non inverting inputs */
+ tmpreg |= (uint32_t)((uint32_t)(OPAMP_InitStruct->OPAMP_InvertingInput<<3) | (uint32_t)(OPAMP_InitStruct->OPAMP_NonInvertingInput<<7));
+
+ /*!< Write to OPAMPx_CSR register */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) = tmpreg;
+}
+
+/**
+ * @brief Enable or disable the timer-controlled mux mode.
+ * @note If the selected OPAMP is locked, enable/disable can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the timer-controlled Mux mode */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_TCMEN);
+ }
+ else
+ {
+ /* Disable the timer-controlled Mux mode */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_TCMEN);
+ }
+}
+
+/**
+ * @brief Enable or disable the OPAMP peripheral.
+ * @note If the selected OPAMP is locked, enable/disable can't be performed.
+ * To unlock the configuration, perform a system reset.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param NewState: new state of the OPAMP peripheral.
+ * This parameter can be: ENABLE or DISABLE.
+ * @retval None
+ */
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+ if (NewState != DISABLE)
+ {
+ /* Enable the selected OPAMPx peripheral */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= (uint32_t) (OPAMP_CSR_OPAMPxEN);
+ }
+ else
+ {
+ /* Disable the selected OPAMPx peripheral */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (uint32_t)(~OPAMP_CSR_OPAMPxEN);
+ }
+}
+
+/**
+ * @brief Return the output level (high or low) during calibration of the selected OPAMP.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * - OPAMP output is low when the non-inverting input is at a lower
+ * voltage than the inverting input
+ * - OPAMP output is high when the non-inverting input is at a higher
+ * voltage than the inverting input
+ * @note OPAMP ouput level is provided only during calibration phase.
+ * @retval Returns the selected OPAMP output level: low or high.
+ *
+ */
+uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection)
+{
+ uint32_t opampout = 0x0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+
+ /* Check if selected OPAMP output is high */
+ if ((*(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) & (OPAMP_CSR_OUTCAL)) != 0)
+ {
+ opampout = OPAMP_OutputLevel_High;
+ }
+ else
+ {
+ opampout = OPAMP_OutputLevel_Low;
+ }
+
+ /* Return the OPAMP output level */
+ return (uint32_t)(opampout);
+}
+
+/**
+ * @brief Select the trimming mode.
+ * @param OffsetTrimming: the selected offset trimming mode.
+ * This parameter can be one of the following values:
+ * @arg OPAMP_Trimming_Factory: factory trimming values are used for offset
+ * calibration
+ * @arg OPAMP_Trimming_User: user trimming values are used for offset
+ * calibration
+ * @note When OffsetTrimming_User is selected, use OPAMP_OffsetTrimConfig()
+ * function or OPAMP_OffsetTrimLowPowerConfig() function to adjust
+ * trimming value.
+ * @retval None
+ */
+void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming)
+{
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_TRIMMING(OPAMP_Trimming));
+
+ /* Reset USERTRIM bit */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) &= (~(uint32_t) (OPAMP_CSR_USERTRIM));
+
+ /* Select trimming mode */
+ *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection) |= OPAMP_Trimming;
+}
+
+/**
+ * @brief Configure the trimming value of the OPAMP.
+ * @param OPAMP_Selection: the selected OPAMP.
+ * This parameter can be OPAMP_Selection_OPAMPx where x can be 1 to 4
+ * to select the OPAMP peripheral.
+ * @param OPAMP_Input: the selected OPAMP input.
+ * This parameter can be one of the following values:
+ * @arg OPAMP_Input_Inverting: Inverting input is selected to configure the trimming value
+ * @arg OPAMP_Input_NonInverting: Non inverting input is selected to configure the trimming value
+ * @param OPAMP_TrimValue: the trimming value. This parameter can be any value lower
+ * or equal to 0x0000001F.
+ * @retval None
+ */
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue)
+{
+ uint32_t tmpreg = 0;
+
+ /* Check the parameters */
+ assert_param(IS_OPAMP_ALL_PERIPH(OPAMP_Selection));
+ assert_param(IS_OPAMP_INPUT(OPAMP_Input));
+ assert_param(IS_OPAMP_TRIMMINGVALUE(OPAMP_TrimValue));
+
+ /*!< Get the OPAMPx_CSR register value */
+ tmpreg = *(__IO uint32_t *) (OPAMP_BASE + OPAMP_Selection);
+
+ /*!< Clear the trimming bits */
+ tmpreg &= ((uint32_t)~(OPAMP_CSR_TRIMMING_MASK<© COPYRIGHT(c) 2014 STMicroelectronics
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F30x_OPAMP_H
+#define __STM32F30x_OPAMP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f30x.h"
+
+/** @addtogroup STM32F30x_StdPeriph_Driver
+ * @{
+ */
+
+/** @addtogroup OPAMP
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+
+/**
+ * @brief OPAMP Init structure definition
+ */
+
+typedef struct
+{
+
+ uint32_t OPAMP_InvertingInput; /*!< Selects the inverting input of the operational amplifier.
+ This parameter can be a value of @ref OPAMP_InvertingInput */
+
+ uint32_t OPAMP_NonInvertingInput; /*!< Selects the non inverting input of the operational amplifier.
+ This parameter can be a value of @ref OPAMP_NonInvertingInput */
+
+}OPAMP_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup OPAMP_Exported_Constants
+ * @{
+ */
+
+/** @defgroup OPAMP_Selection
+ * @{
+ */
+
+#define OPAMP_Selection_OPAMP1 ((uint32_t)0x00000000) /*!< OPAMP1 Selection */
+#define OPAMP_Selection_OPAMP2 ((uint32_t)0x00000004) /*!< OPAMP2 Selection */
+#define OPAMP_Selection_OPAMP3 ((uint32_t)0x00000008) /*!< OPAMP3 Selection */
+#define OPAMP_Selection_OPAMP4 ((uint32_t)0x0000000C) /*!< OPAMP4 Selection */
+
+#define IS_OPAMP_ALL_PERIPH(PERIPH) (((PERIPH) == OPAMP_Selection_OPAMP1) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP2) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP3) || \
+ ((PERIPH) == OPAMP_Selection_OPAMP4))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_InvertingInput
+ * @{
+ */
+
+#define OPAMP_InvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PC5 for OPAMP1 and OPAMP2, PB10 for OPAMP3 and OPAMP4)
+ connected to OPAMPx inverting input */
+#define OPAMP_InvertingInput_IO2 OPAMP_CSR_VMSEL_0 /*!< IO2 (PA3 for OPAMP1, PA5 for OPAMP2, PB2 for OPAMP3, PD8 for OPAMP4)
+ connected to OPAMPx inverting input */
+#define OPAMP_InvertingInput_PGA OPAMP_CSR_VMSEL_1 /*!< Resistor feedback output connected to OPAMPx inverting input (PGA mode) */
+#define OPAMP_InvertingInput_Vout OPAMP_CSR_VMSEL /*!< Vout connected to OPAMPx inverting input (follower mode) */
+
+#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_InvertingInput_IO1) || \
+ ((INPUT) == OPAMP_InvertingInput_IO2) || \
+ ((INPUT) == OPAMP_InvertingInput_PGA) || \
+ ((INPUT) == OPAMP_InvertingInput_Vout))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_NonInvertingInput
+ * @{
+ */
+
+#define OPAMP_NonInvertingInput_IO1 ((uint32_t)0x00000000) /*!< IO1 (PA7 for OPAMP1, PD14 for OPAMP2, PB13 for OPAMP3, PD11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NonInvertingInput_IO2 OPAMP_CSR_VPSEL_0 /*!< IO2 (PA5 for OPAMP1, PB14 for OPAMP2, PA5 for OPAMP3, PB11 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NonInvertingInput_IO3 OPAMP_CSR_VPSEL_1 /*!< IO3 (PA3 for OPAMP1, PB0 for OPAMP2, PA1 for OPAMP3, PA4 for OPAMP4)
+ connected to OPAMPx non inverting input */
+#define OPAMP_NonInvertingInput_IO4 OPAMP_CSR_VPSEL /*!< IO4 (PA1 for OPAMP1, PA7 for OPAMP2, PB0 for OPAMP3, PB13 for OPAMP4)
+ connected to OPAMPx non inverting input */
+
+#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NonInvertingInput_IO1) || \
+ ((INPUT) == OPAMP_NonInvertingInput_IO2) || \
+ ((INPUT) == OPAMP_NonInvertingInput_IO3) || \
+ ((INPUT) == OPAMP_NonInvertingInput_IO4))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PGAGain_Config
+ * @{
+ */
+
+#define OPAMP_OPAMP_PGAGain_2 ((uint32_t)0x00000000)
+#define OPAMP_OPAMP_PGAGain_4 OPAMP_CSR_PGGAIN_0
+#define OPAMP_OPAMP_PGAGain_8 OPAMP_CSR_PGGAIN_1
+#define OPAMP_OPAMP_PGAGain_16 ((uint32_t)0x0000C000)
+
+#define IS_OPAMP_PGAGAIN(GAIN) (((GAIN) == OPAMP_OPAMP_PGAGain_2) || \
+ ((GAIN) == OPAMP_OPAMP_PGAGain_4) || \
+ ((GAIN) == OPAMP_OPAMP_PGAGain_8) || \
+ ((GAIN) == OPAMP_OPAMP_PGAGain_16))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_PGAConnect_Config
+ * @{
+ */
+
+#define OPAMP_PGAConnect_No ((uint32_t)0x00000000)
+#define OPAMP_PGAConnect_IO1 OPAMP_CSR_PGGAIN_3
+#define OPAMP_PGAConnect_IO2 ((uint32_t)0x00030000)
+
+#define IS_OPAMP_PGACONNECT(CONNECT) (((CONNECT) == OPAMP_PGAConnect_No) || \
+ ((CONNECT) == OPAMP_PGAConnect_IO1) || \
+ ((CONNECT) == OPAMP_PGAConnect_IO2))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_SecondaryInvertingInput
+ * @{
+ */
+
+#define IS_OPAMP_SECONDARY_INVINPUT(INVINPUT) (((INVINPUT) == OPAMP_InvertingInput_IO1) || \
+ ((INVINPUT) == OPAMP_InvertingInput_IO2))
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Input
+ * @{
+ */
+
+#define OPAMP_Input_Inverting ((uint32_t)0x00000018) /*!< Inverting input */
+#define OPAMP_Input_NonInverting ((uint32_t)0x00000013) /*!< Non inverting input */
+
+#define IS_OPAMP_INPUT(INPUT) (((INPUT) == OPAMP_Input_Inverting) || \
+ ((INPUT) == OPAMP_Input_NonInverting))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Vref
+ * @{
+ */
+
+#define OPAMP_Vref_3VDDA ((uint32_t)0x00000000) /*!< OPMAP Vref = 3.3% VDDA */
+#define OPAMP_Vref_10VDDA OPAMP_CSR_CALSEL_0 /*!< OPMAP Vref = 10% VDDA */
+#define OPAMP_Vref_50VDDA OPAMP_CSR_CALSEL_1 /*!< OPMAP Vref = 50% VDDA */
+#define OPAMP_Vref_90VDDA OPAMP_CSR_CALSEL /*!< OPMAP Vref = 90% VDDA */
+
+#define IS_OPAMP_VREF(VREF) (((VREF) == OPAMP_Vref_3VDDA) || \
+ ((VREF) == OPAMP_Vref_10VDDA) || \
+ ((VREF) == OPAMP_Vref_50VDDA) || \
+ ((VREF) == OPAMP_Vref_90VDDA))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_Trimming
+ */
+
+#define OPAMP_Trimming_Factory ((uint32_t)0x00000000) /*!< Factory trimming */
+#define OPAMP_Trimming_User OPAMP_CSR_USERTRIM /*!< User trimming */
+
+#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_Trimming_Factory) || \
+ ((TRIMMING) == OPAMP_Trimming_User))
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_TrimValue
+ * @{
+ */
+
+#define IS_OPAMP_TRIMMINGVALUE(VALUE) ((VALUE) <= 0x0000001F) /*!< Trimming value */
+
+/**
+ * @}
+ */
+
+/** @defgroup OPAMP_OutputLevel
+ * @{
+ */
+
+#define OPAMP_OutputLevel_High OPAMP_CSR_OUTCAL
+#define OPAMP_OutputLevel_Low ((uint32_t)0x00000000)
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+/* Function used to set the OPAMP configuration to the default reset state ***/
+void OPAMP_DeInit(uint32_t OPAMP_Selection);
+
+/* Initialization and Configuration functions *********************************/
+void OPAMP_Init(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
+void OPAMP_StructInit(OPAMP_InitTypeDef* OPAMP_InitStruct);
+void OPAMP_PGAConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_PGAGain, uint32_t OPAMP_PGAConnect);
+void OPAMP_VrefConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Vref);
+void OPAMP_VrefConnectADCCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_TimerControlledMuxConfig(uint32_t OPAMP_Selection, OPAMP_InitTypeDef* OPAMP_InitStruct);
+void OPAMP_TimerControlledMuxCmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_Cmd(uint32_t OPAMP_Selection, FunctionalState NewState);
+uint32_t OPAMP_GetOutputLevel(uint32_t OPAMP_Selection);
+
+/* Calibration functions ******************************************************/
+void OPAMP_VrefConnectNonInvertingInput(uint32_t OPAMP_Selection, FunctionalState NewState);
+void OPAMP_OffsetTrimModeSelect(uint32_t OPAMP_Selection, uint32_t OPAMP_Trimming);
+void OPAMP_OffsetTrimConfig(uint32_t OPAMP_Selection, uint32_t OPAMP_Input, uint32_t OPAMP_TrimValue);
+void OPAMP_StartCalibration(uint32_t OPAMP_Selection, FunctionalState NewState);
+
+/* OPAMP configuration locking function ***************************************/
+void OPAMP_LockConfig(uint32_t OPAMP_Selection);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F30x_OPAMP_H */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/