diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.c
index 4bc67d7ad3..d3b3f0aa5f 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_dspi.h"
 
@@ -65,27 +65,27 @@ static void DSPI_SetOnePcsPolarity(SPI_Type *base, dspi_which_pcs_t pcs, dspi_pc
 
 /*!
  * @brief Master fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle);
 
 /*!
  * @brief Master finish up a transfer.
  * It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *handle);
 
 /*!
  * @brief Slave fill up the TX FIFO with data.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *handle);
 
 /*!
  * @brief Slave finish up a transfer.
  * It would call back if there is callback function and set the state to idle.
- * This is not a public API as it is called from other driver functions.
+ * This is not a public API.
  */
 static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *handle);
 
@@ -100,7 +100,7 @@ static void DSPI_CommonIRQHandler(SPI_Type *base, void *param);
 /*!
  * @brief Master prepare the transfer.
  * Basically it set up dspi_master_handle .
- * This is not a public API as it is called from other driver functions. fsl_dspi_edma.c also call this function.
+ * This is not a public API.
  */
 static void DSPI_MasterTransferPrepare(SPI_Type *base, dspi_master_handle_t *handle, dspi_transfer_t *transfer);
 
@@ -129,7 +129,7 @@ static clock_ip_name_t const s_dspiClock[] = DSPI_CLOCKS;
 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
 
 /*! @brief Pointers to dspi handles for each instance. */
-static void *g_dspiHandle[FSL_FEATURE_SOC_DSPI_COUNT];
+static void *g_dspiHandle[ARRAY_SIZE(s_dspiBases)];
 
 /*! @brief Pointer to master IRQ handler for each instance. */
 static dspi_master_isr_t s_dspiMasterIsr;
@@ -137,6 +137,8 @@ static dspi_master_isr_t s_dspiMasterIsr;
 /*! @brief Pointer to slave IRQ handler for each instance. */
 static dspi_slave_isr_t s_dspiSlaveIsr;
 
+/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
+volatile uint8_t s_dummyData[ARRAY_SIZE(s_dspiBases)] = {0};
 /**********************************************************************************************************************
 * Code
 *********************************************************************************************************************/
@@ -145,7 +147,7 @@ uint32_t DSPI_GetInstance(SPI_Type *base)
     uint32_t instance;
 
     /* Find the instance index from base address mappings. */
-    for (instance = 0; instance < FSL_FEATURE_SOC_DSPI_COUNT; instance++)
+    for (instance = 0; instance < ARRAY_SIZE(s_dspiBases); instance++)
     {
         if (s_dspiBases[instance] == base)
         {
@@ -153,11 +155,17 @@ uint32_t DSPI_GetInstance(SPI_Type *base)
         }
     }
 
-    assert(instance < FSL_FEATURE_SOC_DSPI_COUNT);
+    assert(instance < ARRAY_SIZE(s_dspiBases));
 
     return instance;
 }
 
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData)
+{
+    uint32_t instance = DSPI_GetInstance(base);
+    s_dummyData[instance] = dummyData;
+}
+
 void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, uint32_t srcClock_Hz)
 {
     assert(masterConfig);
@@ -202,6 +210,7 @@ void DSPI_MasterInit(SPI_Type *base, const dspi_master_config_t *masterConfig, u
     DSPI_MasterSetDelayTimes(base, masterConfig->whichCtar, kDSPI_BetweenTransfer, srcClock_Hz,
                              masterConfig->ctarConfig.betweenTransferDelayInNanoSec);
 
+    DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
     DSPI_StartTransfer(base);
 }
 
@@ -262,6 +271,8 @@ void DSPI_SlaveInit(SPI_Type *base, const dspi_slave_config_t *slaveConfig)
                                          SPI_CTAR_SLAVE_CPOL(slaveConfig->ctarConfig.cpol) |
                                          SPI_CTAR_SLAVE_CPHA(slaveConfig->ctarConfig.cpha);
 
+    DSPI_SetDummyData(base, DSPI_DUMMY_DATA);
+
     DSPI_StartTransfer(base);
 }
 
@@ -582,7 +593,7 @@ status_t DSPI_MasterTransferBlocking(SPI_Type *base, dspi_transfer_t *transfer)
 
     uint16_t wordToSend = 0;
     uint16_t wordReceived = 0;
-    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
     uint8_t bitsPerFrame;
 
     uint32_t command;
@@ -897,13 +908,10 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha
     handle->state = kDSPI_Busy;
 
     DSPI_MasterTransferPrepare(base, handle, transfer);
-    DSPI_StartTransfer(base);
 
     /* Enable the NVIC for DSPI peripheral. */
     EnableIRQ(s_dspiIRQ[DSPI_GetInstance(base)]);
 
-    DSPI_MasterTransferFillUpTxFifo(base, handle);
-
     /* RX FIFO Drain request: RFDF_RE to enable RFDF interrupt
     * Since SPI is a synchronous interface, we only need to enable the RX interrupt.
     * The IRQ handler will get the status of RX and TX interrupt flags.
@@ -911,7 +919,10 @@ status_t DSPI_MasterTransferNonBlocking(SPI_Type *base, dspi_master_handle_t *ha
     s_dspiMasterIsr = DSPI_MasterTransferHandleIRQ;
 
     DSPI_EnableInterrupts(base, kDSPI_RxFifoDrainRequestInterruptEnable);
+    DSPI_StartTransfer(base);
 
+    /* Fill up the Tx FIFO to trigger the transfer. */
+    DSPI_MasterTransferFillUpTxFifo(base, handle);
     return kStatus_Success;
 }
 
@@ -952,13 +963,12 @@ static void DSPI_MasterTransferComplete(SPI_Type *base, dspi_master_handle_t *ha
         status = kStatus_Success;
     }
 
+    handle->state = kDSPI_Idle;
+
     if (handle->callback)
     {
         handle->callback(base, handle, status, handle->userData);
     }
-
-    /* The transfer is complete.*/
-    handle->state = kDSPI_Idle;
 }
 
 static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t *handle)
@@ -966,7 +976,7 @@ static void DSPI_MasterTransferFillUpTxFifo(SPI_Type *base, dspi_master_handle_t
     assert(handle);
 
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
 
     /* If bits/frame is greater than one byte */
     if (handle->bitsPerFrame > 8)
@@ -1257,11 +1267,6 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand
     DSPI_FlushFifo(base, true, true);
     DSPI_ClearStatusFlags(base, kDSPI_AllStatusFlag);
 
-    DSPI_StartTransfer(base);
-
-    /* Prepare data to transmit */
-    DSPI_SlaveTransferFillUpTxFifo(base, handle);
-
     s_dspiSlaveIsr = DSPI_SlaveTransferHandleIRQ;
 
     /* Enable RX FIFO drain request, the slave only use this interrupt */
@@ -1278,6 +1283,11 @@ status_t DSPI_SlaveTransferNonBlocking(SPI_Type *base, dspi_slave_handle_t *hand
         DSPI_EnableInterrupts(base, kDSPI_TxFifoUnderflowInterruptEnable);
     }
 
+    DSPI_StartTransfer(base);
+
+    /* Prepare data to transmit */
+    DSPI_SlaveTransferFillUpTxFifo(base, handle);
+
     return kStatus_Success;
 }
 
@@ -1306,7 +1316,7 @@ static void DSPI_SlaveTransferFillUpTxFifo(SPI_Type *base, dspi_slave_handle_t *
     assert(handle);
 
     uint16_t transmitData = 0;
-    uint8_t dummyPattern = DSPI_DUMMY_DATA;
+    uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
 
     /* Service the transmitter, if transmit buffer provided, transmit the data,
     * else transmit dummy pattern
@@ -1413,12 +1423,12 @@ static void DSPI_SlaveTransferComplete(SPI_Type *base, dspi_slave_handle_t *hand
         status = kStatus_Success;
     }
 
+    handle->state = kDSPI_Idle;
+
     if (handle->callback)
     {
         handle->callback(base, handle, status, handle->userData);
     }
-
-    handle->state = kDSPI_Idle;
 }
 
 void DSPI_SlaveTransferAbort(SPI_Type *base, dspi_slave_handle_t *handle)
@@ -1440,7 +1450,7 @@ void DSPI_SlaveTransferHandleIRQ(SPI_Type *base, dspi_slave_handle_t *handle)
 {
     assert(handle);
 
-    uint8_t dummyPattern = DSPI_DUMMY_DATA;
+    uint8_t dummyPattern = s_dummyData[DSPI_GetInstance(base)];
     uint32_t dataReceived;
     uint32_t dataSend = 0;
 
@@ -1617,7 +1627,7 @@ static void DSPI_CommonIRQHandler(SPI_Type *base, void *param)
     }
 }
 
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 0)
+#if defined(SPI0)
 void SPI0_DriverIRQHandler(void)
 {
     assert(g_dspiHandle[0]);
@@ -1625,7 +1635,7 @@ void SPI0_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 1)
+#if defined(SPI1)
 void SPI1_DriverIRQHandler(void)
 {
     assert(g_dspiHandle[1]);
@@ -1633,7 +1643,7 @@ void SPI1_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 2)
+#if defined(SPI2)
 void SPI2_DriverIRQHandler(void)
 {
     assert(g_dspiHandle[2]);
@@ -1641,7 +1651,7 @@ void SPI2_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 3)
+#if defined(SPI3)
 void SPI3_DriverIRQHandler(void)
 {
     assert(g_dspiHandle[3]);
@@ -1649,7 +1659,7 @@ void SPI3_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 4)
+#if defined(SPI4)
 void SPI4_DriverIRQHandler(void)
 {
     assert(g_dspiHandle[4]);
@@ -1657,7 +1667,7 @@ void SPI4_DriverIRQHandler(void)
 }
 #endif
 
-#if (FSL_FEATURE_SOC_DSPI_COUNT > 5)
+#if defined(SPI5)
 void SPI5_DriverIRQHandler(void)
 {
     assert(g_dspiHandle[5]);
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.h
index eb730bd13a..48d7353935 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *
@@ -37,15 +37,14 @@
  * @{
  */
 
-
 /**********************************************************************************************************************
  * Definitions
  *********************************************************************************************************************/
 
 /*! @name Driver version */
 /*@{*/
-/*! @brief DSPI driver version 2.1.3. */
-#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 1, 3))
+/*! @brief DSPI driver version 2.2.0. */
+#define FSL_DSPI_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
 /*@}*/
 
 #ifndef DSPI_DUMMY_DATA
@@ -107,7 +106,8 @@ typedef enum _dspi_master_slave_mode
 } dspi_master_slave_mode_t;
 
 /*!
- * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is valid
+ * @brief DSPI Sample Point: Controls when the DSPI master samples SIN in the Modified Transfer Format. This field is
+ * valid
  * only when the CPHA bit in the CTAR register is 0.
  */
 typedef enum _dspi_master_sample_point
@@ -216,8 +216,9 @@ enum _dspi_transfer_config_flag_for_master
     kDSPI_MasterPcs4 = 4U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS4 signal. */
     kDSPI_MasterPcs5 = 5U << DSPI_MASTER_PCS_SHIFT, /*!< DSPI master transfer use PCS5 signal. */
 
-    kDSPI_MasterPcsContinuous = 1U << 20,       /*!< Indicates whether the PCS signal is continuous. */
-    kDSPI_MasterActiveAfterTransfer = 1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
+    kDSPI_MasterPcsContinuous = 1U << 20, /*!< Indicates whether the PCS signal is continuous. */
+    kDSPI_MasterActiveAfterTransfer =
+        1U << 21, /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
 };
 
 #define DSPI_SLAVE_CTAR_SHIFT (0U)   /*!< DSPI slave CTAR shift macro; used internally. */
@@ -240,7 +241,7 @@ enum _dspi_transfer_state
 /*! @brief DSPI master command date configuration used for the SPIx_PUSHR.*/
 typedef struct _dspi_command_data_config
 {
-    bool isPcsContinuous;            /*!< Option to enable the continuous assertion of the chip select between transfers.*/
+    bool isPcsContinuous; /*!< Option to enable the continuous assertion of the chip select between transfers.*/
     dspi_ctar_selection_t whichCtar; /*!< The desired Clock and Transfer Attributes
                                           Register (CTAR) to use for CTAS.*/
     dspi_which_pcs_t whichPcs;       /*!< The desired PCS signal to use for the data transfer.*/
@@ -257,10 +258,10 @@ typedef struct _dspi_master_ctar_config
     dspi_clock_phase_t cpha;          /*!< Clock phase. */
     dspi_shift_direction_t direction; /*!< MSB or LSB data shift direction. */
 
-    uint32_t pcsToSckDelayInNanoSec;        /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
-                                               delay. It also sets the boundary value if out of range.*/
-    uint32_t lastSckToPcsDelayInNanoSec;    /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
-                                               minimum delay. It also sets the boundary value if out of range.*/
+    uint32_t pcsToSckDelayInNanoSec;     /*!< PCS to SCK delay time in nanoseconds; setting to 0 sets the minimum
+                                            delay. It also sets the boundary value if out of range.*/
+    uint32_t lastSckToPcsDelayInNanoSec; /*!< The last SCK to PCS delay time in nanoseconds; setting to 0 sets the
+                                            minimum delay. It also sets the boundary value if out of range.*/
 
     uint32_t betweenTransferDelayInNanoSec; /*!< After the SCK delay time in nanoseconds; setting to 0 sets the minimum
                                              delay. It also sets the boundary value if out of range.*/
@@ -370,8 +371,9 @@ struct _dspi_master_handle
 
     uint8_t fifoSize; /*!< FIFO dataSize. */
 
-    volatile bool isPcsActiveAfterTransfer; /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
-    volatile bool isThereExtraByte;         /*!< Indicates whether there are extra bytes.*/
+    volatile bool
+        isPcsActiveAfterTransfer;   /*!< Indicates whether the PCS signal is active after the last frame transfer.*/
+    volatile bool isThereExtraByte; /*!< Indicates whether there are extra bytes.*/
 
     uint8_t *volatile txData;                  /*!< Send buffer. */
     uint8_t *volatile rxData;                  /*!< Receive buffer. */
@@ -575,6 +577,7 @@ static inline void DSPI_ClearStatusFlags(SPI_Type *base, uint32_t statusFlags)
  *
  * This function configures the various interrupt masks of the DSPI.  The parameters are a base and an interrupt mask.
  * Note, for Tx Fill and Rx FIFO drain requests, enable the interrupt request and disable the DMA request.
+ *       Do not use this API(write to RSER register) while DSPI is in running state.
  *
  * @code
  *  DSPI_EnableInterrupts(base, kDSPI_TxCompleteInterruptEnable | kDSPI_EndOfQueueInterruptEnable );
@@ -950,10 +953,12 @@ static inline uint32_t DSPI_MasterGetFormattedCommand(dspi_command_data_config_t
  * @brief Writes a 32-bit data word (16-bit command appended with 16-bit data) into the data
  *        buffer master mode and waits till complete to return.
  *
- * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total 32-bit word
+ * In this function, the user must append the 16-bit data to the 16-bit command information and then provide the total
+* 32-bit word
  * as the data to send.
  * The command portion provides characteristics of the data, such as the optional continuous chip select operation
- * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the desired PCS
+ * between transfers, the desired Clock and Transfer Attributes register to use for the associated SPI frame, the
+* desired PCS
  * signal to use for the data transfer, whether the current transfer is the last in the queue, and whether to clear the
  * transfer count (normally needed when sending the first frame of a data packet). The user is responsible for
  * appending this command with the data to send. This is an example:
@@ -1022,6 +1027,14 @@ static inline uint32_t DSPI_ReadData(SPI_Type *base)
     return (base->POPR);
 }
 
+/*!
+ * @brief Set up the dummy data.
+ *
+ * @param base DSPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void DSPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
+
 /*!
  *@}
 */
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.c b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.c
index a110c18881..467c892ff4 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.c
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.c
@@ -1,32 +1,32 @@
 /*
-* Copyright (c) 2015, Freescale Semiconductor, Inc.
-* All rights reserved.
-*
-* Redistribution and use in source and binary forms, with or without modification,
-* are permitted provided that the following conditions are met:
-*
-* o Redistributions of source code must retain the above copyright notice, this list
-*   of conditions and the following disclaimer.
-*
-* o Redistributions in binary form must reproduce the above copyright notice, this
-*   list of conditions and the following disclaimer in the documentation and/or
-*   other materials provided with the distribution.
-*
-* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
-*   contributors may be used to endorse or promote products derived from this
-*   software without specific prior written permission.
-*
-* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
+ * Copyright (c) 2015, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ *   of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ *   list of conditions and the following disclaimer in the documentation and/or
+ *   other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ *   contributors may be used to endorse or promote products derived from this
+ *   software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #include "fsl_dspi_edma.h"
 
@@ -57,7 +57,7 @@ typedef struct _dspi_slave_edma_private_handle
 ***********************************************************************************************************************/
 /*!
 * @brief EDMA_DspiMasterCallback after the DSPI master transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
 */
 static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
                                     void *g_dspiEdmaPrivateHandle,
@@ -66,7 +66,7 @@ static void EDMA_DspiMasterCallback(edma_handle_t *edmaHandle,
 
 /*!
 * @brief EDMA_DspiSlaveCallback after the DSPI slave transfer completed by using EDMA.
-* This is not a public API as it is called from other driver functions.
+* This is not a public API.
 */
 static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
                                    void *g_dspiEdmaPrivateHandle,
@@ -89,6 +89,8 @@ extern uint32_t DSPI_GetInstance(SPI_Type *base);
 static dspi_master_edma_private_handle_t s_dspiMasterEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
 static dspi_slave_edma_private_handle_t s_dspiSlaveEdmaPrivateHandle[FSL_FEATURE_SOC_DSPI_COUNT];
 
+/*! @brief Global variable for dummy data value setting. */
+extern volatile uint8_t s_dummyData[];
 /***********************************************************************************************************************
 * Code
 ***********************************************************************************************************************/
@@ -103,7 +105,9 @@ void DSPI_MasterTransferCreateHandleEDMA(SPI_Type *base,
 {
     assert(handle);
     assert(edmaRxRegToRxDataHandle);
+#if (!(defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET))
     assert(edmaTxDataToIntermediaryHandle);
+#endif
     assert(edmaIntermediaryToTxRegHandle);
 
     /* Zero the handle. */
@@ -145,9 +149,11 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         return kStatus_DSPI_Busy;
     }
 
+    handle->state = kDSPI_Busy;
+
     uint32_t instance = DSPI_GetInstance(base);
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
     uint8_t dataAlreadyFed = 0;
     uint8_t dataFedMax = 2;
 
@@ -158,9 +164,8 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
 
     edma_transfer_config_t transferConfigA;
     edma_transfer_config_t transferConfigB;
-    edma_transfer_config_t transferConfigC;
 
-    handle->txBuffIfNull = ((uint32_t)DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
+    handle->txBuffIfNull = ((uint32_t)dummyData << 8) | dummyData;
 
     dspi_command_data_config_t commandStruct;
     DSPI_StopTransfer(base);
@@ -196,20 +201,32 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     handle->remainingReceiveByteCount = transfer->dataSize;
     handle->totalByteCount = transfer->dataSize;
 
-    /* This limits the amount of data we can transfer due to the linked channel.
-    * The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
+    /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
+    * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
     */
+    uint32_t limited_size = 0;
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        limited_size = 32767u;
+    }
+    else
+    {
+        limited_size = 511u;
+    }
+
     if (handle->bitsPerFrame > 8)
     {
-        if (transfer->dataSize > 1022)
+        if (transfer->dataSize > (limited_size << 1u))
         {
+            handle->state = kDSPI_Idle;
             return kStatus_DSPI_OutOfRange;
         }
     }
     else
     {
-        if (transfer->dataSize > 511)
+        if (transfer->dataSize > limited_size)
         {
+            handle->state = kDSPI_Idle;
             return kStatus_DSPI_OutOfRange;
         }
     }
@@ -217,16 +234,38 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
     if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
     {
+        handle->state = kDSPI_Idle;
         return kStatus_InvalidArgument;
     }
 
-    handle->state = kDSPI_Busy;
-
     DSPI_DisableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
     EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiMasterCallback,
                      &s_dspiMasterEdmaPrivateHandle[instance]);
 
+    /*
+    (1)For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
+    channel_A minor link to channel_B , channel_B minor link to channel_C.
+
+    Already pushed 1 or 2 data in SPI_PUSHR , then start the DMA tansfer.
+    channel_A:SPI_POPR to rxData,
+    channel_B:next txData to handle->command (low 16 bits),
+    channel_C:handle->command (32 bits) to SPI_PUSHR, and use the scatter/gather to transfer the last data
+    (handle->lastCommand to SPI_PUSHR).
+
+    (2)For DSPI instances with separate RX and TX DMA requests:
+    Rx DMA request -> channel_A
+    Tx DMA request -> channel_C -> channel_B .
+    channel_C major link to channel_B.
+    So need prepare the first data in "intermediary"  before the DMA
+    transfer and then channel_B is used to prepare the next data to "intermediary"
+
+    channel_A:SPI_POPR to rxData,
+    channel_C: handle->command (32 bits) to SPI_PUSHR,
+    channel_B: next txData to handle->command (low 16 bits), and use the scatter/gather to prepare the last data
+    (handle->lastCommand to handle->Command).
+    */
+
     /*If dspi has separate dma request , prepare the first data in "intermediary" .
     else (dspi has shared dma request) , send first 2 data if there is fifo or send first 1 data if there is no fifo*/
     if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
@@ -252,6 +291,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
                     wordToSend = ((uint32_t)dummyData << 8) | dummyData;
                 }
                 handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                handle->command = handle->lastCommand;
             }
             else /* For all words except the last word , frame > 8bits */
             {
@@ -284,6 +324,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
             if (handle->remainingSendByteCount == 1)
             {
                 handle->lastCommand = (handle->lastCommand & 0xffff0000U) | wordToSend;
+                handle->command = handle->lastCommand;
             }
             else
             {
@@ -293,11 +334,10 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     }
 
     else /*dspi has shared dma request*/
-
     {
         /* For DSPI instances with shared RX/TX DMA requests, we'll use the RX DMA request to
-        * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
-        */
+         * trigger ongoing transfers and will link to the TX DMA channel from the RX DMA channel.
+         */
 
         /* If bits/frame is greater than one byte */
         if (handle->bitsPerFrame > 8)
@@ -388,7 +428,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         }
     }
 
-    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer*/
+    /***channel_A *** used for carry the data from Rx_Data_Register(POPR) to User_Receive_Buffer(rxData)*/
     EDMA_ResetChannel(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel);
 
     transferConfigA.srcAddr = (uint32_t)rxAddr;
@@ -428,71 +468,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     EDMA_EnableChannelInterrupts(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
                                  kEDMA_MajorInterruptEnable);
 
-    /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
-    write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
-    SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
-    EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
-
-    if (handle->remainingSendByteCount > 0)
-    {
-        if (handle->txData)
-        {
-            transferConfigB.srcAddr = (uint32_t)(handle->txData);
-            transferConfigB.srcOffset = 1;
-        }
-        else
-        {
-            transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
-            transferConfigB.srcOffset = 0;
-        }
-
-        transferConfigB.destAddr = (uint32_t)(&handle->command);
-        transferConfigB.destOffset = 0;
-
-        transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
-
-        if (handle->bitsPerFrame <= 8)
-        {
-            transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
-            transferConfigB.minorLoopBytes = 1;
-
-            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
-            {
-                /*already prepared the first data in "intermediary" , so minus 1 */
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
-            }
-            else
-            {
-                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
-                majorlink , the majorlink would not trigger the channel_C*/
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
-            }
-        }
-        else
-        {
-            transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
-            transferConfigB.minorLoopBytes = 2;
-            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
-            {
-                /*already prepared the first data in "intermediary" , so minus 1 */
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
-            }
-            else
-            {
-                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
-                * majorlink*/
-                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
-            }
-        }
-
-        EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
-                               handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
-    }
-
-    /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
-    handle the last data */
-    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
-
+    /*Calculate the last data : handle->lastCommand*/
     if (((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
         ((((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
           ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8))) &&
@@ -543,8 +519,252 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         }
     }
 
+/* The feature of GASKET is that the SPI supports 8-bit or 16-bit writes to the PUSH TX FIFO,
+ * allowing a single write to the command word followed by multiple writes to the transmit word.
+ * The TX FIFO will save the last command word written, and convert a 8-bit/16-bit write to the
+ * transmit word into a 32-bit write that pushes both the command word and transmit word into
+ * the TX FIFO (PUSH TX FIFO Register In Master Mode)
+ * So, if this feature is supported, we can use use one channel to carry the receive data from
+ * receive regsiter to user data buffer, use the other channel to carry the data from user data buffer
+ * to transmit register,and use the scatter/gather function to prepare the last data.
+ * That is to say, if GASKET feature is supported, we can use only two channels for tansferring data.
+ */
+#if defined(FSL_FEATURE_DSPI_HAS_GASKET) && FSL_FEATURE_DSPI_HAS_GASKET
+    /*  For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to PUSHR register.
+     */
+
+    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
+
     if ((1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) ||
-        ((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
+        ((handle->remainingSendByteCount > 0) && (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))))
+    {
+        transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
+        transferConfigB.destAddr = (uint32_t)txAddr;
+        transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.srcOffset = 0;
+        transferConfigB.destOffset = 0;
+        transferConfigB.minorLoopBytes = 4;
+        transferConfigB.majorLoopCounts = 1;
+
+        EDMA_TcdReset(softwareTCD);
+        EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
+    }
+
+    /*User_Send_Buffer(txData) to PUSHR register. */
+    if (((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
+        ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8)))
+    {
+        if (handle->txData)
+        {
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                /* For DSPI with separate RX and TX DMA requests, one frame data has been carry
+                 * to handle->command, so need to reduce the pointer of txData.
+                 */
+                transferConfigB.srcAddr =
+                    (uint32_t)((uint8_t *)(handle->txData) - ((handle->bitsPerFrame <= 8) ? (1U) : (2U)));
+                transferConfigB.srcOffset = 1;
+            }
+            else
+            {
+                /* For DSPI with shared RX and TX DMA requests, one or two frame data have been carry
+                 * to PUSHR register, so no need to change the pointer of txData.
+                 */
+                transferConfigB.srcAddr = (uint32_t)((uint8_t *)(handle->txData));
+                transferConfigB.srcOffset = 1;
+            }
+        }
+        else
+        {
+            transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigB.srcOffset = 0;
+        }
+
+        transferConfigB.destAddr = (uint32_t)txAddr;
+        transferConfigB.destOffset = 0;
+
+        transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigB.minorLoopBytes = 1;
+
+            transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 1;
+        }
+        else
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigB.minorLoopBytes = 2;
+            transferConfigB.majorLoopCounts = (handle->remainingSendByteCount / 2) - 1;
+        }
+
+        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, softwareTCD);
+    }
+    /* If only one word to transmit, only carry the lastcommand. */
+    else
+    {
+        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigB, NULL);
+    }
+
+    /*Start the EDMA channel_A , channel_C. */
+    EDMA_StartTransfer(handle->edmaRxRegToRxDataHandle);
+    EDMA_StartTransfer(handle->edmaIntermediaryToTxRegHandle);
+
+    /* Set the channel link.
+     * For DSPI instances with shared TX and RX DMA requests, setup channel minor link, first receive data from the
+     * receive register, and then carry transmit data to PUSHER register.
+     * For DSPI instance with separate TX and RX DMA requests, there is no need to set up channel link.
+     */
+    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        /*Set channel priority*/
+        uint8_t channelPriorityLow = handle->edmaRxRegToRxDataHandle->channel;
+        uint8_t channelPriorityHigh = handle->edmaIntermediaryToTxRegHandle->channel;
+        uint8_t t = 0;
+
+        if (channelPriorityLow > channelPriorityHigh)
+        {
+            t = channelPriorityLow;
+            channelPriorityLow = channelPriorityHigh;
+            channelPriorityHigh = t;
+        }
+
+        edma_channel_Preemption_config_t preemption_config_t;
+        preemption_config_t.enableChannelPreemption = true;
+        preemption_config_t.enablePreemptAbility = true;
+        preemption_config_t.channelPriority = channelPriorityLow;
+
+        EDMA_SetChannelPreemptionConfig(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                        &preemption_config_t);
+
+        preemption_config_t.channelPriority = channelPriorityHigh;
+        EDMA_SetChannelPreemptionConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                        handle->edmaIntermediaryToTxRegHandle->channel, &preemption_config_t);
+        /*if there is Rx DMA request , carry the 32bits data (handle->command) to user data first , then link to
+          channelC to carry the next data to PUSHER register.(txData to PUSHER) */
+        if (handle->remainingSendByteCount > 0)
+        {
+            EDMA_SetChannelLink(handle->edmaRxRegToRxDataHandle->base, handle->edmaRxRegToRxDataHandle->channel,
+                                kEDMA_MinorLink, handle->edmaIntermediaryToTxRegHandle->channel);
+        }
+    }
+
+    DSPI_EnableDMA(base, kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
+
+    /* Setup control info to PUSHER register. */
+    *((uint16_t *)&(base->PUSHR) + 1) = (handle->command >> 16U);
+#else
+
+    /***channel_B *** used for carry the data from User_Send_Buffer to "intermediary" because the SPIx_PUSHR should
+    write the 32bits at once time . Then use channel_C to carry the "intermediary" to SPIx_PUSHR. Note that the
+    SPIx_PUSHR upper 16 bits are the "command" and the low 16bits are data */
+
+    EDMA_ResetChannel(handle->edmaTxDataToIntermediaryHandle->base, handle->edmaTxDataToIntermediaryHandle->channel);
+
+    /*For DSPI instances with separate RX and TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to handle->Command*/
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    {
+        transferConfigB.srcAddr = (uint32_t) & (handle->lastCommand);
+        transferConfigB.destAddr = (uint32_t) & (handle->command);
+        transferConfigB.srcTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.destTransferSize = kEDMA_TransferSize4Bytes;
+        transferConfigB.srcOffset = 0;
+        transferConfigB.destOffset = 0;
+        transferConfigB.minorLoopBytes = 4;
+        transferConfigB.majorLoopCounts = 1;
+
+        EDMA_TcdReset(softwareTCD);
+        EDMA_TcdSetTransferConfig(softwareTCD, &transferConfigB, NULL);
+    }
+
+    /*User_Send_Buffer(txData) to intermediary(handle->command)*/
+    if (((((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame <= 8)) ||
+          ((handle->remainingSendByteCount > 4) && (handle->bitsPerFrame > 8))) &&
+         (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))) ||
+        (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
+    {
+        if (handle->txData)
+        {
+            transferConfigB.srcAddr = (uint32_t)(handle->txData);
+            transferConfigB.srcOffset = 1;
+        }
+        else
+        {
+            transferConfigB.srcAddr = (uint32_t)(&handle->txBuffIfNull);
+            transferConfigB.srcOffset = 0;
+        }
+
+        transferConfigB.destAddr = (uint32_t)(&handle->command);
+        transferConfigB.destOffset = 0;
+
+        transferConfigB.srcTransferSize = kEDMA_TransferSize1Bytes;
+
+        if (handle->bitsPerFrame <= 8)
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize1Bytes;
+            transferConfigB.minorLoopBytes = 1;
+
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount - 2;
+            }
+            else
+            {
+                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+                majorlink , the majorlink would not trigger the channel_C*/
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount + 1;
+            }
+        }
+        else
+        {
+            transferConfigB.destTransferSize = kEDMA_TransferSize2Bytes;
+            transferConfigB.minorLoopBytes = 2;
+            if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+            {
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 - 2;
+            }
+            else
+            {
+                /*Only enable channel_B minorlink to channel_C , so need to add one count due to the last time is
+                * majorlink*/
+                transferConfigB.majorLoopCounts = handle->remainingSendByteCount / 2 + 1;
+            }
+        }
+
+        if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                   handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, softwareTCD);
+            EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
+                                       handle->edmaIntermediaryToTxRegHandle->channel, false);
+        }
+        else
+        {
+            EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                                   handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+        }
+    }
+    else
+    {
+        EDMA_SetTransferConfig(handle->edmaTxDataToIntermediaryHandle->base,
+                               handle->edmaTxDataToIntermediaryHandle->channel, &transferConfigB, NULL);
+    }
+
+    /***channel_C ***carry the "intermediary" to SPIx_PUSHR. used the edma Scatter Gather function on channel_C to
+    handle the last data */
+
+    edma_transfer_config_t transferConfigC;
+    EDMA_ResetChannel(handle->edmaIntermediaryToTxRegHandle->base, handle->edmaIntermediaryToTxRegHandle->channel);
+
+    /*For DSPI instances with shared RX/TX DMA requests: use the scatter/gather to prepare the last data
+     * (handle->lastCommand) to SPI_PUSHR*/
+    if (((1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)) && (handle->remainingSendByteCount > 0)))
     {
         transferConfigC.srcAddr = (uint32_t) & (handle->lastCommand);
         transferConfigC.destAddr = (uint32_t)txAddr;
@@ -560,7 +780,8 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
     }
 
     if (((handle->remainingSendByteCount > 1) && (handle->bitsPerFrame <= 8)) ||
-        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)))
+        ((handle->remainingSendByteCount > 2) && (handle->bitsPerFrame > 8)) ||
+        (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base)))
     {
         transferConfigC.srcAddr = (uint32_t)(&(handle->command));
         transferConfigC.destAddr = (uint32_t)txAddr;
@@ -570,18 +791,28 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
         transferConfigC.srcOffset = 0;
         transferConfigC.destOffset = 0;
         transferConfigC.minorLoopBytes = 4;
-
-        if (handle->bitsPerFrame <= 8)
+        if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
         {
-            transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+            if (handle->bitsPerFrame <= 8)
+            {
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount - 1;
+            }
+            else
+            {
+                transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            }
+
+            EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
         }
         else
         {
-            transferConfigC.majorLoopCounts = handle->remainingSendByteCount / 2 - 1;
+            transferConfigC.majorLoopCounts = 1;
+
+            EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
+                                   handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, NULL);
         }
 
-        EDMA_SetTransferConfig(handle->edmaIntermediaryToTxRegHandle->base,
-                               handle->edmaIntermediaryToTxRegHandle->channel, &transferConfigC, softwareTCD);
         EDMA_EnableAutoStopRequest(handle->edmaIntermediaryToTxRegHandle->base,
                                    handle->edmaIntermediaryToTxRegHandle->channel, false);
     }
@@ -653,20 +884,15 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
                                         &preemption_config_t);
     }
 
-    /*Set the channel link.
-    For DSPI instances with shared RX/TX DMA requests: Rx DMA request -> channel_A -> channel_B-> channel_C.
-    For DSPI instances with separate RX and TX DMA requests:
-    Rx DMA request -> channel_A
-    Tx DMA request -> channel_C -> channel_B . (so need prepare the first data in "intermediary"  before the DMA
-    transfer and then channel_B is used to prepare the next data to "intermediary" ) */
+    /*Set the channel link.*/
     if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
     {
         /*if there is Tx DMA request , carry the 32bits data (handle->command) to PUSHR first , then link to channelB
-        to prepare the next 32bits data (User_send_buffer to handle->command) */
+        to prepare the next 32bits data (txData to handle->command) */
         if (handle->remainingSendByteCount > 1)
         {
             EDMA_SetChannelLink(handle->edmaIntermediaryToTxRegHandle->base,
-                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MinorLink,
+                                handle->edmaIntermediaryToTxRegHandle->channel, kEDMA_MajorLink,
                                 handle->edmaTxDataToIntermediaryHandle->channel);
         }
 
@@ -686,7 +912,7 @@ status_t DSPI_MasterTransferEDMA(SPI_Type *base, dspi_master_edma_handle_t *hand
 
         DSPI_EnableDMA(base, kDSPI_RxDmaEnable);
     }
-
+#endif
     DSPI_StartTransfer(base);
 
     return kStatus_Success;
@@ -805,6 +1031,8 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
         return kStatus_DSPI_Busy;
     }
 
+    handle->state = kDSPI_Busy;
+
     uint32_t instance = DSPI_GetInstance(base);
     uint8_t whichCtar = (transfer->configFlags & DSPI_SLAVE_CTAR_MASK) >> DSPI_SLAVE_CTAR_SHIFT;
     handle->bitsPerFrame =
@@ -813,34 +1041,42 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
     /* If using a shared RX/TX DMA request, then this limits the amount of data we can transfer
     * due to the linked channel. The max bytes is 511 if 8-bit/frame or 1022 if 16-bit/frame
     */
-    if (1 != FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
+    uint32_t limited_size = 0;
+    if (1 == FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(base))
     {
-        if (handle->bitsPerFrame > 8)
+        limited_size = 32767u;
+    }
+    else
+    {
+        limited_size = 511u;
+    }
+
+    if (handle->bitsPerFrame > 8)
+    {
+        if (transfer->dataSize > (limited_size << 1u))
         {
-            if (transfer->dataSize > 1022)
-            {
-                return kStatus_DSPI_OutOfRange;
-            }
+            handle->state = kDSPI_Idle;
+            return kStatus_DSPI_OutOfRange;
         }
-        else
+    }
+    else
+    {
+        if (transfer->dataSize > limited_size)
         {
-            if (transfer->dataSize > 511)
-            {
-                return kStatus_DSPI_OutOfRange;
-            }
+            handle->state = kDSPI_Idle;
+            return kStatus_DSPI_OutOfRange;
         }
     }
 
     /*The data size should be even if the bitsPerFrame is greater than 8 (that is 2 bytes per frame in dspi) */
     if ((handle->bitsPerFrame > 8) && (transfer->dataSize & 0x1))
     {
+        handle->state = kDSPI_Idle;
         return kStatus_InvalidArgument;
     }
 
     EDMA_SetCallback(handle->edmaRxRegToRxDataHandle, EDMA_DspiSlaveCallback, &s_dspiSlaveEdmaPrivateHandle[instance]);
 
-    handle->state = kDSPI_Busy;
-
     /* Store transfer information */
     handle->txData = transfer->txData;
     handle->rxData = transfer->rxData;
@@ -849,7 +1085,7 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
     handle->totalByteCount = transfer->dataSize;
 
     uint16_t wordToSend = 0;
-    uint8_t dummyData = DSPI_DUMMY_DATA;
+    uint8_t dummyData = s_dummyData[DSPI_GetInstance(base)];
     uint8_t dataAlreadyFed = 0;
     uint8_t dataFedMax = 2;
 
@@ -1003,11 +1239,11 @@ status_t DSPI_SlaveTransferEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle
             transferConfigC.srcOffset = 0;
             if (handle->bitsPerFrame <= 8)
             {
-                handle->txBuffIfNull = DSPI_DUMMY_DATA;
+                handle->txBuffIfNull = dummyData;
             }
             else
             {
-                handle->txBuffIfNull = (DSPI_DUMMY_DATA << 8) | DSPI_DUMMY_DATA;
+                handle->txBuffIfNull = ((uint32_t)dummyData << 8) | dummyData;
             }
         }
 
@@ -1106,13 +1342,13 @@ static void EDMA_DspiSlaveCallback(edma_handle_t *edmaHandle,
 
     DSPI_DisableDMA((dspiEdmaPrivateHandle->base), kDSPI_RxDmaEnable | kDSPI_TxDmaEnable);
 
+    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
+
     if (dspiEdmaPrivateHandle->handle->callback)
     {
         dspiEdmaPrivateHandle->handle->callback(dspiEdmaPrivateHandle->base, dspiEdmaPrivateHandle->handle,
                                                 kStatus_Success, dspiEdmaPrivateHandle->handle->userData);
     }
-
-    dspiEdmaPrivateHandle->handle->state = kDSPI_Idle;
 }
 
 void DSPI_SlaveTransferAbortEDMA(SPI_Type *base, dspi_slave_edma_handle_t *handle)
diff --git a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.h b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.h
index 4b4dbd930e..23e29ce298 100644
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.h
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_dspi_edma.h
@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2015, Freescale Semiconductor, Inc.
- * All rights reserved.
+ * Copyright 2016-2017 NXP
  *
  * Redistribution and use in source and binary forms, with or without modification,
  * are permitted provided that the following conditions are met:
@@ -12,7 +12,7 @@
  *   list of conditions and the following disclaimer in the documentation and/or
  *   other materials provided with the distribution.
  *
- * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+ * o Neither the name of the copyright holder nor the names of its
  *   contributors may be used to endorse or promote products derived from this
  *   software without specific prior written permission.
  *