mirror of https://github.com/ARMmbed/mbed-os.git
Merge pull request #504 from 0xc0170/fix_enet_k64f_ksdk
[NET, HAL] K64F - update files to use address of enet peripheral (not instance as required by KSDK v1.0)pull/505/head
Martin Kojtal
commit
cb3999ca5e
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@ -1,69 +0,0 @@
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/*
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* Copyright (c) 2013 - 2014, Freescale Semiconductor, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_enet_driver.h"
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#include "fsl_clock_manager.h"
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#ifndef MBED_NO_ENET
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#define ENET_INSTANCE 0U
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if defined (K64F12_SERIES) || defined (K70F12_SERIES) || defined (K63F12_SERIES)
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void ENET_Transmit_IRQHandler(void)
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{
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ENET_DRV_TxIRQHandler(ENET_INSTANCE);
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}
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void ENET_Receive_IRQHandler(void)
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{
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ENET_DRV_RxIRQHandler(ENET_INSTANCE);
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}
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#if FSL_FEATURE_ENET_SUPPORT_PTP
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void ENET_1588_Timer_IRQHandler(void)
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{
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ENET_DRV_TsIRQHandler(ENET_INSTANCE);
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}
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#endif
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#endif
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#endif /* MBED_NO_ENET */
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/*******************************************************************************
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* EOF
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******************************************************************************/
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@ -48,7 +48,7 @@
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*END*********************************************************************/
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void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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uint32_t address, data;
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@ -67,7 +67,7 @@ void enet_hal_set_mac_address(uint32_t instance, enetMacAddr hwAddr)
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*END*********************************************************************/
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void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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switch (mode)
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{
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@ -108,7 +108,7 @@ void enet_hal_set_group_hashtable(uint32_t instance, uint32_t crcValue, enet_spe
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*END*********************************************************************/
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void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, enet_special_address_filter_t mode)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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switch (mode)
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{
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@ -148,7 +148,7 @@ void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, ene
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*END*********************************************************************/
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void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *thresholdCfg)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(thresholdCfg);
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BW_ENET_TFWR_STRFWD(instance, thresholdCfg->isStoreForwardEnabled); /* Set store and forward mode*/
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@ -169,7 +169,7 @@ void enet_hal_config_tx_fifo(uint32_t instance, enet_config_tx_fifo_t *threshold
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*END*********************************************************************/
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void enet_hal_config_rx_fifo(uint32_t instance,enet_config_rx_fifo_t *thresholdCfg )
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(thresholdCfg);
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if(thresholdCfg->rxFull > 0)
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{
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@ -404,7 +404,7 @@ bool enet_hal_get_txbd_timestamp_flag(void *curBd)
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*END*********************************************************************/
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void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_config_speed_t speed, enet_config_duplex_t duplex, bool isRxOnTxDisabled, bool isLoopEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_MII_MODE(instance,1); /* Set mii mode */
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BW_ENET_RCR_RMII_MODE(instance,mode);
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@ -432,7 +432,7 @@ void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_confi
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*END*********************************************************************/
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void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyReg, enet_mii_operation_t operation, uint32_t data)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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uint32_t mmfrValue = 0 ;
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mmfrValue = BF_ENET_MMFR_ST(1)| BF_ENET_MMFR_OP(operation)| BF_ENET_MMFR_PA(phyAddr) | BF_ENET_MMFR_RA(phyReg)| BF_ENET_MMFR_TA(2) | (data&0xFFFF); /* mii command*/
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@ -446,7 +446,7 @@ void enet_hal_set_mii_command(uint32_t instance, uint32_t phyAddr, uint32_t phyR
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*END*********************************************************************/
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void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_ECR_ETHEREN(instance,isEnabled); /* Enable/Disable Ethernet module*/
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if (isEnhanced)
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@ -467,7 +467,7 @@ void enet_hal_config_ethernet(uint32_t instance, bool isEnhanced, bool isEnabled
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*END*********************************************************************/
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void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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if (isEnabled)
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{
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@ -486,7 +486,7 @@ void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnable
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*END*********************************************************************/
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void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerator_t *txCfgPtr)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(txCfgPtr);
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HW_ENET_TACC_WR(instance,0); /* Clear all*/
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@ -502,7 +502,7 @@ void enet_hal_config_tx_accelerator(uint32_t instance, enet_config_tx_accelerato
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*END*********************************************************************/
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void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerator_t *rxCfgPtr)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(rxCfgPtr);
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HW_ENET_RACC_WR(instance,0); /* Clear all*/
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@ -523,7 +523,7 @@ void enet_hal_config_rx_accelerator(uint32_t instance, enet_config_rx_accelerato
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*END*********************************************************************/
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void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
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BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
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BW_ENET_TCR_TFC_PAUSE(instance, 1);
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@ -536,7 +536,7 @@ void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration)
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*END*********************************************************************/
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void enet_hal_init_ptp_timer(uint32_t instance,enet_config_ptp_timer_t *ptpCfgPtr)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(ptpCfgPtr);
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BW_ENET_ATINC_INC(instance, ptpCfgPtr->clockIncease); /* Set increase value for ptp timer*/
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@ -431,7 +431,7 @@ extern "C" {
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*/
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static inline void enet_hal_reset_ethernet(uint32_t instance)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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HW_ENET_ECR_SET(instance, BM_ENET_ECR_RESET);
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}
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@ -446,7 +446,7 @@ static inline void enet_hal_reset_ethernet(uint32_t instance)
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*/
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static inline bool enet_hal_is_reset_completed(uint32_t instance)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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return (BR_ENET_ECR_RESET(instance) == 0);
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}
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@ -465,7 +465,7 @@ static inline bool enet_hal_is_reset_completed(uint32_t instance)
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*/
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static inline void enet_hal_enable_stop(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_ECR_STOPEN(instance, isEnabled);
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}
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/*!
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@ -482,7 +482,7 @@ static inline void enet_hal_enable_stop(uint32_t instance, bool isEnabled)
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*/
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static inline void enet_hal_enable_sleep(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_ECR_SLEEP(instance, isEnabled);
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BW_ENET_ECR_MAGICEN(instance, isEnabled);
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}
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@ -536,7 +536,7 @@ void enet_hal_set_individual_hashtable(uint32_t instance, uint32_t crcValue, ene
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*/
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static inline void enet_hal_enable_payloadcheck(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_NLC(instance, isEnabled);
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}
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@ -554,7 +554,7 @@ static inline void enet_hal_enable_payloadcheck(uint32_t instance, bool isEnable
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*/
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static inline void enet_hal_enable_txcrcforward(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_TCR_CRCFWD(instance, !isEnabled);
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}
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@ -573,7 +573,7 @@ static inline void enet_hal_enable_txcrcforward(uint32_t instance, bool isEnable
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*/
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static inline void enet_hal_enable_rxcrcforward(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_CRCFWD(instance, !isEnabled);
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}
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/*!
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@ -588,7 +588,7 @@ static inline void enet_hal_enable_rxcrcforward(uint32_t instance, bool isEnable
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*/
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static inline void enet_hal_enable_pauseforward(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_PAUFWD(instance, isEnabled);
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}
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@ -604,7 +604,7 @@ static inline void enet_hal_enable_pauseforward(uint32_t instance, bool isEnable
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*/
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static inline void enet_hal_enable_padremove(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_PADEN(instance, isEnabled);
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}
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@ -622,7 +622,7 @@ static inline void enet_hal_enable_padremove(uint32_t instance, bool isEnabled)
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*/
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static inline void enet_hal_enable_flowcontrol(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_CFEN(instance, isEnabled);
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BW_ENET_RCR_FCE(instance, isEnabled);
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}
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@ -640,7 +640,7 @@ static inline void enet_hal_enable_flowcontrol(uint32_t instance, bool isEnabled
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*/
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static inline void enet_hal_enable_broadcastreject(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_RCR_BC_REJ(instance, isEnabled);
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}
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@ -657,7 +657,7 @@ static inline void enet_hal_enable_broadcastreject(uint32_t instance, bool isEna
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*/
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static inline void enet_hal_set_pauseduration(uint32_t instance, uint32_t pauseDuration)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(pauseDuration <= BM_ENET_OPD_PAUSE_DUR);
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BW_ENET_OPD_PAUSE_DUR(instance, pauseDuration);
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}
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@ -674,7 +674,7 @@ static inline void enet_hal_set_pauseduration(uint32_t instance, uint32_t pauseD
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*/
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static inline bool enet_hal_get_rxpause_status(uint32_t instance)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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return BR_ENET_TCR_RFC_PAUSE(instance);
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}
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/*!
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@ -692,7 +692,7 @@ static inline bool enet_hal_get_rxpause_status(uint32_t instance)
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*/
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static inline void enet_hal_enable_txpause(uint32_t instance, bool isEnabled)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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BW_ENET_TCR_TFC_PAUSE(instance, isEnabled);
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}
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@ -721,7 +721,7 @@ void enet_hal_set_txpause(uint32_t instance, uint32_t pauseDuration);
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*/
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static inline void enet_hal_set_txipg(uint32_t instance, uint32_t ipgValue)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(ipgValue <= BM_ENET_TIPG_IPG);
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BW_ENET_TIPG_IPG(instance, ipgValue);
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}
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@ -740,7 +740,7 @@ static inline void enet_hal_set_txipg(uint32_t instance, uint32_t ipgValue)
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*/
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static inline void enet_hal_set_truncationlen(uint32_t instance, uint32_t length)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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assert(length <= BM_ENET_FTRL_TRUNC_FL);
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BW_ENET_FTRL_TRUNC_FL(instance, length);
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}
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@ -756,7 +756,7 @@ static inline void enet_hal_set_truncationlen(uint32_t instance, uint32_t length
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*/
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static inline void enet_hal_set_rx_max_size(uint32_t instance, uint32_t maxBufferSize, uint32_t maxFrameSize)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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/* max buffer size must larger than 256 to minimize bus usage*/
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assert(maxBufferSize >= 256);
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assert(maxFrameSize <= (BM_ENET_RCR_MAX_FL >> BP_ENET_RCR_MAX_FL));
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@ -793,7 +793,7 @@ void enet_hal_config_rx_fifo(uint32_t instance, enet_config_rx_fifo_t *threshold
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*/
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static inline void enet_hal_set_rxbd_address(uint32_t instance, uint32_t rxBdAddr)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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HW_ENET_RDSR_WR(instance,rxBdAddr); /* Initialize receive buffer descriptor start address*/
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}
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@ -809,7 +809,7 @@ static inline void enet_hal_set_rxbd_address(uint32_t instance, uint32_t rxBdAdd
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*/
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static inline void enet_hal_set_txbd_address(uint32_t instance, uint32_t txBdAddr)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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HW_ENET_TDSR_WR(instance,txBdAddr); /* Initialize transmit buffer descriptor start address*/
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}
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@ -984,7 +984,7 @@ uint32_t enet_hal_get_bd_timestamp(void *curBd);
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*/
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static inline void enet_hal_active_rxbd(uint32_t instance)
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{
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assert(instance < HW_ENET_INSTANCE_COUNT);
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// assert(instance < HW_ENET_INSTANCE_COUNT);
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HW_ENET_RDAR_SET(instance, BM_ENET_RDAR_RDAR);
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}
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|
|
@ -999,7 +999,7 @@ uint32_t enet_hal_get_bd_timestamp(void *curBd);
|
|||
*/
|
||||
static inline void enet_hal_active_txbd(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
HW_ENET_TDAR_SET(instance, BM_ENET_TDAR_TDAR);
|
||||
}
|
||||
|
|
@ -1035,8 +1035,8 @@ void enet_hal_config_rmii(uint32_t instance, enet_config_rmii_t mode, enet_confi
|
|||
static inline void enet_hal_config_mii(uint32_t instance, uint32_t miiSpeed,
|
||||
enet_mdio_holdon_clkcycle_t clkCycle, bool isPreambleDisabled)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
BW_ENET_MSCR_MII_SPEED(instance, miiSpeed); /* MII speed set*/
|
||||
BW_ENET_MSCR_DIS_PRE(instance, isPreambleDisabled); /* Preamble is disabled*/
|
||||
BW_ENET_MSCR_HOLDTIME(instance, clkCycle); /* hold on clock cycles for MDIO output*/
|
||||
|
|
@ -1056,7 +1056,7 @@ static inline void enet_hal_config_mii(uint32_t instance, uint32_t miiSpeed,
|
|||
*/
|
||||
static inline bool enet_hal_is_mii_enabled(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
return (HW_ENET_MSCR_RD(instance) & 0x7E)!= 0;
|
||||
}
|
||||
|
|
@ -1069,7 +1069,7 @@ static inline bool enet_hal_is_mii_enabled(uint32_t instance)
|
|||
*/
|
||||
static inline uint32_t enet_hal_get_mii_data(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
return (uint32_t)BR_ENET_MMFR_DATA(instance);
|
||||
}
|
||||
|
|
@ -1113,7 +1113,7 @@ void enet_hal_config_interrupt(uint32_t instance, uint32_t source, bool isEnable
|
|||
*/
|
||||
static inline void enet_hal_clear_interrupt(uint32_t instance, uint32_t source)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
HW_ENET_EIR_WR(instance,source);
|
||||
}
|
||||
|
|
@ -1130,7 +1130,7 @@ static inline void enet_hal_clear_interrupt(uint32_t instance, uint32_t source)
|
|||
*/
|
||||
static inline bool enet_hal_get_interrupt_status(uint32_t instance, uint32_t source)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
return ((HW_ENET_EIR_RD(instance) & source) != 0);
|
||||
}
|
||||
|
|
@ -1143,7 +1143,7 @@ static inline bool enet_hal_get_interrupt_status(uint32_t instance, uint32_t sou
|
|||
*/
|
||||
static inline void enet_hal_config_promiscuous(uint32_t instance, bool isEnabled)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
BW_ENET_RCR_PROM(instance,isEnabled);
|
||||
}
|
||||
|
|
@ -1156,7 +1156,7 @@ static inline void enet_hal_config_promiscuous(uint32_t instance, bool isEnabled
|
|||
*/
|
||||
static inline void enet_hal_clear_mib(uint32_t instance, bool isEnabled)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
BW_ENET_MIBC_MIB_CLEAR(instance, isEnabled);
|
||||
|
||||
|
|
@ -1172,7 +1172,7 @@ static inline void enet_hal_clear_mib(uint32_t instance, bool isEnabled)
|
|||
*/
|
||||
static inline void enet_hal_enable_mib(uint32_t instance, bool isEnabled)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
BW_ENET_MIBC_MIB_DIS(instance,!isEnabled);
|
||||
|
||||
|
|
@ -1186,7 +1186,7 @@ static inline void enet_hal_enable_mib(uint32_t instance, bool isEnabled)
|
|||
*/
|
||||
static inline bool enet_hal_get_mib_status(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
return BR_ENET_MIBC_MIB_IDLE(instance);
|
||||
}
|
||||
|
|
@ -1231,7 +1231,7 @@ void enet_hal_init_ptp_timer(uint32_t instance, enet_config_ptp_timer_t *ptpCfgP
|
|||
*/
|
||||
static inline void enet_hal_enable_ptp_timer(uint32_t instance, uint32_t isEnabled)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
BW_ENET_ATCR_EN(instance,isEnabled);
|
||||
}
|
||||
|
|
@ -1245,7 +1245,7 @@ static inline void enet_hal_enable_ptp_timer(uint32_t instance, uint32_t isEnabl
|
|||
*/
|
||||
static inline void enet_hal_restart_ptp_timer(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
BW_ENET_ATCR_RESTART(instance,1);
|
||||
}
|
||||
|
|
@ -1261,7 +1261,7 @@ static inline void enet_hal_restart_ptp_timer(uint32_t instance)
|
|||
*/
|
||||
static inline void enet_hal_adjust_ptp_timer(uint32_t instance, uint32_t increaseCorrection, uint32_t periodCorrection)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
HW_ENET_ATINC_SET(instance,((increaseCorrection << ENET_ATINC_INC_CORR_SHIFT) & ENET_ATINC_INC_CORR_MASK)); /* set correction for ptp timer increase*/
|
||||
/* set correction for ptp timer period*/
|
||||
|
|
@ -1277,7 +1277,7 @@ static inline void enet_hal_adjust_ptp_timer(uint32_t instance, uint32_t increas
|
|||
*/
|
||||
static inline void enet_hal_init_timer_channel(uint32_t instance, uint32_t channel, enet_timer_channel_mode_t mode)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
assert(channel < HW_ENET_TCSRn_COUNT);
|
||||
HW_ENET_TCSRn_SET(instance, channel,
|
||||
(BM_ENET_TCSRn_TMODE &(mode << BP_ENET_TCSRn_TMODE)));
|
||||
|
|
@ -1309,7 +1309,7 @@ static inline void enet_hal_set_timer_channel_compare(uint32_t instance, uint32_
|
|||
*/
|
||||
static inline bool enet_hal_get_timer_channel_status(uint32_t instance, uint32_t channel)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
assert(channel < HW_ENET_TCSRn_COUNT);
|
||||
|
||||
return BR_ENET_TCSRn_TF(instance,channel);
|
||||
|
|
@ -1323,8 +1323,8 @@ static inline bool enet_hal_get_timer_channel_status(uint32_t instance, uint32_t
|
|||
*/
|
||||
static inline void enet_hal_clear_timer_channel_flag(uint32_t instance, uint32_t channel)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
assert(channel < HW_ENET_TCSRn_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
assert(channel < HW_ENET_TCSRn_COUNT);
|
||||
HW_ENET_TCSRn_SET(instance, channel, BM_ENET_TCSRn_TF);/* clear interrupt flag*/
|
||||
HW_ENET_TGSR_WR(instance,(1U << channel)); /* clear channel flag*/
|
||||
}
|
||||
|
|
@ -1353,7 +1353,7 @@ static inline void enet_hal_set_timer_capture(uint32_t instance)
|
|||
*/
|
||||
static inline void enet_hal_set_current_time(uint32_t instance, uint32_t nanSecond)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
HW_ENET_ATVR_WR(instance,nanSecond);
|
||||
}
|
||||
|
|
@ -1366,7 +1366,7 @@ static inline void enet_hal_set_current_time(uint32_t instance, uint32_t nanSeco
|
|||
*/
|
||||
static inline uint32_t enet_hal_get_current_time(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
return HW_ENET_ATVR_RD(instance);
|
||||
}
|
||||
|
|
@ -1379,7 +1379,7 @@ static inline uint32_t enet_hal_get_current_time(uint32_t instance)
|
|||
*/
|
||||
static inline uint32_t enet_hal_get_tx_timestamp(uint32_t instance)
|
||||
{
|
||||
assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
// assert(instance < HW_ENET_INSTANCE_COUNT);
|
||||
|
||||
return HW_ENET_ATSTMP_RD(instance);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -395,11 +395,8 @@ uint32_t enet_mac_init(enet_dev_if_t * enetIfPtr, enet_rxbd_config_t *rxbdCfg,
|
|||
/* Get device number and check the parameter*/
|
||||
devNumber = enetIfPtr->deviceNumber;
|
||||
|
||||
/* Store the global ENET structure for ISR input parameters for instance 0*/
|
||||
if (!devNumber)
|
||||
{
|
||||
enetIfHandle = enetIfPtr;
|
||||
}
|
||||
/* Store the global ENET structure for ISR input parameters */
|
||||
enetIfHandle = enetIfPtr;
|
||||
|
||||
/* Turn on ENET module clock gate */
|
||||
CLOCK_SYS_EnableEnetClock(0U);
|
||||
|
|
|
|||
|
|
@ -50,33 +50,33 @@ void k64f_init_eth_hardware(void)
|
|||
}
|
||||
|
||||
/* Configure gpio*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 12, kPortMuxAlt4); /*!< ENET RMII0_RXD1/MII0_RXD1*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 13, kPortMuxAlt4); /*!< ENET RMII0_RXD0/MII0_RXD0*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 14, kPortMuxAlt4); /*!< ENET RMII0_CRS_DV/MII0_RXDV*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 15, kPortMuxAlt4); /*!< ENET RMII0_TXEN/MII0_TXEN*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 16, kPortMuxAlt4); /*!< ENET RMII0_TXD0/MII0_TXD0*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 17, kPortMuxAlt4); /*!< ENET RMII0_TXD01/MII0_TXD1*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTB, 0, kPortMuxAlt4); /*!< ENET RMII0_MDIO/MII0_MDIO*/
|
||||
PORT_HAL_SetOpenDrainCmd(HW_PORTB,0, true); /*!< ENET RMII0_MDC/MII0_MDC*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 12, kPortMuxAlt4); /*!< ENET RMII0_RXD1/MII0_RXD1*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 13, kPortMuxAlt4); /*!< ENET RMII0_RXD0/MII0_RXD0*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 14, kPortMuxAlt4); /*!< ENET RMII0_CRS_DV/MII0_RXDV*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 15, kPortMuxAlt4); /*!< ENET RMII0_TXEN/MII0_TXEN*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 16, kPortMuxAlt4); /*!< ENET RMII0_TXD0/MII0_TXD0*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 17, kPortMuxAlt4); /*!< ENET RMII0_TXD01/MII0_TXD1*/
|
||||
PORT_HAL_SetMuxMode(PORTB_BASE, 0, kPortMuxAlt4); /*!< ENET RMII0_MDIO/MII0_MDIO*/
|
||||
PORT_HAL_SetOpenDrainCmd(PORTB_BASE,0, true); /*!< ENET RMII0_MDC/MII0_MDC*/
|
||||
|
||||
// Added for FRDM-K64F
|
||||
PORT_HAL_SetPullMode(HW_PORTB, 0, kPortPullUp);
|
||||
PORT_HAL_SetPullCmd(HW_PORTB, 0, true);
|
||||
PORT_HAL_SetPullMode(PORTB_BASE, 0, kPortPullUp);
|
||||
PORT_HAL_SetPullCmd(PORTB_BASE, 0, true);
|
||||
|
||||
PORT_HAL_SetMuxMode(HW_PORTB, 1, kPortMuxAlt4);
|
||||
PORT_HAL_SetMuxMode(PORTB_BASE, 1, kPortMuxAlt4);
|
||||
/* Configure GPIO for MII interface */
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 9, kPortMuxAlt4); /*!< ENET MII0_RXD3*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 10, kPortMuxAlt4); /*!< ENET MII0_RXD2*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 11, kPortMuxAlt4); /*!< ENET MII0_RXCLK*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 24, kPortMuxAlt4); /*!< ENET MII0_TXD2*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 25, kPortMuxAlt4); /*!< ENET MII0_TXCLK*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 26, kPortMuxAlt4); /*!< ENET MII0_TXD3*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 27, kPortMuxAlt4); /*!< ENET MII0_CRS*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 28, kPortMuxAlt4); /*!< ENET MII0_TXER*/
|
||||
PORT_HAL_SetMuxMode(HW_PORTA, 29, kPortMuxAlt4); /*!< ENET MII0_COL*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 9, kPortMuxAlt4); /*!< ENET MII0_RXD3*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 10, kPortMuxAlt4); /*!< ENET MII0_RXD2*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 11, kPortMuxAlt4); /*!< ENET MII0_RXCLK*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 24, kPortMuxAlt4); /*!< ENET MII0_TXD2*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 25, kPortMuxAlt4); /*!< ENET MII0_TXCLK*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 26, kPortMuxAlt4); /*!< ENET MII0_TXD3*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 27, kPortMuxAlt4); /*!< ENET MII0_CRS*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 28, kPortMuxAlt4); /*!< ENET MII0_TXER*/
|
||||
PORT_HAL_SetMuxMode(PORTA_BASE, 29, kPortMuxAlt4); /*!< ENET MII0_COL*/
|
||||
#if FSL_FEATURE_ENET_SUPPORT_PTP
|
||||
PORT_HAL_SetMuxMode(HW_PORTC, (16 + ENET_TIMER_CHANNEL_NUM), kPortMuxAlt4); /* ENET ENET0_1588_TMR0*/
|
||||
PORT_HAL_SetDriveStrengthMode(HW_PORTC, (16 + ENET_TIMER_CHANNEL_NUM), kPortHighDriveStrength);
|
||||
PORT_HAL_SetMuxMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortMuxAlt4); /* ENET ENET0_1588_TMR0*/
|
||||
PORT_HAL_SetDriveStrengthMode(PORTC_BASE, (16 + ENET_TIMER_CHANNEL_NUM), kPortHighDriveStrength);
|
||||
#endif
|
||||
|
||||
/* Open ENET clock gate*/
|
||||
|
|
|
|||
|
|
@ -148,7 +148,7 @@ static void k64f_rxqueue_pbuf(struct k64f_enetdata *k64f_enet, struct pbuf *p, i
|
|||
if (bidx == RX_PBUF_AUTO_INDEX)
|
||||
k64f_enet->rx_fill_index = idx;
|
||||
|
||||
enet_hal_active_rxbd(BOARD_DEBUG_ENET_INSTANCE);
|
||||
enet_hal_active_rxbd(BOARD_DEBUG_ENET_INSTANCE_ADDR);
|
||||
|
||||
LWIP_DEBUGF(UDP_LPC_EMAC | LWIP_DBG_TRACE,
|
||||
("k64f_rxqueue_pbuf: pbuf packet queued: %p (free desc=%d)\n", p,
|
||||
|
|
@ -296,7 +296,7 @@ static void k64f_tx_reclaim(struct k64f_enetdata *k64f_enet)
|
|||
static err_t low_level_init(struct netif *netif)
|
||||
{
|
||||
enet_dev_if_t * enetIfPtr;
|
||||
uint32_t device = BOARD_DEBUG_ENET_INSTANCE;
|
||||
uint32_t device = BOARD_DEBUG_ENET_INSTANCE_ADDR;
|
||||
enet_rxbd_config_t rxbdCfg;
|
||||
enet_txbd_config_t txbdCfg;
|
||||
enet_phy_speed_t phy_speed;
|
||||
|
|
@ -305,10 +305,10 @@ static err_t low_level_init(struct netif *netif)
|
|||
k64f_init_eth_hardware();
|
||||
|
||||
/* Initialize device*/
|
||||
enetIfPtr = (enet_dev_if_t *)&enetDevIf[device];
|
||||
enetIfPtr = (enet_dev_if_t *)&enetDevIf[BOARD_DEBUG_ENET_INSTANCE];
|
||||
enetIfPtr->deviceNumber = device;
|
||||
enetIfPtr->macCfgPtr = &g_enetMacCfg[device];
|
||||
enetIfPtr->phyCfgPtr = &g_enetPhyCfg[device];
|
||||
enetIfPtr->macCfgPtr = &g_enetMacCfg[BOARD_DEBUG_ENET_INSTANCE];
|
||||
enetIfPtr->phyCfgPtr = &g_enetPhyCfg[BOARD_DEBUG_ENET_INSTANCE];
|
||||
enetIfPtr->macApiPtr = &g_enetMacApi;
|
||||
enetIfPtr->phyApiPtr = (void *)&g_enetPhyApi;
|
||||
memcpy(enetIfPtr->macCfgPtr->macAddr, (char*)netif->hwaddr, kEnetMacAddrLen);
|
||||
|
|
@ -317,7 +317,7 @@ static err_t low_level_init(struct netif *netif)
|
|||
enetIfPtr->macContextPtr = (enet_mac_context_t *)calloc(1, sizeof(enet_mac_context_t));
|
||||
if (!enetIfPtr->macContextPtr) {
|
||||
return ERR_BUF;
|
||||
}
|
||||
}
|
||||
|
||||
/* Initialize enet buffers*/
|
||||
if(k64f_rx_setup(netif, &rxbdCfg) != ERR_OK) {
|
||||
|
|
@ -353,7 +353,7 @@ static err_t low_level_init(struct netif *netif)
|
|||
BW_ENET_TCR_FDEN(enetIfPtr->deviceNumber, phy_duplex == kEnetFullDuplex ? kEnetCfgFullDuplex : kEnetCfgHalfDuplex);
|
||||
|
||||
/* Enable Ethernet module*/
|
||||
enet_hal_config_ethernet(device, true, true);
|
||||
enet_hal_config_ethernet(BOARD_DEBUG_ENET_INSTANCE_ADDR, true, true);
|
||||
|
||||
/* Active Receive buffer descriptor must be done after module enable*/
|
||||
enet_hal_active_rxbd(enetIfPtr->deviceNumber);
|
||||
|
|
@ -380,7 +380,7 @@ void enet_mac_tx_isr(void *enetIfPtr)
|
|||
{
|
||||
/*Clear interrupt*/
|
||||
enet_hal_clear_interrupt(((enet_dev_if_t *)enetIfPtr)->deviceNumber, kEnetTxFrameInterrupt);
|
||||
sys_sem_signal(&k64f_enetdata.TxCleanSem);
|
||||
sys_sem_signal(&k64f_enetdata.TxCleanSem);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -393,7 +393,7 @@ void enet_mac_tx_isr(void *enetIfPtr)
|
|||
* \return ERR_OK or error code
|
||||
*/
|
||||
err_t k64f_etharp_output(struct netif *netif, struct pbuf *q, ip_addr_t *ipaddr)
|
||||
{
|
||||
{
|
||||
/* Only send packet is link is up */
|
||||
if (netif->flags & NETIF_FLAG_LINK_UP)
|
||||
return etharp_output(netif, q, ipaddr);
|
||||
|
|
@ -701,7 +701,7 @@ static err_t k64f_low_level_output(struct netif *netif, struct pbuf *p)
|
|||
}
|
||||
|
||||
k64f_enet->tx_produce_index = idx;
|
||||
enet_hal_active_txbd(BOARD_DEBUG_ENET_INSTANCE);
|
||||
enet_hal_active_txbd(BOARD_DEBUG_ENET_INSTANCE_ADDR);
|
||||
LINK_STATS_INC(link.xmit);
|
||||
|
||||
/* Restore access */
|
||||
|
|
@ -844,7 +844,7 @@ err_t eth_arch_enetif_init(struct netif *netif)
|
|||
}
|
||||
|
||||
void eth_arch_enable_interrupts(void) {
|
||||
enet_hal_config_interrupt(BOARD_DEBUG_ENET_INSTANCE, (kEnetTxFrameInterrupt | kEnetRxFrameInterrupt), true);
|
||||
enet_hal_config_interrupt(BOARD_DEBUG_ENET_INSTANCE_ADDR, (kEnetTxFrameInterrupt | kEnetRxFrameInterrupt), true);
|
||||
INT_SYS_EnableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetRxfInt]]);
|
||||
INT_SYS_EnableIRQ(enet_irq_ids[BOARD_DEBUG_ENET_INSTANCE][enetIntMap[kEnetTxfInt]]);
|
||||
}
|
||||
|
|
|
|||
|
|
@ -40,6 +40,7 @@
|
|||
#define RX_BUF_ALIGNMENT (16)
|
||||
#define TX_BUF_ALIGNMENT (8)
|
||||
#define BOARD_DEBUG_ENET_INSTANCE (0)
|
||||
#define BOARD_DEBUG_ENET_INSTANCE_ADDR (ENET_BASE)
|
||||
|
||||
#define ENET_ETH_MAX_FLEN (1522) // recommended size for a VLAN frame
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue